stm32f469xx.h 1.7 MB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f469xx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - peripherals registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32f469xx
  45. * @{
  46. */
  47. #ifndef __STM32F469xx_H
  48. #define __STM32F469xx_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
  59. #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 1U /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32F4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  77. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  78. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  79. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  80. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  81. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  82. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  83. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  84. /****** STM32 specific Interrupt Numbers **********************************************************************/
  85. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  86. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  87. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  88. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  89. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  90. RCC_IRQn = 5, /*!< RCC global Interrupt */
  91. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  92. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  93. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  94. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  95. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  96. DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
  97. DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
  98. DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
  99. DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
  100. DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
  101. DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
  102. DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
  103. ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
  104. CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
  105. CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
  106. CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
  107. CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
  108. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  109. TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
  110. TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
  111. TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
  112. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  113. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  114. TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
  115. TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
  116. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  117. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  118. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  119. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  120. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  121. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  122. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  123. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  124. USART3_IRQn = 39, /*!< USART3 global Interrupt */
  125. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  126. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  127. OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
  128. TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
  129. TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
  130. TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
  131. TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
  132. DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
  133. FMC_IRQn = 48, /*!< FMC global Interrupt */
  134. SDIO_IRQn = 49, /*!< SDIO global Interrupt */
  135. TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
  136. SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
  137. UART4_IRQn = 52, /*!< UART4 global Interrupt */
  138. UART5_IRQn = 53, /*!< UART5 global Interrupt */
  139. TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
  140. TIM7_IRQn = 55, /*!< TIM7 global interrupt */
  141. DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
  142. DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
  143. DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
  144. DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
  145. DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
  146. ETH_IRQn = 61, /*!< Ethernet global Interrupt */
  147. ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
  148. CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
  149. CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
  150. CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
  151. CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
  152. OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
  153. DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
  154. DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
  155. DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
  156. USART6_IRQn = 71, /*!< USART6 global interrupt */
  157. I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
  158. I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
  159. OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
  160. OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
  161. OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
  162. OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
  163. DCMI_IRQn = 78, /*!< DCMI global interrupt */
  164. HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
  165. FPU_IRQn = 81, /*!< FPU global interrupt */
  166. UART7_IRQn = 82, /*!< UART7 global interrupt */
  167. UART8_IRQn = 83, /*!< UART8 global interrupt */
  168. SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
  169. SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
  170. SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
  171. SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
  172. LTDC_IRQn = 88, /*!< LTDC global Interrupt */
  173. LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
  174. DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
  175. QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
  176. DSI_IRQn = 92 /*!< DSI global Interrupt */
  177. } IRQn_Type;
  178. /**
  179. * @}
  180. */
  181. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  182. #include "system_stm32f4xx.h"
  183. #include <stdint.h>
  184. /** @addtogroup Peripheral_registers_structures
  185. * @{
  186. */
  187. /**
  188. * @brief Analog to Digital Converter
  189. */
  190. typedef struct
  191. {
  192. __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
  193. __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
  194. __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
  195. __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
  196. __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
  197. __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  198. __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  199. __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  200. __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  201. __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
  202. __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
  203. __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
  204. __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
  205. __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
  206. __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
  207. __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
  208. __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
  209. __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
  210. __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
  211. __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
  212. } ADC_TypeDef;
  213. typedef struct
  214. {
  215. __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
  216. __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
  217. __IO uint32_t CDR; /*!< ADC common regular data register for dual
  218. AND triple modes, Address offset: ADC1 base address + 0x308 */
  219. } ADC_Common_TypeDef;
  220. /**
  221. * @brief Controller Area Network TxMailBox
  222. */
  223. typedef struct
  224. {
  225. __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
  226. __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
  227. __IO uint32_t TDLR; /*!< CAN mailbox data low register */
  228. __IO uint32_t TDHR; /*!< CAN mailbox data high register */
  229. } CAN_TxMailBox_TypeDef;
  230. /**
  231. * @brief Controller Area Network FIFOMailBox
  232. */
  233. typedef struct
  234. {
  235. __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
  236. __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
  237. __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
  238. __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
  239. } CAN_FIFOMailBox_TypeDef;
  240. /**
  241. * @brief Controller Area Network FilterRegister
  242. */
  243. typedef struct
  244. {
  245. __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
  246. __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
  247. } CAN_FilterRegister_TypeDef;
  248. /**
  249. * @brief Controller Area Network
  250. */
  251. typedef struct
  252. {
  253. __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
  254. __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
  255. __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
  256. __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
  257. __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
  258. __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
  259. __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
  260. __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
  261. uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
  262. CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
  263. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
  264. uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
  265. __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
  266. __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
  267. uint32_t RESERVED2; /*!< Reserved, 0x208 */
  268. __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
  269. uint32_t RESERVED3; /*!< Reserved, 0x210 */
  270. __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
  271. uint32_t RESERVED4; /*!< Reserved, 0x218 */
  272. __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
  273. uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
  274. CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
  275. } CAN_TypeDef;
  276. /**
  277. * @brief CRC calculation unit
  278. */
  279. typedef struct
  280. {
  281. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  282. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  283. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  284. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  285. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  286. } CRC_TypeDef;
  287. /**
  288. * @brief Digital to Analog Converter
  289. */
  290. typedef struct
  291. {
  292. __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
  293. __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
  294. __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  295. __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
  296. __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
  297. __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  298. __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
  299. __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
  300. __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
  301. __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
  302. __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
  303. __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
  304. __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
  305. __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
  306. } DAC_TypeDef;
  307. /**
  308. * @brief Debug MCU
  309. */
  310. typedef struct
  311. {
  312. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  313. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  314. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  315. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  316. }DBGMCU_TypeDef;
  317. /**
  318. * @brief DCMI
  319. */
  320. typedef struct
  321. {
  322. __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
  323. __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
  324. __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
  325. __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
  326. __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
  327. __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
  328. __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
  329. __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
  330. __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
  331. __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
  332. __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
  333. } DCMI_TypeDef;
  334. /**
  335. * @brief DMA Controller
  336. */
  337. typedef struct
  338. {
  339. __IO uint32_t CR; /*!< DMA stream x configuration register */
  340. __IO uint32_t NDTR; /*!< DMA stream x number of data register */
  341. __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
  342. __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
  343. __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
  344. __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
  345. } DMA_Stream_TypeDef;
  346. typedef struct
  347. {
  348. __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
  349. __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
  350. __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
  351. __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
  352. } DMA_TypeDef;
  353. /**
  354. * @brief DMA2D Controller
  355. */
  356. typedef struct
  357. {
  358. __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
  359. __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
  360. __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
  361. __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
  362. __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
  363. __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
  364. __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
  365. __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
  366. __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
  367. __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
  368. __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
  369. __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
  370. __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
  371. __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
  372. __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
  373. __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
  374. __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
  375. __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
  376. __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
  377. __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
  378. uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
  379. __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
  380. __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
  381. } DMA2D_TypeDef;
  382. /**
  383. * @brief DSI Controller
  384. */
  385. typedef struct
  386. {
  387. __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
  388. __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
  389. __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
  390. __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
  391. __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
  392. __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
  393. __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
  394. uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
  395. __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
  396. __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
  397. __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
  398. __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
  399. __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
  400. __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
  401. __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
  402. __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
  403. __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
  404. __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
  405. __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
  406. __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
  407. __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
  408. __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
  409. __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
  410. __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
  411. __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
  412. __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
  413. __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
  414. __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
  415. __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
  416. __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
  417. __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
  418. __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
  419. __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
  420. __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
  421. __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
  422. __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
  423. __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
  424. uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
  425. __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
  426. __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
  427. uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
  428. __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
  429. uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
  430. __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
  431. uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
  432. __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
  433. __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
  434. uint32_t RESERVED5; /*!< Reserved, 0x114 */
  435. __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
  436. uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
  437. __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
  438. __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
  439. __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
  440. __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
  441. __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
  442. __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
  443. __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
  444. __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
  445. __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
  446. __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
  447. __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
  448. uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
  449. __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
  450. uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
  451. __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
  452. __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
  453. __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
  454. __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
  455. __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
  456. uint32_t RESERVED9; /*!< Reserved, 0x414 */
  457. __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
  458. uint32_t RESERVED10; /*!< Reserved, 0x42C */
  459. __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
  460. } DSI_TypeDef;
  461. /**
  462. * @brief Ethernet MAC
  463. */
  464. typedef struct
  465. {
  466. __IO uint32_t MACCR;
  467. __IO uint32_t MACFFR;
  468. __IO uint32_t MACHTHR;
  469. __IO uint32_t MACHTLR;
  470. __IO uint32_t MACMIIAR;
  471. __IO uint32_t MACMIIDR;
  472. __IO uint32_t MACFCR;
  473. __IO uint32_t MACVLANTR; /* 8 */
  474. uint32_t RESERVED0[2];
  475. __IO uint32_t MACRWUFFR; /* 11 */
  476. __IO uint32_t MACPMTCSR;
  477. uint32_t RESERVED1;
  478. __IO uint32_t MACDBGR;
  479. __IO uint32_t MACSR; /* 15 */
  480. __IO uint32_t MACIMR;
  481. __IO uint32_t MACA0HR;
  482. __IO uint32_t MACA0LR;
  483. __IO uint32_t MACA1HR;
  484. __IO uint32_t MACA1LR;
  485. __IO uint32_t MACA2HR;
  486. __IO uint32_t MACA2LR;
  487. __IO uint32_t MACA3HR;
  488. __IO uint32_t MACA3LR; /* 24 */
  489. uint32_t RESERVED2[40];
  490. __IO uint32_t MMCCR; /* 65 */
  491. __IO uint32_t MMCRIR;
  492. __IO uint32_t MMCTIR;
  493. __IO uint32_t MMCRIMR;
  494. __IO uint32_t MMCTIMR; /* 69 */
  495. uint32_t RESERVED3[14];
  496. __IO uint32_t MMCTGFSCCR; /* 84 */
  497. __IO uint32_t MMCTGFMSCCR;
  498. uint32_t RESERVED4[5];
  499. __IO uint32_t MMCTGFCR;
  500. uint32_t RESERVED5[10];
  501. __IO uint32_t MMCRFCECR;
  502. __IO uint32_t MMCRFAECR;
  503. uint32_t RESERVED6[10];
  504. __IO uint32_t MMCRGUFCR;
  505. uint32_t RESERVED7[334];
  506. __IO uint32_t PTPTSCR;
  507. __IO uint32_t PTPSSIR;
  508. __IO uint32_t PTPTSHR;
  509. __IO uint32_t PTPTSLR;
  510. __IO uint32_t PTPTSHUR;
  511. __IO uint32_t PTPTSLUR;
  512. __IO uint32_t PTPTSAR;
  513. __IO uint32_t PTPTTHR;
  514. __IO uint32_t PTPTTLR;
  515. __IO uint32_t RESERVED8;
  516. __IO uint32_t PTPTSSR;
  517. uint32_t RESERVED9[565];
  518. __IO uint32_t DMABMR;
  519. __IO uint32_t DMATPDR;
  520. __IO uint32_t DMARPDR;
  521. __IO uint32_t DMARDLAR;
  522. __IO uint32_t DMATDLAR;
  523. __IO uint32_t DMASR;
  524. __IO uint32_t DMAOMR;
  525. __IO uint32_t DMAIER;
  526. __IO uint32_t DMAMFBOCR;
  527. __IO uint32_t DMARSWTR;
  528. uint32_t RESERVED10[8];
  529. __IO uint32_t DMACHTDR;
  530. __IO uint32_t DMACHRDR;
  531. __IO uint32_t DMACHTBAR;
  532. __IO uint32_t DMACHRBAR;
  533. } ETH_TypeDef;
  534. /**
  535. * @brief External Interrupt/Event Controller
  536. */
  537. typedef struct
  538. {
  539. __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
  540. __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
  541. __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
  542. __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
  543. __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
  544. __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
  545. } EXTI_TypeDef;
  546. /**
  547. * @brief FLASH Registers
  548. */
  549. typedef struct
  550. {
  551. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  552. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
  553. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
  554. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
  555. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
  556. __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
  557. __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
  558. } FLASH_TypeDef;
  559. /**
  560. * @brief Flexible Memory Controller
  561. */
  562. typedef struct
  563. {
  564. __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
  565. } FMC_Bank1_TypeDef;
  566. /**
  567. * @brief Flexible Memory Controller Bank1E
  568. */
  569. typedef struct
  570. {
  571. __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
  572. } FMC_Bank1E_TypeDef;
  573. /**
  574. * @brief Flexible Memory Controller Bank3
  575. */
  576. typedef struct
  577. {
  578. __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
  579. __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
  580. __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
  581. __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
  582. uint32_t RESERVED; /*!< Reserved, 0x90 */
  583. __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
  584. } FMC_Bank3_TypeDef;
  585. /**
  586. * @brief Flexible Memory Controller Bank5_6
  587. */
  588. typedef struct
  589. {
  590. __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
  591. __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
  592. __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
  593. __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
  594. __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
  595. } FMC_Bank5_6_TypeDef;
  596. /**
  597. * @brief General Purpose I/O
  598. */
  599. typedef struct
  600. {
  601. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  602. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  603. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  604. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  605. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  606. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  607. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  608. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  609. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  610. } GPIO_TypeDef;
  611. /**
  612. * @brief System configuration controller
  613. */
  614. typedef struct
  615. {
  616. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  617. __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
  618. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  619. uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
  620. __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
  621. } SYSCFG_TypeDef;
  622. /**
  623. * @brief Inter-integrated Circuit Interface
  624. */
  625. typedef struct
  626. {
  627. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  628. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  629. __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
  630. __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
  631. __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
  632. __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
  633. __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
  634. __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
  635. __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
  636. __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
  637. } I2C_TypeDef;
  638. /**
  639. * @brief Independent WATCHDOG
  640. */
  641. typedef struct
  642. {
  643. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  644. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  645. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  646. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  647. } IWDG_TypeDef;
  648. /**
  649. * @brief LCD-TFT Display Controller
  650. */
  651. typedef struct
  652. {
  653. uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
  654. __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
  655. __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
  656. __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
  657. __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
  658. __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
  659. uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
  660. __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
  661. uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
  662. __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
  663. uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
  664. __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
  665. __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
  666. __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
  667. __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
  668. __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
  669. __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
  670. } LTDC_TypeDef;
  671. /**
  672. * @brief LCD-TFT Display layer x Controller
  673. */
  674. typedef struct
  675. {
  676. __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
  677. __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
  678. __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
  679. __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
  680. __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
  681. __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
  682. __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
  683. __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
  684. uint32_t RESERVED0[2]; /*!< Reserved */
  685. __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
  686. __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
  687. __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
  688. uint32_t RESERVED1[3]; /*!< Reserved */
  689. __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
  690. } LTDC_Layer_TypeDef;
  691. /**
  692. * @brief Power Control
  693. */
  694. typedef struct
  695. {
  696. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  697. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  698. } PWR_TypeDef;
  699. /**
  700. * @brief Reset and Clock Control
  701. */
  702. typedef struct
  703. {
  704. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  705. __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
  706. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  707. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
  708. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
  709. __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
  710. __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
  711. uint32_t RESERVED0; /*!< Reserved, 0x1C */
  712. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
  713. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
  714. uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
  715. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
  716. __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
  717. __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
  718. uint32_t RESERVED2; /*!< Reserved, 0x3C */
  719. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
  720. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
  721. uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
  722. __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  723. __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
  724. __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
  725. uint32_t RESERVED4; /*!< Reserved, 0x5C */
  726. __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  727. __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  728. uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
  729. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
  730. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
  731. uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
  732. __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
  733. __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
  734. __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
  735. __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
  736. } RCC_TypeDef;
  737. /**
  738. * @brief Real-Time Clock
  739. */
  740. typedef struct
  741. {
  742. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  743. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  744. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  745. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  746. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  747. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  748. __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
  749. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  750. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  751. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  752. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  753. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  754. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  755. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  756. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  757. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  758. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  759. __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
  760. __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
  761. uint32_t RESERVED7; /*!< Reserved, 0x4C */
  762. __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
  763. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  764. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  765. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  766. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  767. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  768. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  769. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  770. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  771. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  772. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  773. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  774. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  775. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  776. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  777. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  778. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  779. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  780. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  781. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  782. } RTC_TypeDef;
  783. /**
  784. * @brief Serial Audio Interface
  785. */
  786. typedef struct
  787. {
  788. __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
  789. } SAI_TypeDef;
  790. typedef struct
  791. {
  792. __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
  793. __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
  794. __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
  795. __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
  796. __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
  797. __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
  798. __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
  799. __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
  800. } SAI_Block_TypeDef;
  801. /**
  802. * @brief SD host Interface
  803. */
  804. typedef struct
  805. {
  806. __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
  807. __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
  808. __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
  809. __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
  810. __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
  811. __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
  812. __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
  813. __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
  814. __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
  815. __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
  816. __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
  817. __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
  818. __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
  819. __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
  820. __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
  821. __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
  822. uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
  823. __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
  824. uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
  825. __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
  826. } SDIO_TypeDef;
  827. /**
  828. * @brief Serial Peripheral Interface
  829. */
  830. typedef struct
  831. {
  832. __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
  833. __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
  834. __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
  835. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  836. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  837. __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
  838. __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
  839. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  840. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  841. } SPI_TypeDef;
  842. /**
  843. * @brief QUAD Serial Peripheral Interface
  844. */
  845. typedef struct
  846. {
  847. __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
  848. __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
  849. __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
  850. __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
  851. __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
  852. __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
  853. __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
  854. __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
  855. __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
  856. __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
  857. __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
  858. __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
  859. __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
  860. } QUADSPI_TypeDef;
  861. /**
  862. * @brief TIM
  863. */
  864. typedef struct
  865. {
  866. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  867. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  868. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  869. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  870. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  871. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  872. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  873. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  874. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  875. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  876. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  877. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  878. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  879. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  880. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  881. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  882. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  883. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  884. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  885. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  886. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  887. } TIM_TypeDef;
  888. /**
  889. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  890. */
  891. typedef struct
  892. {
  893. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  894. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  895. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  896. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  897. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  898. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  899. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  900. } USART_TypeDef;
  901. /**
  902. * @brief Window WATCHDOG
  903. */
  904. typedef struct
  905. {
  906. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  907. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  908. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  909. } WWDG_TypeDef;
  910. /**
  911. * @brief RNG
  912. */
  913. typedef struct
  914. {
  915. __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
  916. __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
  917. __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
  918. } RNG_TypeDef;
  919. /**
  920. * @brief USB_OTG_Core_Registers
  921. */
  922. typedef struct
  923. {
  924. __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
  925. __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
  926. __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
  927. __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
  928. __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
  929. __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
  930. __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
  931. __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
  932. __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
  933. __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
  934. __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
  935. __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
  936. uint32_t Reserved30[2]; /*!< Reserved 030h */
  937. __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
  938. __IO uint32_t CID; /*!< User ID Register 03Ch */
  939. uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
  940. __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
  941. uint32_t Reserved6; /*!< Reserved 050h */
  942. __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
  943. uint32_t Reserved; /*!< Reserved 058h */
  944. __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
  945. uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
  946. __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
  947. __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
  948. } USB_OTG_GlobalTypeDef;
  949. /**
  950. * @brief USB_OTG_device_Registers
  951. */
  952. typedef struct
  953. {
  954. __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
  955. __IO uint32_t DCTL; /*!< dev Control Register 804h */
  956. __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
  957. uint32_t Reserved0C; /*!< Reserved 80Ch */
  958. __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
  959. __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
  960. __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
  961. __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
  962. uint32_t Reserved20; /*!< Reserved 820h */
  963. uint32_t Reserved9; /*!< Reserved 824h */
  964. __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
  965. __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
  966. __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
  967. __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
  968. __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
  969. __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
  970. uint32_t Reserved40; /*!< dedicated EP mask 840h */
  971. __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
  972. uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
  973. __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
  974. } USB_OTG_DeviceTypeDef;
  975. /**
  976. * @brief USB_OTG_IN_Endpoint-Specific_Register
  977. */
  978. typedef struct
  979. {
  980. __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
  981. uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
  982. __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
  983. uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
  984. __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
  985. __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
  986. __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
  987. uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
  988. } USB_OTG_INEndpointTypeDef;
  989. /**
  990. * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  991. */
  992. typedef struct
  993. {
  994. __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
  995. uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
  996. __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
  997. uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
  998. __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
  999. __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
  1000. uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
  1001. } USB_OTG_OUTEndpointTypeDef;
  1002. /**
  1003. * @brief USB_OTG_Host_Mode_Register_Structures
  1004. */
  1005. typedef struct
  1006. {
  1007. __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
  1008. __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
  1009. __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
  1010. uint32_t Reserved40C; /*!< Reserved 40Ch */
  1011. __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
  1012. __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
  1013. __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
  1014. } USB_OTG_HostTypeDef;
  1015. /**
  1016. * @brief USB_OTG_Host_Channel_Specific_Registers
  1017. */
  1018. typedef struct
  1019. {
  1020. __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
  1021. __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
  1022. __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
  1023. __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
  1024. __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
  1025. __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
  1026. uint32_t Reserved[2]; /*!< Reserved */
  1027. } USB_OTG_HostChannelTypeDef;
  1028. /**
  1029. * @}
  1030. */
  1031. /** @addtogroup Peripheral_memory_map
  1032. * @{
  1033. */
  1034. #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
  1035. #define CCMDATARAM_BASE 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
  1036. #define SRAM1_BASE 0x20000000UL /*!< SRAM1(160 KB) base address in the alias region */
  1037. #define SRAM2_BASE 0x20028000UL /*!< SRAM2(32 KB) base address in the alias region */
  1038. #define SRAM3_BASE 0x20030000UL /*!< SRAM3(128 KB) base address in the alias region */
  1039. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  1040. #define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
  1041. #define FMC_R_BASE 0xA0000000UL /*!< FMC registers base address */
  1042. #define QSPI_R_BASE 0xA0001000UL /*!< QuadSPI registers base address */
  1043. #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
  1044. #define SRAM2_BB_BASE 0x22500000UL /*!< SRAM2(16 KB) base address in the bit-band region */
  1045. #define SRAM3_BB_BASE 0x22600000UL /*!< SRAM3(64 KB) base address in the bit-band region */
  1046. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  1047. #define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
  1048. #define FLASH_END 0x081FFFFFUL /*!< FLASH end address */
  1049. #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
  1050. #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
  1051. #define CCMDATARAM_END 0x1000FFFFUL /*!< CCM data RAM end address */
  1052. /* Legacy defines */
  1053. #define SRAM_BASE SRAM1_BASE
  1054. #define SRAM_BB_BASE SRAM1_BB_BASE
  1055. /*!< Peripheral memory map */
  1056. #define APB1PERIPH_BASE PERIPH_BASE
  1057. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  1058. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  1059. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
  1060. /*!< APB1 peripherals */
  1061. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
  1062. #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
  1063. #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
  1064. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
  1065. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
  1066. #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
  1067. #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
  1068. #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
  1069. #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
  1070. #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
  1071. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
  1072. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
  1073. #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
  1074. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
  1075. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
  1076. #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
  1077. #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
  1078. #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
  1079. #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
  1080. #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
  1081. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
  1082. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
  1083. #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
  1084. #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
  1085. #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
  1086. #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
  1087. #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
  1088. #define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
  1089. #define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
  1090. /*!< APB2 peripherals */
  1091. #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
  1092. #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
  1093. #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
  1094. #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
  1095. #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
  1096. #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
  1097. #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
  1098. #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
  1099. /* Legacy define */
  1100. #define ADC_BASE ADC123_COMMON_BASE
  1101. #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
  1102. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
  1103. #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
  1104. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
  1105. #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
  1106. #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
  1107. #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
  1108. #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
  1109. #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
  1110. #define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
  1111. #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
  1112. #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
  1113. #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
  1114. #define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
  1115. #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
  1116. #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
  1117. #define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
  1118. /*!< AHB1 peripherals */
  1119. #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
  1120. #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
  1121. #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
  1122. #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
  1123. #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
  1124. #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
  1125. #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
  1126. #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
  1127. #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
  1128. #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
  1129. #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
  1130. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
  1131. #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
  1132. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
  1133. #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
  1134. #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
  1135. #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
  1136. #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
  1137. #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
  1138. #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
  1139. #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
  1140. #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
  1141. #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
  1142. #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
  1143. #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
  1144. #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
  1145. #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
  1146. #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
  1147. #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
  1148. #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
  1149. #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
  1150. #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
  1151. #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
  1152. #define ETH_MAC_BASE (ETH_BASE)
  1153. #define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
  1154. #define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
  1155. #define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
  1156. #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
  1157. /*!< AHB2 peripherals */
  1158. #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
  1159. #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
  1160. /*!< FMC Bankx registers base address */
  1161. #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
  1162. #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
  1163. #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
  1164. #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
  1165. /*!< Debug MCU registers base address */
  1166. #define DBGMCU_BASE 0xE0042000UL
  1167. /*!< USB registers base address */
  1168. #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
  1169. #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
  1170. #define USB_OTG_GLOBAL_BASE 0x000UL
  1171. #define USB_OTG_DEVICE_BASE 0x800UL
  1172. #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
  1173. #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
  1174. #define USB_OTG_EP_REG_SIZE 0x20UL
  1175. #define USB_OTG_HOST_BASE 0x400UL
  1176. #define USB_OTG_HOST_PORT_BASE 0x440UL
  1177. #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
  1178. #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
  1179. #define USB_OTG_PCGCCTL_BASE 0xE00UL
  1180. #define USB_OTG_FIFO_BASE 0x1000UL
  1181. #define USB_OTG_FIFO_SIZE 0x1000UL
  1182. #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
  1183. #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
  1184. #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
  1185. /**
  1186. * @}
  1187. */
  1188. /** @addtogroup Peripheral_declaration
  1189. * @{
  1190. */
  1191. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  1192. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  1193. #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
  1194. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  1195. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  1196. #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
  1197. #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
  1198. #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
  1199. #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
  1200. #define RTC ((RTC_TypeDef *) RTC_BASE)
  1201. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  1202. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  1203. #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
  1204. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  1205. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  1206. #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
  1207. #define USART2 ((USART_TypeDef *) USART2_BASE)
  1208. #define USART3 ((USART_TypeDef *) USART3_BASE)
  1209. #define UART4 ((USART_TypeDef *) UART4_BASE)
  1210. #define UART5 ((USART_TypeDef *) UART5_BASE)
  1211. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  1212. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  1213. #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
  1214. #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
  1215. #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
  1216. #define PWR ((PWR_TypeDef *) PWR_BASE)
  1217. #define DAC1 ((DAC_TypeDef *) DAC_BASE)
  1218. #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
  1219. #define UART7 ((USART_TypeDef *) UART7_BASE)
  1220. #define UART8 ((USART_TypeDef *) UART8_BASE)
  1221. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  1222. #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
  1223. #define USART1 ((USART_TypeDef *) USART1_BASE)
  1224. #define USART6 ((USART_TypeDef *) USART6_BASE)
  1225. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  1226. #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
  1227. #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
  1228. #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
  1229. /* Legacy define */
  1230. #define ADC ADC123_COMMON
  1231. #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
  1232. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  1233. #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
  1234. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  1235. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  1236. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  1237. #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
  1238. #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
  1239. #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
  1240. #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
  1241. #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
  1242. #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
  1243. #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
  1244. #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
  1245. #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
  1246. #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
  1247. #define DSI ((DSI_TypeDef *)DSI_BASE)
  1248. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  1249. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  1250. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  1251. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  1252. #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
  1253. #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
  1254. #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
  1255. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  1256. #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
  1257. #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
  1258. #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
  1259. #define CRC ((CRC_TypeDef *) CRC_BASE)
  1260. #define RCC ((RCC_TypeDef *) RCC_BASE)
  1261. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  1262. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  1263. #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  1264. #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
  1265. #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
  1266. #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
  1267. #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
  1268. #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
  1269. #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
  1270. #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
  1271. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  1272. #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
  1273. #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
  1274. #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
  1275. #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
  1276. #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
  1277. #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
  1278. #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
  1279. #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
  1280. #define ETH ((ETH_TypeDef *) ETH_BASE)
  1281. #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
  1282. #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
  1283. #define RNG ((RNG_TypeDef *) RNG_BASE)
  1284. #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
  1285. #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
  1286. #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
  1287. #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
  1288. #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
  1289. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  1290. #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
  1291. #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
  1292. /**
  1293. * @}
  1294. */
  1295. /** @addtogroup Exported_constants
  1296. * @{
  1297. */
  1298. /** @addtogroup Peripheral_Registers_Bits_Definition
  1299. * @{
  1300. */
  1301. /******************************************************************************/
  1302. /* Peripheral Registers_Bits_Definition */
  1303. /******************************************************************************/
  1304. /******************************************************************************/
  1305. /* */
  1306. /* Analog to Digital Converter */
  1307. /* */
  1308. /******************************************************************************/
  1309. /*
  1310. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  1311. */
  1312. #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
  1313. /******************** Bit definition for ADC_SR register ********************/
  1314. #define ADC_SR_AWD_Pos (0U)
  1315. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  1316. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
  1317. #define ADC_SR_EOC_Pos (1U)
  1318. #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
  1319. #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
  1320. #define ADC_SR_JEOC_Pos (2U)
  1321. #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
  1322. #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
  1323. #define ADC_SR_JSTRT_Pos (3U)
  1324. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  1325. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
  1326. #define ADC_SR_STRT_Pos (4U)
  1327. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  1328. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
  1329. #define ADC_SR_OVR_Pos (5U)
  1330. #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
  1331. #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
  1332. /******************* Bit definition for ADC_CR1 register ********************/
  1333. #define ADC_CR1_AWDCH_Pos (0U)
  1334. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  1335. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
  1336. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  1337. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  1338. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  1339. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  1340. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  1341. #define ADC_CR1_EOCIE_Pos (5U)
  1342. #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
  1343. #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
  1344. #define ADC_CR1_AWDIE_Pos (6U)
  1345. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  1346. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
  1347. #define ADC_CR1_JEOCIE_Pos (7U)
  1348. #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
  1349. #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
  1350. #define ADC_CR1_SCAN_Pos (8U)
  1351. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  1352. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
  1353. #define ADC_CR1_AWDSGL_Pos (9U)
  1354. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  1355. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
  1356. #define ADC_CR1_JAUTO_Pos (10U)
  1357. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  1358. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
  1359. #define ADC_CR1_DISCEN_Pos (11U)
  1360. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  1361. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
  1362. #define ADC_CR1_JDISCEN_Pos (12U)
  1363. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  1364. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
  1365. #define ADC_CR1_DISCNUM_Pos (13U)
  1366. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  1367. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
  1368. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  1369. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  1370. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  1371. #define ADC_CR1_JAWDEN_Pos (22U)
  1372. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  1373. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
  1374. #define ADC_CR1_AWDEN_Pos (23U)
  1375. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  1376. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
  1377. #define ADC_CR1_RES_Pos (24U)
  1378. #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
  1379. #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
  1380. #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
  1381. #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
  1382. #define ADC_CR1_OVRIE_Pos (26U)
  1383. #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
  1384. #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
  1385. /******************* Bit definition for ADC_CR2 register ********************/
  1386. #define ADC_CR2_ADON_Pos (0U)
  1387. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  1388. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
  1389. #define ADC_CR2_CONT_Pos (1U)
  1390. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  1391. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
  1392. #define ADC_CR2_DMA_Pos (8U)
  1393. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  1394. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
  1395. #define ADC_CR2_DDS_Pos (9U)
  1396. #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
  1397. #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
  1398. #define ADC_CR2_EOCS_Pos (10U)
  1399. #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
  1400. #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
  1401. #define ADC_CR2_ALIGN_Pos (11U)
  1402. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  1403. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
  1404. #define ADC_CR2_JEXTSEL_Pos (16U)
  1405. #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
  1406. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
  1407. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
  1408. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
  1409. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
  1410. #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
  1411. #define ADC_CR2_JEXTEN_Pos (20U)
  1412. #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
  1413. #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
  1414. #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
  1415. #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
  1416. #define ADC_CR2_JSWSTART_Pos (22U)
  1417. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
  1418. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
  1419. #define ADC_CR2_EXTSEL_Pos (24U)
  1420. #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
  1421. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
  1422. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
  1423. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
  1424. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
  1425. #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
  1426. #define ADC_CR2_EXTEN_Pos (28U)
  1427. #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
  1428. #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
  1429. #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
  1430. #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
  1431. #define ADC_CR2_SWSTART_Pos (30U)
  1432. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
  1433. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
  1434. /****************** Bit definition for ADC_SMPR1 register *******************/
  1435. #define ADC_SMPR1_SMP10_Pos (0U)
  1436. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  1437. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
  1438. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  1439. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  1440. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  1441. #define ADC_SMPR1_SMP11_Pos (3U)
  1442. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  1443. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
  1444. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  1445. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  1446. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  1447. #define ADC_SMPR1_SMP12_Pos (6U)
  1448. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  1449. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
  1450. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  1451. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  1452. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  1453. #define ADC_SMPR1_SMP13_Pos (9U)
  1454. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  1455. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
  1456. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  1457. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  1458. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  1459. #define ADC_SMPR1_SMP14_Pos (12U)
  1460. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  1461. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
  1462. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  1463. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  1464. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  1465. #define ADC_SMPR1_SMP15_Pos (15U)
  1466. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  1467. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
  1468. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  1469. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  1470. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  1471. #define ADC_SMPR1_SMP16_Pos (18U)
  1472. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  1473. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
  1474. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  1475. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  1476. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  1477. #define ADC_SMPR1_SMP17_Pos (21U)
  1478. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  1479. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
  1480. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  1481. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  1482. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  1483. #define ADC_SMPR1_SMP18_Pos (24U)
  1484. #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
  1485. #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
  1486. #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
  1487. #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
  1488. #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
  1489. /****************** Bit definition for ADC_SMPR2 register *******************/
  1490. #define ADC_SMPR2_SMP0_Pos (0U)
  1491. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  1492. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
  1493. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  1494. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  1495. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  1496. #define ADC_SMPR2_SMP1_Pos (3U)
  1497. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  1498. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
  1499. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  1500. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  1501. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  1502. #define ADC_SMPR2_SMP2_Pos (6U)
  1503. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  1504. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
  1505. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  1506. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  1507. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  1508. #define ADC_SMPR2_SMP3_Pos (9U)
  1509. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  1510. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
  1511. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  1512. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  1513. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  1514. #define ADC_SMPR2_SMP4_Pos (12U)
  1515. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  1516. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
  1517. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  1518. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  1519. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  1520. #define ADC_SMPR2_SMP5_Pos (15U)
  1521. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  1522. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
  1523. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  1524. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  1525. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  1526. #define ADC_SMPR2_SMP6_Pos (18U)
  1527. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  1528. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
  1529. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  1530. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  1531. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  1532. #define ADC_SMPR2_SMP7_Pos (21U)
  1533. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  1534. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
  1535. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  1536. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  1537. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  1538. #define ADC_SMPR2_SMP8_Pos (24U)
  1539. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  1540. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
  1541. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  1542. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  1543. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  1544. #define ADC_SMPR2_SMP9_Pos (27U)
  1545. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  1546. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
  1547. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  1548. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  1549. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  1550. /****************** Bit definition for ADC_JOFR1 register *******************/
  1551. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  1552. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  1553. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
  1554. /****************** Bit definition for ADC_JOFR2 register *******************/
  1555. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  1556. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  1557. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
  1558. /****************** Bit definition for ADC_JOFR3 register *******************/
  1559. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  1560. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  1561. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
  1562. /****************** Bit definition for ADC_JOFR4 register *******************/
  1563. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  1564. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  1565. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
  1566. /******************* Bit definition for ADC_HTR register ********************/
  1567. #define ADC_HTR_HT_Pos (0U)
  1568. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  1569. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
  1570. /******************* Bit definition for ADC_LTR register ********************/
  1571. #define ADC_LTR_LT_Pos (0U)
  1572. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  1573. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
  1574. /******************* Bit definition for ADC_SQR1 register *******************/
  1575. #define ADC_SQR1_SQ13_Pos (0U)
  1576. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  1577. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
  1578. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  1579. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  1580. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  1581. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  1582. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  1583. #define ADC_SQR1_SQ14_Pos (5U)
  1584. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  1585. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
  1586. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  1587. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  1588. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  1589. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  1590. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  1591. #define ADC_SQR1_SQ15_Pos (10U)
  1592. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  1593. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
  1594. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  1595. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  1596. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  1597. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  1598. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  1599. #define ADC_SQR1_SQ16_Pos (15U)
  1600. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  1601. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
  1602. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  1603. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  1604. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  1605. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  1606. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  1607. #define ADC_SQR1_L_Pos (20U)
  1608. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  1609. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
  1610. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  1611. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  1612. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  1613. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  1614. /******************* Bit definition for ADC_SQR2 register *******************/
  1615. #define ADC_SQR2_SQ7_Pos (0U)
  1616. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  1617. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
  1618. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  1619. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  1620. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  1621. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  1622. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  1623. #define ADC_SQR2_SQ8_Pos (5U)
  1624. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  1625. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
  1626. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  1627. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  1628. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  1629. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  1630. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  1631. #define ADC_SQR2_SQ9_Pos (10U)
  1632. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  1633. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
  1634. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  1635. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  1636. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  1637. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  1638. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  1639. #define ADC_SQR2_SQ10_Pos (15U)
  1640. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  1641. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
  1642. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  1643. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  1644. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  1645. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  1646. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  1647. #define ADC_SQR2_SQ11_Pos (20U)
  1648. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  1649. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
  1650. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  1651. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  1652. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  1653. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  1654. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  1655. #define ADC_SQR2_SQ12_Pos (25U)
  1656. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  1657. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
  1658. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  1659. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  1660. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  1661. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  1662. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  1663. /******************* Bit definition for ADC_SQR3 register *******************/
  1664. #define ADC_SQR3_SQ1_Pos (0U)
  1665. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  1666. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
  1667. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  1668. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  1669. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  1670. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  1671. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  1672. #define ADC_SQR3_SQ2_Pos (5U)
  1673. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  1674. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
  1675. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  1676. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  1677. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  1678. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  1679. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  1680. #define ADC_SQR3_SQ3_Pos (10U)
  1681. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  1682. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
  1683. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  1684. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  1685. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  1686. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  1687. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  1688. #define ADC_SQR3_SQ4_Pos (15U)
  1689. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  1690. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
  1691. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  1692. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  1693. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  1694. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  1695. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  1696. #define ADC_SQR3_SQ5_Pos (20U)
  1697. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  1698. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
  1699. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  1700. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  1701. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  1702. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  1703. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  1704. #define ADC_SQR3_SQ6_Pos (25U)
  1705. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  1706. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
  1707. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  1708. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  1709. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  1710. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  1711. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  1712. /******************* Bit definition for ADC_JSQR register *******************/
  1713. #define ADC_JSQR_JSQ1_Pos (0U)
  1714. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  1715. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
  1716. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  1717. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  1718. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  1719. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  1720. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  1721. #define ADC_JSQR_JSQ2_Pos (5U)
  1722. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  1723. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1724. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  1725. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  1726. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  1727. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  1728. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  1729. #define ADC_JSQR_JSQ3_Pos (10U)
  1730. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  1731. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1732. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  1733. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  1734. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  1735. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  1736. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  1737. #define ADC_JSQR_JSQ4_Pos (15U)
  1738. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  1739. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
  1740. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  1741. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  1742. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  1743. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  1744. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  1745. #define ADC_JSQR_JL_Pos (20U)
  1746. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  1747. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
  1748. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  1749. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  1750. /******************* Bit definition for ADC_JDR1 register *******************/
  1751. #define ADC_JDR1_JDATA_Pos (0U)
  1752. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1753. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
  1754. /******************* Bit definition for ADC_JDR2 register *******************/
  1755. #define ADC_JDR2_JDATA_Pos (0U)
  1756. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1757. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
  1758. /******************* Bit definition for ADC_JDR3 register *******************/
  1759. #define ADC_JDR3_JDATA_Pos (0U)
  1760. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1761. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
  1762. /******************* Bit definition for ADC_JDR4 register *******************/
  1763. #define ADC_JDR4_JDATA_Pos (0U)
  1764. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1765. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
  1766. /******************** Bit definition for ADC_DR register ********************/
  1767. #define ADC_DR_DATA_Pos (0U)
  1768. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1769. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
  1770. #define ADC_DR_ADC2DATA_Pos (16U)
  1771. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  1772. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
  1773. /******************* Bit definition for ADC_CSR register ********************/
  1774. #define ADC_CSR_AWD1_Pos (0U)
  1775. #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
  1776. #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
  1777. #define ADC_CSR_EOC1_Pos (1U)
  1778. #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
  1779. #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
  1780. #define ADC_CSR_JEOC1_Pos (2U)
  1781. #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
  1782. #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
  1783. #define ADC_CSR_JSTRT1_Pos (3U)
  1784. #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
  1785. #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
  1786. #define ADC_CSR_STRT1_Pos (4U)
  1787. #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
  1788. #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
  1789. #define ADC_CSR_OVR1_Pos (5U)
  1790. #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
  1791. #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
  1792. #define ADC_CSR_AWD2_Pos (8U)
  1793. #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
  1794. #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
  1795. #define ADC_CSR_EOC2_Pos (9U)
  1796. #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
  1797. #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
  1798. #define ADC_CSR_JEOC2_Pos (10U)
  1799. #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
  1800. #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
  1801. #define ADC_CSR_JSTRT2_Pos (11U)
  1802. #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
  1803. #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
  1804. #define ADC_CSR_STRT2_Pos (12U)
  1805. #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
  1806. #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
  1807. #define ADC_CSR_OVR2_Pos (13U)
  1808. #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
  1809. #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
  1810. #define ADC_CSR_AWD3_Pos (16U)
  1811. #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
  1812. #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
  1813. #define ADC_CSR_EOC3_Pos (17U)
  1814. #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
  1815. #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
  1816. #define ADC_CSR_JEOC3_Pos (18U)
  1817. #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
  1818. #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
  1819. #define ADC_CSR_JSTRT3_Pos (19U)
  1820. #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
  1821. #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
  1822. #define ADC_CSR_STRT3_Pos (20U)
  1823. #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
  1824. #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
  1825. #define ADC_CSR_OVR3_Pos (21U)
  1826. #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
  1827. #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
  1828. /* Legacy defines */
  1829. #define ADC_CSR_DOVR1 ADC_CSR_OVR1
  1830. #define ADC_CSR_DOVR2 ADC_CSR_OVR2
  1831. #define ADC_CSR_DOVR3 ADC_CSR_OVR3
  1832. /******************* Bit definition for ADC_CCR register ********************/
  1833. #define ADC_CCR_MULTI_Pos (0U)
  1834. #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
  1835. #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
  1836. #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
  1837. #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
  1838. #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
  1839. #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
  1840. #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
  1841. #define ADC_CCR_DELAY_Pos (8U)
  1842. #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
  1843. #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
  1844. #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
  1845. #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
  1846. #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
  1847. #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
  1848. #define ADC_CCR_DDS_Pos (13U)
  1849. #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
  1850. #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
  1851. #define ADC_CCR_DMA_Pos (14U)
  1852. #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
  1853. #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
  1854. #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
  1855. #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
  1856. #define ADC_CCR_ADCPRE_Pos (16U)
  1857. #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
  1858. #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
  1859. #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
  1860. #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
  1861. #define ADC_CCR_VBATE_Pos (22U)
  1862. #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
  1863. #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
  1864. #define ADC_CCR_TSVREFE_Pos (23U)
  1865. #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
  1866. #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
  1867. /******************* Bit definition for ADC_CDR register ********************/
  1868. #define ADC_CDR_DATA1_Pos (0U)
  1869. #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
  1870. #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
  1871. #define ADC_CDR_DATA2_Pos (16U)
  1872. #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
  1873. #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
  1874. /* Legacy defines */
  1875. #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
  1876. #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
  1877. /******************************************************************************/
  1878. /* */
  1879. /* Controller Area Network */
  1880. /* */
  1881. /******************************************************************************/
  1882. /*!<CAN control and status registers */
  1883. /******************* Bit definition for CAN_MCR register ********************/
  1884. #define CAN_MCR_INRQ_Pos (0U)
  1885. #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
  1886. #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
  1887. #define CAN_MCR_SLEEP_Pos (1U)
  1888. #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
  1889. #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
  1890. #define CAN_MCR_TXFP_Pos (2U)
  1891. #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
  1892. #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
  1893. #define CAN_MCR_RFLM_Pos (3U)
  1894. #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
  1895. #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
  1896. #define CAN_MCR_NART_Pos (4U)
  1897. #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
  1898. #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
  1899. #define CAN_MCR_AWUM_Pos (5U)
  1900. #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
  1901. #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
  1902. #define CAN_MCR_ABOM_Pos (6U)
  1903. #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
  1904. #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
  1905. #define CAN_MCR_TTCM_Pos (7U)
  1906. #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
  1907. #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
  1908. #define CAN_MCR_RESET_Pos (15U)
  1909. #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
  1910. #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
  1911. #define CAN_MCR_DBF_Pos (16U)
  1912. #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
  1913. #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
  1914. /******************* Bit definition for CAN_MSR register ********************/
  1915. #define CAN_MSR_INAK_Pos (0U)
  1916. #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
  1917. #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
  1918. #define CAN_MSR_SLAK_Pos (1U)
  1919. #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
  1920. #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
  1921. #define CAN_MSR_ERRI_Pos (2U)
  1922. #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
  1923. #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
  1924. #define CAN_MSR_WKUI_Pos (3U)
  1925. #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
  1926. #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
  1927. #define CAN_MSR_SLAKI_Pos (4U)
  1928. #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
  1929. #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
  1930. #define CAN_MSR_TXM_Pos (8U)
  1931. #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
  1932. #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
  1933. #define CAN_MSR_RXM_Pos (9U)
  1934. #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
  1935. #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
  1936. #define CAN_MSR_SAMP_Pos (10U)
  1937. #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
  1938. #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
  1939. #define CAN_MSR_RX_Pos (11U)
  1940. #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
  1941. #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
  1942. /******************* Bit definition for CAN_TSR register ********************/
  1943. #define CAN_TSR_RQCP0_Pos (0U)
  1944. #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
  1945. #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
  1946. #define CAN_TSR_TXOK0_Pos (1U)
  1947. #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
  1948. #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
  1949. #define CAN_TSR_ALST0_Pos (2U)
  1950. #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
  1951. #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
  1952. #define CAN_TSR_TERR0_Pos (3U)
  1953. #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
  1954. #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
  1955. #define CAN_TSR_ABRQ0_Pos (7U)
  1956. #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
  1957. #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
  1958. #define CAN_TSR_RQCP1_Pos (8U)
  1959. #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
  1960. #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
  1961. #define CAN_TSR_TXOK1_Pos (9U)
  1962. #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
  1963. #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
  1964. #define CAN_TSR_ALST1_Pos (10U)
  1965. #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
  1966. #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
  1967. #define CAN_TSR_TERR1_Pos (11U)
  1968. #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
  1969. #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
  1970. #define CAN_TSR_ABRQ1_Pos (15U)
  1971. #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
  1972. #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
  1973. #define CAN_TSR_RQCP2_Pos (16U)
  1974. #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
  1975. #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
  1976. #define CAN_TSR_TXOK2_Pos (17U)
  1977. #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
  1978. #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
  1979. #define CAN_TSR_ALST2_Pos (18U)
  1980. #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
  1981. #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
  1982. #define CAN_TSR_TERR2_Pos (19U)
  1983. #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
  1984. #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
  1985. #define CAN_TSR_ABRQ2_Pos (23U)
  1986. #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
  1987. #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
  1988. #define CAN_TSR_CODE_Pos (24U)
  1989. #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
  1990. #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
  1991. #define CAN_TSR_TME_Pos (26U)
  1992. #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
  1993. #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
  1994. #define CAN_TSR_TME0_Pos (26U)
  1995. #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
  1996. #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
  1997. #define CAN_TSR_TME1_Pos (27U)
  1998. #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
  1999. #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
  2000. #define CAN_TSR_TME2_Pos (28U)
  2001. #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
  2002. #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
  2003. #define CAN_TSR_LOW_Pos (29U)
  2004. #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
  2005. #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
  2006. #define CAN_TSR_LOW0_Pos (29U)
  2007. #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
  2008. #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
  2009. #define CAN_TSR_LOW1_Pos (30U)
  2010. #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
  2011. #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
  2012. #define CAN_TSR_LOW2_Pos (31U)
  2013. #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
  2014. #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
  2015. /******************* Bit definition for CAN_RF0R register *******************/
  2016. #define CAN_RF0R_FMP0_Pos (0U)
  2017. #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
  2018. #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
  2019. #define CAN_RF0R_FULL0_Pos (3U)
  2020. #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
  2021. #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
  2022. #define CAN_RF0R_FOVR0_Pos (4U)
  2023. #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
  2024. #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
  2025. #define CAN_RF0R_RFOM0_Pos (5U)
  2026. #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
  2027. #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
  2028. /******************* Bit definition for CAN_RF1R register *******************/
  2029. #define CAN_RF1R_FMP1_Pos (0U)
  2030. #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
  2031. #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
  2032. #define CAN_RF1R_FULL1_Pos (3U)
  2033. #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
  2034. #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
  2035. #define CAN_RF1R_FOVR1_Pos (4U)
  2036. #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
  2037. #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
  2038. #define CAN_RF1R_RFOM1_Pos (5U)
  2039. #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
  2040. #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
  2041. /******************** Bit definition for CAN_IER register *******************/
  2042. #define CAN_IER_TMEIE_Pos (0U)
  2043. #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
  2044. #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
  2045. #define CAN_IER_FMPIE0_Pos (1U)
  2046. #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
  2047. #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
  2048. #define CAN_IER_FFIE0_Pos (2U)
  2049. #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
  2050. #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
  2051. #define CAN_IER_FOVIE0_Pos (3U)
  2052. #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
  2053. #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
  2054. #define CAN_IER_FMPIE1_Pos (4U)
  2055. #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
  2056. #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
  2057. #define CAN_IER_FFIE1_Pos (5U)
  2058. #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
  2059. #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
  2060. #define CAN_IER_FOVIE1_Pos (6U)
  2061. #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
  2062. #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
  2063. #define CAN_IER_EWGIE_Pos (8U)
  2064. #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
  2065. #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
  2066. #define CAN_IER_EPVIE_Pos (9U)
  2067. #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
  2068. #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
  2069. #define CAN_IER_BOFIE_Pos (10U)
  2070. #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
  2071. #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
  2072. #define CAN_IER_LECIE_Pos (11U)
  2073. #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
  2074. #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
  2075. #define CAN_IER_ERRIE_Pos (15U)
  2076. #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
  2077. #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
  2078. #define CAN_IER_WKUIE_Pos (16U)
  2079. #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
  2080. #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
  2081. #define CAN_IER_SLKIE_Pos (17U)
  2082. #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
  2083. #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
  2084. #define CAN_IER_EWGIE_Pos (8U)
  2085. /******************** Bit definition for CAN_ESR register *******************/
  2086. #define CAN_ESR_EWGF_Pos (0U)
  2087. #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
  2088. #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
  2089. #define CAN_ESR_EPVF_Pos (1U)
  2090. #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
  2091. #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
  2092. #define CAN_ESR_BOFF_Pos (2U)
  2093. #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
  2094. #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
  2095. #define CAN_ESR_LEC_Pos (4U)
  2096. #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
  2097. #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
  2098. #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
  2099. #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
  2100. #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
  2101. #define CAN_ESR_TEC_Pos (16U)
  2102. #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
  2103. #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
  2104. #define CAN_ESR_REC_Pos (24U)
  2105. #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
  2106. #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
  2107. /******************* Bit definition for CAN_BTR register ********************/
  2108. #define CAN_BTR_BRP_Pos (0U)
  2109. #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
  2110. #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
  2111. #define CAN_BTR_TS1_Pos (16U)
  2112. #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
  2113. #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
  2114. #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
  2115. #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
  2116. #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
  2117. #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
  2118. #define CAN_BTR_TS2_Pos (20U)
  2119. #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
  2120. #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
  2121. #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
  2122. #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
  2123. #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
  2124. #define CAN_BTR_SJW_Pos (24U)
  2125. #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
  2126. #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
  2127. #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
  2128. #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
  2129. #define CAN_BTR_LBKM_Pos (30U)
  2130. #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
  2131. #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
  2132. #define CAN_BTR_SILM_Pos (31U)
  2133. #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
  2134. #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
  2135. /*!<Mailbox registers */
  2136. /****************** Bit definition for CAN_TI0R register ********************/
  2137. #define CAN_TI0R_TXRQ_Pos (0U)
  2138. #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
  2139. #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2140. #define CAN_TI0R_RTR_Pos (1U)
  2141. #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
  2142. #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
  2143. #define CAN_TI0R_IDE_Pos (2U)
  2144. #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
  2145. #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
  2146. #define CAN_TI0R_EXID_Pos (3U)
  2147. #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2148. #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
  2149. #define CAN_TI0R_STID_Pos (21U)
  2150. #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
  2151. #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2152. /****************** Bit definition for CAN_TDT0R register *******************/
  2153. #define CAN_TDT0R_DLC_Pos (0U)
  2154. #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
  2155. #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
  2156. #define CAN_TDT0R_TGT_Pos (8U)
  2157. #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
  2158. #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
  2159. #define CAN_TDT0R_TIME_Pos (16U)
  2160. #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2161. #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
  2162. /****************** Bit definition for CAN_TDL0R register *******************/
  2163. #define CAN_TDL0R_DATA0_Pos (0U)
  2164. #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
  2165. #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
  2166. #define CAN_TDL0R_DATA1_Pos (8U)
  2167. #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2168. #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
  2169. #define CAN_TDL0R_DATA2_Pos (16U)
  2170. #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2171. #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
  2172. #define CAN_TDL0R_DATA3_Pos (24U)
  2173. #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2174. #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
  2175. /****************** Bit definition for CAN_TDH0R register *******************/
  2176. #define CAN_TDH0R_DATA4_Pos (0U)
  2177. #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
  2178. #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
  2179. #define CAN_TDH0R_DATA5_Pos (8U)
  2180. #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2181. #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
  2182. #define CAN_TDH0R_DATA6_Pos (16U)
  2183. #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2184. #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
  2185. #define CAN_TDH0R_DATA7_Pos (24U)
  2186. #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2187. #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
  2188. /******************* Bit definition for CAN_TI1R register *******************/
  2189. #define CAN_TI1R_TXRQ_Pos (0U)
  2190. #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
  2191. #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2192. #define CAN_TI1R_RTR_Pos (1U)
  2193. #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
  2194. #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
  2195. #define CAN_TI1R_IDE_Pos (2U)
  2196. #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
  2197. #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
  2198. #define CAN_TI1R_EXID_Pos (3U)
  2199. #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2200. #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
  2201. #define CAN_TI1R_STID_Pos (21U)
  2202. #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
  2203. #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2204. /******************* Bit definition for CAN_TDT1R register ******************/
  2205. #define CAN_TDT1R_DLC_Pos (0U)
  2206. #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
  2207. #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
  2208. #define CAN_TDT1R_TGT_Pos (8U)
  2209. #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
  2210. #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
  2211. #define CAN_TDT1R_TIME_Pos (16U)
  2212. #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2213. #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
  2214. /******************* Bit definition for CAN_TDL1R register ******************/
  2215. #define CAN_TDL1R_DATA0_Pos (0U)
  2216. #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
  2217. #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
  2218. #define CAN_TDL1R_DATA1_Pos (8U)
  2219. #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2220. #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
  2221. #define CAN_TDL1R_DATA2_Pos (16U)
  2222. #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2223. #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
  2224. #define CAN_TDL1R_DATA3_Pos (24U)
  2225. #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2226. #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
  2227. /******************* Bit definition for CAN_TDH1R register ******************/
  2228. #define CAN_TDH1R_DATA4_Pos (0U)
  2229. #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
  2230. #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
  2231. #define CAN_TDH1R_DATA5_Pos (8U)
  2232. #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2233. #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
  2234. #define CAN_TDH1R_DATA6_Pos (16U)
  2235. #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2236. #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
  2237. #define CAN_TDH1R_DATA7_Pos (24U)
  2238. #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2239. #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
  2240. /******************* Bit definition for CAN_TI2R register *******************/
  2241. #define CAN_TI2R_TXRQ_Pos (0U)
  2242. #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
  2243. #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2244. #define CAN_TI2R_RTR_Pos (1U)
  2245. #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
  2246. #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
  2247. #define CAN_TI2R_IDE_Pos (2U)
  2248. #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
  2249. #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
  2250. #define CAN_TI2R_EXID_Pos (3U)
  2251. #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
  2252. #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
  2253. #define CAN_TI2R_STID_Pos (21U)
  2254. #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
  2255. #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2256. /******************* Bit definition for CAN_TDT2R register ******************/
  2257. #define CAN_TDT2R_DLC_Pos (0U)
  2258. #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
  2259. #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
  2260. #define CAN_TDT2R_TGT_Pos (8U)
  2261. #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
  2262. #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
  2263. #define CAN_TDT2R_TIME_Pos (16U)
  2264. #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
  2265. #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
  2266. /******************* Bit definition for CAN_TDL2R register ******************/
  2267. #define CAN_TDL2R_DATA0_Pos (0U)
  2268. #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
  2269. #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
  2270. #define CAN_TDL2R_DATA1_Pos (8U)
  2271. #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
  2272. #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
  2273. #define CAN_TDL2R_DATA2_Pos (16U)
  2274. #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
  2275. #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
  2276. #define CAN_TDL2R_DATA3_Pos (24U)
  2277. #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
  2278. #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
  2279. /******************* Bit definition for CAN_TDH2R register ******************/
  2280. #define CAN_TDH2R_DATA4_Pos (0U)
  2281. #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
  2282. #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
  2283. #define CAN_TDH2R_DATA5_Pos (8U)
  2284. #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
  2285. #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
  2286. #define CAN_TDH2R_DATA6_Pos (16U)
  2287. #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
  2288. #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
  2289. #define CAN_TDH2R_DATA7_Pos (24U)
  2290. #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
  2291. #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
  2292. /******************* Bit definition for CAN_RI0R register *******************/
  2293. #define CAN_RI0R_RTR_Pos (1U)
  2294. #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
  2295. #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
  2296. #define CAN_RI0R_IDE_Pos (2U)
  2297. #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
  2298. #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
  2299. #define CAN_RI0R_EXID_Pos (3U)
  2300. #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2301. #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
  2302. #define CAN_RI0R_STID_Pos (21U)
  2303. #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
  2304. #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2305. /******************* Bit definition for CAN_RDT0R register ******************/
  2306. #define CAN_RDT0R_DLC_Pos (0U)
  2307. #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
  2308. #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
  2309. #define CAN_RDT0R_FMI_Pos (8U)
  2310. #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
  2311. #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
  2312. #define CAN_RDT0R_TIME_Pos (16U)
  2313. #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2314. #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
  2315. /******************* Bit definition for CAN_RDL0R register ******************/
  2316. #define CAN_RDL0R_DATA0_Pos (0U)
  2317. #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
  2318. #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
  2319. #define CAN_RDL0R_DATA1_Pos (8U)
  2320. #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2321. #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
  2322. #define CAN_RDL0R_DATA2_Pos (16U)
  2323. #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2324. #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
  2325. #define CAN_RDL0R_DATA3_Pos (24U)
  2326. #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2327. #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
  2328. /******************* Bit definition for CAN_RDH0R register ******************/
  2329. #define CAN_RDH0R_DATA4_Pos (0U)
  2330. #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
  2331. #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
  2332. #define CAN_RDH0R_DATA5_Pos (8U)
  2333. #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2334. #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
  2335. #define CAN_RDH0R_DATA6_Pos (16U)
  2336. #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2337. #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
  2338. #define CAN_RDH0R_DATA7_Pos (24U)
  2339. #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2340. #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
  2341. /******************* Bit definition for CAN_RI1R register *******************/
  2342. #define CAN_RI1R_RTR_Pos (1U)
  2343. #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
  2344. #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
  2345. #define CAN_RI1R_IDE_Pos (2U)
  2346. #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
  2347. #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
  2348. #define CAN_RI1R_EXID_Pos (3U)
  2349. #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2350. #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
  2351. #define CAN_RI1R_STID_Pos (21U)
  2352. #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
  2353. #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2354. /******************* Bit definition for CAN_RDT1R register ******************/
  2355. #define CAN_RDT1R_DLC_Pos (0U)
  2356. #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
  2357. #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
  2358. #define CAN_RDT1R_FMI_Pos (8U)
  2359. #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
  2360. #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
  2361. #define CAN_RDT1R_TIME_Pos (16U)
  2362. #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2363. #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
  2364. /******************* Bit definition for CAN_RDL1R register ******************/
  2365. #define CAN_RDL1R_DATA0_Pos (0U)
  2366. #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
  2367. #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
  2368. #define CAN_RDL1R_DATA1_Pos (8U)
  2369. #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2370. #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
  2371. #define CAN_RDL1R_DATA2_Pos (16U)
  2372. #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2373. #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
  2374. #define CAN_RDL1R_DATA3_Pos (24U)
  2375. #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2376. #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
  2377. /******************* Bit definition for CAN_RDH1R register ******************/
  2378. #define CAN_RDH1R_DATA4_Pos (0U)
  2379. #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
  2380. #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
  2381. #define CAN_RDH1R_DATA5_Pos (8U)
  2382. #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2383. #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
  2384. #define CAN_RDH1R_DATA6_Pos (16U)
  2385. #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2386. #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
  2387. #define CAN_RDH1R_DATA7_Pos (24U)
  2388. #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2389. #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
  2390. /*!<CAN filter registers */
  2391. /******************* Bit definition for CAN_FMR register ********************/
  2392. #define CAN_FMR_FINIT_Pos (0U)
  2393. #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
  2394. #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
  2395. #define CAN_FMR_CAN2SB_Pos (8U)
  2396. #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
  2397. #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
  2398. /******************* Bit definition for CAN_FM1R register *******************/
  2399. #define CAN_FM1R_FBM_Pos (0U)
  2400. #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
  2401. #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
  2402. #define CAN_FM1R_FBM0_Pos (0U)
  2403. #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
  2404. #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
  2405. #define CAN_FM1R_FBM1_Pos (1U)
  2406. #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
  2407. #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
  2408. #define CAN_FM1R_FBM2_Pos (2U)
  2409. #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
  2410. #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
  2411. #define CAN_FM1R_FBM3_Pos (3U)
  2412. #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
  2413. #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
  2414. #define CAN_FM1R_FBM4_Pos (4U)
  2415. #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
  2416. #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
  2417. #define CAN_FM1R_FBM5_Pos (5U)
  2418. #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
  2419. #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
  2420. #define CAN_FM1R_FBM6_Pos (6U)
  2421. #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
  2422. #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
  2423. #define CAN_FM1R_FBM7_Pos (7U)
  2424. #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
  2425. #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
  2426. #define CAN_FM1R_FBM8_Pos (8U)
  2427. #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
  2428. #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
  2429. #define CAN_FM1R_FBM9_Pos (9U)
  2430. #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
  2431. #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
  2432. #define CAN_FM1R_FBM10_Pos (10U)
  2433. #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
  2434. #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
  2435. #define CAN_FM1R_FBM11_Pos (11U)
  2436. #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
  2437. #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
  2438. #define CAN_FM1R_FBM12_Pos (12U)
  2439. #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
  2440. #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
  2441. #define CAN_FM1R_FBM13_Pos (13U)
  2442. #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
  2443. #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
  2444. #define CAN_FM1R_FBM14_Pos (14U)
  2445. #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
  2446. #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
  2447. #define CAN_FM1R_FBM15_Pos (15U)
  2448. #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
  2449. #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
  2450. #define CAN_FM1R_FBM16_Pos (16U)
  2451. #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
  2452. #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
  2453. #define CAN_FM1R_FBM17_Pos (17U)
  2454. #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
  2455. #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
  2456. #define CAN_FM1R_FBM18_Pos (18U)
  2457. #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
  2458. #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
  2459. #define CAN_FM1R_FBM19_Pos (19U)
  2460. #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
  2461. #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
  2462. #define CAN_FM1R_FBM20_Pos (20U)
  2463. #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
  2464. #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
  2465. #define CAN_FM1R_FBM21_Pos (21U)
  2466. #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
  2467. #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
  2468. #define CAN_FM1R_FBM22_Pos (22U)
  2469. #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
  2470. #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
  2471. #define CAN_FM1R_FBM23_Pos (23U)
  2472. #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
  2473. #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
  2474. #define CAN_FM1R_FBM24_Pos (24U)
  2475. #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
  2476. #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
  2477. #define CAN_FM1R_FBM25_Pos (25U)
  2478. #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
  2479. #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
  2480. #define CAN_FM1R_FBM26_Pos (26U)
  2481. #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
  2482. #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
  2483. #define CAN_FM1R_FBM27_Pos (27U)
  2484. #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
  2485. #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
  2486. /******************* Bit definition for CAN_FS1R register *******************/
  2487. #define CAN_FS1R_FSC_Pos (0U)
  2488. #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
  2489. #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
  2490. #define CAN_FS1R_FSC0_Pos (0U)
  2491. #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
  2492. #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
  2493. #define CAN_FS1R_FSC1_Pos (1U)
  2494. #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
  2495. #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
  2496. #define CAN_FS1R_FSC2_Pos (2U)
  2497. #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
  2498. #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
  2499. #define CAN_FS1R_FSC3_Pos (3U)
  2500. #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
  2501. #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
  2502. #define CAN_FS1R_FSC4_Pos (4U)
  2503. #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
  2504. #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
  2505. #define CAN_FS1R_FSC5_Pos (5U)
  2506. #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
  2507. #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
  2508. #define CAN_FS1R_FSC6_Pos (6U)
  2509. #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
  2510. #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
  2511. #define CAN_FS1R_FSC7_Pos (7U)
  2512. #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
  2513. #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
  2514. #define CAN_FS1R_FSC8_Pos (8U)
  2515. #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
  2516. #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
  2517. #define CAN_FS1R_FSC9_Pos (9U)
  2518. #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
  2519. #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
  2520. #define CAN_FS1R_FSC10_Pos (10U)
  2521. #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
  2522. #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
  2523. #define CAN_FS1R_FSC11_Pos (11U)
  2524. #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
  2525. #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
  2526. #define CAN_FS1R_FSC12_Pos (12U)
  2527. #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
  2528. #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
  2529. #define CAN_FS1R_FSC13_Pos (13U)
  2530. #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
  2531. #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
  2532. #define CAN_FS1R_FSC14_Pos (14U)
  2533. #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
  2534. #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
  2535. #define CAN_FS1R_FSC15_Pos (15U)
  2536. #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
  2537. #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
  2538. #define CAN_FS1R_FSC16_Pos (16U)
  2539. #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
  2540. #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
  2541. #define CAN_FS1R_FSC17_Pos (17U)
  2542. #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
  2543. #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
  2544. #define CAN_FS1R_FSC18_Pos (18U)
  2545. #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
  2546. #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
  2547. #define CAN_FS1R_FSC19_Pos (19U)
  2548. #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
  2549. #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
  2550. #define CAN_FS1R_FSC20_Pos (20U)
  2551. #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
  2552. #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
  2553. #define CAN_FS1R_FSC21_Pos (21U)
  2554. #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
  2555. #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
  2556. #define CAN_FS1R_FSC22_Pos (22U)
  2557. #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
  2558. #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
  2559. #define CAN_FS1R_FSC23_Pos (23U)
  2560. #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
  2561. #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
  2562. #define CAN_FS1R_FSC24_Pos (24U)
  2563. #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
  2564. #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
  2565. #define CAN_FS1R_FSC25_Pos (25U)
  2566. #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
  2567. #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
  2568. #define CAN_FS1R_FSC26_Pos (26U)
  2569. #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
  2570. #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
  2571. #define CAN_FS1R_FSC27_Pos (27U)
  2572. #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
  2573. #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
  2574. /****************** Bit definition for CAN_FFA1R register *******************/
  2575. #define CAN_FFA1R_FFA_Pos (0U)
  2576. #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
  2577. #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
  2578. #define CAN_FFA1R_FFA0_Pos (0U)
  2579. #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
  2580. #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
  2581. #define CAN_FFA1R_FFA1_Pos (1U)
  2582. #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
  2583. #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
  2584. #define CAN_FFA1R_FFA2_Pos (2U)
  2585. #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
  2586. #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
  2587. #define CAN_FFA1R_FFA3_Pos (3U)
  2588. #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
  2589. #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
  2590. #define CAN_FFA1R_FFA4_Pos (4U)
  2591. #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
  2592. #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
  2593. #define CAN_FFA1R_FFA5_Pos (5U)
  2594. #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
  2595. #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
  2596. #define CAN_FFA1R_FFA6_Pos (6U)
  2597. #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
  2598. #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
  2599. #define CAN_FFA1R_FFA7_Pos (7U)
  2600. #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
  2601. #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
  2602. #define CAN_FFA1R_FFA8_Pos (8U)
  2603. #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
  2604. #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
  2605. #define CAN_FFA1R_FFA9_Pos (9U)
  2606. #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
  2607. #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
  2608. #define CAN_FFA1R_FFA10_Pos (10U)
  2609. #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
  2610. #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
  2611. #define CAN_FFA1R_FFA11_Pos (11U)
  2612. #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
  2613. #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
  2614. #define CAN_FFA1R_FFA12_Pos (12U)
  2615. #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
  2616. #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
  2617. #define CAN_FFA1R_FFA13_Pos (13U)
  2618. #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
  2619. #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
  2620. #define CAN_FFA1R_FFA14_Pos (14U)
  2621. #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
  2622. #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
  2623. #define CAN_FFA1R_FFA15_Pos (15U)
  2624. #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
  2625. #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
  2626. #define CAN_FFA1R_FFA16_Pos (16U)
  2627. #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
  2628. #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
  2629. #define CAN_FFA1R_FFA17_Pos (17U)
  2630. #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
  2631. #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
  2632. #define CAN_FFA1R_FFA18_Pos (18U)
  2633. #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
  2634. #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
  2635. #define CAN_FFA1R_FFA19_Pos (19U)
  2636. #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
  2637. #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
  2638. #define CAN_FFA1R_FFA20_Pos (20U)
  2639. #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
  2640. #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
  2641. #define CAN_FFA1R_FFA21_Pos (21U)
  2642. #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
  2643. #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
  2644. #define CAN_FFA1R_FFA22_Pos (22U)
  2645. #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
  2646. #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
  2647. #define CAN_FFA1R_FFA23_Pos (23U)
  2648. #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
  2649. #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
  2650. #define CAN_FFA1R_FFA24_Pos (24U)
  2651. #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
  2652. #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
  2653. #define CAN_FFA1R_FFA25_Pos (25U)
  2654. #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
  2655. #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
  2656. #define CAN_FFA1R_FFA26_Pos (26U)
  2657. #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
  2658. #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
  2659. #define CAN_FFA1R_FFA27_Pos (27U)
  2660. #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
  2661. #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
  2662. /******************* Bit definition for CAN_FA1R register *******************/
  2663. #define CAN_FA1R_FACT_Pos (0U)
  2664. #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
  2665. #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
  2666. #define CAN_FA1R_FACT0_Pos (0U)
  2667. #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
  2668. #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
  2669. #define CAN_FA1R_FACT1_Pos (1U)
  2670. #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
  2671. #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
  2672. #define CAN_FA1R_FACT2_Pos (2U)
  2673. #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
  2674. #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
  2675. #define CAN_FA1R_FACT3_Pos (3U)
  2676. #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
  2677. #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
  2678. #define CAN_FA1R_FACT4_Pos (4U)
  2679. #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
  2680. #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
  2681. #define CAN_FA1R_FACT5_Pos (5U)
  2682. #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
  2683. #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
  2684. #define CAN_FA1R_FACT6_Pos (6U)
  2685. #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
  2686. #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
  2687. #define CAN_FA1R_FACT7_Pos (7U)
  2688. #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
  2689. #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
  2690. #define CAN_FA1R_FACT8_Pos (8U)
  2691. #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
  2692. #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
  2693. #define CAN_FA1R_FACT9_Pos (9U)
  2694. #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
  2695. #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
  2696. #define CAN_FA1R_FACT10_Pos (10U)
  2697. #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
  2698. #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
  2699. #define CAN_FA1R_FACT11_Pos (11U)
  2700. #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
  2701. #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
  2702. #define CAN_FA1R_FACT12_Pos (12U)
  2703. #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
  2704. #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
  2705. #define CAN_FA1R_FACT13_Pos (13U)
  2706. #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
  2707. #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
  2708. #define CAN_FA1R_FACT14_Pos (14U)
  2709. #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
  2710. #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
  2711. #define CAN_FA1R_FACT15_Pos (15U)
  2712. #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
  2713. #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
  2714. #define CAN_FA1R_FACT16_Pos (16U)
  2715. #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
  2716. #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
  2717. #define CAN_FA1R_FACT17_Pos (17U)
  2718. #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
  2719. #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
  2720. #define CAN_FA1R_FACT18_Pos (18U)
  2721. #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
  2722. #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
  2723. #define CAN_FA1R_FACT19_Pos (19U)
  2724. #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
  2725. #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
  2726. #define CAN_FA1R_FACT20_Pos (20U)
  2727. #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
  2728. #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
  2729. #define CAN_FA1R_FACT21_Pos (21U)
  2730. #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
  2731. #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
  2732. #define CAN_FA1R_FACT22_Pos (22U)
  2733. #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
  2734. #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
  2735. #define CAN_FA1R_FACT23_Pos (23U)
  2736. #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
  2737. #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
  2738. #define CAN_FA1R_FACT24_Pos (24U)
  2739. #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
  2740. #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
  2741. #define CAN_FA1R_FACT25_Pos (25U)
  2742. #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
  2743. #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
  2744. #define CAN_FA1R_FACT26_Pos (26U)
  2745. #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
  2746. #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
  2747. #define CAN_FA1R_FACT27_Pos (27U)
  2748. #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
  2749. #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
  2750. /******************* Bit definition for CAN_F0R1 register *******************/
  2751. #define CAN_F0R1_FB0_Pos (0U)
  2752. #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
  2753. #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
  2754. #define CAN_F0R1_FB1_Pos (1U)
  2755. #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
  2756. #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
  2757. #define CAN_F0R1_FB2_Pos (2U)
  2758. #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
  2759. #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
  2760. #define CAN_F0R1_FB3_Pos (3U)
  2761. #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
  2762. #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
  2763. #define CAN_F0R1_FB4_Pos (4U)
  2764. #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
  2765. #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
  2766. #define CAN_F0R1_FB5_Pos (5U)
  2767. #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
  2768. #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
  2769. #define CAN_F0R1_FB6_Pos (6U)
  2770. #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
  2771. #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
  2772. #define CAN_F0R1_FB7_Pos (7U)
  2773. #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
  2774. #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
  2775. #define CAN_F0R1_FB8_Pos (8U)
  2776. #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
  2777. #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
  2778. #define CAN_F0R1_FB9_Pos (9U)
  2779. #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
  2780. #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
  2781. #define CAN_F0R1_FB10_Pos (10U)
  2782. #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
  2783. #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
  2784. #define CAN_F0R1_FB11_Pos (11U)
  2785. #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
  2786. #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
  2787. #define CAN_F0R1_FB12_Pos (12U)
  2788. #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
  2789. #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
  2790. #define CAN_F0R1_FB13_Pos (13U)
  2791. #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
  2792. #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
  2793. #define CAN_F0R1_FB14_Pos (14U)
  2794. #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
  2795. #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
  2796. #define CAN_F0R1_FB15_Pos (15U)
  2797. #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
  2798. #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
  2799. #define CAN_F0R1_FB16_Pos (16U)
  2800. #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
  2801. #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
  2802. #define CAN_F0R1_FB17_Pos (17U)
  2803. #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
  2804. #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
  2805. #define CAN_F0R1_FB18_Pos (18U)
  2806. #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
  2807. #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
  2808. #define CAN_F0R1_FB19_Pos (19U)
  2809. #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
  2810. #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
  2811. #define CAN_F0R1_FB20_Pos (20U)
  2812. #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
  2813. #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
  2814. #define CAN_F0R1_FB21_Pos (21U)
  2815. #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
  2816. #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
  2817. #define CAN_F0R1_FB22_Pos (22U)
  2818. #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
  2819. #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
  2820. #define CAN_F0R1_FB23_Pos (23U)
  2821. #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
  2822. #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
  2823. #define CAN_F0R1_FB24_Pos (24U)
  2824. #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
  2825. #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
  2826. #define CAN_F0R1_FB25_Pos (25U)
  2827. #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
  2828. #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
  2829. #define CAN_F0R1_FB26_Pos (26U)
  2830. #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
  2831. #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
  2832. #define CAN_F0R1_FB27_Pos (27U)
  2833. #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
  2834. #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
  2835. #define CAN_F0R1_FB28_Pos (28U)
  2836. #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
  2837. #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
  2838. #define CAN_F0R1_FB29_Pos (29U)
  2839. #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
  2840. #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
  2841. #define CAN_F0R1_FB30_Pos (30U)
  2842. #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
  2843. #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
  2844. #define CAN_F0R1_FB31_Pos (31U)
  2845. #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
  2846. #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
  2847. /******************* Bit definition for CAN_F1R1 register *******************/
  2848. #define CAN_F1R1_FB0_Pos (0U)
  2849. #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
  2850. #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
  2851. #define CAN_F1R1_FB1_Pos (1U)
  2852. #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
  2853. #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
  2854. #define CAN_F1R1_FB2_Pos (2U)
  2855. #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
  2856. #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
  2857. #define CAN_F1R1_FB3_Pos (3U)
  2858. #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
  2859. #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
  2860. #define CAN_F1R1_FB4_Pos (4U)
  2861. #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
  2862. #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
  2863. #define CAN_F1R1_FB5_Pos (5U)
  2864. #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
  2865. #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
  2866. #define CAN_F1R1_FB6_Pos (6U)
  2867. #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
  2868. #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
  2869. #define CAN_F1R1_FB7_Pos (7U)
  2870. #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
  2871. #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
  2872. #define CAN_F1R1_FB8_Pos (8U)
  2873. #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
  2874. #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
  2875. #define CAN_F1R1_FB9_Pos (9U)
  2876. #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
  2877. #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
  2878. #define CAN_F1R1_FB10_Pos (10U)
  2879. #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
  2880. #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
  2881. #define CAN_F1R1_FB11_Pos (11U)
  2882. #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
  2883. #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
  2884. #define CAN_F1R1_FB12_Pos (12U)
  2885. #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
  2886. #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
  2887. #define CAN_F1R1_FB13_Pos (13U)
  2888. #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
  2889. #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
  2890. #define CAN_F1R1_FB14_Pos (14U)
  2891. #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
  2892. #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
  2893. #define CAN_F1R1_FB15_Pos (15U)
  2894. #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
  2895. #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
  2896. #define CAN_F1R1_FB16_Pos (16U)
  2897. #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
  2898. #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
  2899. #define CAN_F1R1_FB17_Pos (17U)
  2900. #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
  2901. #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
  2902. #define CAN_F1R1_FB18_Pos (18U)
  2903. #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
  2904. #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
  2905. #define CAN_F1R1_FB19_Pos (19U)
  2906. #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
  2907. #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
  2908. #define CAN_F1R1_FB20_Pos (20U)
  2909. #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
  2910. #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
  2911. #define CAN_F1R1_FB21_Pos (21U)
  2912. #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
  2913. #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
  2914. #define CAN_F1R1_FB22_Pos (22U)
  2915. #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
  2916. #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
  2917. #define CAN_F1R1_FB23_Pos (23U)
  2918. #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
  2919. #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
  2920. #define CAN_F1R1_FB24_Pos (24U)
  2921. #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
  2922. #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
  2923. #define CAN_F1R1_FB25_Pos (25U)
  2924. #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
  2925. #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
  2926. #define CAN_F1R1_FB26_Pos (26U)
  2927. #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
  2928. #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
  2929. #define CAN_F1R1_FB27_Pos (27U)
  2930. #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
  2931. #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
  2932. #define CAN_F1R1_FB28_Pos (28U)
  2933. #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
  2934. #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
  2935. #define CAN_F1R1_FB29_Pos (29U)
  2936. #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
  2937. #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
  2938. #define CAN_F1R1_FB30_Pos (30U)
  2939. #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
  2940. #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
  2941. #define CAN_F1R1_FB31_Pos (31U)
  2942. #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
  2943. #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
  2944. /******************* Bit definition for CAN_F2R1 register *******************/
  2945. #define CAN_F2R1_FB0_Pos (0U)
  2946. #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
  2947. #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
  2948. #define CAN_F2R1_FB1_Pos (1U)
  2949. #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
  2950. #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
  2951. #define CAN_F2R1_FB2_Pos (2U)
  2952. #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
  2953. #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
  2954. #define CAN_F2R1_FB3_Pos (3U)
  2955. #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
  2956. #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
  2957. #define CAN_F2R1_FB4_Pos (4U)
  2958. #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
  2959. #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
  2960. #define CAN_F2R1_FB5_Pos (5U)
  2961. #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
  2962. #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
  2963. #define CAN_F2R1_FB6_Pos (6U)
  2964. #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
  2965. #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
  2966. #define CAN_F2R1_FB7_Pos (7U)
  2967. #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
  2968. #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
  2969. #define CAN_F2R1_FB8_Pos (8U)
  2970. #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
  2971. #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
  2972. #define CAN_F2R1_FB9_Pos (9U)
  2973. #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
  2974. #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
  2975. #define CAN_F2R1_FB10_Pos (10U)
  2976. #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
  2977. #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
  2978. #define CAN_F2R1_FB11_Pos (11U)
  2979. #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
  2980. #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
  2981. #define CAN_F2R1_FB12_Pos (12U)
  2982. #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
  2983. #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
  2984. #define CAN_F2R1_FB13_Pos (13U)
  2985. #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
  2986. #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
  2987. #define CAN_F2R1_FB14_Pos (14U)
  2988. #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
  2989. #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
  2990. #define CAN_F2R1_FB15_Pos (15U)
  2991. #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
  2992. #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
  2993. #define CAN_F2R1_FB16_Pos (16U)
  2994. #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
  2995. #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
  2996. #define CAN_F2R1_FB17_Pos (17U)
  2997. #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
  2998. #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
  2999. #define CAN_F2R1_FB18_Pos (18U)
  3000. #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
  3001. #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
  3002. #define CAN_F2R1_FB19_Pos (19U)
  3003. #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
  3004. #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
  3005. #define CAN_F2R1_FB20_Pos (20U)
  3006. #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
  3007. #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
  3008. #define CAN_F2R1_FB21_Pos (21U)
  3009. #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
  3010. #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
  3011. #define CAN_F2R1_FB22_Pos (22U)
  3012. #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
  3013. #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
  3014. #define CAN_F2R1_FB23_Pos (23U)
  3015. #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
  3016. #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
  3017. #define CAN_F2R1_FB24_Pos (24U)
  3018. #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
  3019. #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
  3020. #define CAN_F2R1_FB25_Pos (25U)
  3021. #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
  3022. #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
  3023. #define CAN_F2R1_FB26_Pos (26U)
  3024. #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
  3025. #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
  3026. #define CAN_F2R1_FB27_Pos (27U)
  3027. #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
  3028. #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
  3029. #define CAN_F2R1_FB28_Pos (28U)
  3030. #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
  3031. #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
  3032. #define CAN_F2R1_FB29_Pos (29U)
  3033. #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
  3034. #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
  3035. #define CAN_F2R1_FB30_Pos (30U)
  3036. #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
  3037. #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
  3038. #define CAN_F2R1_FB31_Pos (31U)
  3039. #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
  3040. #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
  3041. /******************* Bit definition for CAN_F3R1 register *******************/
  3042. #define CAN_F3R1_FB0_Pos (0U)
  3043. #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
  3044. #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
  3045. #define CAN_F3R1_FB1_Pos (1U)
  3046. #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
  3047. #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
  3048. #define CAN_F3R1_FB2_Pos (2U)
  3049. #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
  3050. #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
  3051. #define CAN_F3R1_FB3_Pos (3U)
  3052. #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
  3053. #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
  3054. #define CAN_F3R1_FB4_Pos (4U)
  3055. #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
  3056. #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
  3057. #define CAN_F3R1_FB5_Pos (5U)
  3058. #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
  3059. #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
  3060. #define CAN_F3R1_FB6_Pos (6U)
  3061. #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
  3062. #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
  3063. #define CAN_F3R1_FB7_Pos (7U)
  3064. #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
  3065. #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
  3066. #define CAN_F3R1_FB8_Pos (8U)
  3067. #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
  3068. #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
  3069. #define CAN_F3R1_FB9_Pos (9U)
  3070. #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
  3071. #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
  3072. #define CAN_F3R1_FB10_Pos (10U)
  3073. #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
  3074. #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
  3075. #define CAN_F3R1_FB11_Pos (11U)
  3076. #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
  3077. #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
  3078. #define CAN_F3R1_FB12_Pos (12U)
  3079. #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
  3080. #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
  3081. #define CAN_F3R1_FB13_Pos (13U)
  3082. #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
  3083. #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
  3084. #define CAN_F3R1_FB14_Pos (14U)
  3085. #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
  3086. #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
  3087. #define CAN_F3R1_FB15_Pos (15U)
  3088. #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
  3089. #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
  3090. #define CAN_F3R1_FB16_Pos (16U)
  3091. #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
  3092. #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
  3093. #define CAN_F3R1_FB17_Pos (17U)
  3094. #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
  3095. #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
  3096. #define CAN_F3R1_FB18_Pos (18U)
  3097. #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
  3098. #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
  3099. #define CAN_F3R1_FB19_Pos (19U)
  3100. #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
  3101. #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
  3102. #define CAN_F3R1_FB20_Pos (20U)
  3103. #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
  3104. #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
  3105. #define CAN_F3R1_FB21_Pos (21U)
  3106. #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
  3107. #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
  3108. #define CAN_F3R1_FB22_Pos (22U)
  3109. #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
  3110. #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
  3111. #define CAN_F3R1_FB23_Pos (23U)
  3112. #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
  3113. #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
  3114. #define CAN_F3R1_FB24_Pos (24U)
  3115. #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
  3116. #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
  3117. #define CAN_F3R1_FB25_Pos (25U)
  3118. #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
  3119. #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
  3120. #define CAN_F3R1_FB26_Pos (26U)
  3121. #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
  3122. #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
  3123. #define CAN_F3R1_FB27_Pos (27U)
  3124. #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
  3125. #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
  3126. #define CAN_F3R1_FB28_Pos (28U)
  3127. #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
  3128. #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
  3129. #define CAN_F3R1_FB29_Pos (29U)
  3130. #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
  3131. #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
  3132. #define CAN_F3R1_FB30_Pos (30U)
  3133. #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
  3134. #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
  3135. #define CAN_F3R1_FB31_Pos (31U)
  3136. #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
  3137. #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
  3138. /******************* Bit definition for CAN_F4R1 register *******************/
  3139. #define CAN_F4R1_FB0_Pos (0U)
  3140. #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
  3141. #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
  3142. #define CAN_F4R1_FB1_Pos (1U)
  3143. #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
  3144. #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
  3145. #define CAN_F4R1_FB2_Pos (2U)
  3146. #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
  3147. #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
  3148. #define CAN_F4R1_FB3_Pos (3U)
  3149. #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
  3150. #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
  3151. #define CAN_F4R1_FB4_Pos (4U)
  3152. #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
  3153. #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
  3154. #define CAN_F4R1_FB5_Pos (5U)
  3155. #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
  3156. #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
  3157. #define CAN_F4R1_FB6_Pos (6U)
  3158. #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
  3159. #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
  3160. #define CAN_F4R1_FB7_Pos (7U)
  3161. #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
  3162. #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
  3163. #define CAN_F4R1_FB8_Pos (8U)
  3164. #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
  3165. #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
  3166. #define CAN_F4R1_FB9_Pos (9U)
  3167. #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
  3168. #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
  3169. #define CAN_F4R1_FB10_Pos (10U)
  3170. #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
  3171. #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
  3172. #define CAN_F4R1_FB11_Pos (11U)
  3173. #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
  3174. #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
  3175. #define CAN_F4R1_FB12_Pos (12U)
  3176. #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
  3177. #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
  3178. #define CAN_F4R1_FB13_Pos (13U)
  3179. #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
  3180. #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
  3181. #define CAN_F4R1_FB14_Pos (14U)
  3182. #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
  3183. #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
  3184. #define CAN_F4R1_FB15_Pos (15U)
  3185. #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
  3186. #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
  3187. #define CAN_F4R1_FB16_Pos (16U)
  3188. #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
  3189. #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
  3190. #define CAN_F4R1_FB17_Pos (17U)
  3191. #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
  3192. #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
  3193. #define CAN_F4R1_FB18_Pos (18U)
  3194. #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
  3195. #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
  3196. #define CAN_F4R1_FB19_Pos (19U)
  3197. #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
  3198. #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
  3199. #define CAN_F4R1_FB20_Pos (20U)
  3200. #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
  3201. #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
  3202. #define CAN_F4R1_FB21_Pos (21U)
  3203. #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
  3204. #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
  3205. #define CAN_F4R1_FB22_Pos (22U)
  3206. #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
  3207. #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
  3208. #define CAN_F4R1_FB23_Pos (23U)
  3209. #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
  3210. #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
  3211. #define CAN_F4R1_FB24_Pos (24U)
  3212. #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
  3213. #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
  3214. #define CAN_F4R1_FB25_Pos (25U)
  3215. #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
  3216. #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
  3217. #define CAN_F4R1_FB26_Pos (26U)
  3218. #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
  3219. #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
  3220. #define CAN_F4R1_FB27_Pos (27U)
  3221. #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
  3222. #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
  3223. #define CAN_F4R1_FB28_Pos (28U)
  3224. #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
  3225. #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
  3226. #define CAN_F4R1_FB29_Pos (29U)
  3227. #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
  3228. #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
  3229. #define CAN_F4R1_FB30_Pos (30U)
  3230. #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
  3231. #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
  3232. #define CAN_F4R1_FB31_Pos (31U)
  3233. #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
  3234. #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
  3235. /******************* Bit definition for CAN_F5R1 register *******************/
  3236. #define CAN_F5R1_FB0_Pos (0U)
  3237. #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
  3238. #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
  3239. #define CAN_F5R1_FB1_Pos (1U)
  3240. #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
  3241. #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
  3242. #define CAN_F5R1_FB2_Pos (2U)
  3243. #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
  3244. #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
  3245. #define CAN_F5R1_FB3_Pos (3U)
  3246. #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
  3247. #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
  3248. #define CAN_F5R1_FB4_Pos (4U)
  3249. #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
  3250. #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
  3251. #define CAN_F5R1_FB5_Pos (5U)
  3252. #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
  3253. #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
  3254. #define CAN_F5R1_FB6_Pos (6U)
  3255. #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
  3256. #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
  3257. #define CAN_F5R1_FB7_Pos (7U)
  3258. #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
  3259. #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
  3260. #define CAN_F5R1_FB8_Pos (8U)
  3261. #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
  3262. #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
  3263. #define CAN_F5R1_FB9_Pos (9U)
  3264. #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
  3265. #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
  3266. #define CAN_F5R1_FB10_Pos (10U)
  3267. #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
  3268. #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
  3269. #define CAN_F5R1_FB11_Pos (11U)
  3270. #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
  3271. #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
  3272. #define CAN_F5R1_FB12_Pos (12U)
  3273. #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
  3274. #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
  3275. #define CAN_F5R1_FB13_Pos (13U)
  3276. #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
  3277. #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
  3278. #define CAN_F5R1_FB14_Pos (14U)
  3279. #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
  3280. #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
  3281. #define CAN_F5R1_FB15_Pos (15U)
  3282. #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
  3283. #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
  3284. #define CAN_F5R1_FB16_Pos (16U)
  3285. #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
  3286. #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
  3287. #define CAN_F5R1_FB17_Pos (17U)
  3288. #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
  3289. #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
  3290. #define CAN_F5R1_FB18_Pos (18U)
  3291. #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
  3292. #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
  3293. #define CAN_F5R1_FB19_Pos (19U)
  3294. #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
  3295. #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
  3296. #define CAN_F5R1_FB20_Pos (20U)
  3297. #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
  3298. #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
  3299. #define CAN_F5R1_FB21_Pos (21U)
  3300. #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
  3301. #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
  3302. #define CAN_F5R1_FB22_Pos (22U)
  3303. #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
  3304. #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
  3305. #define CAN_F5R1_FB23_Pos (23U)
  3306. #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
  3307. #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
  3308. #define CAN_F5R1_FB24_Pos (24U)
  3309. #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
  3310. #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
  3311. #define CAN_F5R1_FB25_Pos (25U)
  3312. #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
  3313. #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
  3314. #define CAN_F5R1_FB26_Pos (26U)
  3315. #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
  3316. #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
  3317. #define CAN_F5R1_FB27_Pos (27U)
  3318. #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
  3319. #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
  3320. #define CAN_F5R1_FB28_Pos (28U)
  3321. #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
  3322. #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
  3323. #define CAN_F5R1_FB29_Pos (29U)
  3324. #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
  3325. #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
  3326. #define CAN_F5R1_FB30_Pos (30U)
  3327. #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
  3328. #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
  3329. #define CAN_F5R1_FB31_Pos (31U)
  3330. #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
  3331. #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
  3332. /******************* Bit definition for CAN_F6R1 register *******************/
  3333. #define CAN_F6R1_FB0_Pos (0U)
  3334. #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
  3335. #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
  3336. #define CAN_F6R1_FB1_Pos (1U)
  3337. #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
  3338. #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
  3339. #define CAN_F6R1_FB2_Pos (2U)
  3340. #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
  3341. #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
  3342. #define CAN_F6R1_FB3_Pos (3U)
  3343. #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
  3344. #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
  3345. #define CAN_F6R1_FB4_Pos (4U)
  3346. #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
  3347. #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
  3348. #define CAN_F6R1_FB5_Pos (5U)
  3349. #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
  3350. #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
  3351. #define CAN_F6R1_FB6_Pos (6U)
  3352. #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
  3353. #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
  3354. #define CAN_F6R1_FB7_Pos (7U)
  3355. #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
  3356. #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
  3357. #define CAN_F6R1_FB8_Pos (8U)
  3358. #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
  3359. #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
  3360. #define CAN_F6R1_FB9_Pos (9U)
  3361. #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
  3362. #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
  3363. #define CAN_F6R1_FB10_Pos (10U)
  3364. #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
  3365. #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
  3366. #define CAN_F6R1_FB11_Pos (11U)
  3367. #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
  3368. #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
  3369. #define CAN_F6R1_FB12_Pos (12U)
  3370. #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
  3371. #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
  3372. #define CAN_F6R1_FB13_Pos (13U)
  3373. #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
  3374. #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
  3375. #define CAN_F6R1_FB14_Pos (14U)
  3376. #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
  3377. #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
  3378. #define CAN_F6R1_FB15_Pos (15U)
  3379. #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
  3380. #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
  3381. #define CAN_F6R1_FB16_Pos (16U)
  3382. #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
  3383. #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
  3384. #define CAN_F6R1_FB17_Pos (17U)
  3385. #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
  3386. #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
  3387. #define CAN_F6R1_FB18_Pos (18U)
  3388. #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
  3389. #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
  3390. #define CAN_F6R1_FB19_Pos (19U)
  3391. #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
  3392. #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
  3393. #define CAN_F6R1_FB20_Pos (20U)
  3394. #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
  3395. #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
  3396. #define CAN_F6R1_FB21_Pos (21U)
  3397. #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
  3398. #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
  3399. #define CAN_F6R1_FB22_Pos (22U)
  3400. #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
  3401. #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
  3402. #define CAN_F6R1_FB23_Pos (23U)
  3403. #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
  3404. #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
  3405. #define CAN_F6R1_FB24_Pos (24U)
  3406. #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
  3407. #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
  3408. #define CAN_F6R1_FB25_Pos (25U)
  3409. #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
  3410. #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
  3411. #define CAN_F6R1_FB26_Pos (26U)
  3412. #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
  3413. #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
  3414. #define CAN_F6R1_FB27_Pos (27U)
  3415. #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
  3416. #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
  3417. #define CAN_F6R1_FB28_Pos (28U)
  3418. #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
  3419. #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
  3420. #define CAN_F6R1_FB29_Pos (29U)
  3421. #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
  3422. #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
  3423. #define CAN_F6R1_FB30_Pos (30U)
  3424. #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
  3425. #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
  3426. #define CAN_F6R1_FB31_Pos (31U)
  3427. #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
  3428. #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
  3429. /******************* Bit definition for CAN_F7R1 register *******************/
  3430. #define CAN_F7R1_FB0_Pos (0U)
  3431. #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
  3432. #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
  3433. #define CAN_F7R1_FB1_Pos (1U)
  3434. #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
  3435. #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
  3436. #define CAN_F7R1_FB2_Pos (2U)
  3437. #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
  3438. #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
  3439. #define CAN_F7R1_FB3_Pos (3U)
  3440. #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
  3441. #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
  3442. #define CAN_F7R1_FB4_Pos (4U)
  3443. #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
  3444. #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
  3445. #define CAN_F7R1_FB5_Pos (5U)
  3446. #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
  3447. #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
  3448. #define CAN_F7R1_FB6_Pos (6U)
  3449. #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
  3450. #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
  3451. #define CAN_F7R1_FB7_Pos (7U)
  3452. #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
  3453. #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
  3454. #define CAN_F7R1_FB8_Pos (8U)
  3455. #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
  3456. #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
  3457. #define CAN_F7R1_FB9_Pos (9U)
  3458. #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
  3459. #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
  3460. #define CAN_F7R1_FB10_Pos (10U)
  3461. #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
  3462. #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
  3463. #define CAN_F7R1_FB11_Pos (11U)
  3464. #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
  3465. #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
  3466. #define CAN_F7R1_FB12_Pos (12U)
  3467. #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
  3468. #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
  3469. #define CAN_F7R1_FB13_Pos (13U)
  3470. #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
  3471. #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
  3472. #define CAN_F7R1_FB14_Pos (14U)
  3473. #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
  3474. #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
  3475. #define CAN_F7R1_FB15_Pos (15U)
  3476. #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
  3477. #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
  3478. #define CAN_F7R1_FB16_Pos (16U)
  3479. #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
  3480. #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
  3481. #define CAN_F7R1_FB17_Pos (17U)
  3482. #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
  3483. #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
  3484. #define CAN_F7R1_FB18_Pos (18U)
  3485. #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
  3486. #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
  3487. #define CAN_F7R1_FB19_Pos (19U)
  3488. #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
  3489. #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
  3490. #define CAN_F7R1_FB20_Pos (20U)
  3491. #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
  3492. #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
  3493. #define CAN_F7R1_FB21_Pos (21U)
  3494. #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
  3495. #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
  3496. #define CAN_F7R1_FB22_Pos (22U)
  3497. #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
  3498. #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
  3499. #define CAN_F7R1_FB23_Pos (23U)
  3500. #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
  3501. #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
  3502. #define CAN_F7R1_FB24_Pos (24U)
  3503. #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
  3504. #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
  3505. #define CAN_F7R1_FB25_Pos (25U)
  3506. #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
  3507. #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
  3508. #define CAN_F7R1_FB26_Pos (26U)
  3509. #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
  3510. #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
  3511. #define CAN_F7R1_FB27_Pos (27U)
  3512. #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
  3513. #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
  3514. #define CAN_F7R1_FB28_Pos (28U)
  3515. #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
  3516. #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
  3517. #define CAN_F7R1_FB29_Pos (29U)
  3518. #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
  3519. #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
  3520. #define CAN_F7R1_FB30_Pos (30U)
  3521. #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
  3522. #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
  3523. #define CAN_F7R1_FB31_Pos (31U)
  3524. #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
  3525. #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
  3526. /******************* Bit definition for CAN_F8R1 register *******************/
  3527. #define CAN_F8R1_FB0_Pos (0U)
  3528. #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
  3529. #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
  3530. #define CAN_F8R1_FB1_Pos (1U)
  3531. #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
  3532. #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
  3533. #define CAN_F8R1_FB2_Pos (2U)
  3534. #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
  3535. #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
  3536. #define CAN_F8R1_FB3_Pos (3U)
  3537. #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
  3538. #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
  3539. #define CAN_F8R1_FB4_Pos (4U)
  3540. #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
  3541. #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
  3542. #define CAN_F8R1_FB5_Pos (5U)
  3543. #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
  3544. #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
  3545. #define CAN_F8R1_FB6_Pos (6U)
  3546. #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
  3547. #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
  3548. #define CAN_F8R1_FB7_Pos (7U)
  3549. #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
  3550. #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
  3551. #define CAN_F8R1_FB8_Pos (8U)
  3552. #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
  3553. #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
  3554. #define CAN_F8R1_FB9_Pos (9U)
  3555. #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
  3556. #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
  3557. #define CAN_F8R1_FB10_Pos (10U)
  3558. #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
  3559. #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
  3560. #define CAN_F8R1_FB11_Pos (11U)
  3561. #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
  3562. #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
  3563. #define CAN_F8R1_FB12_Pos (12U)
  3564. #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
  3565. #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
  3566. #define CAN_F8R1_FB13_Pos (13U)
  3567. #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
  3568. #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
  3569. #define CAN_F8R1_FB14_Pos (14U)
  3570. #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
  3571. #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
  3572. #define CAN_F8R1_FB15_Pos (15U)
  3573. #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
  3574. #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
  3575. #define CAN_F8R1_FB16_Pos (16U)
  3576. #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
  3577. #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
  3578. #define CAN_F8R1_FB17_Pos (17U)
  3579. #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
  3580. #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
  3581. #define CAN_F8R1_FB18_Pos (18U)
  3582. #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
  3583. #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
  3584. #define CAN_F8R1_FB19_Pos (19U)
  3585. #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
  3586. #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
  3587. #define CAN_F8R1_FB20_Pos (20U)
  3588. #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
  3589. #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
  3590. #define CAN_F8R1_FB21_Pos (21U)
  3591. #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
  3592. #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
  3593. #define CAN_F8R1_FB22_Pos (22U)
  3594. #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
  3595. #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
  3596. #define CAN_F8R1_FB23_Pos (23U)
  3597. #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
  3598. #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
  3599. #define CAN_F8R1_FB24_Pos (24U)
  3600. #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
  3601. #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
  3602. #define CAN_F8R1_FB25_Pos (25U)
  3603. #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
  3604. #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
  3605. #define CAN_F8R1_FB26_Pos (26U)
  3606. #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
  3607. #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
  3608. #define CAN_F8R1_FB27_Pos (27U)
  3609. #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
  3610. #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
  3611. #define CAN_F8R1_FB28_Pos (28U)
  3612. #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
  3613. #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
  3614. #define CAN_F8R1_FB29_Pos (29U)
  3615. #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
  3616. #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
  3617. #define CAN_F8R1_FB30_Pos (30U)
  3618. #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
  3619. #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
  3620. #define CAN_F8R1_FB31_Pos (31U)
  3621. #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
  3622. #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
  3623. /******************* Bit definition for CAN_F9R1 register *******************/
  3624. #define CAN_F9R1_FB0_Pos (0U)
  3625. #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
  3626. #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
  3627. #define CAN_F9R1_FB1_Pos (1U)
  3628. #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
  3629. #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
  3630. #define CAN_F9R1_FB2_Pos (2U)
  3631. #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
  3632. #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
  3633. #define CAN_F9R1_FB3_Pos (3U)
  3634. #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
  3635. #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
  3636. #define CAN_F9R1_FB4_Pos (4U)
  3637. #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
  3638. #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
  3639. #define CAN_F9R1_FB5_Pos (5U)
  3640. #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
  3641. #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
  3642. #define CAN_F9R1_FB6_Pos (6U)
  3643. #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
  3644. #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
  3645. #define CAN_F9R1_FB7_Pos (7U)
  3646. #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
  3647. #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
  3648. #define CAN_F9R1_FB8_Pos (8U)
  3649. #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
  3650. #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
  3651. #define CAN_F9R1_FB9_Pos (9U)
  3652. #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
  3653. #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
  3654. #define CAN_F9R1_FB10_Pos (10U)
  3655. #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
  3656. #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
  3657. #define CAN_F9R1_FB11_Pos (11U)
  3658. #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
  3659. #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
  3660. #define CAN_F9R1_FB12_Pos (12U)
  3661. #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
  3662. #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
  3663. #define CAN_F9R1_FB13_Pos (13U)
  3664. #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
  3665. #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
  3666. #define CAN_F9R1_FB14_Pos (14U)
  3667. #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
  3668. #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
  3669. #define CAN_F9R1_FB15_Pos (15U)
  3670. #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
  3671. #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
  3672. #define CAN_F9R1_FB16_Pos (16U)
  3673. #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
  3674. #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
  3675. #define CAN_F9R1_FB17_Pos (17U)
  3676. #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
  3677. #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
  3678. #define CAN_F9R1_FB18_Pos (18U)
  3679. #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
  3680. #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
  3681. #define CAN_F9R1_FB19_Pos (19U)
  3682. #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
  3683. #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
  3684. #define CAN_F9R1_FB20_Pos (20U)
  3685. #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
  3686. #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
  3687. #define CAN_F9R1_FB21_Pos (21U)
  3688. #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
  3689. #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
  3690. #define CAN_F9R1_FB22_Pos (22U)
  3691. #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
  3692. #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
  3693. #define CAN_F9R1_FB23_Pos (23U)
  3694. #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
  3695. #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
  3696. #define CAN_F9R1_FB24_Pos (24U)
  3697. #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
  3698. #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
  3699. #define CAN_F9R1_FB25_Pos (25U)
  3700. #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
  3701. #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
  3702. #define CAN_F9R1_FB26_Pos (26U)
  3703. #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
  3704. #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
  3705. #define CAN_F9R1_FB27_Pos (27U)
  3706. #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
  3707. #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
  3708. #define CAN_F9R1_FB28_Pos (28U)
  3709. #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
  3710. #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
  3711. #define CAN_F9R1_FB29_Pos (29U)
  3712. #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
  3713. #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
  3714. #define CAN_F9R1_FB30_Pos (30U)
  3715. #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
  3716. #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
  3717. #define CAN_F9R1_FB31_Pos (31U)
  3718. #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
  3719. #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
  3720. /******************* Bit definition for CAN_F10R1 register ******************/
  3721. #define CAN_F10R1_FB0_Pos (0U)
  3722. #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
  3723. #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
  3724. #define CAN_F10R1_FB1_Pos (1U)
  3725. #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
  3726. #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
  3727. #define CAN_F10R1_FB2_Pos (2U)
  3728. #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
  3729. #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
  3730. #define CAN_F10R1_FB3_Pos (3U)
  3731. #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
  3732. #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
  3733. #define CAN_F10R1_FB4_Pos (4U)
  3734. #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
  3735. #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
  3736. #define CAN_F10R1_FB5_Pos (5U)
  3737. #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
  3738. #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
  3739. #define CAN_F10R1_FB6_Pos (6U)
  3740. #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
  3741. #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
  3742. #define CAN_F10R1_FB7_Pos (7U)
  3743. #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
  3744. #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
  3745. #define CAN_F10R1_FB8_Pos (8U)
  3746. #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
  3747. #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
  3748. #define CAN_F10R1_FB9_Pos (9U)
  3749. #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
  3750. #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
  3751. #define CAN_F10R1_FB10_Pos (10U)
  3752. #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
  3753. #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
  3754. #define CAN_F10R1_FB11_Pos (11U)
  3755. #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
  3756. #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
  3757. #define CAN_F10R1_FB12_Pos (12U)
  3758. #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
  3759. #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
  3760. #define CAN_F10R1_FB13_Pos (13U)
  3761. #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
  3762. #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
  3763. #define CAN_F10R1_FB14_Pos (14U)
  3764. #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
  3765. #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
  3766. #define CAN_F10R1_FB15_Pos (15U)
  3767. #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
  3768. #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
  3769. #define CAN_F10R1_FB16_Pos (16U)
  3770. #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
  3771. #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
  3772. #define CAN_F10R1_FB17_Pos (17U)
  3773. #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
  3774. #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
  3775. #define CAN_F10R1_FB18_Pos (18U)
  3776. #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
  3777. #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
  3778. #define CAN_F10R1_FB19_Pos (19U)
  3779. #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
  3780. #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
  3781. #define CAN_F10R1_FB20_Pos (20U)
  3782. #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
  3783. #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
  3784. #define CAN_F10R1_FB21_Pos (21U)
  3785. #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
  3786. #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
  3787. #define CAN_F10R1_FB22_Pos (22U)
  3788. #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
  3789. #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
  3790. #define CAN_F10R1_FB23_Pos (23U)
  3791. #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
  3792. #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
  3793. #define CAN_F10R1_FB24_Pos (24U)
  3794. #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
  3795. #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
  3796. #define CAN_F10R1_FB25_Pos (25U)
  3797. #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
  3798. #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
  3799. #define CAN_F10R1_FB26_Pos (26U)
  3800. #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
  3801. #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
  3802. #define CAN_F10R1_FB27_Pos (27U)
  3803. #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
  3804. #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
  3805. #define CAN_F10R1_FB28_Pos (28U)
  3806. #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
  3807. #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
  3808. #define CAN_F10R1_FB29_Pos (29U)
  3809. #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
  3810. #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
  3811. #define CAN_F10R1_FB30_Pos (30U)
  3812. #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
  3813. #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
  3814. #define CAN_F10R1_FB31_Pos (31U)
  3815. #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
  3816. #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
  3817. /******************* Bit definition for CAN_F11R1 register ******************/
  3818. #define CAN_F11R1_FB0_Pos (0U)
  3819. #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
  3820. #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
  3821. #define CAN_F11R1_FB1_Pos (1U)
  3822. #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
  3823. #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
  3824. #define CAN_F11R1_FB2_Pos (2U)
  3825. #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
  3826. #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
  3827. #define CAN_F11R1_FB3_Pos (3U)
  3828. #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
  3829. #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
  3830. #define CAN_F11R1_FB4_Pos (4U)
  3831. #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
  3832. #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
  3833. #define CAN_F11R1_FB5_Pos (5U)
  3834. #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
  3835. #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
  3836. #define CAN_F11R1_FB6_Pos (6U)
  3837. #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
  3838. #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
  3839. #define CAN_F11R1_FB7_Pos (7U)
  3840. #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
  3841. #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
  3842. #define CAN_F11R1_FB8_Pos (8U)
  3843. #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
  3844. #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
  3845. #define CAN_F11R1_FB9_Pos (9U)
  3846. #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
  3847. #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
  3848. #define CAN_F11R1_FB10_Pos (10U)
  3849. #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
  3850. #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
  3851. #define CAN_F11R1_FB11_Pos (11U)
  3852. #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
  3853. #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
  3854. #define CAN_F11R1_FB12_Pos (12U)
  3855. #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
  3856. #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
  3857. #define CAN_F11R1_FB13_Pos (13U)
  3858. #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
  3859. #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
  3860. #define CAN_F11R1_FB14_Pos (14U)
  3861. #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
  3862. #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
  3863. #define CAN_F11R1_FB15_Pos (15U)
  3864. #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
  3865. #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
  3866. #define CAN_F11R1_FB16_Pos (16U)
  3867. #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
  3868. #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
  3869. #define CAN_F11R1_FB17_Pos (17U)
  3870. #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
  3871. #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
  3872. #define CAN_F11R1_FB18_Pos (18U)
  3873. #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
  3874. #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
  3875. #define CAN_F11R1_FB19_Pos (19U)
  3876. #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
  3877. #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
  3878. #define CAN_F11R1_FB20_Pos (20U)
  3879. #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
  3880. #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
  3881. #define CAN_F11R1_FB21_Pos (21U)
  3882. #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
  3883. #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
  3884. #define CAN_F11R1_FB22_Pos (22U)
  3885. #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
  3886. #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
  3887. #define CAN_F11R1_FB23_Pos (23U)
  3888. #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
  3889. #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
  3890. #define CAN_F11R1_FB24_Pos (24U)
  3891. #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
  3892. #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
  3893. #define CAN_F11R1_FB25_Pos (25U)
  3894. #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
  3895. #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
  3896. #define CAN_F11R1_FB26_Pos (26U)
  3897. #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
  3898. #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
  3899. #define CAN_F11R1_FB27_Pos (27U)
  3900. #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
  3901. #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
  3902. #define CAN_F11R1_FB28_Pos (28U)
  3903. #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
  3904. #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
  3905. #define CAN_F11R1_FB29_Pos (29U)
  3906. #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
  3907. #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
  3908. #define CAN_F11R1_FB30_Pos (30U)
  3909. #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
  3910. #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
  3911. #define CAN_F11R1_FB31_Pos (31U)
  3912. #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
  3913. #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
  3914. /******************* Bit definition for CAN_F12R1 register ******************/
  3915. #define CAN_F12R1_FB0_Pos (0U)
  3916. #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
  3917. #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
  3918. #define CAN_F12R1_FB1_Pos (1U)
  3919. #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
  3920. #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
  3921. #define CAN_F12R1_FB2_Pos (2U)
  3922. #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
  3923. #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
  3924. #define CAN_F12R1_FB3_Pos (3U)
  3925. #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
  3926. #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
  3927. #define CAN_F12R1_FB4_Pos (4U)
  3928. #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
  3929. #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
  3930. #define CAN_F12R1_FB5_Pos (5U)
  3931. #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
  3932. #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
  3933. #define CAN_F12R1_FB6_Pos (6U)
  3934. #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
  3935. #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
  3936. #define CAN_F12R1_FB7_Pos (7U)
  3937. #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
  3938. #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
  3939. #define CAN_F12R1_FB8_Pos (8U)
  3940. #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
  3941. #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
  3942. #define CAN_F12R1_FB9_Pos (9U)
  3943. #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
  3944. #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
  3945. #define CAN_F12R1_FB10_Pos (10U)
  3946. #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
  3947. #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
  3948. #define CAN_F12R1_FB11_Pos (11U)
  3949. #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
  3950. #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
  3951. #define CAN_F12R1_FB12_Pos (12U)
  3952. #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
  3953. #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
  3954. #define CAN_F12R1_FB13_Pos (13U)
  3955. #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
  3956. #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
  3957. #define CAN_F12R1_FB14_Pos (14U)
  3958. #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
  3959. #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
  3960. #define CAN_F12R1_FB15_Pos (15U)
  3961. #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
  3962. #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
  3963. #define CAN_F12R1_FB16_Pos (16U)
  3964. #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
  3965. #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
  3966. #define CAN_F12R1_FB17_Pos (17U)
  3967. #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
  3968. #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
  3969. #define CAN_F12R1_FB18_Pos (18U)
  3970. #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
  3971. #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
  3972. #define CAN_F12R1_FB19_Pos (19U)
  3973. #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
  3974. #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
  3975. #define CAN_F12R1_FB20_Pos (20U)
  3976. #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
  3977. #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
  3978. #define CAN_F12R1_FB21_Pos (21U)
  3979. #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
  3980. #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
  3981. #define CAN_F12R1_FB22_Pos (22U)
  3982. #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
  3983. #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
  3984. #define CAN_F12R1_FB23_Pos (23U)
  3985. #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
  3986. #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
  3987. #define CAN_F12R1_FB24_Pos (24U)
  3988. #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
  3989. #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
  3990. #define CAN_F12R1_FB25_Pos (25U)
  3991. #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
  3992. #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
  3993. #define CAN_F12R1_FB26_Pos (26U)
  3994. #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
  3995. #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
  3996. #define CAN_F12R1_FB27_Pos (27U)
  3997. #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
  3998. #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
  3999. #define CAN_F12R1_FB28_Pos (28U)
  4000. #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
  4001. #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
  4002. #define CAN_F12R1_FB29_Pos (29U)
  4003. #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
  4004. #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
  4005. #define CAN_F12R1_FB30_Pos (30U)
  4006. #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
  4007. #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
  4008. #define CAN_F12R1_FB31_Pos (31U)
  4009. #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
  4010. #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
  4011. /******************* Bit definition for CAN_F13R1 register ******************/
  4012. #define CAN_F13R1_FB0_Pos (0U)
  4013. #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
  4014. #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
  4015. #define CAN_F13R1_FB1_Pos (1U)
  4016. #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
  4017. #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
  4018. #define CAN_F13R1_FB2_Pos (2U)
  4019. #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
  4020. #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
  4021. #define CAN_F13R1_FB3_Pos (3U)
  4022. #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
  4023. #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
  4024. #define CAN_F13R1_FB4_Pos (4U)
  4025. #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
  4026. #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
  4027. #define CAN_F13R1_FB5_Pos (5U)
  4028. #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
  4029. #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
  4030. #define CAN_F13R1_FB6_Pos (6U)
  4031. #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
  4032. #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
  4033. #define CAN_F13R1_FB7_Pos (7U)
  4034. #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
  4035. #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
  4036. #define CAN_F13R1_FB8_Pos (8U)
  4037. #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
  4038. #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
  4039. #define CAN_F13R1_FB9_Pos (9U)
  4040. #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
  4041. #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
  4042. #define CAN_F13R1_FB10_Pos (10U)
  4043. #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
  4044. #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
  4045. #define CAN_F13R1_FB11_Pos (11U)
  4046. #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
  4047. #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
  4048. #define CAN_F13R1_FB12_Pos (12U)
  4049. #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
  4050. #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
  4051. #define CAN_F13R1_FB13_Pos (13U)
  4052. #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
  4053. #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
  4054. #define CAN_F13R1_FB14_Pos (14U)
  4055. #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
  4056. #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
  4057. #define CAN_F13R1_FB15_Pos (15U)
  4058. #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
  4059. #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
  4060. #define CAN_F13R1_FB16_Pos (16U)
  4061. #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
  4062. #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
  4063. #define CAN_F13R1_FB17_Pos (17U)
  4064. #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
  4065. #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
  4066. #define CAN_F13R1_FB18_Pos (18U)
  4067. #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
  4068. #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
  4069. #define CAN_F13R1_FB19_Pos (19U)
  4070. #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
  4071. #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
  4072. #define CAN_F13R1_FB20_Pos (20U)
  4073. #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
  4074. #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
  4075. #define CAN_F13R1_FB21_Pos (21U)
  4076. #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
  4077. #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
  4078. #define CAN_F13R1_FB22_Pos (22U)
  4079. #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
  4080. #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
  4081. #define CAN_F13R1_FB23_Pos (23U)
  4082. #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
  4083. #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
  4084. #define CAN_F13R1_FB24_Pos (24U)
  4085. #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
  4086. #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
  4087. #define CAN_F13R1_FB25_Pos (25U)
  4088. #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
  4089. #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
  4090. #define CAN_F13R1_FB26_Pos (26U)
  4091. #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
  4092. #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
  4093. #define CAN_F13R1_FB27_Pos (27U)
  4094. #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
  4095. #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
  4096. #define CAN_F13R1_FB28_Pos (28U)
  4097. #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
  4098. #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
  4099. #define CAN_F13R1_FB29_Pos (29U)
  4100. #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
  4101. #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
  4102. #define CAN_F13R1_FB30_Pos (30U)
  4103. #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
  4104. #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
  4105. #define CAN_F13R1_FB31_Pos (31U)
  4106. #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
  4107. #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
  4108. /******************* Bit definition for CAN_F0R2 register *******************/
  4109. #define CAN_F0R2_FB0_Pos (0U)
  4110. #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
  4111. #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
  4112. #define CAN_F0R2_FB1_Pos (1U)
  4113. #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
  4114. #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
  4115. #define CAN_F0R2_FB2_Pos (2U)
  4116. #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
  4117. #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
  4118. #define CAN_F0R2_FB3_Pos (3U)
  4119. #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
  4120. #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
  4121. #define CAN_F0R2_FB4_Pos (4U)
  4122. #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
  4123. #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
  4124. #define CAN_F0R2_FB5_Pos (5U)
  4125. #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
  4126. #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
  4127. #define CAN_F0R2_FB6_Pos (6U)
  4128. #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
  4129. #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
  4130. #define CAN_F0R2_FB7_Pos (7U)
  4131. #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
  4132. #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
  4133. #define CAN_F0R2_FB8_Pos (8U)
  4134. #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
  4135. #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
  4136. #define CAN_F0R2_FB9_Pos (9U)
  4137. #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
  4138. #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
  4139. #define CAN_F0R2_FB10_Pos (10U)
  4140. #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
  4141. #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
  4142. #define CAN_F0R2_FB11_Pos (11U)
  4143. #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
  4144. #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
  4145. #define CAN_F0R2_FB12_Pos (12U)
  4146. #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
  4147. #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
  4148. #define CAN_F0R2_FB13_Pos (13U)
  4149. #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
  4150. #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
  4151. #define CAN_F0R2_FB14_Pos (14U)
  4152. #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
  4153. #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
  4154. #define CAN_F0R2_FB15_Pos (15U)
  4155. #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
  4156. #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
  4157. #define CAN_F0R2_FB16_Pos (16U)
  4158. #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
  4159. #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
  4160. #define CAN_F0R2_FB17_Pos (17U)
  4161. #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
  4162. #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
  4163. #define CAN_F0R2_FB18_Pos (18U)
  4164. #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
  4165. #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
  4166. #define CAN_F0R2_FB19_Pos (19U)
  4167. #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
  4168. #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
  4169. #define CAN_F0R2_FB20_Pos (20U)
  4170. #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
  4171. #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
  4172. #define CAN_F0R2_FB21_Pos (21U)
  4173. #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
  4174. #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
  4175. #define CAN_F0R2_FB22_Pos (22U)
  4176. #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
  4177. #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
  4178. #define CAN_F0R2_FB23_Pos (23U)
  4179. #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
  4180. #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
  4181. #define CAN_F0R2_FB24_Pos (24U)
  4182. #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
  4183. #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
  4184. #define CAN_F0R2_FB25_Pos (25U)
  4185. #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
  4186. #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
  4187. #define CAN_F0R2_FB26_Pos (26U)
  4188. #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
  4189. #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
  4190. #define CAN_F0R2_FB27_Pos (27U)
  4191. #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
  4192. #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
  4193. #define CAN_F0R2_FB28_Pos (28U)
  4194. #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
  4195. #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
  4196. #define CAN_F0R2_FB29_Pos (29U)
  4197. #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
  4198. #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
  4199. #define CAN_F0R2_FB30_Pos (30U)
  4200. #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
  4201. #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
  4202. #define CAN_F0R2_FB31_Pos (31U)
  4203. #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
  4204. #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
  4205. /******************* Bit definition for CAN_F1R2 register *******************/
  4206. #define CAN_F1R2_FB0_Pos (0U)
  4207. #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
  4208. #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
  4209. #define CAN_F1R2_FB1_Pos (1U)
  4210. #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
  4211. #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
  4212. #define CAN_F1R2_FB2_Pos (2U)
  4213. #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
  4214. #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
  4215. #define CAN_F1R2_FB3_Pos (3U)
  4216. #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
  4217. #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
  4218. #define CAN_F1R2_FB4_Pos (4U)
  4219. #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
  4220. #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
  4221. #define CAN_F1R2_FB5_Pos (5U)
  4222. #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
  4223. #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
  4224. #define CAN_F1R2_FB6_Pos (6U)
  4225. #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
  4226. #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
  4227. #define CAN_F1R2_FB7_Pos (7U)
  4228. #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
  4229. #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
  4230. #define CAN_F1R2_FB8_Pos (8U)
  4231. #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
  4232. #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
  4233. #define CAN_F1R2_FB9_Pos (9U)
  4234. #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
  4235. #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
  4236. #define CAN_F1R2_FB10_Pos (10U)
  4237. #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
  4238. #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
  4239. #define CAN_F1R2_FB11_Pos (11U)
  4240. #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
  4241. #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
  4242. #define CAN_F1R2_FB12_Pos (12U)
  4243. #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
  4244. #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
  4245. #define CAN_F1R2_FB13_Pos (13U)
  4246. #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
  4247. #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
  4248. #define CAN_F1R2_FB14_Pos (14U)
  4249. #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
  4250. #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
  4251. #define CAN_F1R2_FB15_Pos (15U)
  4252. #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
  4253. #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
  4254. #define CAN_F1R2_FB16_Pos (16U)
  4255. #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
  4256. #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
  4257. #define CAN_F1R2_FB17_Pos (17U)
  4258. #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
  4259. #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
  4260. #define CAN_F1R2_FB18_Pos (18U)
  4261. #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
  4262. #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
  4263. #define CAN_F1R2_FB19_Pos (19U)
  4264. #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
  4265. #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
  4266. #define CAN_F1R2_FB20_Pos (20U)
  4267. #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
  4268. #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
  4269. #define CAN_F1R2_FB21_Pos (21U)
  4270. #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
  4271. #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
  4272. #define CAN_F1R2_FB22_Pos (22U)
  4273. #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
  4274. #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
  4275. #define CAN_F1R2_FB23_Pos (23U)
  4276. #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
  4277. #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
  4278. #define CAN_F1R2_FB24_Pos (24U)
  4279. #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
  4280. #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
  4281. #define CAN_F1R2_FB25_Pos (25U)
  4282. #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
  4283. #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
  4284. #define CAN_F1R2_FB26_Pos (26U)
  4285. #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
  4286. #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
  4287. #define CAN_F1R2_FB27_Pos (27U)
  4288. #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
  4289. #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
  4290. #define CAN_F1R2_FB28_Pos (28U)
  4291. #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
  4292. #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
  4293. #define CAN_F1R2_FB29_Pos (29U)
  4294. #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
  4295. #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
  4296. #define CAN_F1R2_FB30_Pos (30U)
  4297. #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
  4298. #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
  4299. #define CAN_F1R2_FB31_Pos (31U)
  4300. #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
  4301. #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
  4302. /******************* Bit definition for CAN_F2R2 register *******************/
  4303. #define CAN_F2R2_FB0_Pos (0U)
  4304. #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
  4305. #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
  4306. #define CAN_F2R2_FB1_Pos (1U)
  4307. #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
  4308. #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
  4309. #define CAN_F2R2_FB2_Pos (2U)
  4310. #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
  4311. #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
  4312. #define CAN_F2R2_FB3_Pos (3U)
  4313. #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
  4314. #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
  4315. #define CAN_F2R2_FB4_Pos (4U)
  4316. #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
  4317. #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
  4318. #define CAN_F2R2_FB5_Pos (5U)
  4319. #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
  4320. #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
  4321. #define CAN_F2R2_FB6_Pos (6U)
  4322. #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
  4323. #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
  4324. #define CAN_F2R2_FB7_Pos (7U)
  4325. #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
  4326. #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
  4327. #define CAN_F2R2_FB8_Pos (8U)
  4328. #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
  4329. #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
  4330. #define CAN_F2R2_FB9_Pos (9U)
  4331. #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
  4332. #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
  4333. #define CAN_F2R2_FB10_Pos (10U)
  4334. #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
  4335. #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
  4336. #define CAN_F2R2_FB11_Pos (11U)
  4337. #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
  4338. #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
  4339. #define CAN_F2R2_FB12_Pos (12U)
  4340. #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
  4341. #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
  4342. #define CAN_F2R2_FB13_Pos (13U)
  4343. #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
  4344. #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
  4345. #define CAN_F2R2_FB14_Pos (14U)
  4346. #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
  4347. #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
  4348. #define CAN_F2R2_FB15_Pos (15U)
  4349. #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
  4350. #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
  4351. #define CAN_F2R2_FB16_Pos (16U)
  4352. #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
  4353. #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
  4354. #define CAN_F2R2_FB17_Pos (17U)
  4355. #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
  4356. #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
  4357. #define CAN_F2R2_FB18_Pos (18U)
  4358. #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
  4359. #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
  4360. #define CAN_F2R2_FB19_Pos (19U)
  4361. #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
  4362. #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
  4363. #define CAN_F2R2_FB20_Pos (20U)
  4364. #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
  4365. #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
  4366. #define CAN_F2R2_FB21_Pos (21U)
  4367. #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
  4368. #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
  4369. #define CAN_F2R2_FB22_Pos (22U)
  4370. #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
  4371. #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
  4372. #define CAN_F2R2_FB23_Pos (23U)
  4373. #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
  4374. #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
  4375. #define CAN_F2R2_FB24_Pos (24U)
  4376. #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
  4377. #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
  4378. #define CAN_F2R2_FB25_Pos (25U)
  4379. #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
  4380. #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
  4381. #define CAN_F2R2_FB26_Pos (26U)
  4382. #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
  4383. #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
  4384. #define CAN_F2R2_FB27_Pos (27U)
  4385. #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
  4386. #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
  4387. #define CAN_F2R2_FB28_Pos (28U)
  4388. #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
  4389. #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
  4390. #define CAN_F2R2_FB29_Pos (29U)
  4391. #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
  4392. #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
  4393. #define CAN_F2R2_FB30_Pos (30U)
  4394. #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
  4395. #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
  4396. #define CAN_F2R2_FB31_Pos (31U)
  4397. #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
  4398. #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
  4399. /******************* Bit definition for CAN_F3R2 register *******************/
  4400. #define CAN_F3R2_FB0_Pos (0U)
  4401. #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
  4402. #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
  4403. #define CAN_F3R2_FB1_Pos (1U)
  4404. #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
  4405. #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
  4406. #define CAN_F3R2_FB2_Pos (2U)
  4407. #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
  4408. #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
  4409. #define CAN_F3R2_FB3_Pos (3U)
  4410. #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
  4411. #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
  4412. #define CAN_F3R2_FB4_Pos (4U)
  4413. #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
  4414. #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
  4415. #define CAN_F3R2_FB5_Pos (5U)
  4416. #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
  4417. #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
  4418. #define CAN_F3R2_FB6_Pos (6U)
  4419. #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
  4420. #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
  4421. #define CAN_F3R2_FB7_Pos (7U)
  4422. #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
  4423. #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
  4424. #define CAN_F3R2_FB8_Pos (8U)
  4425. #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
  4426. #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
  4427. #define CAN_F3R2_FB9_Pos (9U)
  4428. #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
  4429. #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
  4430. #define CAN_F3R2_FB10_Pos (10U)
  4431. #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
  4432. #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
  4433. #define CAN_F3R2_FB11_Pos (11U)
  4434. #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
  4435. #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
  4436. #define CAN_F3R2_FB12_Pos (12U)
  4437. #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
  4438. #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
  4439. #define CAN_F3R2_FB13_Pos (13U)
  4440. #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
  4441. #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
  4442. #define CAN_F3R2_FB14_Pos (14U)
  4443. #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
  4444. #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
  4445. #define CAN_F3R2_FB15_Pos (15U)
  4446. #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
  4447. #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
  4448. #define CAN_F3R2_FB16_Pos (16U)
  4449. #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
  4450. #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
  4451. #define CAN_F3R2_FB17_Pos (17U)
  4452. #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
  4453. #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
  4454. #define CAN_F3R2_FB18_Pos (18U)
  4455. #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
  4456. #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
  4457. #define CAN_F3R2_FB19_Pos (19U)
  4458. #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
  4459. #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
  4460. #define CAN_F3R2_FB20_Pos (20U)
  4461. #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
  4462. #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
  4463. #define CAN_F3R2_FB21_Pos (21U)
  4464. #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
  4465. #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
  4466. #define CAN_F3R2_FB22_Pos (22U)
  4467. #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
  4468. #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
  4469. #define CAN_F3R2_FB23_Pos (23U)
  4470. #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
  4471. #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
  4472. #define CAN_F3R2_FB24_Pos (24U)
  4473. #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
  4474. #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
  4475. #define CAN_F3R2_FB25_Pos (25U)
  4476. #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
  4477. #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
  4478. #define CAN_F3R2_FB26_Pos (26U)
  4479. #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
  4480. #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
  4481. #define CAN_F3R2_FB27_Pos (27U)
  4482. #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
  4483. #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
  4484. #define CAN_F3R2_FB28_Pos (28U)
  4485. #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
  4486. #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
  4487. #define CAN_F3R2_FB29_Pos (29U)
  4488. #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
  4489. #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
  4490. #define CAN_F3R2_FB30_Pos (30U)
  4491. #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
  4492. #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
  4493. #define CAN_F3R2_FB31_Pos (31U)
  4494. #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
  4495. #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
  4496. /******************* Bit definition for CAN_F4R2 register *******************/
  4497. #define CAN_F4R2_FB0_Pos (0U)
  4498. #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
  4499. #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
  4500. #define CAN_F4R2_FB1_Pos (1U)
  4501. #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
  4502. #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
  4503. #define CAN_F4R2_FB2_Pos (2U)
  4504. #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
  4505. #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
  4506. #define CAN_F4R2_FB3_Pos (3U)
  4507. #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
  4508. #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
  4509. #define CAN_F4R2_FB4_Pos (4U)
  4510. #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
  4511. #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
  4512. #define CAN_F4R2_FB5_Pos (5U)
  4513. #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
  4514. #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
  4515. #define CAN_F4R2_FB6_Pos (6U)
  4516. #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
  4517. #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
  4518. #define CAN_F4R2_FB7_Pos (7U)
  4519. #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
  4520. #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
  4521. #define CAN_F4R2_FB8_Pos (8U)
  4522. #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
  4523. #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
  4524. #define CAN_F4R2_FB9_Pos (9U)
  4525. #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
  4526. #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
  4527. #define CAN_F4R2_FB10_Pos (10U)
  4528. #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
  4529. #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
  4530. #define CAN_F4R2_FB11_Pos (11U)
  4531. #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
  4532. #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
  4533. #define CAN_F4R2_FB12_Pos (12U)
  4534. #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
  4535. #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
  4536. #define CAN_F4R2_FB13_Pos (13U)
  4537. #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
  4538. #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
  4539. #define CAN_F4R2_FB14_Pos (14U)
  4540. #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
  4541. #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
  4542. #define CAN_F4R2_FB15_Pos (15U)
  4543. #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
  4544. #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
  4545. #define CAN_F4R2_FB16_Pos (16U)
  4546. #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
  4547. #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
  4548. #define CAN_F4R2_FB17_Pos (17U)
  4549. #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
  4550. #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
  4551. #define CAN_F4R2_FB18_Pos (18U)
  4552. #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
  4553. #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
  4554. #define CAN_F4R2_FB19_Pos (19U)
  4555. #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
  4556. #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
  4557. #define CAN_F4R2_FB20_Pos (20U)
  4558. #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
  4559. #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
  4560. #define CAN_F4R2_FB21_Pos (21U)
  4561. #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
  4562. #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
  4563. #define CAN_F4R2_FB22_Pos (22U)
  4564. #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
  4565. #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
  4566. #define CAN_F4R2_FB23_Pos (23U)
  4567. #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
  4568. #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
  4569. #define CAN_F4R2_FB24_Pos (24U)
  4570. #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
  4571. #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
  4572. #define CAN_F4R2_FB25_Pos (25U)
  4573. #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
  4574. #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
  4575. #define CAN_F4R2_FB26_Pos (26U)
  4576. #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
  4577. #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
  4578. #define CAN_F4R2_FB27_Pos (27U)
  4579. #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
  4580. #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
  4581. #define CAN_F4R2_FB28_Pos (28U)
  4582. #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
  4583. #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
  4584. #define CAN_F4R2_FB29_Pos (29U)
  4585. #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
  4586. #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
  4587. #define CAN_F4R2_FB30_Pos (30U)
  4588. #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
  4589. #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
  4590. #define CAN_F4R2_FB31_Pos (31U)
  4591. #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
  4592. #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
  4593. /******************* Bit definition for CAN_F5R2 register *******************/
  4594. #define CAN_F5R2_FB0_Pos (0U)
  4595. #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
  4596. #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
  4597. #define CAN_F5R2_FB1_Pos (1U)
  4598. #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
  4599. #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
  4600. #define CAN_F5R2_FB2_Pos (2U)
  4601. #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
  4602. #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
  4603. #define CAN_F5R2_FB3_Pos (3U)
  4604. #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
  4605. #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
  4606. #define CAN_F5R2_FB4_Pos (4U)
  4607. #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
  4608. #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
  4609. #define CAN_F5R2_FB5_Pos (5U)
  4610. #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
  4611. #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
  4612. #define CAN_F5R2_FB6_Pos (6U)
  4613. #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
  4614. #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
  4615. #define CAN_F5R2_FB7_Pos (7U)
  4616. #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
  4617. #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
  4618. #define CAN_F5R2_FB8_Pos (8U)
  4619. #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
  4620. #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
  4621. #define CAN_F5R2_FB9_Pos (9U)
  4622. #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
  4623. #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
  4624. #define CAN_F5R2_FB10_Pos (10U)
  4625. #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
  4626. #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
  4627. #define CAN_F5R2_FB11_Pos (11U)
  4628. #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
  4629. #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
  4630. #define CAN_F5R2_FB12_Pos (12U)
  4631. #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
  4632. #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
  4633. #define CAN_F5R2_FB13_Pos (13U)
  4634. #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
  4635. #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
  4636. #define CAN_F5R2_FB14_Pos (14U)
  4637. #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
  4638. #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
  4639. #define CAN_F5R2_FB15_Pos (15U)
  4640. #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
  4641. #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
  4642. #define CAN_F5R2_FB16_Pos (16U)
  4643. #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
  4644. #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
  4645. #define CAN_F5R2_FB17_Pos (17U)
  4646. #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
  4647. #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
  4648. #define CAN_F5R2_FB18_Pos (18U)
  4649. #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
  4650. #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
  4651. #define CAN_F5R2_FB19_Pos (19U)
  4652. #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
  4653. #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
  4654. #define CAN_F5R2_FB20_Pos (20U)
  4655. #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
  4656. #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
  4657. #define CAN_F5R2_FB21_Pos (21U)
  4658. #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
  4659. #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
  4660. #define CAN_F5R2_FB22_Pos (22U)
  4661. #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
  4662. #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
  4663. #define CAN_F5R2_FB23_Pos (23U)
  4664. #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
  4665. #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
  4666. #define CAN_F5R2_FB24_Pos (24U)
  4667. #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
  4668. #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
  4669. #define CAN_F5R2_FB25_Pos (25U)
  4670. #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
  4671. #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
  4672. #define CAN_F5R2_FB26_Pos (26U)
  4673. #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
  4674. #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
  4675. #define CAN_F5R2_FB27_Pos (27U)
  4676. #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
  4677. #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
  4678. #define CAN_F5R2_FB28_Pos (28U)
  4679. #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
  4680. #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
  4681. #define CAN_F5R2_FB29_Pos (29U)
  4682. #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
  4683. #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
  4684. #define CAN_F5R2_FB30_Pos (30U)
  4685. #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
  4686. #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
  4687. #define CAN_F5R2_FB31_Pos (31U)
  4688. #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
  4689. #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
  4690. /******************* Bit definition for CAN_F6R2 register *******************/
  4691. #define CAN_F6R2_FB0_Pos (0U)
  4692. #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
  4693. #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
  4694. #define CAN_F6R2_FB1_Pos (1U)
  4695. #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
  4696. #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
  4697. #define CAN_F6R2_FB2_Pos (2U)
  4698. #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
  4699. #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
  4700. #define CAN_F6R2_FB3_Pos (3U)
  4701. #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
  4702. #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
  4703. #define CAN_F6R2_FB4_Pos (4U)
  4704. #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
  4705. #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
  4706. #define CAN_F6R2_FB5_Pos (5U)
  4707. #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
  4708. #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
  4709. #define CAN_F6R2_FB6_Pos (6U)
  4710. #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
  4711. #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
  4712. #define CAN_F6R2_FB7_Pos (7U)
  4713. #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
  4714. #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
  4715. #define CAN_F6R2_FB8_Pos (8U)
  4716. #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
  4717. #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
  4718. #define CAN_F6R2_FB9_Pos (9U)
  4719. #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
  4720. #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
  4721. #define CAN_F6R2_FB10_Pos (10U)
  4722. #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
  4723. #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
  4724. #define CAN_F6R2_FB11_Pos (11U)
  4725. #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
  4726. #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
  4727. #define CAN_F6R2_FB12_Pos (12U)
  4728. #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
  4729. #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
  4730. #define CAN_F6R2_FB13_Pos (13U)
  4731. #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
  4732. #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
  4733. #define CAN_F6R2_FB14_Pos (14U)
  4734. #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
  4735. #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
  4736. #define CAN_F6R2_FB15_Pos (15U)
  4737. #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
  4738. #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
  4739. #define CAN_F6R2_FB16_Pos (16U)
  4740. #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
  4741. #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
  4742. #define CAN_F6R2_FB17_Pos (17U)
  4743. #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
  4744. #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
  4745. #define CAN_F6R2_FB18_Pos (18U)
  4746. #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
  4747. #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
  4748. #define CAN_F6R2_FB19_Pos (19U)
  4749. #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
  4750. #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
  4751. #define CAN_F6R2_FB20_Pos (20U)
  4752. #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
  4753. #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
  4754. #define CAN_F6R2_FB21_Pos (21U)
  4755. #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
  4756. #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
  4757. #define CAN_F6R2_FB22_Pos (22U)
  4758. #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
  4759. #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
  4760. #define CAN_F6R2_FB23_Pos (23U)
  4761. #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
  4762. #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
  4763. #define CAN_F6R2_FB24_Pos (24U)
  4764. #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
  4765. #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
  4766. #define CAN_F6R2_FB25_Pos (25U)
  4767. #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
  4768. #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
  4769. #define CAN_F6R2_FB26_Pos (26U)
  4770. #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
  4771. #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
  4772. #define CAN_F6R2_FB27_Pos (27U)
  4773. #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
  4774. #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
  4775. #define CAN_F6R2_FB28_Pos (28U)
  4776. #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
  4777. #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
  4778. #define CAN_F6R2_FB29_Pos (29U)
  4779. #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
  4780. #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
  4781. #define CAN_F6R2_FB30_Pos (30U)
  4782. #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
  4783. #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
  4784. #define CAN_F6R2_FB31_Pos (31U)
  4785. #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
  4786. #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
  4787. /******************* Bit definition for CAN_F7R2 register *******************/
  4788. #define CAN_F7R2_FB0_Pos (0U)
  4789. #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
  4790. #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
  4791. #define CAN_F7R2_FB1_Pos (1U)
  4792. #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
  4793. #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
  4794. #define CAN_F7R2_FB2_Pos (2U)
  4795. #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
  4796. #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
  4797. #define CAN_F7R2_FB3_Pos (3U)
  4798. #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
  4799. #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
  4800. #define CAN_F7R2_FB4_Pos (4U)
  4801. #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
  4802. #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
  4803. #define CAN_F7R2_FB5_Pos (5U)
  4804. #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
  4805. #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
  4806. #define CAN_F7R2_FB6_Pos (6U)
  4807. #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
  4808. #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
  4809. #define CAN_F7R2_FB7_Pos (7U)
  4810. #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
  4811. #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
  4812. #define CAN_F7R2_FB8_Pos (8U)
  4813. #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
  4814. #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
  4815. #define CAN_F7R2_FB9_Pos (9U)
  4816. #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
  4817. #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
  4818. #define CAN_F7R2_FB10_Pos (10U)
  4819. #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
  4820. #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
  4821. #define CAN_F7R2_FB11_Pos (11U)
  4822. #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
  4823. #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
  4824. #define CAN_F7R2_FB12_Pos (12U)
  4825. #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
  4826. #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
  4827. #define CAN_F7R2_FB13_Pos (13U)
  4828. #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
  4829. #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
  4830. #define CAN_F7R2_FB14_Pos (14U)
  4831. #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
  4832. #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
  4833. #define CAN_F7R2_FB15_Pos (15U)
  4834. #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
  4835. #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
  4836. #define CAN_F7R2_FB16_Pos (16U)
  4837. #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
  4838. #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
  4839. #define CAN_F7R2_FB17_Pos (17U)
  4840. #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
  4841. #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
  4842. #define CAN_F7R2_FB18_Pos (18U)
  4843. #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
  4844. #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
  4845. #define CAN_F7R2_FB19_Pos (19U)
  4846. #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
  4847. #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
  4848. #define CAN_F7R2_FB20_Pos (20U)
  4849. #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
  4850. #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
  4851. #define CAN_F7R2_FB21_Pos (21U)
  4852. #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
  4853. #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
  4854. #define CAN_F7R2_FB22_Pos (22U)
  4855. #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
  4856. #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
  4857. #define CAN_F7R2_FB23_Pos (23U)
  4858. #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
  4859. #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
  4860. #define CAN_F7R2_FB24_Pos (24U)
  4861. #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
  4862. #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
  4863. #define CAN_F7R2_FB25_Pos (25U)
  4864. #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
  4865. #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
  4866. #define CAN_F7R2_FB26_Pos (26U)
  4867. #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
  4868. #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
  4869. #define CAN_F7R2_FB27_Pos (27U)
  4870. #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
  4871. #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
  4872. #define CAN_F7R2_FB28_Pos (28U)
  4873. #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
  4874. #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
  4875. #define CAN_F7R2_FB29_Pos (29U)
  4876. #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
  4877. #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
  4878. #define CAN_F7R2_FB30_Pos (30U)
  4879. #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
  4880. #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
  4881. #define CAN_F7R2_FB31_Pos (31U)
  4882. #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
  4883. #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
  4884. /******************* Bit definition for CAN_F8R2 register *******************/
  4885. #define CAN_F8R2_FB0_Pos (0U)
  4886. #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
  4887. #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
  4888. #define CAN_F8R2_FB1_Pos (1U)
  4889. #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
  4890. #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
  4891. #define CAN_F8R2_FB2_Pos (2U)
  4892. #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
  4893. #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
  4894. #define CAN_F8R2_FB3_Pos (3U)
  4895. #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
  4896. #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
  4897. #define CAN_F8R2_FB4_Pos (4U)
  4898. #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
  4899. #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
  4900. #define CAN_F8R2_FB5_Pos (5U)
  4901. #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
  4902. #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
  4903. #define CAN_F8R2_FB6_Pos (6U)
  4904. #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
  4905. #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
  4906. #define CAN_F8R2_FB7_Pos (7U)
  4907. #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
  4908. #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
  4909. #define CAN_F8R2_FB8_Pos (8U)
  4910. #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
  4911. #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
  4912. #define CAN_F8R2_FB9_Pos (9U)
  4913. #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
  4914. #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
  4915. #define CAN_F8R2_FB10_Pos (10U)
  4916. #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
  4917. #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
  4918. #define CAN_F8R2_FB11_Pos (11U)
  4919. #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
  4920. #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
  4921. #define CAN_F8R2_FB12_Pos (12U)
  4922. #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
  4923. #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
  4924. #define CAN_F8R2_FB13_Pos (13U)
  4925. #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
  4926. #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
  4927. #define CAN_F8R2_FB14_Pos (14U)
  4928. #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
  4929. #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
  4930. #define CAN_F8R2_FB15_Pos (15U)
  4931. #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
  4932. #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
  4933. #define CAN_F8R2_FB16_Pos (16U)
  4934. #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
  4935. #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
  4936. #define CAN_F8R2_FB17_Pos (17U)
  4937. #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
  4938. #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
  4939. #define CAN_F8R2_FB18_Pos (18U)
  4940. #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
  4941. #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
  4942. #define CAN_F8R2_FB19_Pos (19U)
  4943. #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
  4944. #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
  4945. #define CAN_F8R2_FB20_Pos (20U)
  4946. #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
  4947. #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
  4948. #define CAN_F8R2_FB21_Pos (21U)
  4949. #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
  4950. #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
  4951. #define CAN_F8R2_FB22_Pos (22U)
  4952. #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
  4953. #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
  4954. #define CAN_F8R2_FB23_Pos (23U)
  4955. #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
  4956. #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
  4957. #define CAN_F8R2_FB24_Pos (24U)
  4958. #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
  4959. #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
  4960. #define CAN_F8R2_FB25_Pos (25U)
  4961. #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
  4962. #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
  4963. #define CAN_F8R2_FB26_Pos (26U)
  4964. #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
  4965. #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
  4966. #define CAN_F8R2_FB27_Pos (27U)
  4967. #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
  4968. #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
  4969. #define CAN_F8R2_FB28_Pos (28U)
  4970. #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
  4971. #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
  4972. #define CAN_F8R2_FB29_Pos (29U)
  4973. #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
  4974. #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
  4975. #define CAN_F8R2_FB30_Pos (30U)
  4976. #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
  4977. #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
  4978. #define CAN_F8R2_FB31_Pos (31U)
  4979. #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
  4980. #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
  4981. /******************* Bit definition for CAN_F9R2 register *******************/
  4982. #define CAN_F9R2_FB0_Pos (0U)
  4983. #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
  4984. #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
  4985. #define CAN_F9R2_FB1_Pos (1U)
  4986. #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
  4987. #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
  4988. #define CAN_F9R2_FB2_Pos (2U)
  4989. #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
  4990. #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
  4991. #define CAN_F9R2_FB3_Pos (3U)
  4992. #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
  4993. #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
  4994. #define CAN_F9R2_FB4_Pos (4U)
  4995. #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
  4996. #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
  4997. #define CAN_F9R2_FB5_Pos (5U)
  4998. #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
  4999. #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
  5000. #define CAN_F9R2_FB6_Pos (6U)
  5001. #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
  5002. #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
  5003. #define CAN_F9R2_FB7_Pos (7U)
  5004. #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
  5005. #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
  5006. #define CAN_F9R2_FB8_Pos (8U)
  5007. #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
  5008. #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
  5009. #define CAN_F9R2_FB9_Pos (9U)
  5010. #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
  5011. #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
  5012. #define CAN_F9R2_FB10_Pos (10U)
  5013. #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
  5014. #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
  5015. #define CAN_F9R2_FB11_Pos (11U)
  5016. #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
  5017. #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
  5018. #define CAN_F9R2_FB12_Pos (12U)
  5019. #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
  5020. #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
  5021. #define CAN_F9R2_FB13_Pos (13U)
  5022. #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
  5023. #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
  5024. #define CAN_F9R2_FB14_Pos (14U)
  5025. #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
  5026. #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
  5027. #define CAN_F9R2_FB15_Pos (15U)
  5028. #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
  5029. #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
  5030. #define CAN_F9R2_FB16_Pos (16U)
  5031. #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
  5032. #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
  5033. #define CAN_F9R2_FB17_Pos (17U)
  5034. #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
  5035. #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
  5036. #define CAN_F9R2_FB18_Pos (18U)
  5037. #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
  5038. #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
  5039. #define CAN_F9R2_FB19_Pos (19U)
  5040. #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
  5041. #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
  5042. #define CAN_F9R2_FB20_Pos (20U)
  5043. #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
  5044. #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
  5045. #define CAN_F9R2_FB21_Pos (21U)
  5046. #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
  5047. #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
  5048. #define CAN_F9R2_FB22_Pos (22U)
  5049. #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
  5050. #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
  5051. #define CAN_F9R2_FB23_Pos (23U)
  5052. #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
  5053. #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
  5054. #define CAN_F9R2_FB24_Pos (24U)
  5055. #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
  5056. #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
  5057. #define CAN_F9R2_FB25_Pos (25U)
  5058. #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
  5059. #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
  5060. #define CAN_F9R2_FB26_Pos (26U)
  5061. #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
  5062. #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
  5063. #define CAN_F9R2_FB27_Pos (27U)
  5064. #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
  5065. #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
  5066. #define CAN_F9R2_FB28_Pos (28U)
  5067. #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
  5068. #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
  5069. #define CAN_F9R2_FB29_Pos (29U)
  5070. #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
  5071. #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
  5072. #define CAN_F9R2_FB30_Pos (30U)
  5073. #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
  5074. #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
  5075. #define CAN_F9R2_FB31_Pos (31U)
  5076. #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
  5077. #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
  5078. /******************* Bit definition for CAN_F10R2 register ******************/
  5079. #define CAN_F10R2_FB0_Pos (0U)
  5080. #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
  5081. #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
  5082. #define CAN_F10R2_FB1_Pos (1U)
  5083. #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
  5084. #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
  5085. #define CAN_F10R2_FB2_Pos (2U)
  5086. #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
  5087. #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
  5088. #define CAN_F10R2_FB3_Pos (3U)
  5089. #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
  5090. #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
  5091. #define CAN_F10R2_FB4_Pos (4U)
  5092. #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
  5093. #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
  5094. #define CAN_F10R2_FB5_Pos (5U)
  5095. #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
  5096. #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
  5097. #define CAN_F10R2_FB6_Pos (6U)
  5098. #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
  5099. #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
  5100. #define CAN_F10R2_FB7_Pos (7U)
  5101. #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
  5102. #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
  5103. #define CAN_F10R2_FB8_Pos (8U)
  5104. #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
  5105. #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
  5106. #define CAN_F10R2_FB9_Pos (9U)
  5107. #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
  5108. #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
  5109. #define CAN_F10R2_FB10_Pos (10U)
  5110. #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
  5111. #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
  5112. #define CAN_F10R2_FB11_Pos (11U)
  5113. #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
  5114. #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
  5115. #define CAN_F10R2_FB12_Pos (12U)
  5116. #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
  5117. #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
  5118. #define CAN_F10R2_FB13_Pos (13U)
  5119. #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
  5120. #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
  5121. #define CAN_F10R2_FB14_Pos (14U)
  5122. #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
  5123. #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
  5124. #define CAN_F10R2_FB15_Pos (15U)
  5125. #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
  5126. #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
  5127. #define CAN_F10R2_FB16_Pos (16U)
  5128. #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
  5129. #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
  5130. #define CAN_F10R2_FB17_Pos (17U)
  5131. #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
  5132. #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
  5133. #define CAN_F10R2_FB18_Pos (18U)
  5134. #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
  5135. #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
  5136. #define CAN_F10R2_FB19_Pos (19U)
  5137. #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
  5138. #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
  5139. #define CAN_F10R2_FB20_Pos (20U)
  5140. #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
  5141. #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
  5142. #define CAN_F10R2_FB21_Pos (21U)
  5143. #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
  5144. #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
  5145. #define CAN_F10R2_FB22_Pos (22U)
  5146. #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
  5147. #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
  5148. #define CAN_F10R2_FB23_Pos (23U)
  5149. #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
  5150. #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
  5151. #define CAN_F10R2_FB24_Pos (24U)
  5152. #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
  5153. #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
  5154. #define CAN_F10R2_FB25_Pos (25U)
  5155. #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
  5156. #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
  5157. #define CAN_F10R2_FB26_Pos (26U)
  5158. #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
  5159. #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
  5160. #define CAN_F10R2_FB27_Pos (27U)
  5161. #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
  5162. #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
  5163. #define CAN_F10R2_FB28_Pos (28U)
  5164. #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
  5165. #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
  5166. #define CAN_F10R2_FB29_Pos (29U)
  5167. #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
  5168. #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
  5169. #define CAN_F10R2_FB30_Pos (30U)
  5170. #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
  5171. #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
  5172. #define CAN_F10R2_FB31_Pos (31U)
  5173. #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
  5174. #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
  5175. /******************* Bit definition for CAN_F11R2 register ******************/
  5176. #define CAN_F11R2_FB0_Pos (0U)
  5177. #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
  5178. #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
  5179. #define CAN_F11R2_FB1_Pos (1U)
  5180. #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
  5181. #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
  5182. #define CAN_F11R2_FB2_Pos (2U)
  5183. #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
  5184. #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
  5185. #define CAN_F11R2_FB3_Pos (3U)
  5186. #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
  5187. #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
  5188. #define CAN_F11R2_FB4_Pos (4U)
  5189. #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
  5190. #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
  5191. #define CAN_F11R2_FB5_Pos (5U)
  5192. #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
  5193. #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
  5194. #define CAN_F11R2_FB6_Pos (6U)
  5195. #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
  5196. #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
  5197. #define CAN_F11R2_FB7_Pos (7U)
  5198. #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
  5199. #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
  5200. #define CAN_F11R2_FB8_Pos (8U)
  5201. #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
  5202. #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
  5203. #define CAN_F11R2_FB9_Pos (9U)
  5204. #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
  5205. #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
  5206. #define CAN_F11R2_FB10_Pos (10U)
  5207. #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
  5208. #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
  5209. #define CAN_F11R2_FB11_Pos (11U)
  5210. #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
  5211. #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
  5212. #define CAN_F11R2_FB12_Pos (12U)
  5213. #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
  5214. #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
  5215. #define CAN_F11R2_FB13_Pos (13U)
  5216. #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
  5217. #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
  5218. #define CAN_F11R2_FB14_Pos (14U)
  5219. #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
  5220. #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
  5221. #define CAN_F11R2_FB15_Pos (15U)
  5222. #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
  5223. #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
  5224. #define CAN_F11R2_FB16_Pos (16U)
  5225. #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
  5226. #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
  5227. #define CAN_F11R2_FB17_Pos (17U)
  5228. #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
  5229. #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
  5230. #define CAN_F11R2_FB18_Pos (18U)
  5231. #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
  5232. #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
  5233. #define CAN_F11R2_FB19_Pos (19U)
  5234. #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
  5235. #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
  5236. #define CAN_F11R2_FB20_Pos (20U)
  5237. #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
  5238. #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
  5239. #define CAN_F11R2_FB21_Pos (21U)
  5240. #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
  5241. #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
  5242. #define CAN_F11R2_FB22_Pos (22U)
  5243. #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
  5244. #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
  5245. #define CAN_F11R2_FB23_Pos (23U)
  5246. #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
  5247. #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
  5248. #define CAN_F11R2_FB24_Pos (24U)
  5249. #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
  5250. #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
  5251. #define CAN_F11R2_FB25_Pos (25U)
  5252. #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
  5253. #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
  5254. #define CAN_F11R2_FB26_Pos (26U)
  5255. #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
  5256. #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
  5257. #define CAN_F11R2_FB27_Pos (27U)
  5258. #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
  5259. #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
  5260. #define CAN_F11R2_FB28_Pos (28U)
  5261. #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
  5262. #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
  5263. #define CAN_F11R2_FB29_Pos (29U)
  5264. #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
  5265. #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
  5266. #define CAN_F11R2_FB30_Pos (30U)
  5267. #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
  5268. #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
  5269. #define CAN_F11R2_FB31_Pos (31U)
  5270. #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
  5271. #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
  5272. /******************* Bit definition for CAN_F12R2 register ******************/
  5273. #define CAN_F12R2_FB0_Pos (0U)
  5274. #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
  5275. #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
  5276. #define CAN_F12R2_FB1_Pos (1U)
  5277. #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
  5278. #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
  5279. #define CAN_F12R2_FB2_Pos (2U)
  5280. #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
  5281. #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
  5282. #define CAN_F12R2_FB3_Pos (3U)
  5283. #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
  5284. #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
  5285. #define CAN_F12R2_FB4_Pos (4U)
  5286. #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
  5287. #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
  5288. #define CAN_F12R2_FB5_Pos (5U)
  5289. #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
  5290. #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
  5291. #define CAN_F12R2_FB6_Pos (6U)
  5292. #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
  5293. #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
  5294. #define CAN_F12R2_FB7_Pos (7U)
  5295. #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
  5296. #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
  5297. #define CAN_F12R2_FB8_Pos (8U)
  5298. #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
  5299. #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
  5300. #define CAN_F12R2_FB9_Pos (9U)
  5301. #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
  5302. #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
  5303. #define CAN_F12R2_FB10_Pos (10U)
  5304. #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
  5305. #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
  5306. #define CAN_F12R2_FB11_Pos (11U)
  5307. #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
  5308. #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
  5309. #define CAN_F12R2_FB12_Pos (12U)
  5310. #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
  5311. #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
  5312. #define CAN_F12R2_FB13_Pos (13U)
  5313. #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
  5314. #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
  5315. #define CAN_F12R2_FB14_Pos (14U)
  5316. #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
  5317. #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
  5318. #define CAN_F12R2_FB15_Pos (15U)
  5319. #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
  5320. #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
  5321. #define CAN_F12R2_FB16_Pos (16U)
  5322. #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
  5323. #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
  5324. #define CAN_F12R2_FB17_Pos (17U)
  5325. #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
  5326. #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
  5327. #define CAN_F12R2_FB18_Pos (18U)
  5328. #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
  5329. #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
  5330. #define CAN_F12R2_FB19_Pos (19U)
  5331. #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
  5332. #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
  5333. #define CAN_F12R2_FB20_Pos (20U)
  5334. #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
  5335. #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
  5336. #define CAN_F12R2_FB21_Pos (21U)
  5337. #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
  5338. #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
  5339. #define CAN_F12R2_FB22_Pos (22U)
  5340. #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
  5341. #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
  5342. #define CAN_F12R2_FB23_Pos (23U)
  5343. #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
  5344. #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
  5345. #define CAN_F12R2_FB24_Pos (24U)
  5346. #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
  5347. #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
  5348. #define CAN_F12R2_FB25_Pos (25U)
  5349. #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
  5350. #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
  5351. #define CAN_F12R2_FB26_Pos (26U)
  5352. #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
  5353. #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
  5354. #define CAN_F12R2_FB27_Pos (27U)
  5355. #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
  5356. #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
  5357. #define CAN_F12R2_FB28_Pos (28U)
  5358. #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
  5359. #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
  5360. #define CAN_F12R2_FB29_Pos (29U)
  5361. #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
  5362. #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
  5363. #define CAN_F12R2_FB30_Pos (30U)
  5364. #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
  5365. #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
  5366. #define CAN_F12R2_FB31_Pos (31U)
  5367. #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
  5368. #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
  5369. /******************* Bit definition for CAN_F13R2 register ******************/
  5370. #define CAN_F13R2_FB0_Pos (0U)
  5371. #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
  5372. #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
  5373. #define CAN_F13R2_FB1_Pos (1U)
  5374. #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
  5375. #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
  5376. #define CAN_F13R2_FB2_Pos (2U)
  5377. #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
  5378. #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
  5379. #define CAN_F13R2_FB3_Pos (3U)
  5380. #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
  5381. #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
  5382. #define CAN_F13R2_FB4_Pos (4U)
  5383. #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
  5384. #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
  5385. #define CAN_F13R2_FB5_Pos (5U)
  5386. #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
  5387. #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
  5388. #define CAN_F13R2_FB6_Pos (6U)
  5389. #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
  5390. #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
  5391. #define CAN_F13R2_FB7_Pos (7U)
  5392. #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
  5393. #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
  5394. #define CAN_F13R2_FB8_Pos (8U)
  5395. #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
  5396. #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
  5397. #define CAN_F13R2_FB9_Pos (9U)
  5398. #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
  5399. #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
  5400. #define CAN_F13R2_FB10_Pos (10U)
  5401. #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
  5402. #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
  5403. #define CAN_F13R2_FB11_Pos (11U)
  5404. #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
  5405. #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
  5406. #define CAN_F13R2_FB12_Pos (12U)
  5407. #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
  5408. #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
  5409. #define CAN_F13R2_FB13_Pos (13U)
  5410. #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
  5411. #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
  5412. #define CAN_F13R2_FB14_Pos (14U)
  5413. #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
  5414. #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
  5415. #define CAN_F13R2_FB15_Pos (15U)
  5416. #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
  5417. #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
  5418. #define CAN_F13R2_FB16_Pos (16U)
  5419. #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
  5420. #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
  5421. #define CAN_F13R2_FB17_Pos (17U)
  5422. #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
  5423. #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
  5424. #define CAN_F13R2_FB18_Pos (18U)
  5425. #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
  5426. #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
  5427. #define CAN_F13R2_FB19_Pos (19U)
  5428. #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
  5429. #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
  5430. #define CAN_F13R2_FB20_Pos (20U)
  5431. #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
  5432. #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
  5433. #define CAN_F13R2_FB21_Pos (21U)
  5434. #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
  5435. #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
  5436. #define CAN_F13R2_FB22_Pos (22U)
  5437. #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
  5438. #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
  5439. #define CAN_F13R2_FB23_Pos (23U)
  5440. #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
  5441. #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
  5442. #define CAN_F13R2_FB24_Pos (24U)
  5443. #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
  5444. #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
  5445. #define CAN_F13R2_FB25_Pos (25U)
  5446. #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
  5447. #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
  5448. #define CAN_F13R2_FB26_Pos (26U)
  5449. #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
  5450. #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
  5451. #define CAN_F13R2_FB27_Pos (27U)
  5452. #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
  5453. #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
  5454. #define CAN_F13R2_FB28_Pos (28U)
  5455. #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
  5456. #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
  5457. #define CAN_F13R2_FB29_Pos (29U)
  5458. #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
  5459. #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
  5460. #define CAN_F13R2_FB30_Pos (30U)
  5461. #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
  5462. #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
  5463. #define CAN_F13R2_FB31_Pos (31U)
  5464. #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
  5465. #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
  5466. /******************************************************************************/
  5467. /* */
  5468. /* CRC calculation unit */
  5469. /* */
  5470. /******************************************************************************/
  5471. /******************* Bit definition for CRC_DR register *********************/
  5472. #define CRC_DR_DR_Pos (0U)
  5473. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  5474. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  5475. /******************* Bit definition for CRC_IDR register ********************/
  5476. #define CRC_IDR_IDR_Pos (0U)
  5477. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  5478. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  5479. /******************** Bit definition for CRC_CR register ********************/
  5480. #define CRC_CR_RESET_Pos (0U)
  5481. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  5482. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  5483. /******************************************************************************/
  5484. /* */
  5485. /* Digital to Analog Converter */
  5486. /* */
  5487. /******************************************************************************/
  5488. /*
  5489. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  5490. */
  5491. #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
  5492. /******************** Bit definition for DAC_CR register ********************/
  5493. #define DAC_CR_EN1_Pos (0U)
  5494. #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
  5495. #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
  5496. #define DAC_CR_BOFF1_Pos (1U)
  5497. #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
  5498. #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
  5499. #define DAC_CR_TEN1_Pos (2U)
  5500. #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
  5501. #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
  5502. #define DAC_CR_TSEL1_Pos (3U)
  5503. #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
  5504. #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
  5505. #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
  5506. #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
  5507. #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
  5508. #define DAC_CR_WAVE1_Pos (6U)
  5509. #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
  5510. #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  5511. #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
  5512. #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
  5513. #define DAC_CR_MAMP1_Pos (8U)
  5514. #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
  5515. #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  5516. #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
  5517. #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
  5518. #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
  5519. #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
  5520. #define DAC_CR_DMAEN1_Pos (12U)
  5521. #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
  5522. #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
  5523. #define DAC_CR_DMAUDRIE1_Pos (13U)
  5524. #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
  5525. #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
  5526. #define DAC_CR_EN2_Pos (16U)
  5527. #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
  5528. #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
  5529. #define DAC_CR_BOFF2_Pos (17U)
  5530. #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
  5531. #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
  5532. #define DAC_CR_TEN2_Pos (18U)
  5533. #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
  5534. #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
  5535. #define DAC_CR_TSEL2_Pos (19U)
  5536. #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
  5537. #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
  5538. #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
  5539. #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
  5540. #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
  5541. #define DAC_CR_WAVE2_Pos (22U)
  5542. #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
  5543. #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  5544. #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
  5545. #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
  5546. #define DAC_CR_MAMP2_Pos (24U)
  5547. #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
  5548. #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  5549. #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
  5550. #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
  5551. #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
  5552. #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
  5553. #define DAC_CR_DMAEN2_Pos (28U)
  5554. #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
  5555. #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
  5556. #define DAC_CR_DMAUDRIE2_Pos (29U)
  5557. #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
  5558. #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
  5559. /***************** Bit definition for DAC_SWTRIGR register ******************/
  5560. #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
  5561. #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
  5562. #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
  5563. #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
  5564. #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
  5565. #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
  5566. /***************** Bit definition for DAC_DHR12R1 register ******************/
  5567. #define DAC_DHR12R1_DACC1DHR_Pos (0U)
  5568. #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
  5569. #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5570. /***************** Bit definition for DAC_DHR12L1 register ******************/
  5571. #define DAC_DHR12L1_DACC1DHR_Pos (4U)
  5572. #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5573. #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5574. /****************** Bit definition for DAC_DHR8R1 register ******************/
  5575. #define DAC_DHR8R1_DACC1DHR_Pos (0U)
  5576. #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
  5577. #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5578. /***************** Bit definition for DAC_DHR12R2 register ******************/
  5579. #define DAC_DHR12R2_DACC2DHR_Pos (0U)
  5580. #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
  5581. #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5582. /***************** Bit definition for DAC_DHR12L2 register ******************/
  5583. #define DAC_DHR12L2_DACC2DHR_Pos (4U)
  5584. #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
  5585. #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5586. /****************** Bit definition for DAC_DHR8R2 register ******************/
  5587. #define DAC_DHR8R2_DACC2DHR_Pos (0U)
  5588. #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
  5589. #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5590. /***************** Bit definition for DAC_DHR12RD register ******************/
  5591. #define DAC_DHR12RD_DACC1DHR_Pos (0U)
  5592. #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
  5593. #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5594. #define DAC_DHR12RD_DACC2DHR_Pos (16U)
  5595. #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
  5596. #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5597. /***************** Bit definition for DAC_DHR12LD register ******************/
  5598. #define DAC_DHR12LD_DACC1DHR_Pos (4U)
  5599. #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5600. #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5601. #define DAC_DHR12LD_DACC2DHR_Pos (20U)
  5602. #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
  5603. #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5604. /****************** Bit definition for DAC_DHR8RD register ******************/
  5605. #define DAC_DHR8RD_DACC1DHR_Pos (0U)
  5606. #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
  5607. #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5608. #define DAC_DHR8RD_DACC2DHR_Pos (8U)
  5609. #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
  5610. #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5611. /******************* Bit definition for DAC_DOR1 register *******************/
  5612. #define DAC_DOR1_DACC1DOR_Pos (0U)
  5613. #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
  5614. #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
  5615. /******************* Bit definition for DAC_DOR2 register *******************/
  5616. #define DAC_DOR2_DACC2DOR_Pos (0U)
  5617. #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
  5618. #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
  5619. /******************** Bit definition for DAC_SR register ********************/
  5620. #define DAC_SR_DMAUDR1_Pos (13U)
  5621. #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
  5622. #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
  5623. #define DAC_SR_DMAUDR2_Pos (29U)
  5624. #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
  5625. #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
  5626. /******************************************************************************/
  5627. /* */
  5628. /* DCMI */
  5629. /* */
  5630. /******************************************************************************/
  5631. /******************** Bits definition for DCMI_CR register ******************/
  5632. #define DCMI_CR_CAPTURE_Pos (0U)
  5633. #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
  5634. #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
  5635. #define DCMI_CR_CM_Pos (1U)
  5636. #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
  5637. #define DCMI_CR_CM DCMI_CR_CM_Msk
  5638. #define DCMI_CR_CROP_Pos (2U)
  5639. #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
  5640. #define DCMI_CR_CROP DCMI_CR_CROP_Msk
  5641. #define DCMI_CR_JPEG_Pos (3U)
  5642. #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
  5643. #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
  5644. #define DCMI_CR_ESS_Pos (4U)
  5645. #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
  5646. #define DCMI_CR_ESS DCMI_CR_ESS_Msk
  5647. #define DCMI_CR_PCKPOL_Pos (5U)
  5648. #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
  5649. #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
  5650. #define DCMI_CR_HSPOL_Pos (6U)
  5651. #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
  5652. #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
  5653. #define DCMI_CR_VSPOL_Pos (7U)
  5654. #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
  5655. #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
  5656. #define DCMI_CR_FCRC_0 0x00000100U
  5657. #define DCMI_CR_FCRC_1 0x00000200U
  5658. #define DCMI_CR_EDM_0 0x00000400U
  5659. #define DCMI_CR_EDM_1 0x00000800U
  5660. #define DCMI_CR_OUTEN_Pos (13U)
  5661. #define DCMI_CR_OUTEN_Msk (0x1UL << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
  5662. #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
  5663. #define DCMI_CR_ENABLE_Pos (14U)
  5664. #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
  5665. #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
  5666. #define DCMI_CR_BSM_0 0x00010000U
  5667. #define DCMI_CR_BSM_1 0x00020000U
  5668. #define DCMI_CR_OEBS_Pos (18U)
  5669. #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
  5670. #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
  5671. #define DCMI_CR_LSM_Pos (19U)
  5672. #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
  5673. #define DCMI_CR_LSM DCMI_CR_LSM_Msk
  5674. #define DCMI_CR_OELS_Pos (20U)
  5675. #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
  5676. #define DCMI_CR_OELS DCMI_CR_OELS_Msk
  5677. /******************** Bits definition for DCMI_SR register ******************/
  5678. #define DCMI_SR_HSYNC_Pos (0U)
  5679. #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
  5680. #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
  5681. #define DCMI_SR_VSYNC_Pos (1U)
  5682. #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
  5683. #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
  5684. #define DCMI_SR_FNE_Pos (2U)
  5685. #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
  5686. #define DCMI_SR_FNE DCMI_SR_FNE_Msk
  5687. /******************** Bits definition for DCMI_RIS register *****************/
  5688. #define DCMI_RIS_FRAME_RIS_Pos (0U)
  5689. #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
  5690. #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
  5691. #define DCMI_RIS_OVR_RIS_Pos (1U)
  5692. #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
  5693. #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
  5694. #define DCMI_RIS_ERR_RIS_Pos (2U)
  5695. #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
  5696. #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
  5697. #define DCMI_RIS_VSYNC_RIS_Pos (3U)
  5698. #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
  5699. #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
  5700. #define DCMI_RIS_LINE_RIS_Pos (4U)
  5701. #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
  5702. #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
  5703. /* Legacy defines */
  5704. #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
  5705. #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
  5706. #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
  5707. #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
  5708. #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
  5709. #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
  5710. /******************** Bits definition for DCMI_IER register *****************/
  5711. #define DCMI_IER_FRAME_IE_Pos (0U)
  5712. #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
  5713. #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
  5714. #define DCMI_IER_OVR_IE_Pos (1U)
  5715. #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
  5716. #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
  5717. #define DCMI_IER_ERR_IE_Pos (2U)
  5718. #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
  5719. #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
  5720. #define DCMI_IER_VSYNC_IE_Pos (3U)
  5721. #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
  5722. #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
  5723. #define DCMI_IER_LINE_IE_Pos (4U)
  5724. #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
  5725. #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
  5726. /* Legacy defines */
  5727. #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
  5728. /******************** Bits definition for DCMI_MIS register *****************/
  5729. #define DCMI_MIS_FRAME_MIS_Pos (0U)
  5730. #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
  5731. #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
  5732. #define DCMI_MIS_OVR_MIS_Pos (1U)
  5733. #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
  5734. #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
  5735. #define DCMI_MIS_ERR_MIS_Pos (2U)
  5736. #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
  5737. #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
  5738. #define DCMI_MIS_VSYNC_MIS_Pos (3U)
  5739. #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
  5740. #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
  5741. #define DCMI_MIS_LINE_MIS_Pos (4U)
  5742. #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
  5743. #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
  5744. /* Legacy defines */
  5745. #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
  5746. #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
  5747. #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
  5748. #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
  5749. #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
  5750. /******************** Bits definition for DCMI_ICR register *****************/
  5751. #define DCMI_ICR_FRAME_ISC_Pos (0U)
  5752. #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
  5753. #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
  5754. #define DCMI_ICR_OVR_ISC_Pos (1U)
  5755. #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
  5756. #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
  5757. #define DCMI_ICR_ERR_ISC_Pos (2U)
  5758. #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
  5759. #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
  5760. #define DCMI_ICR_VSYNC_ISC_Pos (3U)
  5761. #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
  5762. #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
  5763. #define DCMI_ICR_LINE_ISC_Pos (4U)
  5764. #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
  5765. #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
  5766. /* Legacy defines */
  5767. #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
  5768. /******************** Bits definition for DCMI_ESCR register ******************/
  5769. #define DCMI_ESCR_FSC_Pos (0U)
  5770. #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
  5771. #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
  5772. #define DCMI_ESCR_LSC_Pos (8U)
  5773. #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
  5774. #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
  5775. #define DCMI_ESCR_LEC_Pos (16U)
  5776. #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
  5777. #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
  5778. #define DCMI_ESCR_FEC_Pos (24U)
  5779. #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
  5780. #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
  5781. /******************** Bits definition for DCMI_ESUR register ******************/
  5782. #define DCMI_ESUR_FSU_Pos (0U)
  5783. #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
  5784. #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
  5785. #define DCMI_ESUR_LSU_Pos (8U)
  5786. #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
  5787. #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
  5788. #define DCMI_ESUR_LEU_Pos (16U)
  5789. #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
  5790. #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
  5791. #define DCMI_ESUR_FEU_Pos (24U)
  5792. #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
  5793. #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
  5794. /******************** Bits definition for DCMI_CWSTRT register ******************/
  5795. #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
  5796. #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
  5797. #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
  5798. #define DCMI_CWSTRT_VST_Pos (16U)
  5799. #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
  5800. #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
  5801. /******************** Bits definition for DCMI_CWSIZE register ******************/
  5802. #define DCMI_CWSIZE_CAPCNT_Pos (0U)
  5803. #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
  5804. #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
  5805. #define DCMI_CWSIZE_VLINE_Pos (16U)
  5806. #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
  5807. #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
  5808. /******************** Bits definition for DCMI_DR register *********************/
  5809. #define DCMI_DR_BYTE0_Pos (0U)
  5810. #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
  5811. #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
  5812. #define DCMI_DR_BYTE1_Pos (8U)
  5813. #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
  5814. #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
  5815. #define DCMI_DR_BYTE2_Pos (16U)
  5816. #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
  5817. #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
  5818. #define DCMI_DR_BYTE3_Pos (24U)
  5819. #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
  5820. #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
  5821. /******************************************************************************/
  5822. /* */
  5823. /* DMA Controller */
  5824. /* */
  5825. /******************************************************************************/
  5826. /******************** Bits definition for DMA_SxCR register *****************/
  5827. #define DMA_SxCR_CHSEL_Pos (25U)
  5828. #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
  5829. #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
  5830. #define DMA_SxCR_CHSEL_0 0x02000000U
  5831. #define DMA_SxCR_CHSEL_1 0x04000000U
  5832. #define DMA_SxCR_CHSEL_2 0x08000000U
  5833. #define DMA_SxCR_MBURST_Pos (23U)
  5834. #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
  5835. #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
  5836. #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
  5837. #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
  5838. #define DMA_SxCR_PBURST_Pos (21U)
  5839. #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
  5840. #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
  5841. #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
  5842. #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
  5843. #define DMA_SxCR_CT_Pos (19U)
  5844. #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
  5845. #define DMA_SxCR_CT DMA_SxCR_CT_Msk
  5846. #define DMA_SxCR_DBM_Pos (18U)
  5847. #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
  5848. #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
  5849. #define DMA_SxCR_PL_Pos (16U)
  5850. #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
  5851. #define DMA_SxCR_PL DMA_SxCR_PL_Msk
  5852. #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
  5853. #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
  5854. #define DMA_SxCR_PINCOS_Pos (15U)
  5855. #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
  5856. #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
  5857. #define DMA_SxCR_MSIZE_Pos (13U)
  5858. #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
  5859. #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
  5860. #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
  5861. #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
  5862. #define DMA_SxCR_PSIZE_Pos (11U)
  5863. #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
  5864. #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
  5865. #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
  5866. #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
  5867. #define DMA_SxCR_MINC_Pos (10U)
  5868. #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
  5869. #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
  5870. #define DMA_SxCR_PINC_Pos (9U)
  5871. #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
  5872. #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
  5873. #define DMA_SxCR_CIRC_Pos (8U)
  5874. #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
  5875. #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
  5876. #define DMA_SxCR_DIR_Pos (6U)
  5877. #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
  5878. #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
  5879. #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
  5880. #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
  5881. #define DMA_SxCR_PFCTRL_Pos (5U)
  5882. #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
  5883. #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
  5884. #define DMA_SxCR_TCIE_Pos (4U)
  5885. #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
  5886. #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
  5887. #define DMA_SxCR_HTIE_Pos (3U)
  5888. #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
  5889. #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
  5890. #define DMA_SxCR_TEIE_Pos (2U)
  5891. #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
  5892. #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
  5893. #define DMA_SxCR_DMEIE_Pos (1U)
  5894. #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
  5895. #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
  5896. #define DMA_SxCR_EN_Pos (0U)
  5897. #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
  5898. #define DMA_SxCR_EN DMA_SxCR_EN_Msk
  5899. /* Legacy defines */
  5900. #define DMA_SxCR_ACK_Pos (20U)
  5901. #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
  5902. #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
  5903. /******************** Bits definition for DMA_SxCNDTR register **************/
  5904. #define DMA_SxNDT_Pos (0U)
  5905. #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
  5906. #define DMA_SxNDT DMA_SxNDT_Msk
  5907. #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
  5908. #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
  5909. #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
  5910. #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
  5911. #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
  5912. #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
  5913. #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
  5914. #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
  5915. #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
  5916. #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
  5917. #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
  5918. #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
  5919. #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
  5920. #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
  5921. #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
  5922. #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
  5923. /******************** Bits definition for DMA_SxFCR register ****************/
  5924. #define DMA_SxFCR_FEIE_Pos (7U)
  5925. #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
  5926. #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
  5927. #define DMA_SxFCR_FS_Pos (3U)
  5928. #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
  5929. #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
  5930. #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
  5931. #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
  5932. #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
  5933. #define DMA_SxFCR_DMDIS_Pos (2U)
  5934. #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
  5935. #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
  5936. #define DMA_SxFCR_FTH_Pos (0U)
  5937. #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
  5938. #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
  5939. #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
  5940. #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
  5941. /******************** Bits definition for DMA_LISR register *****************/
  5942. #define DMA_LISR_TCIF3_Pos (27U)
  5943. #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
  5944. #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
  5945. #define DMA_LISR_HTIF3_Pos (26U)
  5946. #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
  5947. #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
  5948. #define DMA_LISR_TEIF3_Pos (25U)
  5949. #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
  5950. #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
  5951. #define DMA_LISR_DMEIF3_Pos (24U)
  5952. #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
  5953. #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
  5954. #define DMA_LISR_FEIF3_Pos (22U)
  5955. #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
  5956. #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
  5957. #define DMA_LISR_TCIF2_Pos (21U)
  5958. #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
  5959. #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
  5960. #define DMA_LISR_HTIF2_Pos (20U)
  5961. #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
  5962. #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
  5963. #define DMA_LISR_TEIF2_Pos (19U)
  5964. #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
  5965. #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
  5966. #define DMA_LISR_DMEIF2_Pos (18U)
  5967. #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
  5968. #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
  5969. #define DMA_LISR_FEIF2_Pos (16U)
  5970. #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
  5971. #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
  5972. #define DMA_LISR_TCIF1_Pos (11U)
  5973. #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
  5974. #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
  5975. #define DMA_LISR_HTIF1_Pos (10U)
  5976. #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
  5977. #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
  5978. #define DMA_LISR_TEIF1_Pos (9U)
  5979. #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
  5980. #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
  5981. #define DMA_LISR_DMEIF1_Pos (8U)
  5982. #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
  5983. #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
  5984. #define DMA_LISR_FEIF1_Pos (6U)
  5985. #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
  5986. #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
  5987. #define DMA_LISR_TCIF0_Pos (5U)
  5988. #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
  5989. #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
  5990. #define DMA_LISR_HTIF0_Pos (4U)
  5991. #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
  5992. #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
  5993. #define DMA_LISR_TEIF0_Pos (3U)
  5994. #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
  5995. #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
  5996. #define DMA_LISR_DMEIF0_Pos (2U)
  5997. #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
  5998. #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
  5999. #define DMA_LISR_FEIF0_Pos (0U)
  6000. #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
  6001. #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
  6002. /******************** Bits definition for DMA_HISR register *****************/
  6003. #define DMA_HISR_TCIF7_Pos (27U)
  6004. #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
  6005. #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
  6006. #define DMA_HISR_HTIF7_Pos (26U)
  6007. #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
  6008. #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
  6009. #define DMA_HISR_TEIF7_Pos (25U)
  6010. #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
  6011. #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
  6012. #define DMA_HISR_DMEIF7_Pos (24U)
  6013. #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
  6014. #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
  6015. #define DMA_HISR_FEIF7_Pos (22U)
  6016. #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
  6017. #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
  6018. #define DMA_HISR_TCIF6_Pos (21U)
  6019. #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
  6020. #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
  6021. #define DMA_HISR_HTIF6_Pos (20U)
  6022. #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
  6023. #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
  6024. #define DMA_HISR_TEIF6_Pos (19U)
  6025. #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
  6026. #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
  6027. #define DMA_HISR_DMEIF6_Pos (18U)
  6028. #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
  6029. #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
  6030. #define DMA_HISR_FEIF6_Pos (16U)
  6031. #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
  6032. #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
  6033. #define DMA_HISR_TCIF5_Pos (11U)
  6034. #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
  6035. #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
  6036. #define DMA_HISR_HTIF5_Pos (10U)
  6037. #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
  6038. #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
  6039. #define DMA_HISR_TEIF5_Pos (9U)
  6040. #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
  6041. #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
  6042. #define DMA_HISR_DMEIF5_Pos (8U)
  6043. #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
  6044. #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
  6045. #define DMA_HISR_FEIF5_Pos (6U)
  6046. #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
  6047. #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
  6048. #define DMA_HISR_TCIF4_Pos (5U)
  6049. #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
  6050. #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
  6051. #define DMA_HISR_HTIF4_Pos (4U)
  6052. #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
  6053. #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
  6054. #define DMA_HISR_TEIF4_Pos (3U)
  6055. #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
  6056. #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
  6057. #define DMA_HISR_DMEIF4_Pos (2U)
  6058. #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
  6059. #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
  6060. #define DMA_HISR_FEIF4_Pos (0U)
  6061. #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
  6062. #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
  6063. /******************** Bits definition for DMA_LIFCR register ****************/
  6064. #define DMA_LIFCR_CTCIF3_Pos (27U)
  6065. #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
  6066. #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
  6067. #define DMA_LIFCR_CHTIF3_Pos (26U)
  6068. #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
  6069. #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
  6070. #define DMA_LIFCR_CTEIF3_Pos (25U)
  6071. #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
  6072. #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
  6073. #define DMA_LIFCR_CDMEIF3_Pos (24U)
  6074. #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
  6075. #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
  6076. #define DMA_LIFCR_CFEIF3_Pos (22U)
  6077. #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
  6078. #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
  6079. #define DMA_LIFCR_CTCIF2_Pos (21U)
  6080. #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
  6081. #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
  6082. #define DMA_LIFCR_CHTIF2_Pos (20U)
  6083. #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
  6084. #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
  6085. #define DMA_LIFCR_CTEIF2_Pos (19U)
  6086. #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
  6087. #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
  6088. #define DMA_LIFCR_CDMEIF2_Pos (18U)
  6089. #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
  6090. #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
  6091. #define DMA_LIFCR_CFEIF2_Pos (16U)
  6092. #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
  6093. #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
  6094. #define DMA_LIFCR_CTCIF1_Pos (11U)
  6095. #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
  6096. #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
  6097. #define DMA_LIFCR_CHTIF1_Pos (10U)
  6098. #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
  6099. #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
  6100. #define DMA_LIFCR_CTEIF1_Pos (9U)
  6101. #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
  6102. #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
  6103. #define DMA_LIFCR_CDMEIF1_Pos (8U)
  6104. #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
  6105. #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
  6106. #define DMA_LIFCR_CFEIF1_Pos (6U)
  6107. #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
  6108. #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
  6109. #define DMA_LIFCR_CTCIF0_Pos (5U)
  6110. #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
  6111. #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
  6112. #define DMA_LIFCR_CHTIF0_Pos (4U)
  6113. #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
  6114. #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
  6115. #define DMA_LIFCR_CTEIF0_Pos (3U)
  6116. #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
  6117. #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
  6118. #define DMA_LIFCR_CDMEIF0_Pos (2U)
  6119. #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
  6120. #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
  6121. #define DMA_LIFCR_CFEIF0_Pos (0U)
  6122. #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
  6123. #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
  6124. /******************** Bits definition for DMA_HIFCR register ****************/
  6125. #define DMA_HIFCR_CTCIF7_Pos (27U)
  6126. #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
  6127. #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
  6128. #define DMA_HIFCR_CHTIF7_Pos (26U)
  6129. #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
  6130. #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
  6131. #define DMA_HIFCR_CTEIF7_Pos (25U)
  6132. #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
  6133. #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
  6134. #define DMA_HIFCR_CDMEIF7_Pos (24U)
  6135. #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
  6136. #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
  6137. #define DMA_HIFCR_CFEIF7_Pos (22U)
  6138. #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
  6139. #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
  6140. #define DMA_HIFCR_CTCIF6_Pos (21U)
  6141. #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
  6142. #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
  6143. #define DMA_HIFCR_CHTIF6_Pos (20U)
  6144. #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
  6145. #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
  6146. #define DMA_HIFCR_CTEIF6_Pos (19U)
  6147. #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
  6148. #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
  6149. #define DMA_HIFCR_CDMEIF6_Pos (18U)
  6150. #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
  6151. #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
  6152. #define DMA_HIFCR_CFEIF6_Pos (16U)
  6153. #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
  6154. #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
  6155. #define DMA_HIFCR_CTCIF5_Pos (11U)
  6156. #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
  6157. #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
  6158. #define DMA_HIFCR_CHTIF5_Pos (10U)
  6159. #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
  6160. #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
  6161. #define DMA_HIFCR_CTEIF5_Pos (9U)
  6162. #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
  6163. #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
  6164. #define DMA_HIFCR_CDMEIF5_Pos (8U)
  6165. #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
  6166. #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
  6167. #define DMA_HIFCR_CFEIF5_Pos (6U)
  6168. #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
  6169. #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
  6170. #define DMA_HIFCR_CTCIF4_Pos (5U)
  6171. #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
  6172. #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
  6173. #define DMA_HIFCR_CHTIF4_Pos (4U)
  6174. #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
  6175. #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
  6176. #define DMA_HIFCR_CTEIF4_Pos (3U)
  6177. #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
  6178. #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
  6179. #define DMA_HIFCR_CDMEIF4_Pos (2U)
  6180. #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
  6181. #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
  6182. #define DMA_HIFCR_CFEIF4_Pos (0U)
  6183. #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
  6184. #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
  6185. /****************** Bit definition for DMA_SxPAR register ********************/
  6186. #define DMA_SxPAR_PA_Pos (0U)
  6187. #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
  6188. #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
  6189. /****************** Bit definition for DMA_SxM0AR register ********************/
  6190. #define DMA_SxM0AR_M0A_Pos (0U)
  6191. #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
  6192. #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
  6193. /****************** Bit definition for DMA_SxM1AR register ********************/
  6194. #define DMA_SxM1AR_M1A_Pos (0U)
  6195. #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
  6196. #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
  6197. /******************************************************************************/
  6198. /* */
  6199. /* AHB Master DMA2D Controller (DMA2D) */
  6200. /* */
  6201. /******************************************************************************/
  6202. /******************** Bit definition for DMA2D_CR register ******************/
  6203. #define DMA2D_CR_START_Pos (0U)
  6204. #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
  6205. #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
  6206. #define DMA2D_CR_SUSP_Pos (1U)
  6207. #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
  6208. #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
  6209. #define DMA2D_CR_ABORT_Pos (2U)
  6210. #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
  6211. #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
  6212. #define DMA2D_CR_TEIE_Pos (8U)
  6213. #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
  6214. #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
  6215. #define DMA2D_CR_TCIE_Pos (9U)
  6216. #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
  6217. #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
  6218. #define DMA2D_CR_TWIE_Pos (10U)
  6219. #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
  6220. #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
  6221. #define DMA2D_CR_CAEIE_Pos (11U)
  6222. #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
  6223. #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
  6224. #define DMA2D_CR_CTCIE_Pos (12U)
  6225. #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
  6226. #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
  6227. #define DMA2D_CR_CEIE_Pos (13U)
  6228. #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
  6229. #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
  6230. #define DMA2D_CR_MODE_Pos (16U)
  6231. #define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
  6232. #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
  6233. #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
  6234. #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
  6235. /******************** Bit definition for DMA2D_ISR register *****************/
  6236. #define DMA2D_ISR_TEIF_Pos (0U)
  6237. #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
  6238. #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
  6239. #define DMA2D_ISR_TCIF_Pos (1U)
  6240. #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
  6241. #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
  6242. #define DMA2D_ISR_TWIF_Pos (2U)
  6243. #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
  6244. #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
  6245. #define DMA2D_ISR_CAEIF_Pos (3U)
  6246. #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
  6247. #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
  6248. #define DMA2D_ISR_CTCIF_Pos (4U)
  6249. #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
  6250. #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
  6251. #define DMA2D_ISR_CEIF_Pos (5U)
  6252. #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
  6253. #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
  6254. /******************** Bit definition for DMA2D_IFCR register ****************/
  6255. #define DMA2D_IFCR_CTEIF_Pos (0U)
  6256. #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
  6257. #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
  6258. #define DMA2D_IFCR_CTCIF_Pos (1U)
  6259. #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
  6260. #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
  6261. #define DMA2D_IFCR_CTWIF_Pos (2U)
  6262. #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
  6263. #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
  6264. #define DMA2D_IFCR_CAECIF_Pos (3U)
  6265. #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
  6266. #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
  6267. #define DMA2D_IFCR_CCTCIF_Pos (4U)
  6268. #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
  6269. #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
  6270. #define DMA2D_IFCR_CCEIF_Pos (5U)
  6271. #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
  6272. #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
  6273. /* Legacy defines */
  6274. #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
  6275. #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
  6276. #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
  6277. #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
  6278. #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
  6279. #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
  6280. /******************** Bit definition for DMA2D_FGMAR register ***************/
  6281. #define DMA2D_FGMAR_MA_Pos (0U)
  6282. #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6283. #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
  6284. /******************** Bit definition for DMA2D_FGOR register ****************/
  6285. #define DMA2D_FGOR_LO_Pos (0U)
  6286. #define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
  6287. #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
  6288. /******************** Bit definition for DMA2D_BGMAR register ***************/
  6289. #define DMA2D_BGMAR_MA_Pos (0U)
  6290. #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6291. #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
  6292. /******************** Bit definition for DMA2D_BGOR register ****************/
  6293. #define DMA2D_BGOR_LO_Pos (0U)
  6294. #define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
  6295. #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
  6296. /******************** Bit definition for DMA2D_FGPFCCR register *************/
  6297. #define DMA2D_FGPFCCR_CM_Pos (0U)
  6298. #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
  6299. #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
  6300. #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
  6301. #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
  6302. #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
  6303. #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
  6304. #define DMA2D_FGPFCCR_CCM_Pos (4U)
  6305. #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
  6306. #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
  6307. #define DMA2D_FGPFCCR_START_Pos (5U)
  6308. #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
  6309. #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
  6310. #define DMA2D_FGPFCCR_CS_Pos (8U)
  6311. #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
  6312. #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
  6313. #define DMA2D_FGPFCCR_AM_Pos (16U)
  6314. #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
  6315. #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
  6316. #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
  6317. #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
  6318. #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
  6319. #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
  6320. #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
  6321. /******************** Bit definition for DMA2D_FGCOLR register **************/
  6322. #define DMA2D_FGCOLR_BLUE_Pos (0U)
  6323. #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
  6324. #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
  6325. #define DMA2D_FGCOLR_GREEN_Pos (8U)
  6326. #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
  6327. #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
  6328. #define DMA2D_FGCOLR_RED_Pos (16U)
  6329. #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
  6330. #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
  6331. /******************** Bit definition for DMA2D_BGPFCCR register *************/
  6332. #define DMA2D_BGPFCCR_CM_Pos (0U)
  6333. #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
  6334. #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
  6335. #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
  6336. #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
  6337. #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
  6338. #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
  6339. #define DMA2D_BGPFCCR_CCM_Pos (4U)
  6340. #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
  6341. #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
  6342. #define DMA2D_BGPFCCR_START_Pos (5U)
  6343. #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
  6344. #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
  6345. #define DMA2D_BGPFCCR_CS_Pos (8U)
  6346. #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
  6347. #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
  6348. #define DMA2D_BGPFCCR_AM_Pos (16U)
  6349. #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
  6350. #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
  6351. #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
  6352. #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
  6353. #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
  6354. #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
  6355. #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
  6356. /******************** Bit definition for DMA2D_BGCOLR register **************/
  6357. #define DMA2D_BGCOLR_BLUE_Pos (0U)
  6358. #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
  6359. #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
  6360. #define DMA2D_BGCOLR_GREEN_Pos (8U)
  6361. #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
  6362. #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
  6363. #define DMA2D_BGCOLR_RED_Pos (16U)
  6364. #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
  6365. #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
  6366. /******************** Bit definition for DMA2D_FGCMAR register **************/
  6367. #define DMA2D_FGCMAR_MA_Pos (0U)
  6368. #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6369. #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
  6370. /******************** Bit definition for DMA2D_BGCMAR register **************/
  6371. #define DMA2D_BGCMAR_MA_Pos (0U)
  6372. #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6373. #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
  6374. /******************** Bit definition for DMA2D_OPFCCR register **************/
  6375. #define DMA2D_OPFCCR_CM_Pos (0U)
  6376. #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
  6377. #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
  6378. #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
  6379. #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
  6380. #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
  6381. /******************** Bit definition for DMA2D_OCOLR register ***************/
  6382. /*!<Mode_ARGB8888/RGB888 */
  6383. #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
  6384. #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
  6385. #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
  6386. #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
  6387. /*!<Mode_RGB565 */
  6388. #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
  6389. #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
  6390. #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
  6391. /*!<Mode_ARGB1555 */
  6392. #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
  6393. #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
  6394. #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
  6395. #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
  6396. /*!<Mode_ARGB4444 */
  6397. #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
  6398. #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
  6399. #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
  6400. #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
  6401. /******************** Bit definition for DMA2D_OMAR register ****************/
  6402. #define DMA2D_OMAR_MA_Pos (0U)
  6403. #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6404. #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
  6405. /******************** Bit definition for DMA2D_OOR register *****************/
  6406. #define DMA2D_OOR_LO_Pos (0U)
  6407. #define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
  6408. #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
  6409. /******************** Bit definition for DMA2D_NLR register *****************/
  6410. #define DMA2D_NLR_NL_Pos (0U)
  6411. #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
  6412. #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
  6413. #define DMA2D_NLR_PL_Pos (16U)
  6414. #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
  6415. #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
  6416. /******************** Bit definition for DMA2D_LWR register *****************/
  6417. #define DMA2D_LWR_LW_Pos (0U)
  6418. #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
  6419. #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
  6420. /******************** Bit definition for DMA2D_AMTCR register ***************/
  6421. #define DMA2D_AMTCR_EN_Pos (0U)
  6422. #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
  6423. #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
  6424. #define DMA2D_AMTCR_DT_Pos (8U)
  6425. #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
  6426. #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
  6427. /******************** Bit definition for DMA2D_FGCLUT register **************/
  6428. /******************** Bit definition for DMA2D_BGCLUT register **************/
  6429. /******************************************************************************/
  6430. /* */
  6431. /* Display Serial Interface (DSI) */
  6432. /* */
  6433. /******************************************************************************/
  6434. /******************* Bit definition for DSI_VR register *****************/
  6435. #define DSI_VR_Pos (1U)
  6436. #define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos) /*!< 0x3133302A */
  6437. #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
  6438. /******************* Bit definition for DSI_CR register *****************/
  6439. #define DSI_CR_EN_Pos (0U)
  6440. #define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos) /*!< 0x00000001 */
  6441. #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
  6442. /******************* Bit definition for DSI_CCR register ****************/
  6443. #define DSI_CCR_TXECKDIV_Pos (0U)
  6444. #define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
  6445. #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
  6446. #define DSI_CCR_TXECKDIV0_Pos (0U)
  6447. #define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
  6448. #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
  6449. #define DSI_CCR_TXECKDIV1_Pos (1U)
  6450. #define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
  6451. #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
  6452. #define DSI_CCR_TXECKDIV2_Pos (2U)
  6453. #define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
  6454. #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
  6455. #define DSI_CCR_TXECKDIV3_Pos (3U)
  6456. #define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
  6457. #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
  6458. #define DSI_CCR_TXECKDIV4_Pos (4U)
  6459. #define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
  6460. #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
  6461. #define DSI_CCR_TXECKDIV5_Pos (5U)
  6462. #define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
  6463. #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
  6464. #define DSI_CCR_TXECKDIV6_Pos (6U)
  6465. #define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
  6466. #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
  6467. #define DSI_CCR_TXECKDIV7_Pos (7U)
  6468. #define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
  6469. #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
  6470. #define DSI_CCR_TOCKDIV_Pos (8U)
  6471. #define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
  6472. #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
  6473. #define DSI_CCR_TOCKDIV0_Pos (8U)
  6474. #define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
  6475. #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
  6476. #define DSI_CCR_TOCKDIV1_Pos (9U)
  6477. #define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
  6478. #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
  6479. #define DSI_CCR_TOCKDIV2_Pos (10U)
  6480. #define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
  6481. #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
  6482. #define DSI_CCR_TOCKDIV3_Pos (11U)
  6483. #define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
  6484. #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
  6485. #define DSI_CCR_TOCKDIV4_Pos (12U)
  6486. #define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
  6487. #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
  6488. #define DSI_CCR_TOCKDIV5_Pos (13U)
  6489. #define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
  6490. #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
  6491. #define DSI_CCR_TOCKDIV6_Pos (14U)
  6492. #define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
  6493. #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
  6494. #define DSI_CCR_TOCKDIV7_Pos (15U)
  6495. #define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
  6496. #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
  6497. /******************* Bit definition for DSI_LVCIDR register *************/
  6498. #define DSI_LVCIDR_VCID_Pos (0U)
  6499. #define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
  6500. #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
  6501. #define DSI_LVCIDR_VCID0_Pos (0U)
  6502. #define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
  6503. #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
  6504. #define DSI_LVCIDR_VCID1_Pos (1U)
  6505. #define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
  6506. #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
  6507. /******************* Bit definition for DSI_LCOLCR register *************/
  6508. #define DSI_LCOLCR_COLC_Pos (0U)
  6509. #define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
  6510. #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
  6511. #define DSI_LCOLCR_COLC0_Pos (0U)
  6512. #define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
  6513. #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
  6514. #define DSI_LCOLCR_COLC1_Pos (5U)
  6515. #define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
  6516. #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
  6517. #define DSI_LCOLCR_COLC2_Pos (6U)
  6518. #define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
  6519. #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
  6520. #define DSI_LCOLCR_COLC3_Pos (7U)
  6521. #define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
  6522. #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
  6523. #define DSI_LCOLCR_LPE_Pos (8U)
  6524. #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
  6525. #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
  6526. /******************* Bit definition for DSI_LPCR register ***************/
  6527. #define DSI_LPCR_DEP_Pos (0U)
  6528. #define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
  6529. #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
  6530. #define DSI_LPCR_VSP_Pos (1U)
  6531. #define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
  6532. #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
  6533. #define DSI_LPCR_HSP_Pos (2U)
  6534. #define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
  6535. #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
  6536. /******************* Bit definition for DSI_LPMCR register **************/
  6537. #define DSI_LPMCR_VLPSIZE_Pos (0U)
  6538. #define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
  6539. #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
  6540. #define DSI_LPMCR_VLPSIZE0_Pos (0U)
  6541. #define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
  6542. #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
  6543. #define DSI_LPMCR_VLPSIZE1_Pos (1U)
  6544. #define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
  6545. #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
  6546. #define DSI_LPMCR_VLPSIZE2_Pos (2U)
  6547. #define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
  6548. #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
  6549. #define DSI_LPMCR_VLPSIZE3_Pos (3U)
  6550. #define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
  6551. #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
  6552. #define DSI_LPMCR_VLPSIZE4_Pos (4U)
  6553. #define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
  6554. #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
  6555. #define DSI_LPMCR_VLPSIZE5_Pos (5U)
  6556. #define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
  6557. #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
  6558. #define DSI_LPMCR_VLPSIZE6_Pos (6U)
  6559. #define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
  6560. #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
  6561. #define DSI_LPMCR_VLPSIZE7_Pos (7U)
  6562. #define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
  6563. #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
  6564. #define DSI_LPMCR_LPSIZE_Pos (16U)
  6565. #define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
  6566. #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
  6567. #define DSI_LPMCR_LPSIZE0_Pos (16U)
  6568. #define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
  6569. #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
  6570. #define DSI_LPMCR_LPSIZE1_Pos (17U)
  6571. #define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
  6572. #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
  6573. #define DSI_LPMCR_LPSIZE2_Pos (18U)
  6574. #define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
  6575. #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
  6576. #define DSI_LPMCR_LPSIZE3_Pos (19U)
  6577. #define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
  6578. #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
  6579. #define DSI_LPMCR_LPSIZE4_Pos (20U)
  6580. #define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
  6581. #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
  6582. #define DSI_LPMCR_LPSIZE5_Pos (21U)
  6583. #define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
  6584. #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
  6585. #define DSI_LPMCR_LPSIZE6_Pos (22U)
  6586. #define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
  6587. #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
  6588. #define DSI_LPMCR_LPSIZE7_Pos (23U)
  6589. #define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
  6590. #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
  6591. /******************* Bit definition for DSI_PCR register ****************/
  6592. #define DSI_PCR_ETTXE_Pos (0U)
  6593. #define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
  6594. #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
  6595. #define DSI_PCR_ETRXE_Pos (1U)
  6596. #define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
  6597. #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
  6598. #define DSI_PCR_BTAE_Pos (2U)
  6599. #define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
  6600. #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
  6601. #define DSI_PCR_ECCRXE_Pos (3U)
  6602. #define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
  6603. #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
  6604. #define DSI_PCR_CRCRXE_Pos (4U)
  6605. #define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
  6606. #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
  6607. /******************* Bit definition for DSI_GVCIDR register *************/
  6608. #define DSI_GVCIDR_VCID_Pos (0U)
  6609. #define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
  6610. #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
  6611. #define DSI_GVCIDR_VCID0_Pos (0U)
  6612. #define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
  6613. #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
  6614. #define DSI_GVCIDR_VCID1_Pos (1U)
  6615. #define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
  6616. #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
  6617. /******************* Bit definition for DSI_MCR register ****************/
  6618. #define DSI_MCR_CMDM_Pos (0U)
  6619. #define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
  6620. #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
  6621. /******************* Bit definition for DSI_VMCR register ***************/
  6622. #define DSI_VMCR_VMT_Pos (0U)
  6623. #define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
  6624. #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
  6625. #define DSI_VMCR_VMT0_Pos (0U)
  6626. #define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
  6627. #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
  6628. #define DSI_VMCR_VMT1_Pos (1U)
  6629. #define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
  6630. #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
  6631. #define DSI_VMCR_LPVSAE_Pos (8U)
  6632. #define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
  6633. #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
  6634. #define DSI_VMCR_LPVBPE_Pos (9U)
  6635. #define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
  6636. #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
  6637. #define DSI_VMCR_LPVFPE_Pos (10U)
  6638. #define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
  6639. #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
  6640. #define DSI_VMCR_LPVAE_Pos (11U)
  6641. #define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
  6642. #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
  6643. #define DSI_VMCR_LPHBPE_Pos (12U)
  6644. #define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
  6645. #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
  6646. #define DSI_VMCR_LPHFPE_Pos (13U)
  6647. #define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
  6648. #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
  6649. #define DSI_VMCR_FBTAAE_Pos (14U)
  6650. #define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
  6651. #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
  6652. #define DSI_VMCR_LPCE_Pos (15U)
  6653. #define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
  6654. #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
  6655. #define DSI_VMCR_PGE_Pos (16U)
  6656. #define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
  6657. #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
  6658. #define DSI_VMCR_PGM_Pos (20U)
  6659. #define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
  6660. #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
  6661. #define DSI_VMCR_PGO_Pos (24U)
  6662. #define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
  6663. #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
  6664. /******************* Bit definition for DSI_VPCR register ***************/
  6665. #define DSI_VPCR_VPSIZE_Pos (0U)
  6666. #define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
  6667. #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
  6668. #define DSI_VPCR_VPSIZE0_Pos (0U)
  6669. #define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
  6670. #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
  6671. #define DSI_VPCR_VPSIZE1_Pos (1U)
  6672. #define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
  6673. #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
  6674. #define DSI_VPCR_VPSIZE2_Pos (2U)
  6675. #define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
  6676. #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
  6677. #define DSI_VPCR_VPSIZE3_Pos (3U)
  6678. #define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
  6679. #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
  6680. #define DSI_VPCR_VPSIZE4_Pos (4U)
  6681. #define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
  6682. #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
  6683. #define DSI_VPCR_VPSIZE5_Pos (5U)
  6684. #define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
  6685. #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
  6686. #define DSI_VPCR_VPSIZE6_Pos (6U)
  6687. #define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
  6688. #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
  6689. #define DSI_VPCR_VPSIZE7_Pos (7U)
  6690. #define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
  6691. #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
  6692. #define DSI_VPCR_VPSIZE8_Pos (8U)
  6693. #define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
  6694. #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
  6695. #define DSI_VPCR_VPSIZE9_Pos (9U)
  6696. #define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
  6697. #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
  6698. #define DSI_VPCR_VPSIZE10_Pos (10U)
  6699. #define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
  6700. #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
  6701. #define DSI_VPCR_VPSIZE11_Pos (11U)
  6702. #define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
  6703. #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
  6704. #define DSI_VPCR_VPSIZE12_Pos (12U)
  6705. #define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
  6706. #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
  6707. #define DSI_VPCR_VPSIZE13_Pos (13U)
  6708. #define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
  6709. #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
  6710. /******************* Bit definition for DSI_VCCR register ***************/
  6711. #define DSI_VCCR_NUMC_Pos (0U)
  6712. #define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
  6713. #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
  6714. #define DSI_VCCR_NUMC0_Pos (0U)
  6715. #define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
  6716. #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
  6717. #define DSI_VCCR_NUMC1_Pos (1U)
  6718. #define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
  6719. #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
  6720. #define DSI_VCCR_NUMC2_Pos (2U)
  6721. #define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
  6722. #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
  6723. #define DSI_VCCR_NUMC3_Pos (3U)
  6724. #define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
  6725. #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
  6726. #define DSI_VCCR_NUMC4_Pos (4U)
  6727. #define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
  6728. #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
  6729. #define DSI_VCCR_NUMC5_Pos (5U)
  6730. #define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
  6731. #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
  6732. #define DSI_VCCR_NUMC6_Pos (6U)
  6733. #define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
  6734. #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
  6735. #define DSI_VCCR_NUMC7_Pos (7U)
  6736. #define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
  6737. #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
  6738. #define DSI_VCCR_NUMC8_Pos (8U)
  6739. #define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
  6740. #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
  6741. #define DSI_VCCR_NUMC9_Pos (9U)
  6742. #define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
  6743. #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
  6744. #define DSI_VCCR_NUMC10_Pos (10U)
  6745. #define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
  6746. #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
  6747. #define DSI_VCCR_NUMC11_Pos (11U)
  6748. #define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
  6749. #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
  6750. #define DSI_VCCR_NUMC12_Pos (12U)
  6751. #define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
  6752. #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
  6753. /******************* Bit definition for DSI_VNPCR register **************/
  6754. #define DSI_VNPCR_NPSIZE_Pos (0U)
  6755. #define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
  6756. #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
  6757. #define DSI_VNPCR_NPSIZE0_Pos (0U)
  6758. #define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
  6759. #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
  6760. #define DSI_VNPCR_NPSIZE1_Pos (1U)
  6761. #define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
  6762. #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
  6763. #define DSI_VNPCR_NPSIZE2_Pos (2U)
  6764. #define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
  6765. #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
  6766. #define DSI_VNPCR_NPSIZE3_Pos (3U)
  6767. #define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
  6768. #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
  6769. #define DSI_VNPCR_NPSIZE4_Pos (4U)
  6770. #define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
  6771. #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
  6772. #define DSI_VNPCR_NPSIZE5_Pos (5U)
  6773. #define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
  6774. #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
  6775. #define DSI_VNPCR_NPSIZE6_Pos (6U)
  6776. #define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
  6777. #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
  6778. #define DSI_VNPCR_NPSIZE7_Pos (7U)
  6779. #define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
  6780. #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
  6781. #define DSI_VNPCR_NPSIZE8_Pos (8U)
  6782. #define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
  6783. #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
  6784. #define DSI_VNPCR_NPSIZE9_Pos (9U)
  6785. #define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
  6786. #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
  6787. #define DSI_VNPCR_NPSIZE10_Pos (10U)
  6788. #define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
  6789. #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
  6790. #define DSI_VNPCR_NPSIZE11_Pos (11U)
  6791. #define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
  6792. #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
  6793. #define DSI_VNPCR_NPSIZE12_Pos (12U)
  6794. #define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
  6795. #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
  6796. /******************* Bit definition for DSI_VHSACR register *************/
  6797. #define DSI_VHSACR_HSA_Pos (0U)
  6798. #define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
  6799. #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
  6800. #define DSI_VHSACR_HSA0_Pos (0U)
  6801. #define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
  6802. #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
  6803. #define DSI_VHSACR_HSA1_Pos (1U)
  6804. #define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
  6805. #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
  6806. #define DSI_VHSACR_HSA2_Pos (2U)
  6807. #define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
  6808. #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
  6809. #define DSI_VHSACR_HSA3_Pos (3U)
  6810. #define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
  6811. #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
  6812. #define DSI_VHSACR_HSA4_Pos (4U)
  6813. #define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
  6814. #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
  6815. #define DSI_VHSACR_HSA5_Pos (5U)
  6816. #define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
  6817. #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
  6818. #define DSI_VHSACR_HSA6_Pos (6U)
  6819. #define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
  6820. #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
  6821. #define DSI_VHSACR_HSA7_Pos (7U)
  6822. #define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
  6823. #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
  6824. #define DSI_VHSACR_HSA8_Pos (8U)
  6825. #define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
  6826. #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
  6827. #define DSI_VHSACR_HSA9_Pos (9U)
  6828. #define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
  6829. #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
  6830. #define DSI_VHSACR_HSA10_Pos (10U)
  6831. #define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
  6832. #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
  6833. #define DSI_VHSACR_HSA11_Pos (11U)
  6834. #define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
  6835. #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
  6836. /******************* Bit definition for DSI_VHBPCR register *************/
  6837. #define DSI_VHBPCR_HBP_Pos (0U)
  6838. #define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
  6839. #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
  6840. #define DSI_VHBPCR_HBP0_Pos (0U)
  6841. #define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
  6842. #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
  6843. #define DSI_VHBPCR_HBP1_Pos (1U)
  6844. #define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
  6845. #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
  6846. #define DSI_VHBPCR_HBP2_Pos (2U)
  6847. #define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
  6848. #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
  6849. #define DSI_VHBPCR_HBP3_Pos (3U)
  6850. #define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
  6851. #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
  6852. #define DSI_VHBPCR_HBP4_Pos (4U)
  6853. #define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
  6854. #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
  6855. #define DSI_VHBPCR_HBP5_Pos (5U)
  6856. #define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
  6857. #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
  6858. #define DSI_VHBPCR_HBP6_Pos (6U)
  6859. #define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
  6860. #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
  6861. #define DSI_VHBPCR_HBP7_Pos (7U)
  6862. #define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
  6863. #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
  6864. #define DSI_VHBPCR_HBP8_Pos (8U)
  6865. #define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
  6866. #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
  6867. #define DSI_VHBPCR_HBP9_Pos (9U)
  6868. #define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
  6869. #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
  6870. #define DSI_VHBPCR_HBP10_Pos (10U)
  6871. #define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
  6872. #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
  6873. #define DSI_VHBPCR_HBP11_Pos (11U)
  6874. #define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
  6875. #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
  6876. /******************* Bit definition for DSI_VLCR register ***************/
  6877. #define DSI_VLCR_HLINE_Pos (0U)
  6878. #define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
  6879. #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
  6880. #define DSI_VLCR_HLINE0_Pos (0U)
  6881. #define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
  6882. #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
  6883. #define DSI_VLCR_HLINE1_Pos (1U)
  6884. #define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
  6885. #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
  6886. #define DSI_VLCR_HLINE2_Pos (2U)
  6887. #define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
  6888. #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
  6889. #define DSI_VLCR_HLINE3_Pos (3U)
  6890. #define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
  6891. #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
  6892. #define DSI_VLCR_HLINE4_Pos (4U)
  6893. #define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
  6894. #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
  6895. #define DSI_VLCR_HLINE5_Pos (5U)
  6896. #define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
  6897. #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
  6898. #define DSI_VLCR_HLINE6_Pos (6U)
  6899. #define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
  6900. #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
  6901. #define DSI_VLCR_HLINE7_Pos (7U)
  6902. #define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
  6903. #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
  6904. #define DSI_VLCR_HLINE8_Pos (8U)
  6905. #define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
  6906. #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
  6907. #define DSI_VLCR_HLINE9_Pos (9U)
  6908. #define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
  6909. #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
  6910. #define DSI_VLCR_HLINE10_Pos (10U)
  6911. #define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
  6912. #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
  6913. #define DSI_VLCR_HLINE11_Pos (11U)
  6914. #define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
  6915. #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
  6916. #define DSI_VLCR_HLINE12_Pos (12U)
  6917. #define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
  6918. #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
  6919. #define DSI_VLCR_HLINE13_Pos (13U)
  6920. #define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
  6921. #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
  6922. #define DSI_VLCR_HLINE14_Pos (14U)
  6923. #define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
  6924. #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
  6925. /******************* Bit definition for DSI_VVSACR register *************/
  6926. #define DSI_VVSACR_VSA_Pos (0U)
  6927. #define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
  6928. #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
  6929. #define DSI_VVSACR_VSA0_Pos (0U)
  6930. #define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
  6931. #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
  6932. #define DSI_VVSACR_VSA1_Pos (1U)
  6933. #define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
  6934. #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
  6935. #define DSI_VVSACR_VSA2_Pos (2U)
  6936. #define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
  6937. #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
  6938. #define DSI_VVSACR_VSA3_Pos (3U)
  6939. #define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
  6940. #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
  6941. #define DSI_VVSACR_VSA4_Pos (4U)
  6942. #define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
  6943. #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
  6944. #define DSI_VVSACR_VSA5_Pos (5U)
  6945. #define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
  6946. #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
  6947. #define DSI_VVSACR_VSA6_Pos (6U)
  6948. #define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
  6949. #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
  6950. #define DSI_VVSACR_VSA7_Pos (7U)
  6951. #define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
  6952. #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
  6953. #define DSI_VVSACR_VSA8_Pos (8U)
  6954. #define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
  6955. #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
  6956. #define DSI_VVSACR_VSA9_Pos (9U)
  6957. #define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
  6958. #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
  6959. /******************* Bit definition for DSI_VVBPCR register *************/
  6960. #define DSI_VVBPCR_VBP_Pos (0U)
  6961. #define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
  6962. #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
  6963. #define DSI_VVBPCR_VBP0_Pos (0U)
  6964. #define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
  6965. #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
  6966. #define DSI_VVBPCR_VBP1_Pos (1U)
  6967. #define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
  6968. #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
  6969. #define DSI_VVBPCR_VBP2_Pos (2U)
  6970. #define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
  6971. #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
  6972. #define DSI_VVBPCR_VBP3_Pos (3U)
  6973. #define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
  6974. #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
  6975. #define DSI_VVBPCR_VBP4_Pos (4U)
  6976. #define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
  6977. #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
  6978. #define DSI_VVBPCR_VBP5_Pos (5U)
  6979. #define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
  6980. #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
  6981. #define DSI_VVBPCR_VBP6_Pos (6U)
  6982. #define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
  6983. #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
  6984. #define DSI_VVBPCR_VBP7_Pos (7U)
  6985. #define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
  6986. #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
  6987. #define DSI_VVBPCR_VBP8_Pos (8U)
  6988. #define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
  6989. #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
  6990. #define DSI_VVBPCR_VBP9_Pos (9U)
  6991. #define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
  6992. #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
  6993. /******************* Bit definition for DSI_VVFPCR register *************/
  6994. #define DSI_VVFPCR_VFP_Pos (0U)
  6995. #define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
  6996. #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
  6997. #define DSI_VVFPCR_VFP0_Pos (0U)
  6998. #define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
  6999. #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
  7000. #define DSI_VVFPCR_VFP1_Pos (1U)
  7001. #define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
  7002. #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
  7003. #define DSI_VVFPCR_VFP2_Pos (2U)
  7004. #define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
  7005. #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
  7006. #define DSI_VVFPCR_VFP3_Pos (3U)
  7007. #define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
  7008. #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
  7009. #define DSI_VVFPCR_VFP4_Pos (4U)
  7010. #define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
  7011. #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
  7012. #define DSI_VVFPCR_VFP5_Pos (5U)
  7013. #define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
  7014. #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
  7015. #define DSI_VVFPCR_VFP6_Pos (6U)
  7016. #define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
  7017. #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
  7018. #define DSI_VVFPCR_VFP7_Pos (7U)
  7019. #define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
  7020. #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
  7021. #define DSI_VVFPCR_VFP8_Pos (8U)
  7022. #define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
  7023. #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
  7024. #define DSI_VVFPCR_VFP9_Pos (9U)
  7025. #define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
  7026. #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
  7027. /******************* Bit definition for DSI_VVACR register **************/
  7028. #define DSI_VVACR_VA_Pos (0U)
  7029. #define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
  7030. #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
  7031. #define DSI_VVACR_VA0_Pos (0U)
  7032. #define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
  7033. #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
  7034. #define DSI_VVACR_VA1_Pos (1U)
  7035. #define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
  7036. #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
  7037. #define DSI_VVACR_VA2_Pos (2U)
  7038. #define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
  7039. #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
  7040. #define DSI_VVACR_VA3_Pos (3U)
  7041. #define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
  7042. #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
  7043. #define DSI_VVACR_VA4_Pos (4U)
  7044. #define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
  7045. #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
  7046. #define DSI_VVACR_VA5_Pos (5U)
  7047. #define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
  7048. #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
  7049. #define DSI_VVACR_VA6_Pos (6U)
  7050. #define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
  7051. #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
  7052. #define DSI_VVACR_VA7_Pos (7U)
  7053. #define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
  7054. #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
  7055. #define DSI_VVACR_VA8_Pos (8U)
  7056. #define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
  7057. #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
  7058. #define DSI_VVACR_VA9_Pos (9U)
  7059. #define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
  7060. #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
  7061. #define DSI_VVACR_VA10_Pos (10U)
  7062. #define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
  7063. #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
  7064. #define DSI_VVACR_VA11_Pos (11U)
  7065. #define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
  7066. #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
  7067. #define DSI_VVACR_VA12_Pos (12U)
  7068. #define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
  7069. #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
  7070. #define DSI_VVACR_VA13_Pos (13U)
  7071. #define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
  7072. #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
  7073. /******************* Bit definition for DSI_LCCR register ***************/
  7074. #define DSI_LCCR_CMDSIZE_Pos (0U)
  7075. #define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
  7076. #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
  7077. #define DSI_LCCR_CMDSIZE0_Pos (0U)
  7078. #define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
  7079. #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
  7080. #define DSI_LCCR_CMDSIZE1_Pos (1U)
  7081. #define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
  7082. #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
  7083. #define DSI_LCCR_CMDSIZE2_Pos (2U)
  7084. #define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
  7085. #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
  7086. #define DSI_LCCR_CMDSIZE3_Pos (3U)
  7087. #define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
  7088. #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
  7089. #define DSI_LCCR_CMDSIZE4_Pos (4U)
  7090. #define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
  7091. #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
  7092. #define DSI_LCCR_CMDSIZE5_Pos (5U)
  7093. #define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
  7094. #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
  7095. #define DSI_LCCR_CMDSIZE6_Pos (6U)
  7096. #define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
  7097. #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
  7098. #define DSI_LCCR_CMDSIZE7_Pos (7U)
  7099. #define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
  7100. #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
  7101. #define DSI_LCCR_CMDSIZE8_Pos (8U)
  7102. #define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
  7103. #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
  7104. #define DSI_LCCR_CMDSIZE9_Pos (9U)
  7105. #define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
  7106. #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
  7107. #define DSI_LCCR_CMDSIZE10_Pos (10U)
  7108. #define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
  7109. #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
  7110. #define DSI_LCCR_CMDSIZE11_Pos (11U)
  7111. #define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
  7112. #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
  7113. #define DSI_LCCR_CMDSIZE12_Pos (12U)
  7114. #define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
  7115. #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
  7116. #define DSI_LCCR_CMDSIZE13_Pos (13U)
  7117. #define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
  7118. #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
  7119. #define DSI_LCCR_CMDSIZE14_Pos (14U)
  7120. #define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
  7121. #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
  7122. #define DSI_LCCR_CMDSIZE15_Pos (15U)
  7123. #define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
  7124. #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
  7125. /******************* Bit definition for DSI_CMCR register ***************/
  7126. #define DSI_CMCR_TEARE_Pos (0U)
  7127. #define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
  7128. #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
  7129. #define DSI_CMCR_ARE_Pos (1U)
  7130. #define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
  7131. #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
  7132. #define DSI_CMCR_GSW0TX_Pos (8U)
  7133. #define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
  7134. #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
  7135. #define DSI_CMCR_GSW1TX_Pos (9U)
  7136. #define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
  7137. #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
  7138. #define DSI_CMCR_GSW2TX_Pos (10U)
  7139. #define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
  7140. #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
  7141. #define DSI_CMCR_GSR0TX_Pos (11U)
  7142. #define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
  7143. #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
  7144. #define DSI_CMCR_GSR1TX_Pos (12U)
  7145. #define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
  7146. #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
  7147. #define DSI_CMCR_GSR2TX_Pos (13U)
  7148. #define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
  7149. #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
  7150. #define DSI_CMCR_GLWTX_Pos (14U)
  7151. #define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
  7152. #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
  7153. #define DSI_CMCR_DSW0TX_Pos (16U)
  7154. #define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
  7155. #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
  7156. #define DSI_CMCR_DSW1TX_Pos (17U)
  7157. #define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
  7158. #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
  7159. #define DSI_CMCR_DSR0TX_Pos (18U)
  7160. #define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
  7161. #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
  7162. #define DSI_CMCR_DLWTX_Pos (19U)
  7163. #define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
  7164. #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
  7165. #define DSI_CMCR_MRDPS_Pos (24U)
  7166. #define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
  7167. #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
  7168. /******************* Bit definition for DSI_GHCR register ***************/
  7169. #define DSI_GHCR_DT_Pos (0U)
  7170. #define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
  7171. #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
  7172. #define DSI_GHCR_DT0_Pos (0U)
  7173. #define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
  7174. #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
  7175. #define DSI_GHCR_DT1_Pos (1U)
  7176. #define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
  7177. #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
  7178. #define DSI_GHCR_DT2_Pos (2U)
  7179. #define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
  7180. #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
  7181. #define DSI_GHCR_DT3_Pos (3U)
  7182. #define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
  7183. #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
  7184. #define DSI_GHCR_DT4_Pos (4U)
  7185. #define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
  7186. #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
  7187. #define DSI_GHCR_DT5_Pos (5U)
  7188. #define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
  7189. #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
  7190. #define DSI_GHCR_VCID_Pos (6U)
  7191. #define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
  7192. #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
  7193. #define DSI_GHCR_VCID0_Pos (6U)
  7194. #define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
  7195. #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
  7196. #define DSI_GHCR_VCID1_Pos (7U)
  7197. #define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
  7198. #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
  7199. #define DSI_GHCR_WCLSB_Pos (8U)
  7200. #define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
  7201. #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
  7202. #define DSI_GHCR_WCLSB0_Pos (8U)
  7203. #define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
  7204. #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
  7205. #define DSI_GHCR_WCLSB1_Pos (9U)
  7206. #define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
  7207. #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
  7208. #define DSI_GHCR_WCLSB2_Pos (10U)
  7209. #define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
  7210. #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
  7211. #define DSI_GHCR_WCLSB3_Pos (11U)
  7212. #define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
  7213. #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
  7214. #define DSI_GHCR_WCLSB4_Pos (12U)
  7215. #define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
  7216. #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
  7217. #define DSI_GHCR_WCLSB5_Pos (13U)
  7218. #define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
  7219. #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
  7220. #define DSI_GHCR_WCLSB6_Pos (14U)
  7221. #define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
  7222. #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
  7223. #define DSI_GHCR_WCLSB7_Pos (15U)
  7224. #define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
  7225. #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
  7226. #define DSI_GHCR_WCMSB_Pos (16U)
  7227. #define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
  7228. #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
  7229. #define DSI_GHCR_WCMSB0_Pos (16U)
  7230. #define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
  7231. #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
  7232. #define DSI_GHCR_WCMSB1_Pos (17U)
  7233. #define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
  7234. #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
  7235. #define DSI_GHCR_WCMSB2_Pos (18U)
  7236. #define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
  7237. #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
  7238. #define DSI_GHCR_WCMSB3_Pos (19U)
  7239. #define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
  7240. #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
  7241. #define DSI_GHCR_WCMSB4_Pos (20U)
  7242. #define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
  7243. #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
  7244. #define DSI_GHCR_WCMSB5_Pos (21U)
  7245. #define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
  7246. #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
  7247. #define DSI_GHCR_WCMSB6_Pos (22U)
  7248. #define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
  7249. #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
  7250. #define DSI_GHCR_WCMSB7_Pos (23U)
  7251. #define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
  7252. #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
  7253. /******************* Bit definition for DSI_GPDR register ***************/
  7254. #define DSI_GPDR_DATA1_Pos (0U)
  7255. #define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
  7256. #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
  7257. #define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
  7258. #define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
  7259. #define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
  7260. #define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
  7261. #define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
  7262. #define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
  7263. #define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
  7264. #define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
  7265. #define DSI_GPDR_DATA2_Pos (8U)
  7266. #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
  7267. #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
  7268. #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
  7269. #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
  7270. #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
  7271. #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
  7272. #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
  7273. #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
  7274. #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
  7275. #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
  7276. #define DSI_GPDR_DATA3_Pos (16U)
  7277. #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
  7278. #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
  7279. #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
  7280. #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
  7281. #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
  7282. #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
  7283. #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
  7284. #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
  7285. #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
  7286. #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
  7287. #define DSI_GPDR_DATA4_Pos (24U)
  7288. #define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
  7289. #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
  7290. #define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
  7291. #define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
  7292. #define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
  7293. #define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
  7294. #define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
  7295. #define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
  7296. #define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
  7297. #define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
  7298. /******************* Bit definition for DSI_GPSR register ***************/
  7299. #define DSI_GPSR_CMDFE_Pos (0U)
  7300. #define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
  7301. #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
  7302. #define DSI_GPSR_CMDFF_Pos (1U)
  7303. #define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
  7304. #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
  7305. #define DSI_GPSR_PWRFE_Pos (2U)
  7306. #define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
  7307. #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
  7308. #define DSI_GPSR_PWRFF_Pos (3U)
  7309. #define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
  7310. #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
  7311. #define DSI_GPSR_PRDFE_Pos (4U)
  7312. #define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
  7313. #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
  7314. #define DSI_GPSR_PRDFF_Pos (5U)
  7315. #define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
  7316. #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
  7317. #define DSI_GPSR_RCB_Pos (6U)
  7318. #define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
  7319. #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
  7320. /******************* Bit definition for DSI_TCCR0 register **************/
  7321. #define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
  7322. #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
  7323. #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
  7324. #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
  7325. #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
  7326. #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
  7327. #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
  7328. #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
  7329. #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
  7330. #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
  7331. #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
  7332. #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
  7333. #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
  7334. #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
  7335. #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
  7336. #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
  7337. #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
  7338. #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
  7339. #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
  7340. #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
  7341. #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
  7342. #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
  7343. #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
  7344. #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
  7345. #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
  7346. #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
  7347. #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
  7348. #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
  7349. #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
  7350. #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
  7351. #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
  7352. #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
  7353. #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
  7354. #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
  7355. #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
  7356. #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
  7357. #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
  7358. #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
  7359. #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
  7360. #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
  7361. #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
  7362. #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
  7363. #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
  7364. #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
  7365. #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
  7366. #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
  7367. #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
  7368. #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
  7369. #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
  7370. #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
  7371. #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
  7372. #define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
  7373. #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
  7374. #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
  7375. #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
  7376. #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
  7377. #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
  7378. #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
  7379. #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
  7380. #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
  7381. #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
  7382. #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
  7383. #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
  7384. #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
  7385. #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
  7386. #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
  7387. #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
  7388. #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
  7389. #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
  7390. #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
  7391. #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
  7392. #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
  7393. #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
  7394. #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
  7395. #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
  7396. #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
  7397. #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
  7398. #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
  7399. #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
  7400. #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
  7401. #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
  7402. #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
  7403. #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
  7404. #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
  7405. #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
  7406. #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
  7407. #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
  7408. #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
  7409. #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
  7410. #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
  7411. #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
  7412. #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
  7413. #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
  7414. #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
  7415. #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
  7416. #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
  7417. #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
  7418. #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
  7419. #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
  7420. #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
  7421. #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
  7422. #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
  7423. /******************* Bit definition for DSI_TCCR1 register **************/
  7424. #define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
  7425. #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
  7426. #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
  7427. #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
  7428. #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
  7429. #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
  7430. #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
  7431. #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
  7432. #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
  7433. #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
  7434. #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
  7435. #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
  7436. #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
  7437. #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
  7438. #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
  7439. #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
  7440. #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
  7441. #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
  7442. #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
  7443. #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
  7444. #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
  7445. #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
  7446. #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
  7447. #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
  7448. #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
  7449. #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
  7450. #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
  7451. #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
  7452. #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
  7453. #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
  7454. #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
  7455. #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
  7456. #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
  7457. #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
  7458. #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
  7459. #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
  7460. #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
  7461. #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
  7462. #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
  7463. #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
  7464. #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
  7465. #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
  7466. #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
  7467. #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
  7468. #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
  7469. #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
  7470. #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
  7471. #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
  7472. #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
  7473. #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
  7474. #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
  7475. /******************* Bit definition for DSI_TCCR2 register **************/
  7476. #define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
  7477. #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
  7478. #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
  7479. #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
  7480. #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
  7481. #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
  7482. #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
  7483. #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
  7484. #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
  7485. #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
  7486. #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
  7487. #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
  7488. #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
  7489. #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
  7490. #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
  7491. #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
  7492. #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
  7493. #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
  7494. #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
  7495. #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
  7496. #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
  7497. #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
  7498. #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
  7499. #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
  7500. #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
  7501. #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
  7502. #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
  7503. #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
  7504. #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
  7505. #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
  7506. #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
  7507. #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
  7508. #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
  7509. #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
  7510. #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
  7511. #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
  7512. #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
  7513. #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
  7514. #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
  7515. #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
  7516. #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
  7517. #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
  7518. #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
  7519. #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
  7520. #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
  7521. #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
  7522. #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
  7523. #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
  7524. #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
  7525. #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
  7526. #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
  7527. /******************* Bit definition for DSI_TCCR3 register **************/
  7528. #define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
  7529. #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
  7530. #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
  7531. #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
  7532. #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
  7533. #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
  7534. #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
  7535. #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
  7536. #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
  7537. #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
  7538. #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
  7539. #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
  7540. #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
  7541. #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
  7542. #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
  7543. #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
  7544. #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
  7545. #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
  7546. #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
  7547. #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
  7548. #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
  7549. #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
  7550. #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
  7551. #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
  7552. #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
  7553. #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
  7554. #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
  7555. #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
  7556. #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
  7557. #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
  7558. #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
  7559. #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
  7560. #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
  7561. #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
  7562. #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
  7563. #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
  7564. #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
  7565. #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
  7566. #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
  7567. #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
  7568. #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
  7569. #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
  7570. #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
  7571. #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
  7572. #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
  7573. #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
  7574. #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
  7575. #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
  7576. #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
  7577. #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
  7578. #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
  7579. #define DSI_TCCR3_PM_Pos (24U)
  7580. #define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
  7581. #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
  7582. /******************* Bit definition for DSI_TCCR4 register **************/
  7583. #define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
  7584. #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
  7585. #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
  7586. #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
  7587. #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
  7588. #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
  7589. #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
  7590. #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
  7591. #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
  7592. #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
  7593. #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
  7594. #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
  7595. #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
  7596. #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
  7597. #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
  7598. #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
  7599. #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
  7600. #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
  7601. #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
  7602. #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
  7603. #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
  7604. #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
  7605. #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
  7606. #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
  7607. #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
  7608. #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
  7609. #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
  7610. #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
  7611. #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
  7612. #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
  7613. #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
  7614. #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
  7615. #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
  7616. #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
  7617. #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
  7618. #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
  7619. #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
  7620. #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
  7621. #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
  7622. #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
  7623. #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
  7624. #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
  7625. #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
  7626. #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
  7627. #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
  7628. #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
  7629. #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
  7630. #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
  7631. #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
  7632. #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
  7633. #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
  7634. /******************* Bit definition for DSI_TCCR5 register **************/
  7635. #define DSI_TCCR5_BTA_TOCNT_Pos (0U)
  7636. #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
  7637. #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
  7638. #define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
  7639. #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
  7640. #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
  7641. #define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
  7642. #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
  7643. #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
  7644. #define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
  7645. #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
  7646. #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
  7647. #define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
  7648. #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
  7649. #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
  7650. #define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
  7651. #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
  7652. #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
  7653. #define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
  7654. #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
  7655. #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
  7656. #define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
  7657. #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
  7658. #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
  7659. #define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
  7660. #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
  7661. #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
  7662. #define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
  7663. #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
  7664. #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
  7665. #define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
  7666. #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
  7667. #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
  7668. #define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
  7669. #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
  7670. #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
  7671. #define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
  7672. #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
  7673. #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
  7674. #define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
  7675. #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
  7676. #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
  7677. #define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
  7678. #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
  7679. #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
  7680. #define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
  7681. #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
  7682. #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
  7683. #define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
  7684. #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
  7685. #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
  7686. /******************* Bit definition for DSI_TDCR register ***************/
  7687. #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
  7688. #define DSI_TDCR_3DM0 0x00000001U
  7689. #define DSI_TDCR_3DM1 0x00000002U
  7690. #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
  7691. #define DSI_TDCR_3DF0 0x00000004U
  7692. #define DSI_TDCR_3DF1 0x00000008U
  7693. #define DSI_TDCR_SVS_Pos (4U)
  7694. #define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
  7695. #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
  7696. #define DSI_TDCR_RF_Pos (5U)
  7697. #define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
  7698. #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
  7699. #define DSI_TDCR_S3DC_Pos (16U)
  7700. #define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
  7701. #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
  7702. /******************* Bit definition for DSI_CLCR register ***************/
  7703. #define DSI_CLCR_DPCC_Pos (0U)
  7704. #define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
  7705. #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
  7706. #define DSI_CLCR_ACR_Pos (1U)
  7707. #define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
  7708. #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
  7709. /******************* Bit definition for DSI_CLTCR register **************/
  7710. #define DSI_CLTCR_LP2HS_TIME_Pos (0U)
  7711. #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
  7712. #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
  7713. #define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
  7714. #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
  7715. #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
  7716. #define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
  7717. #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
  7718. #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
  7719. #define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
  7720. #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
  7721. #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
  7722. #define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
  7723. #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
  7724. #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
  7725. #define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
  7726. #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
  7727. #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
  7728. #define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
  7729. #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
  7730. #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
  7731. #define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
  7732. #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
  7733. #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
  7734. #define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
  7735. #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
  7736. #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
  7737. #define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
  7738. #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
  7739. #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
  7740. #define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
  7741. #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
  7742. #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
  7743. #define DSI_CLTCR_HS2LP_TIME_Pos (16U)
  7744. #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
  7745. #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
  7746. #define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
  7747. #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
  7748. #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
  7749. #define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
  7750. #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
  7751. #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
  7752. #define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
  7753. #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
  7754. #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
  7755. #define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
  7756. #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
  7757. #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
  7758. #define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
  7759. #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
  7760. #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
  7761. #define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
  7762. #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
  7763. #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
  7764. #define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
  7765. #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
  7766. #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
  7767. #define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
  7768. #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
  7769. #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
  7770. #define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
  7771. #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
  7772. #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
  7773. #define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
  7774. #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
  7775. #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
  7776. /******************* Bit definition for DSI_DLTCR register **************/
  7777. #define DSI_DLTCR_MRD_TIME_Pos (0U)
  7778. #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
  7779. #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
  7780. #define DSI_DLTCR_MRD_TIME0_Pos (0U)
  7781. #define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
  7782. #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
  7783. #define DSI_DLTCR_MRD_TIME1_Pos (1U)
  7784. #define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
  7785. #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
  7786. #define DSI_DLTCR_MRD_TIME2_Pos (2U)
  7787. #define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
  7788. #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
  7789. #define DSI_DLTCR_MRD_TIME3_Pos (3U)
  7790. #define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
  7791. #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
  7792. #define DSI_DLTCR_MRD_TIME4_Pos (4U)
  7793. #define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
  7794. #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
  7795. #define DSI_DLTCR_MRD_TIME5_Pos (5U)
  7796. #define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
  7797. #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
  7798. #define DSI_DLTCR_MRD_TIME6_Pos (6U)
  7799. #define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
  7800. #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
  7801. #define DSI_DLTCR_MRD_TIME7_Pos (7U)
  7802. #define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
  7803. #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
  7804. #define DSI_DLTCR_MRD_TIME8_Pos (8U)
  7805. #define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
  7806. #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
  7807. #define DSI_DLTCR_MRD_TIME9_Pos (9U)
  7808. #define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
  7809. #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
  7810. #define DSI_DLTCR_MRD_TIME10_Pos (10U)
  7811. #define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
  7812. #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
  7813. #define DSI_DLTCR_MRD_TIME11_Pos (11U)
  7814. #define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
  7815. #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
  7816. #define DSI_DLTCR_MRD_TIME12_Pos (12U)
  7817. #define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
  7818. #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
  7819. #define DSI_DLTCR_MRD_TIME13_Pos (13U)
  7820. #define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
  7821. #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
  7822. #define DSI_DLTCR_MRD_TIME14_Pos (14U)
  7823. #define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
  7824. #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
  7825. #define DSI_DLTCR_LP2HS_TIME_Pos (16U)
  7826. #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
  7827. #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
  7828. #define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
  7829. #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
  7830. #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
  7831. #define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
  7832. #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
  7833. #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
  7834. #define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
  7835. #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
  7836. #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
  7837. #define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
  7838. #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
  7839. #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
  7840. #define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
  7841. #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
  7842. #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
  7843. #define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
  7844. #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
  7845. #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
  7846. #define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
  7847. #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
  7848. #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
  7849. #define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
  7850. #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
  7851. #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
  7852. #define DSI_DLTCR_HS2LP_TIME_Pos (24U)
  7853. #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
  7854. #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
  7855. #define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
  7856. #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
  7857. #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
  7858. #define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
  7859. #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
  7860. #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
  7861. #define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
  7862. #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
  7863. #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
  7864. #define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
  7865. #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
  7866. #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
  7867. #define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
  7868. #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
  7869. #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
  7870. #define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
  7871. #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
  7872. #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
  7873. #define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
  7874. #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
  7875. #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
  7876. #define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
  7877. #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
  7878. #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
  7879. /******************* Bit definition for DSI_PCTLR register **************/
  7880. #define DSI_PCTLR_DEN_Pos (1U)
  7881. #define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
  7882. #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
  7883. #define DSI_PCTLR_CKE_Pos (2U)
  7884. #define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
  7885. #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
  7886. /******************* Bit definition for DSI_PCONFR register *************/
  7887. #define DSI_PCONFR_NL_Pos (0U)
  7888. #define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
  7889. #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
  7890. #define DSI_PCONFR_NL0_Pos (0U)
  7891. #define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
  7892. #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
  7893. #define DSI_PCONFR_NL1_Pos (1U)
  7894. #define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
  7895. #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
  7896. #define DSI_PCONFR_SW_TIME_Pos (8U)
  7897. #define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
  7898. #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
  7899. #define DSI_PCONFR_SW_TIME0_Pos (8U)
  7900. #define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
  7901. #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
  7902. #define DSI_PCONFR_SW_TIME1_Pos (9U)
  7903. #define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
  7904. #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
  7905. #define DSI_PCONFR_SW_TIME2_Pos (10U)
  7906. #define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
  7907. #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
  7908. #define DSI_PCONFR_SW_TIME3_Pos (11U)
  7909. #define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
  7910. #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
  7911. #define DSI_PCONFR_SW_TIME4_Pos (12U)
  7912. #define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
  7913. #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
  7914. #define DSI_PCONFR_SW_TIME5_Pos (13U)
  7915. #define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
  7916. #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
  7917. #define DSI_PCONFR_SW_TIME6_Pos (14U)
  7918. #define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
  7919. #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
  7920. #define DSI_PCONFR_SW_TIME7_Pos (15U)
  7921. #define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
  7922. #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
  7923. /******************* Bit definition for DSI_PUCR register ***************/
  7924. #define DSI_PUCR_URCL_Pos (0U)
  7925. #define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
  7926. #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
  7927. #define DSI_PUCR_UECL_Pos (1U)
  7928. #define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
  7929. #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
  7930. #define DSI_PUCR_URDL_Pos (2U)
  7931. #define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
  7932. #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
  7933. #define DSI_PUCR_UEDL_Pos (3U)
  7934. #define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
  7935. #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
  7936. /******************* Bit definition for DSI_PTTCR register **************/
  7937. #define DSI_PTTCR_TX_TRIG_Pos (0U)
  7938. #define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
  7939. #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
  7940. #define DSI_PTTCR_TX_TRIG0_Pos (0U)
  7941. #define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
  7942. #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
  7943. #define DSI_PTTCR_TX_TRIG1_Pos (1U)
  7944. #define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
  7945. #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
  7946. #define DSI_PTTCR_TX_TRIG2_Pos (2U)
  7947. #define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
  7948. #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
  7949. #define DSI_PTTCR_TX_TRIG3_Pos (3U)
  7950. #define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
  7951. #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
  7952. /******************* Bit definition for DSI_PSR register ****************/
  7953. #define DSI_PSR_PD_Pos (1U)
  7954. #define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos) /*!< 0x00000002 */
  7955. #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
  7956. #define DSI_PSR_PSSC_Pos (2U)
  7957. #define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
  7958. #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
  7959. #define DSI_PSR_UANC_Pos (3U)
  7960. #define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
  7961. #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
  7962. #define DSI_PSR_PSS0_Pos (4U)
  7963. #define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
  7964. #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
  7965. #define DSI_PSR_UAN0_Pos (5U)
  7966. #define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
  7967. #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
  7968. #define DSI_PSR_RUE0_Pos (6U)
  7969. #define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
  7970. #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
  7971. #define DSI_PSR_PSS1_Pos (7U)
  7972. #define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
  7973. #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
  7974. #define DSI_PSR_UAN1_Pos (8U)
  7975. #define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
  7976. #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
  7977. /******************* Bit definition for DSI_ISR0 register ***************/
  7978. #define DSI_ISR0_AE0_Pos (0U)
  7979. #define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
  7980. #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
  7981. #define DSI_ISR0_AE1_Pos (1U)
  7982. #define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
  7983. #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
  7984. #define DSI_ISR0_AE2_Pos (2U)
  7985. #define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
  7986. #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
  7987. #define DSI_ISR0_AE3_Pos (3U)
  7988. #define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
  7989. #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
  7990. #define DSI_ISR0_AE4_Pos (4U)
  7991. #define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
  7992. #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
  7993. #define DSI_ISR0_AE5_Pos (5U)
  7994. #define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
  7995. #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
  7996. #define DSI_ISR0_AE6_Pos (6U)
  7997. #define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
  7998. #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
  7999. #define DSI_ISR0_AE7_Pos (7U)
  8000. #define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
  8001. #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
  8002. #define DSI_ISR0_AE8_Pos (8U)
  8003. #define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
  8004. #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
  8005. #define DSI_ISR0_AE9_Pos (9U)
  8006. #define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
  8007. #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
  8008. #define DSI_ISR0_AE10_Pos (10U)
  8009. #define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
  8010. #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
  8011. #define DSI_ISR0_AE11_Pos (11U)
  8012. #define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
  8013. #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
  8014. #define DSI_ISR0_AE12_Pos (12U)
  8015. #define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
  8016. #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
  8017. #define DSI_ISR0_AE13_Pos (13U)
  8018. #define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
  8019. #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
  8020. #define DSI_ISR0_AE14_Pos (14U)
  8021. #define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
  8022. #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
  8023. #define DSI_ISR0_AE15_Pos (15U)
  8024. #define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
  8025. #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
  8026. #define DSI_ISR0_PE0_Pos (16U)
  8027. #define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
  8028. #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
  8029. #define DSI_ISR0_PE1_Pos (17U)
  8030. #define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
  8031. #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
  8032. #define DSI_ISR0_PE2_Pos (18U)
  8033. #define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
  8034. #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
  8035. #define DSI_ISR0_PE3_Pos (19U)
  8036. #define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
  8037. #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
  8038. #define DSI_ISR0_PE4_Pos (20U)
  8039. #define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
  8040. #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
  8041. /******************* Bit definition for DSI_ISR1 register ***************/
  8042. #define DSI_ISR1_TOHSTX_Pos (0U)
  8043. #define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
  8044. #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
  8045. #define DSI_ISR1_TOLPRX_Pos (1U)
  8046. #define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
  8047. #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
  8048. #define DSI_ISR1_ECCSE_Pos (2U)
  8049. #define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
  8050. #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
  8051. #define DSI_ISR1_ECCME_Pos (3U)
  8052. #define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
  8053. #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
  8054. #define DSI_ISR1_CRCE_Pos (4U)
  8055. #define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
  8056. #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
  8057. #define DSI_ISR1_PSE_Pos (5U)
  8058. #define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
  8059. #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
  8060. #define DSI_ISR1_EOTPE_Pos (6U)
  8061. #define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
  8062. #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
  8063. #define DSI_ISR1_LPWRE_Pos (7U)
  8064. #define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
  8065. #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
  8066. #define DSI_ISR1_GCWRE_Pos (8U)
  8067. #define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
  8068. #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
  8069. #define DSI_ISR1_GPWRE_Pos (9U)
  8070. #define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
  8071. #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
  8072. #define DSI_ISR1_GPTXE_Pos (10U)
  8073. #define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
  8074. #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
  8075. #define DSI_ISR1_GPRDE_Pos (11U)
  8076. #define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
  8077. #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
  8078. #define DSI_ISR1_GPRXE_Pos (12U)
  8079. #define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
  8080. #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
  8081. /******************* Bit definition for DSI_IER0 register ***************/
  8082. #define DSI_IER0_AE0IE_Pos (0U)
  8083. #define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
  8084. #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
  8085. #define DSI_IER0_AE1IE_Pos (1U)
  8086. #define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
  8087. #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
  8088. #define DSI_IER0_AE2IE_Pos (2U)
  8089. #define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
  8090. #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
  8091. #define DSI_IER0_AE3IE_Pos (3U)
  8092. #define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
  8093. #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
  8094. #define DSI_IER0_AE4IE_Pos (4U)
  8095. #define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
  8096. #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
  8097. #define DSI_IER0_AE5IE_Pos (5U)
  8098. #define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
  8099. #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
  8100. #define DSI_IER0_AE6IE_Pos (6U)
  8101. #define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
  8102. #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
  8103. #define DSI_IER0_AE7IE_Pos (7U)
  8104. #define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
  8105. #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
  8106. #define DSI_IER0_AE8IE_Pos (8U)
  8107. #define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
  8108. #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
  8109. #define DSI_IER0_AE9IE_Pos (9U)
  8110. #define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
  8111. #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
  8112. #define DSI_IER0_AE10IE_Pos (10U)
  8113. #define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
  8114. #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
  8115. #define DSI_IER0_AE11IE_Pos (11U)
  8116. #define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
  8117. #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
  8118. #define DSI_IER0_AE12IE_Pos (12U)
  8119. #define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
  8120. #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
  8121. #define DSI_IER0_AE13IE_Pos (13U)
  8122. #define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
  8123. #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
  8124. #define DSI_IER0_AE14IE_Pos (14U)
  8125. #define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
  8126. #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
  8127. #define DSI_IER0_AE15IE_Pos (15U)
  8128. #define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
  8129. #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
  8130. #define DSI_IER0_PE0IE_Pos (16U)
  8131. #define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
  8132. #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
  8133. #define DSI_IER0_PE1IE_Pos (17U)
  8134. #define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
  8135. #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
  8136. #define DSI_IER0_PE2IE_Pos (18U)
  8137. #define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
  8138. #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
  8139. #define DSI_IER0_PE3IE_Pos (19U)
  8140. #define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
  8141. #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
  8142. #define DSI_IER0_PE4IE_Pos (20U)
  8143. #define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
  8144. #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
  8145. /******************* Bit definition for DSI_IER1 register ***************/
  8146. #define DSI_IER1_TOHSTXIE_Pos (0U)
  8147. #define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
  8148. #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
  8149. #define DSI_IER1_TOLPRXIE_Pos (1U)
  8150. #define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
  8151. #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
  8152. #define DSI_IER1_ECCSEIE_Pos (2U)
  8153. #define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
  8154. #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
  8155. #define DSI_IER1_ECCMEIE_Pos (3U)
  8156. #define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
  8157. #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
  8158. #define DSI_IER1_CRCEIE_Pos (4U)
  8159. #define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
  8160. #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
  8161. #define DSI_IER1_PSEIE_Pos (5U)
  8162. #define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
  8163. #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
  8164. #define DSI_IER1_EOTPEIE_Pos (6U)
  8165. #define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
  8166. #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
  8167. #define DSI_IER1_LPWREIE_Pos (7U)
  8168. #define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
  8169. #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
  8170. #define DSI_IER1_GCWREIE_Pos (8U)
  8171. #define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
  8172. #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
  8173. #define DSI_IER1_GPWREIE_Pos (9U)
  8174. #define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
  8175. #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
  8176. #define DSI_IER1_GPTXEIE_Pos (10U)
  8177. #define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
  8178. #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
  8179. #define DSI_IER1_GPRDEIE_Pos (11U)
  8180. #define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
  8181. #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
  8182. #define DSI_IER1_GPRXEIE_Pos (12U)
  8183. #define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
  8184. #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
  8185. /******************* Bit definition for DSI_FIR0 register ***************/
  8186. #define DSI_FIR0_FAE0_Pos (0U)
  8187. #define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
  8188. #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
  8189. #define DSI_FIR0_FAE1_Pos (1U)
  8190. #define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
  8191. #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
  8192. #define DSI_FIR0_FAE2_Pos (2U)
  8193. #define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
  8194. #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
  8195. #define DSI_FIR0_FAE3_Pos (3U)
  8196. #define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
  8197. #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
  8198. #define DSI_FIR0_FAE4_Pos (4U)
  8199. #define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
  8200. #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
  8201. #define DSI_FIR0_FAE5_Pos (5U)
  8202. #define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
  8203. #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
  8204. #define DSI_FIR0_FAE6_Pos (6U)
  8205. #define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
  8206. #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
  8207. #define DSI_FIR0_FAE7_Pos (7U)
  8208. #define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
  8209. #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
  8210. #define DSI_FIR0_FAE8_Pos (8U)
  8211. #define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
  8212. #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
  8213. #define DSI_FIR0_FAE9_Pos (9U)
  8214. #define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
  8215. #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
  8216. #define DSI_FIR0_FAE10_Pos (10U)
  8217. #define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
  8218. #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
  8219. #define DSI_FIR0_FAE11_Pos (11U)
  8220. #define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
  8221. #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
  8222. #define DSI_FIR0_FAE12_Pos (12U)
  8223. #define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
  8224. #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
  8225. #define DSI_FIR0_FAE13_Pos (13U)
  8226. #define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
  8227. #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
  8228. #define DSI_FIR0_FAE14_Pos (14U)
  8229. #define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
  8230. #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
  8231. #define DSI_FIR0_FAE15_Pos (15U)
  8232. #define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
  8233. #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
  8234. #define DSI_FIR0_FPE0_Pos (16U)
  8235. #define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
  8236. #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
  8237. #define DSI_FIR0_FPE1_Pos (17U)
  8238. #define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
  8239. #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
  8240. #define DSI_FIR0_FPE2_Pos (18U)
  8241. #define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
  8242. #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
  8243. #define DSI_FIR0_FPE3_Pos (19U)
  8244. #define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
  8245. #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
  8246. #define DSI_FIR0_FPE4_Pos (20U)
  8247. #define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
  8248. #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
  8249. /******************* Bit definition for DSI_FIR1 register ***************/
  8250. #define DSI_FIR1_FTOHSTX_Pos (0U)
  8251. #define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
  8252. #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
  8253. #define DSI_FIR1_FTOLPRX_Pos (1U)
  8254. #define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
  8255. #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
  8256. #define DSI_FIR1_FECCSE_Pos (2U)
  8257. #define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
  8258. #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
  8259. #define DSI_FIR1_FECCME_Pos (3U)
  8260. #define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
  8261. #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
  8262. #define DSI_FIR1_FCRCE_Pos (4U)
  8263. #define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
  8264. #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
  8265. #define DSI_FIR1_FPSE_Pos (5U)
  8266. #define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
  8267. #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
  8268. #define DSI_FIR1_FEOTPE_Pos (6U)
  8269. #define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
  8270. #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
  8271. #define DSI_FIR1_FLPWRE_Pos (7U)
  8272. #define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
  8273. #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
  8274. #define DSI_FIR1_FGCWRE_Pos (8U)
  8275. #define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
  8276. #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
  8277. #define DSI_FIR1_FGPWRE_Pos (9U)
  8278. #define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
  8279. #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
  8280. #define DSI_FIR1_FGPTXE_Pos (10U)
  8281. #define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
  8282. #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
  8283. #define DSI_FIR1_FGPRDE_Pos (11U)
  8284. #define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
  8285. #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
  8286. #define DSI_FIR1_FGPRXE_Pos (12U)
  8287. #define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
  8288. #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
  8289. /******************* Bit definition for DSI_VSCR register ***************/
  8290. #define DSI_VSCR_EN_Pos (0U)
  8291. #define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
  8292. #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
  8293. #define DSI_VSCR_UR_Pos (8U)
  8294. #define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
  8295. #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
  8296. /******************* Bit definition for DSI_LCVCIDR register ************/
  8297. #define DSI_LCVCIDR_VCID_Pos (0U)
  8298. #define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
  8299. #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
  8300. #define DSI_LCVCIDR_VCID0_Pos (0U)
  8301. #define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
  8302. #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
  8303. #define DSI_LCVCIDR_VCID1_Pos (1U)
  8304. #define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
  8305. #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
  8306. /******************* Bit definition for DSI_LCCCR register **************/
  8307. #define DSI_LCCCR_COLC_Pos (0U)
  8308. #define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
  8309. #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
  8310. #define DSI_LCCCR_COLC0_Pos (0U)
  8311. #define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
  8312. #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
  8313. #define DSI_LCCCR_COLC1_Pos (1U)
  8314. #define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
  8315. #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
  8316. #define DSI_LCCCR_COLC2_Pos (2U)
  8317. #define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
  8318. #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
  8319. #define DSI_LCCCR_COLC3_Pos (3U)
  8320. #define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
  8321. #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
  8322. #define DSI_LCCCR_LPE_Pos (8U)
  8323. #define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
  8324. #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
  8325. /******************* Bit definition for DSI_LPMCCR register *************/
  8326. #define DSI_LPMCCR_VLPSIZE_Pos (0U)
  8327. #define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
  8328. #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
  8329. #define DSI_LPMCCR_VLPSIZE0_Pos (0U)
  8330. #define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
  8331. #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
  8332. #define DSI_LPMCCR_VLPSIZE1_Pos (1U)
  8333. #define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
  8334. #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
  8335. #define DSI_LPMCCR_VLPSIZE2_Pos (2U)
  8336. #define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
  8337. #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
  8338. #define DSI_LPMCCR_VLPSIZE3_Pos (3U)
  8339. #define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
  8340. #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
  8341. #define DSI_LPMCCR_VLPSIZE4_Pos (4U)
  8342. #define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
  8343. #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
  8344. #define DSI_LPMCCR_VLPSIZE5_Pos (5U)
  8345. #define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
  8346. #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
  8347. #define DSI_LPMCCR_VLPSIZE6_Pos (6U)
  8348. #define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
  8349. #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
  8350. #define DSI_LPMCCR_VLPSIZE7_Pos (7U)
  8351. #define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
  8352. #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
  8353. #define DSI_LPMCCR_LPSIZE_Pos (16U)
  8354. #define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
  8355. #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
  8356. #define DSI_LPMCCR_LPSIZE0_Pos (16U)
  8357. #define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
  8358. #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
  8359. #define DSI_LPMCCR_LPSIZE1_Pos (17U)
  8360. #define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
  8361. #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
  8362. #define DSI_LPMCCR_LPSIZE2_Pos (18U)
  8363. #define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
  8364. #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
  8365. #define DSI_LPMCCR_LPSIZE3_Pos (19U)
  8366. #define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
  8367. #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
  8368. #define DSI_LPMCCR_LPSIZE4_Pos (20U)
  8369. #define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
  8370. #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
  8371. #define DSI_LPMCCR_LPSIZE5_Pos (21U)
  8372. #define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
  8373. #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
  8374. #define DSI_LPMCCR_LPSIZE6_Pos (22U)
  8375. #define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
  8376. #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
  8377. #define DSI_LPMCCR_LPSIZE7_Pos (23U)
  8378. #define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
  8379. #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
  8380. /******************* Bit definition for DSI_VMCCR register **************/
  8381. #define DSI_VMCCR_VMT_Pos (0U)
  8382. #define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
  8383. #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
  8384. #define DSI_VMCCR_VMT0_Pos (0U)
  8385. #define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
  8386. #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
  8387. #define DSI_VMCCR_VMT1_Pos (1U)
  8388. #define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
  8389. #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
  8390. #define DSI_VMCCR_LPVSAE_Pos (8U)
  8391. #define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
  8392. #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
  8393. #define DSI_VMCCR_LPVBPE_Pos (9U)
  8394. #define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
  8395. #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
  8396. #define DSI_VMCCR_LPVFPE_Pos (10U)
  8397. #define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
  8398. #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
  8399. #define DSI_VMCCR_LPVAE_Pos (11U)
  8400. #define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
  8401. #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
  8402. #define DSI_VMCCR_LPHBPE_Pos (12U)
  8403. #define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
  8404. #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
  8405. #define DSI_VMCCR_LPHFE_Pos (13U)
  8406. #define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
  8407. #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
  8408. #define DSI_VMCCR_FBTAAE_Pos (14U)
  8409. #define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
  8410. #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
  8411. #define DSI_VMCCR_LPCE_Pos (15U)
  8412. #define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
  8413. #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
  8414. /******************* Bit definition for DSI_VPCCR register **************/
  8415. #define DSI_VPCCR_VPSIZE_Pos (0U)
  8416. #define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
  8417. #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
  8418. #define DSI_VPCCR_VPSIZE0_Pos (0U)
  8419. #define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
  8420. #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
  8421. #define DSI_VPCCR_VPSIZE1_Pos (1U)
  8422. #define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
  8423. #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
  8424. #define DSI_VPCCR_VPSIZE2_Pos (2U)
  8425. #define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
  8426. #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
  8427. #define DSI_VPCCR_VPSIZE3_Pos (3U)
  8428. #define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
  8429. #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
  8430. #define DSI_VPCCR_VPSIZE4_Pos (4U)
  8431. #define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
  8432. #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
  8433. #define DSI_VPCCR_VPSIZE5_Pos (5U)
  8434. #define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
  8435. #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
  8436. #define DSI_VPCCR_VPSIZE6_Pos (6U)
  8437. #define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
  8438. #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
  8439. #define DSI_VPCCR_VPSIZE7_Pos (7U)
  8440. #define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
  8441. #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
  8442. #define DSI_VPCCR_VPSIZE8_Pos (8U)
  8443. #define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
  8444. #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
  8445. #define DSI_VPCCR_VPSIZE9_Pos (9U)
  8446. #define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
  8447. #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
  8448. #define DSI_VPCCR_VPSIZE10_Pos (10U)
  8449. #define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
  8450. #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
  8451. #define DSI_VPCCR_VPSIZE11_Pos (11U)
  8452. #define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
  8453. #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
  8454. #define DSI_VPCCR_VPSIZE12_Pos (12U)
  8455. #define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
  8456. #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
  8457. #define DSI_VPCCR_VPSIZE13_Pos (13U)
  8458. #define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
  8459. #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
  8460. /******************* Bit definition for DSI_VCCCR register **************/
  8461. #define DSI_VCCCR_NUMC_Pos (0U)
  8462. #define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
  8463. #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
  8464. #define DSI_VCCCR_NUMC0_Pos (0U)
  8465. #define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
  8466. #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
  8467. #define DSI_VCCCR_NUMC1_Pos (1U)
  8468. #define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
  8469. #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
  8470. #define DSI_VCCCR_NUMC2_Pos (2U)
  8471. #define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
  8472. #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
  8473. #define DSI_VCCCR_NUMC3_Pos (3U)
  8474. #define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
  8475. #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
  8476. #define DSI_VCCCR_NUMC4_Pos (4U)
  8477. #define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
  8478. #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
  8479. #define DSI_VCCCR_NUMC5_Pos (5U)
  8480. #define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
  8481. #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
  8482. #define DSI_VCCCR_NUMC6_Pos (6U)
  8483. #define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
  8484. #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
  8485. #define DSI_VCCCR_NUMC7_Pos (7U)
  8486. #define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
  8487. #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
  8488. #define DSI_VCCCR_NUMC8_Pos (8U)
  8489. #define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
  8490. #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
  8491. #define DSI_VCCCR_NUMC9_Pos (9U)
  8492. #define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
  8493. #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
  8494. #define DSI_VCCCR_NUMC10_Pos (10U)
  8495. #define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
  8496. #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
  8497. #define DSI_VCCCR_NUMC11_Pos (11U)
  8498. #define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
  8499. #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
  8500. #define DSI_VCCCR_NUMC12_Pos (12U)
  8501. #define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
  8502. #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
  8503. /******************* Bit definition for DSI_VNPCCR register *************/
  8504. #define DSI_VNPCCR_NPSIZE_Pos (0U)
  8505. #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
  8506. #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
  8507. #define DSI_VNPCCR_NPSIZE0_Pos (0U)
  8508. #define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
  8509. #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
  8510. #define DSI_VNPCCR_NPSIZE1_Pos (1U)
  8511. #define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
  8512. #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
  8513. #define DSI_VNPCCR_NPSIZE2_Pos (2U)
  8514. #define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
  8515. #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
  8516. #define DSI_VNPCCR_NPSIZE3_Pos (3U)
  8517. #define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
  8518. #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
  8519. #define DSI_VNPCCR_NPSIZE4_Pos (4U)
  8520. #define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
  8521. #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
  8522. #define DSI_VNPCCR_NPSIZE5_Pos (5U)
  8523. #define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
  8524. #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
  8525. #define DSI_VNPCCR_NPSIZE6_Pos (6U)
  8526. #define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
  8527. #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
  8528. #define DSI_VNPCCR_NPSIZE7_Pos (7U)
  8529. #define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
  8530. #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
  8531. #define DSI_VNPCCR_NPSIZE8_Pos (8U)
  8532. #define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
  8533. #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
  8534. #define DSI_VNPCCR_NPSIZE9_Pos (9U)
  8535. #define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
  8536. #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
  8537. #define DSI_VNPCCR_NPSIZE10_Pos (10U)
  8538. #define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
  8539. #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
  8540. #define DSI_VNPCCR_NPSIZE11_Pos (11U)
  8541. #define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
  8542. #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
  8543. #define DSI_VNPCCR_NPSIZE12_Pos (12U)
  8544. #define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
  8545. #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
  8546. /******************* Bit definition for DSI_VHSACCR register ************/
  8547. #define DSI_VHSACCR_HSA_Pos (0U)
  8548. #define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
  8549. #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
  8550. #define DSI_VHSACCR_HSA0_Pos (0U)
  8551. #define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
  8552. #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
  8553. #define DSI_VHSACCR_HSA1_Pos (1U)
  8554. #define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
  8555. #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
  8556. #define DSI_VHSACCR_HSA2_Pos (2U)
  8557. #define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
  8558. #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
  8559. #define DSI_VHSACCR_HSA3_Pos (3U)
  8560. #define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
  8561. #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
  8562. #define DSI_VHSACCR_HSA4_Pos (4U)
  8563. #define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
  8564. #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
  8565. #define DSI_VHSACCR_HSA5_Pos (5U)
  8566. #define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
  8567. #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
  8568. #define DSI_VHSACCR_HSA6_Pos (6U)
  8569. #define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
  8570. #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
  8571. #define DSI_VHSACCR_HSA7_Pos (7U)
  8572. #define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
  8573. #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
  8574. #define DSI_VHSACCR_HSA8_Pos (8U)
  8575. #define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
  8576. #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
  8577. #define DSI_VHSACCR_HSA9_Pos (9U)
  8578. #define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
  8579. #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
  8580. #define DSI_VHSACCR_HSA10_Pos (10U)
  8581. #define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
  8582. #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
  8583. #define DSI_VHSACCR_HSA11_Pos (11U)
  8584. #define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
  8585. #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
  8586. /******************* Bit definition for DSI_VHBPCCR register ************/
  8587. #define DSI_VHBPCCR_HBP_Pos (0U)
  8588. #define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
  8589. #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
  8590. #define DSI_VHBPCCR_HBP0_Pos (0U)
  8591. #define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
  8592. #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
  8593. #define DSI_VHBPCCR_HBP1_Pos (1U)
  8594. #define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
  8595. #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
  8596. #define DSI_VHBPCCR_HBP2_Pos (2U)
  8597. #define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
  8598. #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
  8599. #define DSI_VHBPCCR_HBP3_Pos (3U)
  8600. #define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
  8601. #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
  8602. #define DSI_VHBPCCR_HBP4_Pos (4U)
  8603. #define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
  8604. #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
  8605. #define DSI_VHBPCCR_HBP5_Pos (5U)
  8606. #define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
  8607. #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
  8608. #define DSI_VHBPCCR_HBP6_Pos (6U)
  8609. #define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
  8610. #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
  8611. #define DSI_VHBPCCR_HBP7_Pos (7U)
  8612. #define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
  8613. #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
  8614. #define DSI_VHBPCCR_HBP8_Pos (8U)
  8615. #define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
  8616. #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
  8617. #define DSI_VHBPCCR_HBP9_Pos (9U)
  8618. #define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
  8619. #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
  8620. #define DSI_VHBPCCR_HBP10_Pos (10U)
  8621. #define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
  8622. #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
  8623. #define DSI_VHBPCCR_HBP11_Pos (11U)
  8624. #define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
  8625. #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
  8626. /******************* Bit definition for DSI_VLCCR register **************/
  8627. #define DSI_VLCCR_HLINE_Pos (0U)
  8628. #define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
  8629. #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
  8630. #define DSI_VLCCR_HLINE0_Pos (0U)
  8631. #define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
  8632. #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
  8633. #define DSI_VLCCR_HLINE1_Pos (1U)
  8634. #define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
  8635. #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
  8636. #define DSI_VLCCR_HLINE2_Pos (2U)
  8637. #define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
  8638. #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
  8639. #define DSI_VLCCR_HLINE3_Pos (3U)
  8640. #define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
  8641. #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
  8642. #define DSI_VLCCR_HLINE4_Pos (4U)
  8643. #define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
  8644. #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
  8645. #define DSI_VLCCR_HLINE5_Pos (5U)
  8646. #define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
  8647. #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
  8648. #define DSI_VLCCR_HLINE6_Pos (6U)
  8649. #define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
  8650. #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
  8651. #define DSI_VLCCR_HLINE7_Pos (7U)
  8652. #define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
  8653. #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
  8654. #define DSI_VLCCR_HLINE8_Pos (8U)
  8655. #define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
  8656. #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
  8657. #define DSI_VLCCR_HLINE9_Pos (9U)
  8658. #define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
  8659. #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
  8660. #define DSI_VLCCR_HLINE10_Pos (10U)
  8661. #define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
  8662. #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
  8663. #define DSI_VLCCR_HLINE11_Pos (11U)
  8664. #define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
  8665. #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
  8666. #define DSI_VLCCR_HLINE12_Pos (12U)
  8667. #define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
  8668. #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
  8669. #define DSI_VLCCR_HLINE13_Pos (13U)
  8670. #define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
  8671. #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
  8672. #define DSI_VLCCR_HLINE14_Pos (14U)
  8673. #define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
  8674. #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
  8675. /******************* Bit definition for DSI_VVSACCR register ***************/
  8676. #define DSI_VVSACCR_VSA_Pos (0U)
  8677. #define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
  8678. #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
  8679. #define DSI_VVSACCR_VSA0_Pos (0U)
  8680. #define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
  8681. #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
  8682. #define DSI_VVSACCR_VSA1_Pos (1U)
  8683. #define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
  8684. #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
  8685. #define DSI_VVSACCR_VSA2_Pos (2U)
  8686. #define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
  8687. #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
  8688. #define DSI_VVSACCR_VSA3_Pos (3U)
  8689. #define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
  8690. #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
  8691. #define DSI_VVSACCR_VSA4_Pos (4U)
  8692. #define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
  8693. #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
  8694. #define DSI_VVSACCR_VSA5_Pos (5U)
  8695. #define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
  8696. #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
  8697. #define DSI_VVSACCR_VSA6_Pos (6U)
  8698. #define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
  8699. #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
  8700. #define DSI_VVSACCR_VSA7_Pos (7U)
  8701. #define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
  8702. #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
  8703. #define DSI_VVSACCR_VSA8_Pos (8U)
  8704. #define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
  8705. #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
  8706. #define DSI_VVSACCR_VSA9_Pos (9U)
  8707. #define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
  8708. #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
  8709. /******************* Bit definition for DSI_VVBPCCR register ************/
  8710. #define DSI_VVBPCCR_VBP_Pos (0U)
  8711. #define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
  8712. #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
  8713. #define DSI_VVBPCCR_VBP0_Pos (0U)
  8714. #define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
  8715. #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
  8716. #define DSI_VVBPCCR_VBP1_Pos (1U)
  8717. #define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
  8718. #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
  8719. #define DSI_VVBPCCR_VBP2_Pos (2U)
  8720. #define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
  8721. #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
  8722. #define DSI_VVBPCCR_VBP3_Pos (3U)
  8723. #define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
  8724. #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
  8725. #define DSI_VVBPCCR_VBP4_Pos (4U)
  8726. #define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
  8727. #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
  8728. #define DSI_VVBPCCR_VBP5_Pos (5U)
  8729. #define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
  8730. #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
  8731. #define DSI_VVBPCCR_VBP6_Pos (6U)
  8732. #define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
  8733. #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
  8734. #define DSI_VVBPCCR_VBP7_Pos (7U)
  8735. #define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
  8736. #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
  8737. #define DSI_VVBPCCR_VBP8_Pos (8U)
  8738. #define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
  8739. #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
  8740. #define DSI_VVBPCCR_VBP9_Pos (9U)
  8741. #define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
  8742. #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
  8743. /******************* Bit definition for DSI_VVFPCCR register ************/
  8744. #define DSI_VVFPCCR_VFP_Pos (0U)
  8745. #define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
  8746. #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
  8747. #define DSI_VVFPCCR_VFP0_Pos (0U)
  8748. #define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
  8749. #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
  8750. #define DSI_VVFPCCR_VFP1_Pos (1U)
  8751. #define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
  8752. #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
  8753. #define DSI_VVFPCCR_VFP2_Pos (2U)
  8754. #define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
  8755. #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
  8756. #define DSI_VVFPCCR_VFP3_Pos (3U)
  8757. #define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
  8758. #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
  8759. #define DSI_VVFPCCR_VFP4_Pos (4U)
  8760. #define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
  8761. #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
  8762. #define DSI_VVFPCCR_VFP5_Pos (5U)
  8763. #define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
  8764. #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
  8765. #define DSI_VVFPCCR_VFP6_Pos (6U)
  8766. #define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
  8767. #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
  8768. #define DSI_VVFPCCR_VFP7_Pos (7U)
  8769. #define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
  8770. #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
  8771. #define DSI_VVFPCCR_VFP8_Pos (8U)
  8772. #define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
  8773. #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
  8774. #define DSI_VVFPCCR_VFP9_Pos (9U)
  8775. #define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
  8776. #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
  8777. /******************* Bit definition for DSI_VVACCR register *************/
  8778. #define DSI_VVACCR_VA_Pos (0U)
  8779. #define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
  8780. #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
  8781. #define DSI_VVACCR_VA0_Pos (0U)
  8782. #define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
  8783. #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
  8784. #define DSI_VVACCR_VA1_Pos (1U)
  8785. #define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
  8786. #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
  8787. #define DSI_VVACCR_VA2_Pos (2U)
  8788. #define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
  8789. #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
  8790. #define DSI_VVACCR_VA3_Pos (3U)
  8791. #define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
  8792. #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
  8793. #define DSI_VVACCR_VA4_Pos (4U)
  8794. #define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
  8795. #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
  8796. #define DSI_VVACCR_VA5_Pos (5U)
  8797. #define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
  8798. #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
  8799. #define DSI_VVACCR_VA6_Pos (6U)
  8800. #define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
  8801. #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
  8802. #define DSI_VVACCR_VA7_Pos (7U)
  8803. #define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
  8804. #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
  8805. #define DSI_VVACCR_VA8_Pos (8U)
  8806. #define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
  8807. #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
  8808. #define DSI_VVACCR_VA9_Pos (9U)
  8809. #define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
  8810. #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
  8811. #define DSI_VVACCR_VA10_Pos (10U)
  8812. #define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
  8813. #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
  8814. #define DSI_VVACCR_VA11_Pos (11U)
  8815. #define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
  8816. #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
  8817. #define DSI_VVACCR_VA12_Pos (12U)
  8818. #define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
  8819. #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
  8820. #define DSI_VVACCR_VA13_Pos (13U)
  8821. #define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
  8822. #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
  8823. /******************* Bit definition for DSI_TDCCR register **************/
  8824. #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
  8825. #define DSI_TDCCR_3DM0 0x00000001U
  8826. #define DSI_TDCCR_3DM1 0x00000002U
  8827. #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
  8828. #define DSI_TDCCR_3DF0 0x00000004U
  8829. #define DSI_TDCCR_3DF1 0x00000008U
  8830. #define DSI_TDCCR_SVS_Pos (4U)
  8831. #define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
  8832. #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
  8833. #define DSI_TDCCR_RF_Pos (5U)
  8834. #define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
  8835. #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
  8836. #define DSI_TDCCR_S3DC_Pos (16U)
  8837. #define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
  8838. #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
  8839. /******************* Bit definition for DSI_WCFGR register ***************/
  8840. #define DSI_WCFGR_DSIM_Pos (0U)
  8841. #define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
  8842. #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
  8843. #define DSI_WCFGR_COLMUX_Pos (1U)
  8844. #define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
  8845. #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
  8846. #define DSI_WCFGR_COLMUX0_Pos (1U)
  8847. #define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
  8848. #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
  8849. #define DSI_WCFGR_COLMUX1_Pos (2U)
  8850. #define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
  8851. #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
  8852. #define DSI_WCFGR_COLMUX2_Pos (3U)
  8853. #define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
  8854. #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
  8855. #define DSI_WCFGR_TESRC_Pos (4U)
  8856. #define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
  8857. #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
  8858. #define DSI_WCFGR_TEPOL_Pos (5U)
  8859. #define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
  8860. #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
  8861. #define DSI_WCFGR_AR_Pos (6U)
  8862. #define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
  8863. #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
  8864. #define DSI_WCFGR_VSPOL_Pos (7U)
  8865. #define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
  8866. #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
  8867. /******************* Bit definition for DSI_WCR register *****************/
  8868. #define DSI_WCR_COLM_Pos (0U)
  8869. #define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
  8870. #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
  8871. #define DSI_WCR_SHTDN_Pos (1U)
  8872. #define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
  8873. #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
  8874. #define DSI_WCR_LTDCEN_Pos (2U)
  8875. #define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
  8876. #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
  8877. #define DSI_WCR_DSIEN_Pos (3U)
  8878. #define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
  8879. #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
  8880. /******************* Bit definition for DSI_WIER register ****************/
  8881. #define DSI_WIER_TEIE_Pos (0U)
  8882. #define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
  8883. #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
  8884. #define DSI_WIER_ERIE_Pos (1U)
  8885. #define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
  8886. #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
  8887. #define DSI_WIER_PLLLIE_Pos (9U)
  8888. #define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
  8889. #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
  8890. #define DSI_WIER_PLLUIE_Pos (10U)
  8891. #define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
  8892. #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
  8893. #define DSI_WIER_RRIE_Pos (13U)
  8894. #define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
  8895. #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
  8896. /******************* Bit definition for DSI_WISR register ****************/
  8897. #define DSI_WISR_TEIF_Pos (0U)
  8898. #define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
  8899. #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
  8900. #define DSI_WISR_ERIF_Pos (1U)
  8901. #define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
  8902. #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
  8903. #define DSI_WISR_BUSY_Pos (2U)
  8904. #define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
  8905. #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
  8906. #define DSI_WISR_PLLLS_Pos (8U)
  8907. #define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
  8908. #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
  8909. #define DSI_WISR_PLLLIF_Pos (9U)
  8910. #define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
  8911. #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
  8912. #define DSI_WISR_PLLUIF_Pos (10U)
  8913. #define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
  8914. #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
  8915. #define DSI_WISR_RRS_Pos (12U)
  8916. #define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
  8917. #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
  8918. #define DSI_WISR_RRIF_Pos (13U)
  8919. #define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
  8920. #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
  8921. /******************* Bit definition for DSI_WIFCR register ***************/
  8922. #define DSI_WIFCR_CTEIF_Pos (0U)
  8923. #define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
  8924. #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
  8925. #define DSI_WIFCR_CERIF_Pos (1U)
  8926. #define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
  8927. #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
  8928. #define DSI_WIFCR_CPLLLIF_Pos (9U)
  8929. #define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
  8930. #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
  8931. #define DSI_WIFCR_CPLLUIF_Pos (10U)
  8932. #define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
  8933. #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
  8934. #define DSI_WIFCR_CRRIF_Pos (13U)
  8935. #define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
  8936. #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
  8937. /******************* Bit definition for DSI_WPCR0 register ***************/
  8938. #define DSI_WPCR0_UIX4_Pos (0U)
  8939. #define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
  8940. #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
  8941. #define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
  8942. #define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
  8943. #define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
  8944. #define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
  8945. #define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
  8946. #define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
  8947. #define DSI_WPCR0_SWCL_Pos (6U)
  8948. #define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
  8949. #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
  8950. #define DSI_WPCR0_SWDL0_Pos (7U)
  8951. #define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
  8952. #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
  8953. #define DSI_WPCR0_SWDL1_Pos (8U)
  8954. #define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
  8955. #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
  8956. #define DSI_WPCR0_HSICL_Pos (9U)
  8957. #define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
  8958. #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
  8959. #define DSI_WPCR0_HSIDL0_Pos (10U)
  8960. #define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
  8961. #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
  8962. #define DSI_WPCR0_HSIDL1_Pos (11U)
  8963. #define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
  8964. #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
  8965. #define DSI_WPCR0_FTXSMCL_Pos (12U)
  8966. #define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
  8967. #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
  8968. #define DSI_WPCR0_FTXSMDL_Pos (13U)
  8969. #define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
  8970. #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
  8971. #define DSI_WPCR0_CDOFFDL_Pos (14U)
  8972. #define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
  8973. #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
  8974. #define DSI_WPCR0_TDDL_Pos (16U)
  8975. #define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
  8976. #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
  8977. #define DSI_WPCR0_PDEN_Pos (18U)
  8978. #define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
  8979. #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
  8980. #define DSI_WPCR0_TCLKPREPEN_Pos (19U)
  8981. #define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
  8982. #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
  8983. #define DSI_WPCR0_TCLKZEROEN_Pos (20U)
  8984. #define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
  8985. #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
  8986. #define DSI_WPCR0_THSPREPEN_Pos (21U)
  8987. #define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
  8988. #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
  8989. #define DSI_WPCR0_THSTRAILEN_Pos (22U)
  8990. #define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
  8991. #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
  8992. #define DSI_WPCR0_THSZEROEN_Pos (23U)
  8993. #define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
  8994. #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
  8995. #define DSI_WPCR0_TLPXDEN_Pos (24U)
  8996. #define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
  8997. #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
  8998. #define DSI_WPCR0_THSEXITEN_Pos (25U)
  8999. #define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
  9000. #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
  9001. #define DSI_WPCR0_TLPXCEN_Pos (26U)
  9002. #define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
  9003. #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
  9004. #define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
  9005. #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
  9006. #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
  9007. /******************* Bit definition for DSI_WPCR1 register ***************/
  9008. #define DSI_WPCR1_HSTXDCL_Pos (0U)
  9009. #define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
  9010. #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
  9011. #define DSI_WPCR1_HSTXDCL0_Pos (0U)
  9012. #define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
  9013. #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
  9014. #define DSI_WPCR1_HSTXDCL1_Pos (1U)
  9015. #define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
  9016. #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
  9017. #define DSI_WPCR1_HSTXDDL_Pos (2U)
  9018. #define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
  9019. #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
  9020. #define DSI_WPCR1_HSTXDDL0_Pos (2U)
  9021. #define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
  9022. #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
  9023. #define DSI_WPCR1_HSTXDDL1_Pos (3U)
  9024. #define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
  9025. #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
  9026. #define DSI_WPCR1_LPSRCCL_Pos (6U)
  9027. #define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
  9028. #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
  9029. #define DSI_WPCR1_LPSRCCL0_Pos (6U)
  9030. #define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
  9031. #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
  9032. #define DSI_WPCR1_LPSRCCL1_Pos (7U)
  9033. #define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
  9034. #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
  9035. #define DSI_WPCR1_LPSRCDL_Pos (8U)
  9036. #define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
  9037. #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
  9038. #define DSI_WPCR1_LPSRCDL0_Pos (8U)
  9039. #define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
  9040. #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
  9041. #define DSI_WPCR1_LPSRCDL1_Pos (9U)
  9042. #define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
  9043. #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
  9044. #define DSI_WPCR1_SDDC_Pos (12U)
  9045. #define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
  9046. #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
  9047. #define DSI_WPCR1_LPRXVCDL_Pos (14U)
  9048. #define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
  9049. #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
  9050. #define DSI_WPCR1_LPRXVCDL0_Pos (14U)
  9051. #define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
  9052. #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
  9053. #define DSI_WPCR1_LPRXVCDL1_Pos (15U)
  9054. #define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
  9055. #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
  9056. #define DSI_WPCR1_HSTXSRCCL_Pos (16U)
  9057. #define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
  9058. #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
  9059. #define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
  9060. #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
  9061. #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
  9062. #define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
  9063. #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
  9064. #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
  9065. #define DSI_WPCR1_HSTXSRCDL_Pos (18U)
  9066. #define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
  9067. #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
  9068. #define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
  9069. #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
  9070. #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
  9071. #define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
  9072. #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
  9073. #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
  9074. #define DSI_WPCR1_FLPRXLPM_Pos (22U)
  9075. #define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
  9076. #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
  9077. #define DSI_WPCR1_LPRXFT_Pos (25U)
  9078. #define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
  9079. #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
  9080. #define DSI_WPCR1_LPRXFT0_Pos (25U)
  9081. #define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
  9082. #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
  9083. #define DSI_WPCR1_LPRXFT1_Pos (26U)
  9084. #define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
  9085. #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
  9086. /******************* Bit definition for DSI_WPCR2 register ***************/
  9087. #define DSI_WPCR2_TCLKPREP_Pos (0U)
  9088. #define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
  9089. #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
  9090. #define DSI_WPCR2_TCLKPREP0_Pos (0U)
  9091. #define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
  9092. #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
  9093. #define DSI_WPCR2_TCLKPREP1_Pos (1U)
  9094. #define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
  9095. #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
  9096. #define DSI_WPCR2_TCLKPREP2_Pos (2U)
  9097. #define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
  9098. #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
  9099. #define DSI_WPCR2_TCLKPREP3_Pos (3U)
  9100. #define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
  9101. #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
  9102. #define DSI_WPCR2_TCLKPREP4_Pos (4U)
  9103. #define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
  9104. #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
  9105. #define DSI_WPCR2_TCLKPREP5_Pos (5U)
  9106. #define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
  9107. #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
  9108. #define DSI_WPCR2_TCLKPREP6_Pos (6U)
  9109. #define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
  9110. #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
  9111. #define DSI_WPCR2_TCLKPREP7_Pos (7U)
  9112. #define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
  9113. #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
  9114. #define DSI_WPCR2_TCLKZERO_Pos (8U)
  9115. #define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
  9116. #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
  9117. #define DSI_WPCR2_TCLKZERO0_Pos (8U)
  9118. #define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
  9119. #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
  9120. #define DSI_WPCR2_TCLKZERO1_Pos (9U)
  9121. #define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
  9122. #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
  9123. #define DSI_WPCR2_TCLKZERO2_Pos (10U)
  9124. #define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
  9125. #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
  9126. #define DSI_WPCR2_TCLKZERO3_Pos (11U)
  9127. #define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
  9128. #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
  9129. #define DSI_WPCR2_TCLKZERO4_Pos (12U)
  9130. #define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
  9131. #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
  9132. #define DSI_WPCR2_TCLKZERO5_Pos (13U)
  9133. #define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
  9134. #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
  9135. #define DSI_WPCR2_TCLKZERO6_Pos (14U)
  9136. #define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
  9137. #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
  9138. #define DSI_WPCR2_TCLKZERO7_Pos (15U)
  9139. #define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
  9140. #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
  9141. #define DSI_WPCR2_THSPREP_Pos (16U)
  9142. #define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
  9143. #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
  9144. #define DSI_WPCR2_THSPREP0_Pos (16U)
  9145. #define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
  9146. #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
  9147. #define DSI_WPCR2_THSPREP1_Pos (17U)
  9148. #define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
  9149. #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
  9150. #define DSI_WPCR2_THSPREP2_Pos (18U)
  9151. #define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
  9152. #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
  9153. #define DSI_WPCR2_THSPREP3_Pos (19U)
  9154. #define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
  9155. #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
  9156. #define DSI_WPCR2_THSPREP4_Pos (20U)
  9157. #define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
  9158. #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
  9159. #define DSI_WPCR2_THSPREP5_Pos (21U)
  9160. #define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
  9161. #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
  9162. #define DSI_WPCR2_THSPREP6_Pos (22U)
  9163. #define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
  9164. #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
  9165. #define DSI_WPCR2_THSPREP7_Pos (23U)
  9166. #define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
  9167. #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
  9168. #define DSI_WPCR2_THSTRAIL_Pos (24U)
  9169. #define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
  9170. #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
  9171. #define DSI_WPCR2_THSTRAIL0_Pos (24U)
  9172. #define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
  9173. #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
  9174. #define DSI_WPCR2_THSTRAIL1_Pos (25U)
  9175. #define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
  9176. #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
  9177. #define DSI_WPCR2_THSTRAIL2_Pos (26U)
  9178. #define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
  9179. #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
  9180. #define DSI_WPCR2_THSTRAIL3_Pos (27U)
  9181. #define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
  9182. #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
  9183. #define DSI_WPCR2_THSTRAIL4_Pos (28U)
  9184. #define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
  9185. #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
  9186. #define DSI_WPCR2_THSTRAIL5_Pos (29U)
  9187. #define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
  9188. #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
  9189. #define DSI_WPCR2_THSTRAIL6_Pos (30U)
  9190. #define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
  9191. #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
  9192. #define DSI_WPCR2_THSTRAIL7_Pos (31U)
  9193. #define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
  9194. #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
  9195. /******************* Bit definition for DSI_WPCR3 register ***************/
  9196. #define DSI_WPCR3_THSZERO_Pos (0U)
  9197. #define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
  9198. #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
  9199. #define DSI_WPCR3_THSZERO0_Pos (0U)
  9200. #define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
  9201. #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
  9202. #define DSI_WPCR3_THSZERO1_Pos (1U)
  9203. #define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
  9204. #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
  9205. #define DSI_WPCR3_THSZERO2_Pos (2U)
  9206. #define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
  9207. #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
  9208. #define DSI_WPCR3_THSZERO3_Pos (3U)
  9209. #define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
  9210. #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
  9211. #define DSI_WPCR3_THSZERO4_Pos (4U)
  9212. #define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
  9213. #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
  9214. #define DSI_WPCR3_THSZERO5_Pos (5U)
  9215. #define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
  9216. #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
  9217. #define DSI_WPCR3_THSZERO6_Pos (6U)
  9218. #define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
  9219. #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
  9220. #define DSI_WPCR3_THSZERO7_Pos (7U)
  9221. #define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
  9222. #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
  9223. #define DSI_WPCR3_TLPXD_Pos (8U)
  9224. #define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
  9225. #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
  9226. #define DSI_WPCR3_TLPXD0_Pos (8U)
  9227. #define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
  9228. #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
  9229. #define DSI_WPCR3_TLPXD1_Pos (9U)
  9230. #define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
  9231. #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
  9232. #define DSI_WPCR3_TLPXD2_Pos (10U)
  9233. #define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
  9234. #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
  9235. #define DSI_WPCR3_TLPXD3_Pos (11U)
  9236. #define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
  9237. #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
  9238. #define DSI_WPCR3_TLPXD4_Pos (12U)
  9239. #define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
  9240. #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
  9241. #define DSI_WPCR3_TLPXD5_Pos (13U)
  9242. #define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
  9243. #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
  9244. #define DSI_WPCR3_TLPXD6_Pos (14U)
  9245. #define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
  9246. #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
  9247. #define DSI_WPCR3_TLPXD7_Pos (15U)
  9248. #define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
  9249. #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
  9250. #define DSI_WPCR3_THSEXIT_Pos (16U)
  9251. #define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
  9252. #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
  9253. #define DSI_WPCR3_THSEXIT0_Pos (16U)
  9254. #define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
  9255. #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
  9256. #define DSI_WPCR3_THSEXIT1_Pos (17U)
  9257. #define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
  9258. #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
  9259. #define DSI_WPCR3_THSEXIT2_Pos (18U)
  9260. #define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
  9261. #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
  9262. #define DSI_WPCR3_THSEXIT3_Pos (19U)
  9263. #define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
  9264. #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
  9265. #define DSI_WPCR3_THSEXIT4_Pos (20U)
  9266. #define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
  9267. #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
  9268. #define DSI_WPCR3_THSEXIT5_Pos (21U)
  9269. #define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
  9270. #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
  9271. #define DSI_WPCR3_THSEXIT6_Pos (22U)
  9272. #define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
  9273. #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
  9274. #define DSI_WPCR3_THSEXIT7_Pos (23U)
  9275. #define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
  9276. #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
  9277. #define DSI_WPCR3_TLPXC_Pos (24U)
  9278. #define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
  9279. #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
  9280. #define DSI_WPCR3_TLPXC0_Pos (24U)
  9281. #define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
  9282. #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
  9283. #define DSI_WPCR3_TLPXC1_Pos (25U)
  9284. #define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
  9285. #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
  9286. #define DSI_WPCR3_TLPXC2_Pos (26U)
  9287. #define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
  9288. #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
  9289. #define DSI_WPCR3_TLPXC3_Pos (27U)
  9290. #define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
  9291. #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
  9292. #define DSI_WPCR3_TLPXC4_Pos (28U)
  9293. #define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
  9294. #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
  9295. #define DSI_WPCR3_TLPXC5_Pos (29U)
  9296. #define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
  9297. #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
  9298. #define DSI_WPCR3_TLPXC6_Pos (30U)
  9299. #define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
  9300. #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
  9301. #define DSI_WPCR3_TLPXC7_Pos (31U)
  9302. #define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
  9303. #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
  9304. /******************* Bit definition for DSI_WPCR4 register ***************/
  9305. #define DSI_WPCR4_TCLKPOST_Pos (0U)
  9306. #define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
  9307. #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
  9308. #define DSI_WPCR4_TCLKPOST0_Pos (0U)
  9309. #define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
  9310. #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
  9311. #define DSI_WPCR4_TCLKPOST1_Pos (1U)
  9312. #define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
  9313. #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
  9314. #define DSI_WPCR4_TCLKPOST2_Pos (2U)
  9315. #define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
  9316. #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
  9317. #define DSI_WPCR4_TCLKPOST3_Pos (3U)
  9318. #define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
  9319. #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
  9320. #define DSI_WPCR4_TCLKPOST4_Pos (4U)
  9321. #define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
  9322. #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
  9323. #define DSI_WPCR4_TCLKPOST5_Pos (5U)
  9324. #define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
  9325. #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
  9326. #define DSI_WPCR4_TCLKPOST6_Pos (6U)
  9327. #define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
  9328. #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
  9329. #define DSI_WPCR4_TCLKPOST7_Pos (7U)
  9330. #define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
  9331. #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
  9332. /******************* Bit definition for DSI_WRPCR register ***************/
  9333. #define DSI_WRPCR_PLLEN_Pos (0U)
  9334. #define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
  9335. #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
  9336. #define DSI_WRPCR_PLL_NDIV_Pos (2U)
  9337. #define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
  9338. #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
  9339. #define DSI_WRPCR_PLL_NDIV0_Pos (2U)
  9340. #define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
  9341. #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
  9342. #define DSI_WRPCR_PLL_NDIV1_Pos (3U)
  9343. #define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
  9344. #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
  9345. #define DSI_WRPCR_PLL_NDIV2_Pos (4U)
  9346. #define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
  9347. #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
  9348. #define DSI_WRPCR_PLL_NDIV3_Pos (5U)
  9349. #define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
  9350. #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
  9351. #define DSI_WRPCR_PLL_NDIV4_Pos (6U)
  9352. #define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
  9353. #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
  9354. #define DSI_WRPCR_PLL_NDIV5_Pos (7U)
  9355. #define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
  9356. #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
  9357. #define DSI_WRPCR_PLL_NDIV6_Pos (8U)
  9358. #define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
  9359. #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
  9360. #define DSI_WRPCR_PLL_IDF_Pos (11U)
  9361. #define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
  9362. #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
  9363. #define DSI_WRPCR_PLL_IDF0_Pos (11U)
  9364. #define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
  9365. #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
  9366. #define DSI_WRPCR_PLL_IDF1_Pos (12U)
  9367. #define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
  9368. #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
  9369. #define DSI_WRPCR_PLL_IDF2_Pos (13U)
  9370. #define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
  9371. #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
  9372. #define DSI_WRPCR_PLL_IDF3_Pos (14U)
  9373. #define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
  9374. #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
  9375. #define DSI_WRPCR_PLL_ODF_Pos (16U)
  9376. #define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
  9377. #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
  9378. #define DSI_WRPCR_PLL_ODF0_Pos (16U)
  9379. #define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
  9380. #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
  9381. #define DSI_WRPCR_PLL_ODF1_Pos (17U)
  9382. #define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
  9383. #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
  9384. #define DSI_WRPCR_REGEN_Pos (24U)
  9385. #define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
  9386. #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
  9387. /******************************************************************************/
  9388. /* */
  9389. /* External Interrupt/Event Controller */
  9390. /* */
  9391. /******************************************************************************/
  9392. /******************* Bit definition for EXTI_IMR register *******************/
  9393. #define EXTI_IMR_MR0_Pos (0U)
  9394. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  9395. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  9396. #define EXTI_IMR_MR1_Pos (1U)
  9397. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  9398. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  9399. #define EXTI_IMR_MR2_Pos (2U)
  9400. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  9401. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  9402. #define EXTI_IMR_MR3_Pos (3U)
  9403. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  9404. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  9405. #define EXTI_IMR_MR4_Pos (4U)
  9406. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  9407. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  9408. #define EXTI_IMR_MR5_Pos (5U)
  9409. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  9410. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  9411. #define EXTI_IMR_MR6_Pos (6U)
  9412. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  9413. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  9414. #define EXTI_IMR_MR7_Pos (7U)
  9415. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  9416. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  9417. #define EXTI_IMR_MR8_Pos (8U)
  9418. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  9419. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  9420. #define EXTI_IMR_MR9_Pos (9U)
  9421. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  9422. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  9423. #define EXTI_IMR_MR10_Pos (10U)
  9424. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  9425. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  9426. #define EXTI_IMR_MR11_Pos (11U)
  9427. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  9428. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  9429. #define EXTI_IMR_MR12_Pos (12U)
  9430. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  9431. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  9432. #define EXTI_IMR_MR13_Pos (13U)
  9433. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  9434. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  9435. #define EXTI_IMR_MR14_Pos (14U)
  9436. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  9437. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  9438. #define EXTI_IMR_MR15_Pos (15U)
  9439. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  9440. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  9441. #define EXTI_IMR_MR16_Pos (16U)
  9442. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  9443. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  9444. #define EXTI_IMR_MR17_Pos (17U)
  9445. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  9446. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  9447. #define EXTI_IMR_MR18_Pos (18U)
  9448. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  9449. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  9450. #define EXTI_IMR_MR19_Pos (19U)
  9451. #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  9452. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  9453. #define EXTI_IMR_MR20_Pos (20U)
  9454. #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
  9455. #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
  9456. #define EXTI_IMR_MR21_Pos (21U)
  9457. #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
  9458. #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
  9459. #define EXTI_IMR_MR22_Pos (22U)
  9460. #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
  9461. #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
  9462. /* Reference Defines */
  9463. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  9464. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  9465. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  9466. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  9467. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  9468. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  9469. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  9470. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  9471. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  9472. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  9473. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  9474. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  9475. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  9476. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  9477. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  9478. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  9479. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  9480. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  9481. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  9482. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  9483. #define EXTI_IMR_IM20 EXTI_IMR_MR20
  9484. #define EXTI_IMR_IM21 EXTI_IMR_MR21
  9485. #define EXTI_IMR_IM22 EXTI_IMR_MR22
  9486. #define EXTI_IMR_IM_Pos (0U)
  9487. #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
  9488. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  9489. /******************* Bit definition for EXTI_EMR register *******************/
  9490. #define EXTI_EMR_MR0_Pos (0U)
  9491. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  9492. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  9493. #define EXTI_EMR_MR1_Pos (1U)
  9494. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  9495. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  9496. #define EXTI_EMR_MR2_Pos (2U)
  9497. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  9498. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  9499. #define EXTI_EMR_MR3_Pos (3U)
  9500. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  9501. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  9502. #define EXTI_EMR_MR4_Pos (4U)
  9503. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  9504. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  9505. #define EXTI_EMR_MR5_Pos (5U)
  9506. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  9507. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  9508. #define EXTI_EMR_MR6_Pos (6U)
  9509. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  9510. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  9511. #define EXTI_EMR_MR7_Pos (7U)
  9512. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  9513. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  9514. #define EXTI_EMR_MR8_Pos (8U)
  9515. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  9516. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  9517. #define EXTI_EMR_MR9_Pos (9U)
  9518. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  9519. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  9520. #define EXTI_EMR_MR10_Pos (10U)
  9521. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  9522. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  9523. #define EXTI_EMR_MR11_Pos (11U)
  9524. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  9525. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  9526. #define EXTI_EMR_MR12_Pos (12U)
  9527. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  9528. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  9529. #define EXTI_EMR_MR13_Pos (13U)
  9530. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  9531. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  9532. #define EXTI_EMR_MR14_Pos (14U)
  9533. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  9534. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  9535. #define EXTI_EMR_MR15_Pos (15U)
  9536. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  9537. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  9538. #define EXTI_EMR_MR16_Pos (16U)
  9539. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  9540. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  9541. #define EXTI_EMR_MR17_Pos (17U)
  9542. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  9543. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  9544. #define EXTI_EMR_MR18_Pos (18U)
  9545. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  9546. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  9547. #define EXTI_EMR_MR19_Pos (19U)
  9548. #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  9549. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  9550. #define EXTI_EMR_MR20_Pos (20U)
  9551. #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
  9552. #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
  9553. #define EXTI_EMR_MR21_Pos (21U)
  9554. #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
  9555. #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
  9556. #define EXTI_EMR_MR22_Pos (22U)
  9557. #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
  9558. #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
  9559. /* Reference Defines */
  9560. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  9561. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  9562. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  9563. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  9564. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  9565. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  9566. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  9567. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  9568. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  9569. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  9570. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  9571. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  9572. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  9573. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  9574. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  9575. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  9576. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  9577. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  9578. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  9579. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  9580. #define EXTI_EMR_EM20 EXTI_EMR_MR20
  9581. #define EXTI_EMR_EM21 EXTI_EMR_MR21
  9582. #define EXTI_EMR_EM22 EXTI_EMR_MR22
  9583. /****************** Bit definition for EXTI_RTSR register *******************/
  9584. #define EXTI_RTSR_TR0_Pos (0U)
  9585. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  9586. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  9587. #define EXTI_RTSR_TR1_Pos (1U)
  9588. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  9589. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  9590. #define EXTI_RTSR_TR2_Pos (2U)
  9591. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  9592. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  9593. #define EXTI_RTSR_TR3_Pos (3U)
  9594. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  9595. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  9596. #define EXTI_RTSR_TR4_Pos (4U)
  9597. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  9598. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  9599. #define EXTI_RTSR_TR5_Pos (5U)
  9600. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  9601. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  9602. #define EXTI_RTSR_TR6_Pos (6U)
  9603. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  9604. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  9605. #define EXTI_RTSR_TR7_Pos (7U)
  9606. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  9607. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  9608. #define EXTI_RTSR_TR8_Pos (8U)
  9609. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  9610. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  9611. #define EXTI_RTSR_TR9_Pos (9U)
  9612. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  9613. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  9614. #define EXTI_RTSR_TR10_Pos (10U)
  9615. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  9616. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  9617. #define EXTI_RTSR_TR11_Pos (11U)
  9618. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  9619. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  9620. #define EXTI_RTSR_TR12_Pos (12U)
  9621. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  9622. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  9623. #define EXTI_RTSR_TR13_Pos (13U)
  9624. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  9625. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  9626. #define EXTI_RTSR_TR14_Pos (14U)
  9627. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  9628. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  9629. #define EXTI_RTSR_TR15_Pos (15U)
  9630. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  9631. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  9632. #define EXTI_RTSR_TR16_Pos (16U)
  9633. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  9634. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  9635. #define EXTI_RTSR_TR17_Pos (17U)
  9636. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  9637. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  9638. #define EXTI_RTSR_TR18_Pos (18U)
  9639. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  9640. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  9641. #define EXTI_RTSR_TR19_Pos (19U)
  9642. #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  9643. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  9644. #define EXTI_RTSR_TR20_Pos (20U)
  9645. #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
  9646. #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
  9647. #define EXTI_RTSR_TR21_Pos (21U)
  9648. #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
  9649. #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
  9650. #define EXTI_RTSR_TR22_Pos (22U)
  9651. #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
  9652. #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
  9653. /****************** Bit definition for EXTI_FTSR register *******************/
  9654. #define EXTI_FTSR_TR0_Pos (0U)
  9655. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  9656. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  9657. #define EXTI_FTSR_TR1_Pos (1U)
  9658. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  9659. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  9660. #define EXTI_FTSR_TR2_Pos (2U)
  9661. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  9662. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  9663. #define EXTI_FTSR_TR3_Pos (3U)
  9664. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  9665. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  9666. #define EXTI_FTSR_TR4_Pos (4U)
  9667. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  9668. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  9669. #define EXTI_FTSR_TR5_Pos (5U)
  9670. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  9671. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  9672. #define EXTI_FTSR_TR6_Pos (6U)
  9673. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  9674. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  9675. #define EXTI_FTSR_TR7_Pos (7U)
  9676. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  9677. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  9678. #define EXTI_FTSR_TR8_Pos (8U)
  9679. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  9680. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  9681. #define EXTI_FTSR_TR9_Pos (9U)
  9682. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  9683. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  9684. #define EXTI_FTSR_TR10_Pos (10U)
  9685. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  9686. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  9687. #define EXTI_FTSR_TR11_Pos (11U)
  9688. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  9689. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  9690. #define EXTI_FTSR_TR12_Pos (12U)
  9691. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  9692. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  9693. #define EXTI_FTSR_TR13_Pos (13U)
  9694. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  9695. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  9696. #define EXTI_FTSR_TR14_Pos (14U)
  9697. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  9698. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  9699. #define EXTI_FTSR_TR15_Pos (15U)
  9700. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  9701. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  9702. #define EXTI_FTSR_TR16_Pos (16U)
  9703. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  9704. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  9705. #define EXTI_FTSR_TR17_Pos (17U)
  9706. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  9707. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  9708. #define EXTI_FTSR_TR18_Pos (18U)
  9709. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  9710. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  9711. #define EXTI_FTSR_TR19_Pos (19U)
  9712. #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  9713. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  9714. #define EXTI_FTSR_TR20_Pos (20U)
  9715. #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
  9716. #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
  9717. #define EXTI_FTSR_TR21_Pos (21U)
  9718. #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
  9719. #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
  9720. #define EXTI_FTSR_TR22_Pos (22U)
  9721. #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
  9722. #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
  9723. /****************** Bit definition for EXTI_SWIER register ******************/
  9724. #define EXTI_SWIER_SWIER0_Pos (0U)
  9725. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  9726. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  9727. #define EXTI_SWIER_SWIER1_Pos (1U)
  9728. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  9729. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  9730. #define EXTI_SWIER_SWIER2_Pos (2U)
  9731. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  9732. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  9733. #define EXTI_SWIER_SWIER3_Pos (3U)
  9734. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  9735. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  9736. #define EXTI_SWIER_SWIER4_Pos (4U)
  9737. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  9738. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  9739. #define EXTI_SWIER_SWIER5_Pos (5U)
  9740. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  9741. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  9742. #define EXTI_SWIER_SWIER6_Pos (6U)
  9743. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  9744. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  9745. #define EXTI_SWIER_SWIER7_Pos (7U)
  9746. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  9747. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  9748. #define EXTI_SWIER_SWIER8_Pos (8U)
  9749. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  9750. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  9751. #define EXTI_SWIER_SWIER9_Pos (9U)
  9752. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  9753. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  9754. #define EXTI_SWIER_SWIER10_Pos (10U)
  9755. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  9756. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  9757. #define EXTI_SWIER_SWIER11_Pos (11U)
  9758. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  9759. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  9760. #define EXTI_SWIER_SWIER12_Pos (12U)
  9761. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  9762. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  9763. #define EXTI_SWIER_SWIER13_Pos (13U)
  9764. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  9765. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  9766. #define EXTI_SWIER_SWIER14_Pos (14U)
  9767. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  9768. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  9769. #define EXTI_SWIER_SWIER15_Pos (15U)
  9770. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  9771. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  9772. #define EXTI_SWIER_SWIER16_Pos (16U)
  9773. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  9774. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  9775. #define EXTI_SWIER_SWIER17_Pos (17U)
  9776. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  9777. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  9778. #define EXTI_SWIER_SWIER18_Pos (18U)
  9779. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  9780. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  9781. #define EXTI_SWIER_SWIER19_Pos (19U)
  9782. #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  9783. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  9784. #define EXTI_SWIER_SWIER20_Pos (20U)
  9785. #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
  9786. #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
  9787. #define EXTI_SWIER_SWIER21_Pos (21U)
  9788. #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
  9789. #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
  9790. #define EXTI_SWIER_SWIER22_Pos (22U)
  9791. #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
  9792. #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
  9793. /******************* Bit definition for EXTI_PR register ********************/
  9794. #define EXTI_PR_PR0_Pos (0U)
  9795. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  9796. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  9797. #define EXTI_PR_PR1_Pos (1U)
  9798. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  9799. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  9800. #define EXTI_PR_PR2_Pos (2U)
  9801. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  9802. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  9803. #define EXTI_PR_PR3_Pos (3U)
  9804. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  9805. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  9806. #define EXTI_PR_PR4_Pos (4U)
  9807. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  9808. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  9809. #define EXTI_PR_PR5_Pos (5U)
  9810. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  9811. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  9812. #define EXTI_PR_PR6_Pos (6U)
  9813. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  9814. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  9815. #define EXTI_PR_PR7_Pos (7U)
  9816. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  9817. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  9818. #define EXTI_PR_PR8_Pos (8U)
  9819. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  9820. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  9821. #define EXTI_PR_PR9_Pos (9U)
  9822. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  9823. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  9824. #define EXTI_PR_PR10_Pos (10U)
  9825. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  9826. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  9827. #define EXTI_PR_PR11_Pos (11U)
  9828. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  9829. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  9830. #define EXTI_PR_PR12_Pos (12U)
  9831. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  9832. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  9833. #define EXTI_PR_PR13_Pos (13U)
  9834. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  9835. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  9836. #define EXTI_PR_PR14_Pos (14U)
  9837. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  9838. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  9839. #define EXTI_PR_PR15_Pos (15U)
  9840. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  9841. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  9842. #define EXTI_PR_PR16_Pos (16U)
  9843. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  9844. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  9845. #define EXTI_PR_PR17_Pos (17U)
  9846. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  9847. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  9848. #define EXTI_PR_PR18_Pos (18U)
  9849. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  9850. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  9851. #define EXTI_PR_PR19_Pos (19U)
  9852. #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  9853. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
  9854. #define EXTI_PR_PR20_Pos (20U)
  9855. #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
  9856. #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
  9857. #define EXTI_PR_PR21_Pos (21U)
  9858. #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
  9859. #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
  9860. #define EXTI_PR_PR22_Pos (22U)
  9861. #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
  9862. #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
  9863. /******************************************************************************/
  9864. /* */
  9865. /* FLASH */
  9866. /* */
  9867. /******************************************************************************/
  9868. /******************* Bits definition for FLASH_ACR register *****************/
  9869. #define FLASH_ACR_LATENCY_Pos (0U)
  9870. #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
  9871. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  9872. #define FLASH_ACR_LATENCY_0WS 0x00000000U
  9873. #define FLASH_ACR_LATENCY_1WS 0x00000001U
  9874. #define FLASH_ACR_LATENCY_2WS 0x00000002U
  9875. #define FLASH_ACR_LATENCY_3WS 0x00000003U
  9876. #define FLASH_ACR_LATENCY_4WS 0x00000004U
  9877. #define FLASH_ACR_LATENCY_5WS 0x00000005U
  9878. #define FLASH_ACR_LATENCY_6WS 0x00000006U
  9879. #define FLASH_ACR_LATENCY_7WS 0x00000007U
  9880. #define FLASH_ACR_LATENCY_8WS 0x00000008U
  9881. #define FLASH_ACR_LATENCY_9WS 0x00000009U
  9882. #define FLASH_ACR_LATENCY_10WS 0x0000000AU
  9883. #define FLASH_ACR_LATENCY_11WS 0x0000000BU
  9884. #define FLASH_ACR_LATENCY_12WS 0x0000000CU
  9885. #define FLASH_ACR_LATENCY_13WS 0x0000000DU
  9886. #define FLASH_ACR_LATENCY_14WS 0x0000000EU
  9887. #define FLASH_ACR_LATENCY_15WS 0x0000000FU
  9888. #define FLASH_ACR_PRFTEN_Pos (8U)
  9889. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  9890. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  9891. #define FLASH_ACR_ICEN_Pos (9U)
  9892. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  9893. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  9894. #define FLASH_ACR_DCEN_Pos (10U)
  9895. #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  9896. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  9897. #define FLASH_ACR_ICRST_Pos (11U)
  9898. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  9899. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  9900. #define FLASH_ACR_DCRST_Pos (12U)
  9901. #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  9902. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  9903. #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
  9904. #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
  9905. #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
  9906. #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
  9907. #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
  9908. #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
  9909. /******************* Bits definition for FLASH_SR register ******************/
  9910. #define FLASH_SR_EOP_Pos (0U)
  9911. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  9912. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  9913. #define FLASH_SR_SOP_Pos (1U)
  9914. #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
  9915. #define FLASH_SR_SOP FLASH_SR_SOP_Msk
  9916. #define FLASH_SR_WRPERR_Pos (4U)
  9917. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  9918. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  9919. #define FLASH_SR_PGAERR_Pos (5U)
  9920. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  9921. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  9922. #define FLASH_SR_PGPERR_Pos (6U)
  9923. #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
  9924. #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
  9925. #define FLASH_SR_PGSERR_Pos (7U)
  9926. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  9927. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  9928. #define FLASH_SR_RDERR_Pos (8U)
  9929. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
  9930. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  9931. #define FLASH_SR_BSY_Pos (16U)
  9932. #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  9933. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  9934. /******************* Bits definition for FLASH_CR register ******************/
  9935. #define FLASH_CR_PG_Pos (0U)
  9936. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  9937. #define FLASH_CR_PG FLASH_CR_PG_Msk
  9938. #define FLASH_CR_SER_Pos (1U)
  9939. #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
  9940. #define FLASH_CR_SER FLASH_CR_SER_Msk
  9941. #define FLASH_CR_MER_Pos (2U)
  9942. #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  9943. #define FLASH_CR_MER FLASH_CR_MER_Msk
  9944. #define FLASH_CR_MER1 FLASH_CR_MER
  9945. #define FLASH_CR_SNB_Pos (3U)
  9946. #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
  9947. #define FLASH_CR_SNB FLASH_CR_SNB_Msk
  9948. #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
  9949. #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
  9950. #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
  9951. #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
  9952. #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
  9953. #define FLASH_CR_PSIZE_Pos (8U)
  9954. #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
  9955. #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
  9956. #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
  9957. #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
  9958. #define FLASH_CR_MER2_Pos (15U)
  9959. #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
  9960. #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
  9961. #define FLASH_CR_STRT_Pos (16U)
  9962. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  9963. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  9964. #define FLASH_CR_EOPIE_Pos (24U)
  9965. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  9966. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  9967. #define FLASH_CR_LOCK_Pos (31U)
  9968. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  9969. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  9970. /******************* Bits definition for FLASH_OPTCR register ***************/
  9971. #define FLASH_OPTCR_OPTLOCK_Pos (0U)
  9972. #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
  9973. #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
  9974. #define FLASH_OPTCR_OPTSTRT_Pos (1U)
  9975. #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
  9976. #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
  9977. #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
  9978. #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
  9979. #define FLASH_OPTCR_BOR_LEV_Pos (2U)
  9980. #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
  9981. #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
  9982. #define FLASH_OPTCR_BFB2_Pos (4U)
  9983. #define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
  9984. #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
  9985. #define FLASH_OPTCR_WDG_SW_Pos (5U)
  9986. #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
  9987. #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
  9988. #define FLASH_OPTCR_nRST_STOP_Pos (6U)
  9989. #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
  9990. #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
  9991. #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
  9992. #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
  9993. #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
  9994. #define FLASH_OPTCR_RDP_Pos (8U)
  9995. #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
  9996. #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
  9997. #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
  9998. #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
  9999. #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
  10000. #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
  10001. #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
  10002. #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
  10003. #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
  10004. #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
  10005. #define FLASH_OPTCR_nWRP_Pos (16U)
  10006. #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
  10007. #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
  10008. #define FLASH_OPTCR_nWRP_0 0x00010000U
  10009. #define FLASH_OPTCR_nWRP_1 0x00020000U
  10010. #define FLASH_OPTCR_nWRP_2 0x00040000U
  10011. #define FLASH_OPTCR_nWRP_3 0x00080000U
  10012. #define FLASH_OPTCR_nWRP_4 0x00100000U
  10013. #define FLASH_OPTCR_nWRP_5 0x00200000U
  10014. #define FLASH_OPTCR_nWRP_6 0x00400000U
  10015. #define FLASH_OPTCR_nWRP_7 0x00800000U
  10016. #define FLASH_OPTCR_nWRP_8 0x01000000U
  10017. #define FLASH_OPTCR_nWRP_9 0x02000000U
  10018. #define FLASH_OPTCR_nWRP_10 0x04000000U
  10019. #define FLASH_OPTCR_nWRP_11 0x08000000U
  10020. #define FLASH_OPTCR_DB1M_Pos (30U)
  10021. #define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
  10022. #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
  10023. #define FLASH_OPTCR_SPRMOD_Pos (31U)
  10024. #define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
  10025. #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
  10026. /****************** Bits definition for FLASH_OPTCR1 register ***************/
  10027. #define FLASH_OPTCR1_nWRP_Pos (16U)
  10028. #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
  10029. #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
  10030. #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
  10031. #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
  10032. #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
  10033. #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
  10034. #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
  10035. #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
  10036. #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
  10037. #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
  10038. #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
  10039. #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
  10040. #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
  10041. #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
  10042. /******************************************************************************/
  10043. /* */
  10044. /* Flexible Memory Controller */
  10045. /* */
  10046. /******************************************************************************/
  10047. /****************** Bit definition for FMC_BCR1 register *******************/
  10048. #define FMC_BCR1_MBKEN_Pos (0U)
  10049. #define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
  10050. #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
  10051. #define FMC_BCR1_MUXEN_Pos (1U)
  10052. #define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
  10053. #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  10054. #define FMC_BCR1_MTYP_Pos (2U)
  10055. #define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
  10056. #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  10057. #define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
  10058. #define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
  10059. #define FMC_BCR1_MWID_Pos (4U)
  10060. #define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
  10061. #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  10062. #define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
  10063. #define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
  10064. #define FMC_BCR1_FACCEN_Pos (6U)
  10065. #define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
  10066. #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
  10067. #define FMC_BCR1_BURSTEN_Pos (8U)
  10068. #define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
  10069. #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
  10070. #define FMC_BCR1_WAITPOL_Pos (9U)
  10071. #define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
  10072. #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
  10073. #define FMC_BCR1_WAITCFG_Pos (11U)
  10074. #define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
  10075. #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
  10076. #define FMC_BCR1_WREN_Pos (12U)
  10077. #define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
  10078. #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
  10079. #define FMC_BCR1_WAITEN_Pos (13U)
  10080. #define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
  10081. #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
  10082. #define FMC_BCR1_EXTMOD_Pos (14U)
  10083. #define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
  10084. #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
  10085. #define FMC_BCR1_ASYNCWAIT_Pos (15U)
  10086. #define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
  10087. #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
  10088. #define FMC_BCR1_CPSIZE_Pos (16U)
  10089. #define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
  10090. #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
  10091. #define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
  10092. #define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
  10093. #define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
  10094. #define FMC_BCR1_CBURSTRW_Pos (19U)
  10095. #define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
  10096. #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
  10097. #define FMC_BCR1_CCLKEN_Pos (20U)
  10098. #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
  10099. #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
  10100. #define FMC_BCR1_WFDIS_Pos (21U)
  10101. #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
  10102. #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
  10103. /****************** Bit definition for FMC_BCR2 register *******************/
  10104. #define FMC_BCR2_MBKEN_Pos (0U)
  10105. #define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
  10106. #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
  10107. #define FMC_BCR2_MUXEN_Pos (1U)
  10108. #define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
  10109. #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  10110. #define FMC_BCR2_MTYP_Pos (2U)
  10111. #define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
  10112. #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  10113. #define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
  10114. #define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
  10115. #define FMC_BCR2_MWID_Pos (4U)
  10116. #define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
  10117. #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  10118. #define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
  10119. #define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
  10120. #define FMC_BCR2_FACCEN_Pos (6U)
  10121. #define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
  10122. #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
  10123. #define FMC_BCR2_BURSTEN_Pos (8U)
  10124. #define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
  10125. #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
  10126. #define FMC_BCR2_WAITPOL_Pos (9U)
  10127. #define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
  10128. #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
  10129. #define FMC_BCR2_WAITCFG_Pos (11U)
  10130. #define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
  10131. #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
  10132. #define FMC_BCR2_WREN_Pos (12U)
  10133. #define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
  10134. #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
  10135. #define FMC_BCR2_WAITEN_Pos (13U)
  10136. #define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
  10137. #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
  10138. #define FMC_BCR2_EXTMOD_Pos (14U)
  10139. #define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
  10140. #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
  10141. #define FMC_BCR2_ASYNCWAIT_Pos (15U)
  10142. #define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
  10143. #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
  10144. #define FMC_BCR2_CBURSTRW_Pos (19U)
  10145. #define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
  10146. #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
  10147. /****************** Bit definition for FMC_BCR3 register *******************/
  10148. #define FMC_BCR3_MBKEN_Pos (0U)
  10149. #define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
  10150. #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
  10151. #define FMC_BCR3_MUXEN_Pos (1U)
  10152. #define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
  10153. #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  10154. #define FMC_BCR3_MTYP_Pos (2U)
  10155. #define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
  10156. #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  10157. #define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
  10158. #define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
  10159. #define FMC_BCR3_MWID_Pos (4U)
  10160. #define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
  10161. #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  10162. #define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
  10163. #define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
  10164. #define FMC_BCR3_FACCEN_Pos (6U)
  10165. #define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
  10166. #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
  10167. #define FMC_BCR3_BURSTEN_Pos (8U)
  10168. #define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
  10169. #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
  10170. #define FMC_BCR3_WAITPOL_Pos (9U)
  10171. #define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
  10172. #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
  10173. #define FMC_BCR3_WAITCFG_Pos (11U)
  10174. #define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
  10175. #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
  10176. #define FMC_BCR3_WREN_Pos (12U)
  10177. #define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
  10178. #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
  10179. #define FMC_BCR3_WAITEN_Pos (13U)
  10180. #define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
  10181. #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
  10182. #define FMC_BCR3_EXTMOD_Pos (14U)
  10183. #define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
  10184. #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
  10185. #define FMC_BCR3_ASYNCWAIT_Pos (15U)
  10186. #define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
  10187. #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
  10188. #define FMC_BCR3_CBURSTRW_Pos (19U)
  10189. #define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
  10190. #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
  10191. /****************** Bit definition for FMC_BCR4 register *******************/
  10192. #define FMC_BCR4_MBKEN_Pos (0U)
  10193. #define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
  10194. #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
  10195. #define FMC_BCR4_MUXEN_Pos (1U)
  10196. #define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
  10197. #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  10198. #define FMC_BCR4_MTYP_Pos (2U)
  10199. #define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
  10200. #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  10201. #define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
  10202. #define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
  10203. #define FMC_BCR4_MWID_Pos (4U)
  10204. #define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
  10205. #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  10206. #define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
  10207. #define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
  10208. #define FMC_BCR4_FACCEN_Pos (6U)
  10209. #define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
  10210. #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
  10211. #define FMC_BCR4_BURSTEN_Pos (8U)
  10212. #define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
  10213. #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
  10214. #define FMC_BCR4_WAITPOL_Pos (9U)
  10215. #define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
  10216. #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
  10217. #define FMC_BCR4_WAITCFG_Pos (11U)
  10218. #define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
  10219. #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
  10220. #define FMC_BCR4_WREN_Pos (12U)
  10221. #define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
  10222. #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
  10223. #define FMC_BCR4_WAITEN_Pos (13U)
  10224. #define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
  10225. #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
  10226. #define FMC_BCR4_EXTMOD_Pos (14U)
  10227. #define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
  10228. #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
  10229. #define FMC_BCR4_ASYNCWAIT_Pos (15U)
  10230. #define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
  10231. #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
  10232. #define FMC_BCR4_CBURSTRW_Pos (19U)
  10233. #define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
  10234. #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
  10235. /****************** Bit definition for FMC_BTR1 register ******************/
  10236. #define FMC_BTR1_ADDSET_Pos (0U)
  10237. #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
  10238. #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10239. #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
  10240. #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
  10241. #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
  10242. #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
  10243. #define FMC_BTR1_ADDHLD_Pos (4U)
  10244. #define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  10245. #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10246. #define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
  10247. #define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
  10248. #define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
  10249. #define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
  10250. #define FMC_BTR1_DATAST_Pos (8U)
  10251. #define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
  10252. #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10253. #define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
  10254. #define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
  10255. #define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
  10256. #define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
  10257. #define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
  10258. #define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
  10259. #define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
  10260. #define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
  10261. #define FMC_BTR1_BUSTURN_Pos (16U)
  10262. #define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  10263. #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  10264. #define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
  10265. #define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
  10266. #define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
  10267. #define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
  10268. #define FMC_BTR1_CLKDIV_Pos (20U)
  10269. #define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
  10270. #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  10271. #define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
  10272. #define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
  10273. #define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
  10274. #define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
  10275. #define FMC_BTR1_DATLAT_Pos (24U)
  10276. #define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
  10277. #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  10278. #define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
  10279. #define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
  10280. #define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
  10281. #define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
  10282. #define FMC_BTR1_ACCMOD_Pos (28U)
  10283. #define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
  10284. #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10285. #define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
  10286. #define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
  10287. /****************** Bit definition for FMC_BTR2 register *******************/
  10288. #define FMC_BTR2_ADDSET_Pos (0U)
  10289. #define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
  10290. #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10291. #define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
  10292. #define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
  10293. #define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
  10294. #define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
  10295. #define FMC_BTR2_ADDHLD_Pos (4U)
  10296. #define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  10297. #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10298. #define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
  10299. #define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
  10300. #define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
  10301. #define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
  10302. #define FMC_BTR2_DATAST_Pos (8U)
  10303. #define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
  10304. #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10305. #define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
  10306. #define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
  10307. #define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
  10308. #define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
  10309. #define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
  10310. #define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
  10311. #define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
  10312. #define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
  10313. #define FMC_BTR2_BUSTURN_Pos (16U)
  10314. #define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  10315. #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  10316. #define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
  10317. #define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
  10318. #define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
  10319. #define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
  10320. #define FMC_BTR2_CLKDIV_Pos (20U)
  10321. #define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
  10322. #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  10323. #define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
  10324. #define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
  10325. #define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
  10326. #define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
  10327. #define FMC_BTR2_DATLAT_Pos (24U)
  10328. #define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
  10329. #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  10330. #define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
  10331. #define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
  10332. #define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
  10333. #define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
  10334. #define FMC_BTR2_ACCMOD_Pos (28U)
  10335. #define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
  10336. #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10337. #define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
  10338. #define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
  10339. /******************* Bit definition for FMC_BTR3 register *******************/
  10340. #define FMC_BTR3_ADDSET_Pos (0U)
  10341. #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
  10342. #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10343. #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
  10344. #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
  10345. #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
  10346. #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
  10347. #define FMC_BTR3_ADDHLD_Pos (4U)
  10348. #define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  10349. #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10350. #define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
  10351. #define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
  10352. #define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
  10353. #define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
  10354. #define FMC_BTR3_DATAST_Pos (8U)
  10355. #define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
  10356. #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10357. #define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
  10358. #define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
  10359. #define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
  10360. #define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
  10361. #define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
  10362. #define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
  10363. #define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
  10364. #define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
  10365. #define FMC_BTR3_BUSTURN_Pos (16U)
  10366. #define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  10367. #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  10368. #define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
  10369. #define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
  10370. #define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
  10371. #define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
  10372. #define FMC_BTR3_CLKDIV_Pos (20U)
  10373. #define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
  10374. #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  10375. #define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
  10376. #define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
  10377. #define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
  10378. #define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
  10379. #define FMC_BTR3_DATLAT_Pos (24U)
  10380. #define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
  10381. #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  10382. #define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
  10383. #define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
  10384. #define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
  10385. #define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
  10386. #define FMC_BTR3_ACCMOD_Pos (28U)
  10387. #define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
  10388. #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10389. #define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
  10390. #define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
  10391. /****************** Bit definition for FMC_BTR4 register *******************/
  10392. #define FMC_BTR4_ADDSET_Pos (0U)
  10393. #define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
  10394. #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10395. #define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
  10396. #define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
  10397. #define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
  10398. #define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
  10399. #define FMC_BTR4_ADDHLD_Pos (4U)
  10400. #define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  10401. #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10402. #define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
  10403. #define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
  10404. #define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
  10405. #define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
  10406. #define FMC_BTR4_DATAST_Pos (8U)
  10407. #define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
  10408. #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10409. #define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
  10410. #define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
  10411. #define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
  10412. #define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
  10413. #define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
  10414. #define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
  10415. #define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
  10416. #define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
  10417. #define FMC_BTR4_BUSTURN_Pos (16U)
  10418. #define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  10419. #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  10420. #define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
  10421. #define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
  10422. #define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
  10423. #define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
  10424. #define FMC_BTR4_CLKDIV_Pos (20U)
  10425. #define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
  10426. #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  10427. #define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
  10428. #define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
  10429. #define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
  10430. #define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
  10431. #define FMC_BTR4_DATLAT_Pos (24U)
  10432. #define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
  10433. #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  10434. #define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
  10435. #define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
  10436. #define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
  10437. #define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
  10438. #define FMC_BTR4_ACCMOD_Pos (28U)
  10439. #define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
  10440. #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10441. #define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
  10442. #define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
  10443. /****************** Bit definition for FMC_BWTR1 register ******************/
  10444. #define FMC_BWTR1_ADDSET_Pos (0U)
  10445. #define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
  10446. #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10447. #define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
  10448. #define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
  10449. #define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
  10450. #define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
  10451. #define FMC_BWTR1_ADDHLD_Pos (4U)
  10452. #define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  10453. #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10454. #define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
  10455. #define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
  10456. #define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
  10457. #define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
  10458. #define FMC_BWTR1_DATAST_Pos (8U)
  10459. #define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
  10460. #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10461. #define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
  10462. #define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
  10463. #define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
  10464. #define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
  10465. #define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
  10466. #define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
  10467. #define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
  10468. #define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
  10469. #define FMC_BWTR1_BUSTURN_Pos (16U)
  10470. #define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  10471. #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  10472. #define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
  10473. #define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
  10474. #define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
  10475. #define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
  10476. #define FMC_BWTR1_ACCMOD_Pos (28U)
  10477. #define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
  10478. #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10479. #define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
  10480. #define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
  10481. /****************** Bit definition for FMC_BWTR2 register ******************/
  10482. #define FMC_BWTR2_ADDSET_Pos (0U)
  10483. #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
  10484. #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10485. #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
  10486. #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
  10487. #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
  10488. #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
  10489. #define FMC_BWTR2_ADDHLD_Pos (4U)
  10490. #define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  10491. #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10492. #define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
  10493. #define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
  10494. #define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
  10495. #define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
  10496. #define FMC_BWTR2_DATAST_Pos (8U)
  10497. #define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
  10498. #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10499. #define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
  10500. #define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
  10501. #define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
  10502. #define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
  10503. #define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
  10504. #define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
  10505. #define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
  10506. #define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
  10507. #define FMC_BWTR2_BUSTURN_Pos (16U)
  10508. #define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  10509. #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  10510. #define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
  10511. #define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
  10512. #define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
  10513. #define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
  10514. #define FMC_BWTR2_ACCMOD_Pos (28U)
  10515. #define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
  10516. #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10517. #define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
  10518. #define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
  10519. /****************** Bit definition for FMC_BWTR3 register ******************/
  10520. #define FMC_BWTR3_ADDSET_Pos (0U)
  10521. #define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
  10522. #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10523. #define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
  10524. #define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
  10525. #define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
  10526. #define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
  10527. #define FMC_BWTR3_ADDHLD_Pos (4U)
  10528. #define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  10529. #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10530. #define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
  10531. #define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
  10532. #define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
  10533. #define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
  10534. #define FMC_BWTR3_DATAST_Pos (8U)
  10535. #define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
  10536. #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10537. #define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
  10538. #define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
  10539. #define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
  10540. #define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
  10541. #define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
  10542. #define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
  10543. #define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
  10544. #define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
  10545. #define FMC_BWTR3_BUSTURN_Pos (16U)
  10546. #define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  10547. #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  10548. #define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
  10549. #define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
  10550. #define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
  10551. #define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
  10552. #define FMC_BWTR3_ACCMOD_Pos (28U)
  10553. #define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
  10554. #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10555. #define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
  10556. #define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
  10557. /****************** Bit definition for FMC_BWTR4 register ******************/
  10558. #define FMC_BWTR4_ADDSET_Pos (0U)
  10559. #define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
  10560. #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  10561. #define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
  10562. #define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
  10563. #define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
  10564. #define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
  10565. #define FMC_BWTR4_ADDHLD_Pos (4U)
  10566. #define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  10567. #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  10568. #define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
  10569. #define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
  10570. #define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
  10571. #define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
  10572. #define FMC_BWTR4_DATAST_Pos (8U)
  10573. #define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
  10574. #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  10575. #define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
  10576. #define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
  10577. #define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
  10578. #define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
  10579. #define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
  10580. #define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
  10581. #define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
  10582. #define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
  10583. #define FMC_BWTR4_BUSTURN_Pos (16U)
  10584. #define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  10585. #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  10586. #define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
  10587. #define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
  10588. #define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
  10589. #define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
  10590. #define FMC_BWTR4_ACCMOD_Pos (28U)
  10591. #define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
  10592. #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  10593. #define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
  10594. #define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
  10595. /****************** Bit definition for FMC_PCR register *******************/
  10596. #define FMC_PCR_PWAITEN_Pos (1U)
  10597. #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
  10598. #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
  10599. #define FMC_PCR_PBKEN_Pos (2U)
  10600. #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
  10601. #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
  10602. #define FMC_PCR_PTYP_Pos (3U)
  10603. #define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
  10604. #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
  10605. #define FMC_PCR_PWID_Pos (4U)
  10606. #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
  10607. #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
  10608. #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
  10609. #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
  10610. #define FMC_PCR_ECCEN_Pos (6U)
  10611. #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
  10612. #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
  10613. #define FMC_PCR_TCLR_Pos (9U)
  10614. #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
  10615. #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
  10616. #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
  10617. #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
  10618. #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
  10619. #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
  10620. #define FMC_PCR_TAR_Pos (13U)
  10621. #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
  10622. #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
  10623. #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
  10624. #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
  10625. #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
  10626. #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
  10627. #define FMC_PCR_ECCPS_Pos (17U)
  10628. #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
  10629. #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
  10630. #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
  10631. #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
  10632. #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
  10633. /******************* Bit definition for FMC_SR register *******************/
  10634. #define FMC_SR_IRS_Pos (0U)
  10635. #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
  10636. #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
  10637. #define FMC_SR_ILS_Pos (1U)
  10638. #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
  10639. #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
  10640. #define FMC_SR_IFS_Pos (2U)
  10641. #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
  10642. #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
  10643. #define FMC_SR_IREN_Pos (3U)
  10644. #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
  10645. #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
  10646. #define FMC_SR_ILEN_Pos (4U)
  10647. #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
  10648. #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
  10649. #define FMC_SR_IFEN_Pos (5U)
  10650. #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
  10651. #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
  10652. #define FMC_SR_FEMPT_Pos (6U)
  10653. #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
  10654. #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
  10655. /****************** Bit definition for FMC_PMEM register ******************/
  10656. #define FMC_PMEM_MEMSET2_Pos (0U)
  10657. #define FMC_PMEM_MEMSET2_Msk (0xFFUL << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
  10658. #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
  10659. #define FMC_PMEM_MEMSET2_0 (0x01UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
  10660. #define FMC_PMEM_MEMSET2_1 (0x02UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
  10661. #define FMC_PMEM_MEMSET2_2 (0x04UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
  10662. #define FMC_PMEM_MEMSET2_3 (0x08UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
  10663. #define FMC_PMEM_MEMSET2_4 (0x10UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
  10664. #define FMC_PMEM_MEMSET2_5 (0x20UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
  10665. #define FMC_PMEM_MEMSET2_6 (0x40UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
  10666. #define FMC_PMEM_MEMSET2_7 (0x80UL << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
  10667. #define FMC_PMEM_MEMWAIT2_Pos (8U)
  10668. #define FMC_PMEM_MEMWAIT2_Msk (0xFFUL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
  10669. #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
  10670. #define FMC_PMEM_MEMWAIT2_0 (0x01UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
  10671. #define FMC_PMEM_MEMWAIT2_1 (0x02UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
  10672. #define FMC_PMEM_MEMWAIT2_2 (0x04UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
  10673. #define FMC_PMEM_MEMWAIT2_3 (0x08UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
  10674. #define FMC_PMEM_MEMWAIT2_4 (0x10UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
  10675. #define FMC_PMEM_MEMWAIT2_5 (0x20UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
  10676. #define FMC_PMEM_MEMWAIT2_6 (0x40UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
  10677. #define FMC_PMEM_MEMWAIT2_7 (0x80UL << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
  10678. #define FMC_PMEM_MEMHOLD2_Pos (16U)
  10679. #define FMC_PMEM_MEMHOLD2_Msk (0xFFUL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
  10680. #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
  10681. #define FMC_PMEM_MEMHOLD2_0 (0x01UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
  10682. #define FMC_PMEM_MEMHOLD2_1 (0x02UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
  10683. #define FMC_PMEM_MEMHOLD2_2 (0x04UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
  10684. #define FMC_PMEM_MEMHOLD2_3 (0x08UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
  10685. #define FMC_PMEM_MEMHOLD2_4 (0x10UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
  10686. #define FMC_PMEM_MEMHOLD2_5 (0x20UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
  10687. #define FMC_PMEM_MEMHOLD2_6 (0x40UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
  10688. #define FMC_PMEM_MEMHOLD2_7 (0x80UL << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
  10689. #define FMC_PMEM_MEMHIZ2_Pos (24U)
  10690. #define FMC_PMEM_MEMHIZ2_Msk (0xFFUL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
  10691. #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
  10692. #define FMC_PMEM_MEMHIZ2_0 (0x01UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
  10693. #define FMC_PMEM_MEMHIZ2_1 (0x02UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
  10694. #define FMC_PMEM_MEMHIZ2_2 (0x04UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
  10695. #define FMC_PMEM_MEMHIZ2_3 (0x08UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
  10696. #define FMC_PMEM_MEMHIZ2_4 (0x10UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
  10697. #define FMC_PMEM_MEMHIZ2_5 (0x20UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
  10698. #define FMC_PMEM_MEMHIZ2_6 (0x40UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
  10699. #define FMC_PMEM_MEMHIZ2_7 (0x80UL << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
  10700. /****************** Bit definition for FMC_PATT register ******************/
  10701. #define FMC_PATT_ATTSET2_Pos (0U)
  10702. #define FMC_PATT_ATTSET2_Msk (0xFFUL << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
  10703. #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
  10704. #define FMC_PATT_ATTSET2_0 (0x01UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
  10705. #define FMC_PATT_ATTSET2_1 (0x02UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
  10706. #define FMC_PATT_ATTSET2_2 (0x04UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
  10707. #define FMC_PATT_ATTSET2_3 (0x08UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
  10708. #define FMC_PATT_ATTSET2_4 (0x10UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
  10709. #define FMC_PATT_ATTSET2_5 (0x20UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
  10710. #define FMC_PATT_ATTSET2_6 (0x40UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
  10711. #define FMC_PATT_ATTSET2_7 (0x80UL << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
  10712. #define FMC_PATT_ATTWAIT2_Pos (8U)
  10713. #define FMC_PATT_ATTWAIT2_Msk (0xFFUL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
  10714. #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
  10715. #define FMC_PATT_ATTWAIT2_0 (0x01UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
  10716. #define FMC_PATT_ATTWAIT2_1 (0x02UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
  10717. #define FMC_PATT_ATTWAIT2_2 (0x04UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
  10718. #define FMC_PATT_ATTWAIT2_3 (0x08UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
  10719. #define FMC_PATT_ATTWAIT2_4 (0x10UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
  10720. #define FMC_PATT_ATTWAIT2_5 (0x20UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
  10721. #define FMC_PATT_ATTWAIT2_6 (0x40UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
  10722. #define FMC_PATT_ATTWAIT2_7 (0x80UL << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
  10723. #define FMC_PATT_ATTHOLD2_Pos (16U)
  10724. #define FMC_PATT_ATTHOLD2_Msk (0xFFUL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
  10725. #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
  10726. #define FMC_PATT_ATTHOLD2_0 (0x01UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
  10727. #define FMC_PATT_ATTHOLD2_1 (0x02UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
  10728. #define FMC_PATT_ATTHOLD2_2 (0x04UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
  10729. #define FMC_PATT_ATTHOLD2_3 (0x08UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
  10730. #define FMC_PATT_ATTHOLD2_4 (0x10UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
  10731. #define FMC_PATT_ATTHOLD2_5 (0x20UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
  10732. #define FMC_PATT_ATTHOLD2_6 (0x40UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
  10733. #define FMC_PATT_ATTHOLD2_7 (0x80UL << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
  10734. #define FMC_PATT_ATTHIZ2_Pos (24U)
  10735. #define FMC_PATT_ATTHIZ2_Msk (0xFFUL << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
  10736. #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
  10737. #define FMC_PATT_ATTHIZ2_0 (0x01UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
  10738. #define FMC_PATT_ATTHIZ2_1 (0x02UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
  10739. #define FMC_PATT_ATTHIZ2_2 (0x04UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
  10740. #define FMC_PATT_ATTHIZ2_3 (0x08UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
  10741. #define FMC_PATT_ATTHIZ2_4 (0x10UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
  10742. #define FMC_PATT_ATTHIZ2_5 (0x20UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
  10743. #define FMC_PATT_ATTHIZ2_6 (0x40UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
  10744. #define FMC_PATT_ATTHIZ2_7 (0x80UL << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
  10745. /****************** Bit definition for FMC_ECCR register ******************/
  10746. #define FMC_ECCR_ECC2_Pos (0U)
  10747. #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
  10748. #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
  10749. /****************** Bit definition for FMC_SDCR1 register ******************/
  10750. #define FMC_SDCR1_NC_Pos (0U)
  10751. #define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
  10752. #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
  10753. #define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
  10754. #define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
  10755. #define FMC_SDCR1_NR_Pos (2U)
  10756. #define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
  10757. #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
  10758. #define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
  10759. #define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
  10760. #define FMC_SDCR1_MWID_Pos (4U)
  10761. #define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
  10762. #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
  10763. #define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
  10764. #define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
  10765. #define FMC_SDCR1_NB_Pos (6U)
  10766. #define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
  10767. #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
  10768. #define FMC_SDCR1_CAS_Pos (7U)
  10769. #define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
  10770. #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
  10771. #define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
  10772. #define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
  10773. #define FMC_SDCR1_WP_Pos (9U)
  10774. #define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
  10775. #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
  10776. #define FMC_SDCR1_SDCLK_Pos (10U)
  10777. #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
  10778. #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
  10779. #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
  10780. #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
  10781. #define FMC_SDCR1_RBURST_Pos (12U)
  10782. #define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
  10783. #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
  10784. #define FMC_SDCR1_RPIPE_Pos (13U)
  10785. #define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
  10786. #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
  10787. #define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
  10788. #define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
  10789. /****************** Bit definition for FMC_SDCR2 register ******************/
  10790. #define FMC_SDCR2_NC_Pos (0U)
  10791. #define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
  10792. #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
  10793. #define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
  10794. #define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
  10795. #define FMC_SDCR2_NR_Pos (2U)
  10796. #define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
  10797. #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
  10798. #define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
  10799. #define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
  10800. #define FMC_SDCR2_MWID_Pos (4U)
  10801. #define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
  10802. #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
  10803. #define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
  10804. #define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
  10805. #define FMC_SDCR2_NB_Pos (6U)
  10806. #define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
  10807. #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
  10808. #define FMC_SDCR2_CAS_Pos (7U)
  10809. #define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
  10810. #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
  10811. #define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
  10812. #define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
  10813. #define FMC_SDCR2_WP_Pos (9U)
  10814. #define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
  10815. #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
  10816. #define FMC_SDCR2_SDCLK_Pos (10U)
  10817. #define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
  10818. #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
  10819. #define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
  10820. #define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
  10821. #define FMC_SDCR2_RBURST_Pos (12U)
  10822. #define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
  10823. #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
  10824. #define FMC_SDCR2_RPIPE_Pos (13U)
  10825. #define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
  10826. #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
  10827. #define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
  10828. #define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
  10829. /****************** Bit definition for FMC_SDTR1 register ******************/
  10830. #define FMC_SDTR1_TMRD_Pos (0U)
  10831. #define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
  10832. #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
  10833. #define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
  10834. #define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
  10835. #define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
  10836. #define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
  10837. #define FMC_SDTR1_TXSR_Pos (4U)
  10838. #define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
  10839. #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
  10840. #define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
  10841. #define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
  10842. #define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
  10843. #define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
  10844. #define FMC_SDTR1_TRAS_Pos (8U)
  10845. #define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
  10846. #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
  10847. #define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
  10848. #define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
  10849. #define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
  10850. #define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
  10851. #define FMC_SDTR1_TRC_Pos (12U)
  10852. #define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
  10853. #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
  10854. #define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
  10855. #define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
  10856. #define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
  10857. #define FMC_SDTR1_TWR_Pos (16U)
  10858. #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
  10859. #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
  10860. #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
  10861. #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
  10862. #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
  10863. #define FMC_SDTR1_TRP_Pos (20U)
  10864. #define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
  10865. #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
  10866. #define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
  10867. #define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
  10868. #define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
  10869. #define FMC_SDTR1_TRCD_Pos (24U)
  10870. #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
  10871. #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
  10872. #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
  10873. #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
  10874. #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
  10875. /****************** Bit definition for FMC_SDTR2 register ******************/
  10876. #define FMC_SDTR2_TMRD_Pos (0U)
  10877. #define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
  10878. #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
  10879. #define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
  10880. #define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
  10881. #define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
  10882. #define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
  10883. #define FMC_SDTR2_TXSR_Pos (4U)
  10884. #define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
  10885. #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
  10886. #define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
  10887. #define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
  10888. #define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
  10889. #define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
  10890. #define FMC_SDTR2_TRAS_Pos (8U)
  10891. #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
  10892. #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
  10893. #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
  10894. #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
  10895. #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
  10896. #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
  10897. #define FMC_SDTR2_TRC_Pos (12U)
  10898. #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
  10899. #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
  10900. #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
  10901. #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
  10902. #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
  10903. #define FMC_SDTR2_TWR_Pos (16U)
  10904. #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
  10905. #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
  10906. #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
  10907. #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
  10908. #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
  10909. #define FMC_SDTR2_TRP_Pos (20U)
  10910. #define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
  10911. #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
  10912. #define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
  10913. #define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
  10914. #define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
  10915. #define FMC_SDTR2_TRCD_Pos (24U)
  10916. #define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
  10917. #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
  10918. #define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
  10919. #define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
  10920. #define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
  10921. /****************** Bit definition for FMC_SDCMR register ******************/
  10922. #define FMC_SDCMR_MODE_Pos (0U)
  10923. #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
  10924. #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
  10925. #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
  10926. #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
  10927. #define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
  10928. #define FMC_SDCMR_CTB2_Pos (3U)
  10929. #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
  10930. #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
  10931. #define FMC_SDCMR_CTB1_Pos (4U)
  10932. #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
  10933. #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
  10934. #define FMC_SDCMR_NRFS_Pos (5U)
  10935. #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
  10936. #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
  10937. #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
  10938. #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
  10939. #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
  10940. #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
  10941. #define FMC_SDCMR_MRD_Pos (9U)
  10942. #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
  10943. #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
  10944. /****************** Bit definition for FMC_SDRTR register ******************/
  10945. #define FMC_SDRTR_CRE_Pos (0U)
  10946. #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
  10947. #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
  10948. #define FMC_SDRTR_COUNT_Pos (1U)
  10949. #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
  10950. #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
  10951. #define FMC_SDRTR_REIE_Pos (14U)
  10952. #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
  10953. #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
  10954. /****************** Bit definition for FMC_SDSR register ******************/
  10955. #define FMC_SDSR_RE_Pos (0U)
  10956. #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
  10957. #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
  10958. #define FMC_SDSR_MODES1_Pos (1U)
  10959. #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
  10960. #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
  10961. #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
  10962. #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
  10963. #define FMC_SDSR_MODES2_Pos (3U)
  10964. #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
  10965. #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
  10966. #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
  10967. #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
  10968. #define FMC_SDSR_BUSY_Pos (5U)
  10969. #define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
  10970. #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
  10971. /******************************************************************************/
  10972. /* */
  10973. /* General Purpose I/O */
  10974. /* */
  10975. /******************************************************************************/
  10976. /****************** Bits definition for GPIO_MODER register *****************/
  10977. #define GPIO_MODER_MODER0_Pos (0U)
  10978. #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  10979. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  10980. #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  10981. #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  10982. #define GPIO_MODER_MODER1_Pos (2U)
  10983. #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  10984. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  10985. #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  10986. #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  10987. #define GPIO_MODER_MODER2_Pos (4U)
  10988. #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  10989. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  10990. #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  10991. #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  10992. #define GPIO_MODER_MODER3_Pos (6U)
  10993. #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  10994. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  10995. #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  10996. #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  10997. #define GPIO_MODER_MODER4_Pos (8U)
  10998. #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  10999. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  11000. #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  11001. #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  11002. #define GPIO_MODER_MODER5_Pos (10U)
  11003. #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  11004. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  11005. #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  11006. #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  11007. #define GPIO_MODER_MODER6_Pos (12U)
  11008. #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  11009. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  11010. #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  11011. #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  11012. #define GPIO_MODER_MODER7_Pos (14U)
  11013. #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  11014. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  11015. #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  11016. #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  11017. #define GPIO_MODER_MODER8_Pos (16U)
  11018. #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  11019. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  11020. #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  11021. #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  11022. #define GPIO_MODER_MODER9_Pos (18U)
  11023. #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  11024. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  11025. #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  11026. #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  11027. #define GPIO_MODER_MODER10_Pos (20U)
  11028. #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  11029. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  11030. #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  11031. #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  11032. #define GPIO_MODER_MODER11_Pos (22U)
  11033. #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  11034. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  11035. #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  11036. #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  11037. #define GPIO_MODER_MODER12_Pos (24U)
  11038. #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  11039. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  11040. #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  11041. #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  11042. #define GPIO_MODER_MODER13_Pos (26U)
  11043. #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  11044. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  11045. #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  11046. #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  11047. #define GPIO_MODER_MODER14_Pos (28U)
  11048. #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  11049. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  11050. #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  11051. #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  11052. #define GPIO_MODER_MODER15_Pos (30U)
  11053. #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  11054. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  11055. #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  11056. #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  11057. /* Legacy defines */
  11058. #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
  11059. #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
  11060. #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
  11061. #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
  11062. #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
  11063. #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
  11064. #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
  11065. #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
  11066. #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
  11067. #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
  11068. #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
  11069. #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
  11070. #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
  11071. #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
  11072. #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
  11073. #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
  11074. #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
  11075. #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
  11076. #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
  11077. #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
  11078. #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
  11079. #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
  11080. #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
  11081. #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
  11082. #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
  11083. #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
  11084. #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
  11085. #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
  11086. #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
  11087. #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
  11088. #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
  11089. #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
  11090. #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
  11091. #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
  11092. #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
  11093. #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
  11094. #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
  11095. #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
  11096. #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
  11097. #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
  11098. #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
  11099. #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
  11100. #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
  11101. #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
  11102. #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
  11103. #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
  11104. #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
  11105. #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
  11106. #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
  11107. #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
  11108. #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
  11109. #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
  11110. #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
  11111. #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
  11112. #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
  11113. #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
  11114. #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
  11115. #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
  11116. #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
  11117. #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
  11118. #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
  11119. #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
  11120. #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
  11121. #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
  11122. #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
  11123. #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
  11124. #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
  11125. #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
  11126. #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
  11127. #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
  11128. #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
  11129. #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
  11130. #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
  11131. #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
  11132. #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
  11133. #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
  11134. #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
  11135. #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
  11136. #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
  11137. #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
  11138. /****************** Bits definition for GPIO_OTYPER register ****************/
  11139. #define GPIO_OTYPER_OT0_Pos (0U)
  11140. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  11141. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  11142. #define GPIO_OTYPER_OT1_Pos (1U)
  11143. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  11144. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  11145. #define GPIO_OTYPER_OT2_Pos (2U)
  11146. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  11147. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  11148. #define GPIO_OTYPER_OT3_Pos (3U)
  11149. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  11150. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  11151. #define GPIO_OTYPER_OT4_Pos (4U)
  11152. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  11153. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  11154. #define GPIO_OTYPER_OT5_Pos (5U)
  11155. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  11156. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  11157. #define GPIO_OTYPER_OT6_Pos (6U)
  11158. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  11159. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  11160. #define GPIO_OTYPER_OT7_Pos (7U)
  11161. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  11162. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  11163. #define GPIO_OTYPER_OT8_Pos (8U)
  11164. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  11165. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  11166. #define GPIO_OTYPER_OT9_Pos (9U)
  11167. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  11168. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  11169. #define GPIO_OTYPER_OT10_Pos (10U)
  11170. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  11171. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  11172. #define GPIO_OTYPER_OT11_Pos (11U)
  11173. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  11174. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  11175. #define GPIO_OTYPER_OT12_Pos (12U)
  11176. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  11177. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  11178. #define GPIO_OTYPER_OT13_Pos (13U)
  11179. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  11180. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  11181. #define GPIO_OTYPER_OT14_Pos (14U)
  11182. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  11183. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  11184. #define GPIO_OTYPER_OT15_Pos (15U)
  11185. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  11186. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  11187. /* Legacy defines */
  11188. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  11189. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  11190. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  11191. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  11192. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  11193. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  11194. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  11195. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  11196. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  11197. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  11198. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  11199. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  11200. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  11201. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  11202. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  11203. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  11204. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  11205. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  11206. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  11207. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  11208. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  11209. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  11210. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  11211. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  11212. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  11213. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  11214. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  11215. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  11216. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  11217. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  11218. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  11219. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  11220. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  11221. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  11222. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  11223. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  11224. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  11225. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  11226. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  11227. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  11228. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  11229. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  11230. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  11231. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  11232. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  11233. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  11234. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  11235. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  11236. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  11237. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  11238. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  11239. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  11240. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  11241. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  11242. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  11243. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  11244. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  11245. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  11246. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  11247. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  11248. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  11249. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  11250. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  11251. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  11252. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  11253. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  11254. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  11255. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  11256. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  11257. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  11258. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  11259. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  11260. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  11261. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  11262. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  11263. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  11264. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  11265. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  11266. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  11267. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  11268. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  11269. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  11270. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  11271. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  11272. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  11273. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  11274. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  11275. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  11276. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  11277. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  11278. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  11279. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  11280. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  11281. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  11282. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  11283. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  11284. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  11285. /* Legacy defines */
  11286. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  11287. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  11288. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  11289. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  11290. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  11291. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  11292. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  11293. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  11294. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  11295. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  11296. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  11297. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  11298. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  11299. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  11300. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  11301. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  11302. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  11303. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  11304. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  11305. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  11306. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  11307. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  11308. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  11309. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  11310. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  11311. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  11312. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  11313. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  11314. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  11315. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  11316. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  11317. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  11318. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  11319. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  11320. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  11321. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  11322. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  11323. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  11324. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  11325. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  11326. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  11327. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  11328. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  11329. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  11330. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  11331. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  11332. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  11333. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  11334. /****************** Bits definition for GPIO_PUPDR register *****************/
  11335. #define GPIO_PUPDR_PUPD0_Pos (0U)
  11336. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  11337. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  11338. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  11339. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  11340. #define GPIO_PUPDR_PUPD1_Pos (2U)
  11341. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  11342. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  11343. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  11344. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  11345. #define GPIO_PUPDR_PUPD2_Pos (4U)
  11346. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  11347. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  11348. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  11349. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  11350. #define GPIO_PUPDR_PUPD3_Pos (6U)
  11351. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  11352. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  11353. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  11354. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  11355. #define GPIO_PUPDR_PUPD4_Pos (8U)
  11356. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  11357. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  11358. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  11359. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  11360. #define GPIO_PUPDR_PUPD5_Pos (10U)
  11361. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  11362. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  11363. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  11364. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  11365. #define GPIO_PUPDR_PUPD6_Pos (12U)
  11366. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  11367. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  11368. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  11369. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  11370. #define GPIO_PUPDR_PUPD7_Pos (14U)
  11371. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  11372. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  11373. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  11374. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  11375. #define GPIO_PUPDR_PUPD8_Pos (16U)
  11376. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  11377. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  11378. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  11379. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  11380. #define GPIO_PUPDR_PUPD9_Pos (18U)
  11381. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  11382. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  11383. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  11384. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  11385. #define GPIO_PUPDR_PUPD10_Pos (20U)
  11386. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  11387. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  11388. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  11389. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  11390. #define GPIO_PUPDR_PUPD11_Pos (22U)
  11391. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  11392. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  11393. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  11394. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  11395. #define GPIO_PUPDR_PUPD12_Pos (24U)
  11396. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  11397. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  11398. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  11399. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  11400. #define GPIO_PUPDR_PUPD13_Pos (26U)
  11401. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  11402. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  11403. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  11404. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  11405. #define GPIO_PUPDR_PUPD14_Pos (28U)
  11406. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  11407. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  11408. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  11409. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  11410. #define GPIO_PUPDR_PUPD15_Pos (30U)
  11411. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  11412. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  11413. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  11414. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  11415. /* Legacy defines */
  11416. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  11417. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  11418. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  11419. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  11420. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  11421. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  11422. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  11423. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  11424. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  11425. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  11426. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  11427. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  11428. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  11429. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  11430. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  11431. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  11432. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  11433. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  11434. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  11435. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  11436. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  11437. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  11438. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  11439. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  11440. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  11441. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  11442. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  11443. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  11444. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  11445. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  11446. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  11447. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  11448. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  11449. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  11450. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  11451. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  11452. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  11453. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  11454. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  11455. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  11456. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  11457. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  11458. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  11459. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  11460. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  11461. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  11462. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  11463. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  11464. /****************** Bits definition for GPIO_IDR register *******************/
  11465. #define GPIO_IDR_ID0_Pos (0U)
  11466. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  11467. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  11468. #define GPIO_IDR_ID1_Pos (1U)
  11469. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  11470. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  11471. #define GPIO_IDR_ID2_Pos (2U)
  11472. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  11473. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  11474. #define GPIO_IDR_ID3_Pos (3U)
  11475. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  11476. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  11477. #define GPIO_IDR_ID4_Pos (4U)
  11478. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  11479. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  11480. #define GPIO_IDR_ID5_Pos (5U)
  11481. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  11482. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  11483. #define GPIO_IDR_ID6_Pos (6U)
  11484. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  11485. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  11486. #define GPIO_IDR_ID7_Pos (7U)
  11487. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  11488. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  11489. #define GPIO_IDR_ID8_Pos (8U)
  11490. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  11491. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  11492. #define GPIO_IDR_ID9_Pos (9U)
  11493. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  11494. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  11495. #define GPIO_IDR_ID10_Pos (10U)
  11496. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  11497. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  11498. #define GPIO_IDR_ID11_Pos (11U)
  11499. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  11500. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  11501. #define GPIO_IDR_ID12_Pos (12U)
  11502. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  11503. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  11504. #define GPIO_IDR_ID13_Pos (13U)
  11505. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  11506. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  11507. #define GPIO_IDR_ID14_Pos (14U)
  11508. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  11509. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  11510. #define GPIO_IDR_ID15_Pos (15U)
  11511. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  11512. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  11513. /* Legacy defines */
  11514. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  11515. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  11516. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  11517. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  11518. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  11519. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  11520. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  11521. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  11522. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  11523. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  11524. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  11525. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  11526. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  11527. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  11528. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  11529. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  11530. /****************** Bits definition for GPIO_ODR register *******************/
  11531. #define GPIO_ODR_OD0_Pos (0U)
  11532. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  11533. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  11534. #define GPIO_ODR_OD1_Pos (1U)
  11535. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  11536. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  11537. #define GPIO_ODR_OD2_Pos (2U)
  11538. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  11539. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  11540. #define GPIO_ODR_OD3_Pos (3U)
  11541. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  11542. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  11543. #define GPIO_ODR_OD4_Pos (4U)
  11544. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  11545. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  11546. #define GPIO_ODR_OD5_Pos (5U)
  11547. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  11548. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  11549. #define GPIO_ODR_OD6_Pos (6U)
  11550. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  11551. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  11552. #define GPIO_ODR_OD7_Pos (7U)
  11553. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  11554. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  11555. #define GPIO_ODR_OD8_Pos (8U)
  11556. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  11557. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  11558. #define GPIO_ODR_OD9_Pos (9U)
  11559. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  11560. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  11561. #define GPIO_ODR_OD10_Pos (10U)
  11562. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  11563. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  11564. #define GPIO_ODR_OD11_Pos (11U)
  11565. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  11566. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  11567. #define GPIO_ODR_OD12_Pos (12U)
  11568. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  11569. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  11570. #define GPIO_ODR_OD13_Pos (13U)
  11571. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  11572. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  11573. #define GPIO_ODR_OD14_Pos (14U)
  11574. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  11575. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  11576. #define GPIO_ODR_OD15_Pos (15U)
  11577. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  11578. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  11579. /* Legacy defines */
  11580. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  11581. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  11582. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  11583. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  11584. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  11585. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  11586. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  11587. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  11588. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  11589. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  11590. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  11591. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  11592. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  11593. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  11594. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  11595. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  11596. /****************** Bits definition for GPIO_BSRR register ******************/
  11597. #define GPIO_BSRR_BS0_Pos (0U)
  11598. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  11599. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  11600. #define GPIO_BSRR_BS1_Pos (1U)
  11601. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  11602. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  11603. #define GPIO_BSRR_BS2_Pos (2U)
  11604. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  11605. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  11606. #define GPIO_BSRR_BS3_Pos (3U)
  11607. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  11608. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  11609. #define GPIO_BSRR_BS4_Pos (4U)
  11610. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  11611. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  11612. #define GPIO_BSRR_BS5_Pos (5U)
  11613. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  11614. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  11615. #define GPIO_BSRR_BS6_Pos (6U)
  11616. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  11617. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  11618. #define GPIO_BSRR_BS7_Pos (7U)
  11619. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  11620. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  11621. #define GPIO_BSRR_BS8_Pos (8U)
  11622. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  11623. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  11624. #define GPIO_BSRR_BS9_Pos (9U)
  11625. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  11626. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  11627. #define GPIO_BSRR_BS10_Pos (10U)
  11628. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  11629. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  11630. #define GPIO_BSRR_BS11_Pos (11U)
  11631. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  11632. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  11633. #define GPIO_BSRR_BS12_Pos (12U)
  11634. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  11635. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  11636. #define GPIO_BSRR_BS13_Pos (13U)
  11637. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  11638. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  11639. #define GPIO_BSRR_BS14_Pos (14U)
  11640. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  11641. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  11642. #define GPIO_BSRR_BS15_Pos (15U)
  11643. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  11644. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  11645. #define GPIO_BSRR_BR0_Pos (16U)
  11646. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  11647. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  11648. #define GPIO_BSRR_BR1_Pos (17U)
  11649. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  11650. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  11651. #define GPIO_BSRR_BR2_Pos (18U)
  11652. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  11653. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  11654. #define GPIO_BSRR_BR3_Pos (19U)
  11655. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  11656. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  11657. #define GPIO_BSRR_BR4_Pos (20U)
  11658. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  11659. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  11660. #define GPIO_BSRR_BR5_Pos (21U)
  11661. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  11662. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  11663. #define GPIO_BSRR_BR6_Pos (22U)
  11664. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  11665. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  11666. #define GPIO_BSRR_BR7_Pos (23U)
  11667. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  11668. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  11669. #define GPIO_BSRR_BR8_Pos (24U)
  11670. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  11671. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  11672. #define GPIO_BSRR_BR9_Pos (25U)
  11673. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  11674. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  11675. #define GPIO_BSRR_BR10_Pos (26U)
  11676. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  11677. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  11678. #define GPIO_BSRR_BR11_Pos (27U)
  11679. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  11680. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  11681. #define GPIO_BSRR_BR12_Pos (28U)
  11682. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  11683. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  11684. #define GPIO_BSRR_BR13_Pos (29U)
  11685. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  11686. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  11687. #define GPIO_BSRR_BR14_Pos (30U)
  11688. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  11689. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  11690. #define GPIO_BSRR_BR15_Pos (31U)
  11691. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  11692. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  11693. /* Legacy defines */
  11694. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  11695. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  11696. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  11697. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  11698. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  11699. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  11700. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  11701. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  11702. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  11703. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  11704. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  11705. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  11706. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  11707. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  11708. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  11709. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  11710. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  11711. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  11712. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  11713. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  11714. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  11715. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  11716. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  11717. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  11718. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  11719. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  11720. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  11721. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  11722. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  11723. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  11724. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  11725. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  11726. #define GPIO_BRR_BR0 GPIO_BSRR_BR0
  11727. #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
  11728. #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
  11729. #define GPIO_BRR_BR1 GPIO_BSRR_BR1
  11730. #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
  11731. #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
  11732. #define GPIO_BRR_BR2 GPIO_BSRR_BR2
  11733. #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
  11734. #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
  11735. #define GPIO_BRR_BR3 GPIO_BSRR_BR3
  11736. #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
  11737. #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
  11738. #define GPIO_BRR_BR4 GPIO_BSRR_BR4
  11739. #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
  11740. #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
  11741. #define GPIO_BRR_BR5 GPIO_BSRR_BR5
  11742. #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
  11743. #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
  11744. #define GPIO_BRR_BR6 GPIO_BSRR_BR6
  11745. #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
  11746. #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
  11747. #define GPIO_BRR_BR7 GPIO_BSRR_BR7
  11748. #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
  11749. #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
  11750. #define GPIO_BRR_BR8 GPIO_BSRR_BR8
  11751. #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
  11752. #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
  11753. #define GPIO_BRR_BR9 GPIO_BSRR_BR9
  11754. #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
  11755. #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
  11756. #define GPIO_BRR_BR10 GPIO_BSRR_BR10
  11757. #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
  11758. #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
  11759. #define GPIO_BRR_BR11 GPIO_BSRR_BR11
  11760. #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
  11761. #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
  11762. #define GPIO_BRR_BR12 GPIO_BSRR_BR12
  11763. #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
  11764. #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
  11765. #define GPIO_BRR_BR13 GPIO_BSRR_BR13
  11766. #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
  11767. #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
  11768. #define GPIO_BRR_BR14 GPIO_BSRR_BR14
  11769. #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
  11770. #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
  11771. #define GPIO_BRR_BR15 GPIO_BSRR_BR15
  11772. #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
  11773. #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
  11774. /****************** Bit definition for GPIO_LCKR register *********************/
  11775. #define GPIO_LCKR_LCK0_Pos (0U)
  11776. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  11777. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  11778. #define GPIO_LCKR_LCK1_Pos (1U)
  11779. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  11780. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  11781. #define GPIO_LCKR_LCK2_Pos (2U)
  11782. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  11783. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  11784. #define GPIO_LCKR_LCK3_Pos (3U)
  11785. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  11786. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  11787. #define GPIO_LCKR_LCK4_Pos (4U)
  11788. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  11789. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  11790. #define GPIO_LCKR_LCK5_Pos (5U)
  11791. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  11792. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  11793. #define GPIO_LCKR_LCK6_Pos (6U)
  11794. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  11795. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  11796. #define GPIO_LCKR_LCK7_Pos (7U)
  11797. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  11798. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  11799. #define GPIO_LCKR_LCK8_Pos (8U)
  11800. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  11801. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  11802. #define GPIO_LCKR_LCK9_Pos (9U)
  11803. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  11804. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  11805. #define GPIO_LCKR_LCK10_Pos (10U)
  11806. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  11807. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  11808. #define GPIO_LCKR_LCK11_Pos (11U)
  11809. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  11810. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  11811. #define GPIO_LCKR_LCK12_Pos (12U)
  11812. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  11813. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  11814. #define GPIO_LCKR_LCK13_Pos (13U)
  11815. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  11816. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  11817. #define GPIO_LCKR_LCK14_Pos (14U)
  11818. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  11819. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  11820. #define GPIO_LCKR_LCK15_Pos (15U)
  11821. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  11822. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  11823. #define GPIO_LCKR_LCKK_Pos (16U)
  11824. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  11825. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  11826. /****************** Bit definition for GPIO_AFRL register *********************/
  11827. #define GPIO_AFRL_AFSEL0_Pos (0U)
  11828. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  11829. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  11830. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  11831. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  11832. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  11833. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  11834. #define GPIO_AFRL_AFSEL1_Pos (4U)
  11835. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  11836. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  11837. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  11838. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  11839. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  11840. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  11841. #define GPIO_AFRL_AFSEL2_Pos (8U)
  11842. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  11843. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  11844. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  11845. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  11846. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  11847. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  11848. #define GPIO_AFRL_AFSEL3_Pos (12U)
  11849. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  11850. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  11851. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  11852. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  11853. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  11854. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  11855. #define GPIO_AFRL_AFSEL4_Pos (16U)
  11856. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  11857. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  11858. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  11859. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  11860. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  11861. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  11862. #define GPIO_AFRL_AFSEL5_Pos (20U)
  11863. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  11864. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  11865. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  11866. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  11867. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  11868. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  11869. #define GPIO_AFRL_AFSEL6_Pos (24U)
  11870. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  11871. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  11872. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  11873. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  11874. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  11875. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  11876. #define GPIO_AFRL_AFSEL7_Pos (28U)
  11877. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  11878. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  11879. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  11880. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  11881. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  11882. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  11883. /* Legacy defines */
  11884. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  11885. #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
  11886. #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
  11887. #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
  11888. #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
  11889. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  11890. #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
  11891. #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
  11892. #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
  11893. #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
  11894. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  11895. #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
  11896. #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
  11897. #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
  11898. #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
  11899. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  11900. #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
  11901. #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
  11902. #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
  11903. #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
  11904. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  11905. #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
  11906. #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
  11907. #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
  11908. #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
  11909. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  11910. #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
  11911. #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
  11912. #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
  11913. #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
  11914. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  11915. #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
  11916. #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
  11917. #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
  11918. #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
  11919. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  11920. #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
  11921. #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
  11922. #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
  11923. #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
  11924. /****************** Bit definition for GPIO_AFRH register *********************/
  11925. #define GPIO_AFRH_AFSEL8_Pos (0U)
  11926. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  11927. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  11928. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  11929. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  11930. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  11931. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  11932. #define GPIO_AFRH_AFSEL9_Pos (4U)
  11933. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  11934. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  11935. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  11936. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  11937. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  11938. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  11939. #define GPIO_AFRH_AFSEL10_Pos (8U)
  11940. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  11941. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  11942. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  11943. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  11944. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  11945. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  11946. #define GPIO_AFRH_AFSEL11_Pos (12U)
  11947. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  11948. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  11949. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  11950. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  11951. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  11952. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  11953. #define GPIO_AFRH_AFSEL12_Pos (16U)
  11954. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  11955. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  11956. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  11957. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  11958. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  11959. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  11960. #define GPIO_AFRH_AFSEL13_Pos (20U)
  11961. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  11962. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  11963. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  11964. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  11965. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  11966. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  11967. #define GPIO_AFRH_AFSEL14_Pos (24U)
  11968. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  11969. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  11970. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  11971. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  11972. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  11973. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  11974. #define GPIO_AFRH_AFSEL15_Pos (28U)
  11975. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  11976. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  11977. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  11978. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  11979. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  11980. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  11981. /* Legacy defines */
  11982. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  11983. #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
  11984. #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
  11985. #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
  11986. #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
  11987. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  11988. #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
  11989. #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
  11990. #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
  11991. #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
  11992. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  11993. #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
  11994. #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
  11995. #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
  11996. #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
  11997. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  11998. #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
  11999. #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
  12000. #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
  12001. #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
  12002. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  12003. #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
  12004. #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
  12005. #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
  12006. #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
  12007. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  12008. #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
  12009. #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
  12010. #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
  12011. #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
  12012. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  12013. #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
  12014. #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
  12015. #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
  12016. #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
  12017. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  12018. #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
  12019. #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
  12020. #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
  12021. #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
  12022. /******************************************************************************/
  12023. /* */
  12024. /* Inter-integrated Circuit Interface */
  12025. /* */
  12026. /******************************************************************************/
  12027. /******************* Bit definition for I2C_CR1 register ********************/
  12028. #define I2C_CR1_PE_Pos (0U)
  12029. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  12030. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
  12031. #define I2C_CR1_SMBUS_Pos (1U)
  12032. #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
  12033. #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
  12034. #define I2C_CR1_SMBTYPE_Pos (3U)
  12035. #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
  12036. #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
  12037. #define I2C_CR1_ENARP_Pos (4U)
  12038. #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
  12039. #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
  12040. #define I2C_CR1_ENPEC_Pos (5U)
  12041. #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
  12042. #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
  12043. #define I2C_CR1_ENGC_Pos (6U)
  12044. #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
  12045. #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
  12046. #define I2C_CR1_NOSTRETCH_Pos (7U)
  12047. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
  12048. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
  12049. #define I2C_CR1_START_Pos (8U)
  12050. #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
  12051. #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
  12052. #define I2C_CR1_STOP_Pos (9U)
  12053. #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
  12054. #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
  12055. #define I2C_CR1_ACK_Pos (10U)
  12056. #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
  12057. #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
  12058. #define I2C_CR1_POS_Pos (11U)
  12059. #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
  12060. #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
  12061. #define I2C_CR1_PEC_Pos (12U)
  12062. #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
  12063. #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
  12064. #define I2C_CR1_ALERT_Pos (13U)
  12065. #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
  12066. #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
  12067. #define I2C_CR1_SWRST_Pos (15U)
  12068. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
  12069. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
  12070. /******************* Bit definition for I2C_CR2 register ********************/
  12071. #define I2C_CR2_FREQ_Pos (0U)
  12072. #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
  12073. #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
  12074. #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
  12075. #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
  12076. #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
  12077. #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
  12078. #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
  12079. #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
  12080. #define I2C_CR2_ITERREN_Pos (8U)
  12081. #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
  12082. #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
  12083. #define I2C_CR2_ITEVTEN_Pos (9U)
  12084. #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
  12085. #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
  12086. #define I2C_CR2_ITBUFEN_Pos (10U)
  12087. #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
  12088. #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
  12089. #define I2C_CR2_DMAEN_Pos (11U)
  12090. #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
  12091. #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
  12092. #define I2C_CR2_LAST_Pos (12U)
  12093. #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
  12094. #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
  12095. /******************* Bit definition for I2C_OAR1 register *******************/
  12096. #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
  12097. #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
  12098. #define I2C_OAR1_ADD0_Pos (0U)
  12099. #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
  12100. #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
  12101. #define I2C_OAR1_ADD1_Pos (1U)
  12102. #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
  12103. #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
  12104. #define I2C_OAR1_ADD2_Pos (2U)
  12105. #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
  12106. #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
  12107. #define I2C_OAR1_ADD3_Pos (3U)
  12108. #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
  12109. #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
  12110. #define I2C_OAR1_ADD4_Pos (4U)
  12111. #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
  12112. #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
  12113. #define I2C_OAR1_ADD5_Pos (5U)
  12114. #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
  12115. #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
  12116. #define I2C_OAR1_ADD6_Pos (6U)
  12117. #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
  12118. #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
  12119. #define I2C_OAR1_ADD7_Pos (7U)
  12120. #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
  12121. #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
  12122. #define I2C_OAR1_ADD8_Pos (8U)
  12123. #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
  12124. #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
  12125. #define I2C_OAR1_ADD9_Pos (9U)
  12126. #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
  12127. #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
  12128. #define I2C_OAR1_ADDMODE_Pos (15U)
  12129. #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
  12130. #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
  12131. /******************* Bit definition for I2C_OAR2 register *******************/
  12132. #define I2C_OAR2_ENDUAL_Pos (0U)
  12133. #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
  12134. #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
  12135. #define I2C_OAR2_ADD2_Pos (1U)
  12136. #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
  12137. #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
  12138. /******************** Bit definition for I2C_DR register ********************/
  12139. #define I2C_DR_DR_Pos (0U)
  12140. #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
  12141. #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
  12142. /******************* Bit definition for I2C_SR1 register ********************/
  12143. #define I2C_SR1_SB_Pos (0U)
  12144. #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
  12145. #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
  12146. #define I2C_SR1_ADDR_Pos (1U)
  12147. #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
  12148. #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
  12149. #define I2C_SR1_BTF_Pos (2U)
  12150. #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
  12151. #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
  12152. #define I2C_SR1_ADD10_Pos (3U)
  12153. #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
  12154. #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
  12155. #define I2C_SR1_STOPF_Pos (4U)
  12156. #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
  12157. #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
  12158. #define I2C_SR1_RXNE_Pos (6U)
  12159. #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
  12160. #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
  12161. #define I2C_SR1_TXE_Pos (7U)
  12162. #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
  12163. #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
  12164. #define I2C_SR1_BERR_Pos (8U)
  12165. #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
  12166. #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
  12167. #define I2C_SR1_ARLO_Pos (9U)
  12168. #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
  12169. #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
  12170. #define I2C_SR1_AF_Pos (10U)
  12171. #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
  12172. #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
  12173. #define I2C_SR1_OVR_Pos (11U)
  12174. #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
  12175. #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
  12176. #define I2C_SR1_PECERR_Pos (12U)
  12177. #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
  12178. #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
  12179. #define I2C_SR1_TIMEOUT_Pos (14U)
  12180. #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
  12181. #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
  12182. #define I2C_SR1_SMBALERT_Pos (15U)
  12183. #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
  12184. #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
  12185. /******************* Bit definition for I2C_SR2 register ********************/
  12186. #define I2C_SR2_MSL_Pos (0U)
  12187. #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
  12188. #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
  12189. #define I2C_SR2_BUSY_Pos (1U)
  12190. #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
  12191. #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
  12192. #define I2C_SR2_TRA_Pos (2U)
  12193. #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
  12194. #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
  12195. #define I2C_SR2_GENCALL_Pos (4U)
  12196. #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
  12197. #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
  12198. #define I2C_SR2_SMBDEFAULT_Pos (5U)
  12199. #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
  12200. #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
  12201. #define I2C_SR2_SMBHOST_Pos (6U)
  12202. #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
  12203. #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
  12204. #define I2C_SR2_DUALF_Pos (7U)
  12205. #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
  12206. #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
  12207. #define I2C_SR2_PEC_Pos (8U)
  12208. #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
  12209. #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
  12210. /******************* Bit definition for I2C_CCR register ********************/
  12211. #define I2C_CCR_CCR_Pos (0U)
  12212. #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
  12213. #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
  12214. #define I2C_CCR_DUTY_Pos (14U)
  12215. #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
  12216. #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
  12217. #define I2C_CCR_FS_Pos (15U)
  12218. #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
  12219. #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
  12220. /****************** Bit definition for I2C_TRISE register *******************/
  12221. #define I2C_TRISE_TRISE_Pos (0U)
  12222. #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
  12223. #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
  12224. /****************** Bit definition for I2C_FLTR register *******************/
  12225. #define I2C_FLTR_DNF_Pos (0U)
  12226. #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
  12227. #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
  12228. #define I2C_FLTR_ANOFF_Pos (4U)
  12229. #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
  12230. #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
  12231. /******************************************************************************/
  12232. /* */
  12233. /* Independent WATCHDOG */
  12234. /* */
  12235. /******************************************************************************/
  12236. /******************* Bit definition for IWDG_KR register ********************/
  12237. #define IWDG_KR_KEY_Pos (0U)
  12238. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  12239. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  12240. /******************* Bit definition for IWDG_PR register ********************/
  12241. #define IWDG_PR_PR_Pos (0U)
  12242. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  12243. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  12244. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
  12245. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
  12246. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
  12247. /******************* Bit definition for IWDG_RLR register *******************/
  12248. #define IWDG_RLR_RL_Pos (0U)
  12249. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  12250. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  12251. /******************* Bit definition for IWDG_SR register ********************/
  12252. #define IWDG_SR_PVU_Pos (0U)
  12253. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  12254. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
  12255. #define IWDG_SR_RVU_Pos (1U)
  12256. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  12257. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
  12258. /******************************************************************************/
  12259. /* */
  12260. /* LCD-TFT Display Controller (LTDC) */
  12261. /* */
  12262. /******************************************************************************/
  12263. /******************** Bit definition for LTDC_SSCR register *****************/
  12264. #define LTDC_SSCR_VSH_Pos (0U)
  12265. #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
  12266. #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
  12267. #define LTDC_SSCR_HSW_Pos (16U)
  12268. #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
  12269. #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
  12270. /******************** Bit definition for LTDC_BPCR register *****************/
  12271. #define LTDC_BPCR_AVBP_Pos (0U)
  12272. #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
  12273. #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
  12274. #define LTDC_BPCR_AHBP_Pos (16U)
  12275. #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
  12276. #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
  12277. /******************** Bit definition for LTDC_AWCR register *****************/
  12278. #define LTDC_AWCR_AAH_Pos (0U)
  12279. #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
  12280. #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
  12281. #define LTDC_AWCR_AAW_Pos (16U)
  12282. #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
  12283. #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
  12284. /******************** Bit definition for LTDC_TWCR register *****************/
  12285. #define LTDC_TWCR_TOTALH_Pos (0U)
  12286. #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
  12287. #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
  12288. #define LTDC_TWCR_TOTALW_Pos (16U)
  12289. #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
  12290. #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
  12291. /******************** Bit definition for LTDC_GCR register ******************/
  12292. #define LTDC_GCR_LTDCEN_Pos (0U)
  12293. #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
  12294. #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
  12295. #define LTDC_GCR_DBW_Pos (4U)
  12296. #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
  12297. #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
  12298. #define LTDC_GCR_DGW_Pos (8U)
  12299. #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
  12300. #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
  12301. #define LTDC_GCR_DRW_Pos (12U)
  12302. #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
  12303. #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
  12304. #define LTDC_GCR_DEN_Pos (16U)
  12305. #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
  12306. #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
  12307. #define LTDC_GCR_PCPOL_Pos (28U)
  12308. #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
  12309. #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
  12310. #define LTDC_GCR_DEPOL_Pos (29U)
  12311. #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
  12312. #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
  12313. #define LTDC_GCR_VSPOL_Pos (30U)
  12314. #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
  12315. #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
  12316. #define LTDC_GCR_HSPOL_Pos (31U)
  12317. #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
  12318. #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
  12319. /* Legacy defines */
  12320. #define LTDC_GCR_DTEN LTDC_GCR_DEN
  12321. /******************** Bit definition for LTDC_SRCR register *****************/
  12322. #define LTDC_SRCR_IMR_Pos (0U)
  12323. #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
  12324. #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
  12325. #define LTDC_SRCR_VBR_Pos (1U)
  12326. #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
  12327. #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
  12328. /******************** Bit definition for LTDC_BCCR register *****************/
  12329. #define LTDC_BCCR_BCBLUE_Pos (0U)
  12330. #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
  12331. #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
  12332. #define LTDC_BCCR_BCGREEN_Pos (8U)
  12333. #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
  12334. #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
  12335. #define LTDC_BCCR_BCRED_Pos (16U)
  12336. #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
  12337. #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
  12338. /******************** Bit definition for LTDC_IER register ******************/
  12339. #define LTDC_IER_LIE_Pos (0U)
  12340. #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
  12341. #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
  12342. #define LTDC_IER_FUIE_Pos (1U)
  12343. #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
  12344. #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
  12345. #define LTDC_IER_TERRIE_Pos (2U)
  12346. #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
  12347. #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
  12348. #define LTDC_IER_RRIE_Pos (3U)
  12349. #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
  12350. #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
  12351. /******************** Bit definition for LTDC_ISR register ******************/
  12352. #define LTDC_ISR_LIF_Pos (0U)
  12353. #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
  12354. #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
  12355. #define LTDC_ISR_FUIF_Pos (1U)
  12356. #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
  12357. #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
  12358. #define LTDC_ISR_TERRIF_Pos (2U)
  12359. #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
  12360. #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
  12361. #define LTDC_ISR_RRIF_Pos (3U)
  12362. #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
  12363. #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
  12364. /******************** Bit definition for LTDC_ICR register ******************/
  12365. #define LTDC_ICR_CLIF_Pos (0U)
  12366. #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
  12367. #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
  12368. #define LTDC_ICR_CFUIF_Pos (1U)
  12369. #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
  12370. #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
  12371. #define LTDC_ICR_CTERRIF_Pos (2U)
  12372. #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
  12373. #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
  12374. #define LTDC_ICR_CRRIF_Pos (3U)
  12375. #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
  12376. #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
  12377. /******************** Bit definition for LTDC_LIPCR register ****************/
  12378. #define LTDC_LIPCR_LIPOS_Pos (0U)
  12379. #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
  12380. #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
  12381. /******************** Bit definition for LTDC_CPSR register *****************/
  12382. #define LTDC_CPSR_CYPOS_Pos (0U)
  12383. #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
  12384. #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
  12385. #define LTDC_CPSR_CXPOS_Pos (16U)
  12386. #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
  12387. #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
  12388. /******************** Bit definition for LTDC_CDSR register *****************/
  12389. #define LTDC_CDSR_VDES_Pos (0U)
  12390. #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
  12391. #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
  12392. #define LTDC_CDSR_HDES_Pos (1U)
  12393. #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
  12394. #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
  12395. #define LTDC_CDSR_VSYNCS_Pos (2U)
  12396. #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
  12397. #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
  12398. #define LTDC_CDSR_HSYNCS_Pos (3U)
  12399. #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
  12400. #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
  12401. /******************** Bit definition for LTDC_LxCR register *****************/
  12402. #define LTDC_LxCR_LEN_Pos (0U)
  12403. #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
  12404. #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
  12405. #define LTDC_LxCR_COLKEN_Pos (1U)
  12406. #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
  12407. #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
  12408. #define LTDC_LxCR_CLUTEN_Pos (4U)
  12409. #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
  12410. #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
  12411. /******************** Bit definition for LTDC_LxWHPCR register **************/
  12412. #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
  12413. #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
  12414. #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
  12415. #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
  12416. #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
  12417. #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
  12418. /******************** Bit definition for LTDC_LxWVPCR register **************/
  12419. #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
  12420. #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
  12421. #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
  12422. #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
  12423. #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
  12424. #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
  12425. /******************** Bit definition for LTDC_LxCKCR register ***************/
  12426. #define LTDC_LxCKCR_CKBLUE_Pos (0U)
  12427. #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
  12428. #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
  12429. #define LTDC_LxCKCR_CKGREEN_Pos (8U)
  12430. #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
  12431. #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
  12432. #define LTDC_LxCKCR_CKRED_Pos (16U)
  12433. #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
  12434. #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
  12435. /******************** Bit definition for LTDC_LxPFCR register ***************/
  12436. #define LTDC_LxPFCR_PF_Pos (0U)
  12437. #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
  12438. #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
  12439. /******************** Bit definition for LTDC_LxCACR register ***************/
  12440. #define LTDC_LxCACR_CONSTA_Pos (0U)
  12441. #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
  12442. #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
  12443. /******************** Bit definition for LTDC_LxDCCR register ***************/
  12444. #define LTDC_LxDCCR_DCBLUE_Pos (0U)
  12445. #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
  12446. #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
  12447. #define LTDC_LxDCCR_DCGREEN_Pos (8U)
  12448. #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
  12449. #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
  12450. #define LTDC_LxDCCR_DCRED_Pos (16U)
  12451. #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
  12452. #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
  12453. #define LTDC_LxDCCR_DCALPHA_Pos (24U)
  12454. #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
  12455. #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
  12456. /******************** Bit definition for LTDC_LxBFCR register ***************/
  12457. #define LTDC_LxBFCR_BF2_Pos (0U)
  12458. #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
  12459. #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
  12460. #define LTDC_LxBFCR_BF1_Pos (8U)
  12461. #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
  12462. #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
  12463. /******************** Bit definition for LTDC_LxCFBAR register **************/
  12464. #define LTDC_LxCFBAR_CFBADD_Pos (0U)
  12465. #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
  12466. #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
  12467. /******************** Bit definition for LTDC_LxCFBLR register **************/
  12468. #define LTDC_LxCFBLR_CFBLL_Pos (0U)
  12469. #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
  12470. #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
  12471. #define LTDC_LxCFBLR_CFBP_Pos (16U)
  12472. #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
  12473. #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
  12474. /******************** Bit definition for LTDC_LxCFBLNR register *************/
  12475. #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
  12476. #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
  12477. #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
  12478. /******************** Bit definition for LTDC_LxCLUTWR register *************/
  12479. #define LTDC_LxCLUTWR_BLUE_Pos (0U)
  12480. #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
  12481. #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
  12482. #define LTDC_LxCLUTWR_GREEN_Pos (8U)
  12483. #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
  12484. #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
  12485. #define LTDC_LxCLUTWR_RED_Pos (16U)
  12486. #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
  12487. #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
  12488. #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
  12489. #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
  12490. #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
  12491. /******************************************************************************/
  12492. /* */
  12493. /* Power Control */
  12494. /* */
  12495. /******************************************************************************/
  12496. /******************** Bit definition for PWR_CR register ********************/
  12497. #define PWR_CR_LPDS_Pos (0U)
  12498. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  12499. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  12500. #define PWR_CR_PDDS_Pos (1U)
  12501. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  12502. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  12503. #define PWR_CR_CWUF_Pos (2U)
  12504. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  12505. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  12506. #define PWR_CR_CSBF_Pos (3U)
  12507. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  12508. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  12509. #define PWR_CR_PVDE_Pos (4U)
  12510. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  12511. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  12512. #define PWR_CR_PLS_Pos (5U)
  12513. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  12514. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  12515. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  12516. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  12517. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  12518. /*!< PVD level configuration */
  12519. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
  12520. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
  12521. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
  12522. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
  12523. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
  12524. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
  12525. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
  12526. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
  12527. #define PWR_CR_DBP_Pos (8U)
  12528. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  12529. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  12530. #define PWR_CR_FPDS_Pos (9U)
  12531. #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
  12532. #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
  12533. #define PWR_CR_LPLVDS_Pos (10U)
  12534. #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
  12535. #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
  12536. #define PWR_CR_MRLVDS_Pos (11U)
  12537. #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
  12538. #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
  12539. #define PWR_CR_ADCDC1_Pos (13U)
  12540. #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
  12541. #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
  12542. #define PWR_CR_VOS_Pos (14U)
  12543. #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
  12544. #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  12545. #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
  12546. #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
  12547. #define PWR_CR_ODEN_Pos (16U)
  12548. #define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
  12549. #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
  12550. #define PWR_CR_ODSWEN_Pos (17U)
  12551. #define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
  12552. #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
  12553. #define PWR_CR_UDEN_Pos (18U)
  12554. #define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
  12555. #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
  12556. #define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
  12557. #define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
  12558. /* Legacy define */
  12559. #define PWR_CR_PMODE PWR_CR_VOS
  12560. #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
  12561. #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
  12562. /******************* Bit definition for PWR_CSR register ********************/
  12563. #define PWR_CSR_WUF_Pos (0U)
  12564. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  12565. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  12566. #define PWR_CSR_SBF_Pos (1U)
  12567. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  12568. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  12569. #define PWR_CSR_PVDO_Pos (2U)
  12570. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  12571. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  12572. #define PWR_CSR_BRR_Pos (3U)
  12573. #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
  12574. #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
  12575. #define PWR_CSR_EWUP_Pos (8U)
  12576. #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
  12577. #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
  12578. #define PWR_CSR_BRE_Pos (9U)
  12579. #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
  12580. #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
  12581. #define PWR_CSR_VOSRDY_Pos (14U)
  12582. #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
  12583. #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
  12584. #define PWR_CSR_ODRDY_Pos (16U)
  12585. #define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
  12586. #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
  12587. #define PWR_CSR_ODSWRDY_Pos (17U)
  12588. #define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
  12589. #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
  12590. #define PWR_CSR_UDRDY_Pos (18U)
  12591. #define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
  12592. #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
  12593. /* Legacy define */
  12594. #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
  12595. /* Legacy define */
  12596. #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
  12597. /******************************************************************************/
  12598. /* */
  12599. /* QUADSPI */
  12600. /* */
  12601. /******************************************************************************/
  12602. /***************** Bit definition for QUADSPI_CR register *******************/
  12603. #define QUADSPI_CR_EN_Pos (0U)
  12604. #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
  12605. #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
  12606. #define QUADSPI_CR_ABORT_Pos (1U)
  12607. #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
  12608. #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
  12609. #define QUADSPI_CR_DMAEN_Pos (2U)
  12610. #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
  12611. #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
  12612. #define QUADSPI_CR_TCEN_Pos (3U)
  12613. #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
  12614. #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
  12615. #define QUADSPI_CR_SSHIFT_Pos (4U)
  12616. #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
  12617. #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
  12618. #define QUADSPI_CR_DFM_Pos (6U)
  12619. #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
  12620. #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
  12621. #define QUADSPI_CR_FSEL_Pos (7U)
  12622. #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
  12623. #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
  12624. #define QUADSPI_CR_FTHRES_Pos (8U)
  12625. #define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
  12626. #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
  12627. #define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
  12628. #define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
  12629. #define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
  12630. #define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
  12631. #define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
  12632. #define QUADSPI_CR_TEIE_Pos (16U)
  12633. #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
  12634. #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
  12635. #define QUADSPI_CR_TCIE_Pos (17U)
  12636. #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
  12637. #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
  12638. #define QUADSPI_CR_FTIE_Pos (18U)
  12639. #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
  12640. #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
  12641. #define QUADSPI_CR_SMIE_Pos (19U)
  12642. #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
  12643. #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
  12644. #define QUADSPI_CR_TOIE_Pos (20U)
  12645. #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
  12646. #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
  12647. #define QUADSPI_CR_APMS_Pos (22U)
  12648. #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
  12649. #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
  12650. #define QUADSPI_CR_PMM_Pos (23U)
  12651. #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
  12652. #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
  12653. #define QUADSPI_CR_PRESCALER_Pos (24U)
  12654. #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
  12655. #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
  12656. #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
  12657. #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
  12658. #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
  12659. #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
  12660. #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
  12661. #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
  12662. #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
  12663. #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
  12664. /***************** Bit definition for QUADSPI_DCR register ******************/
  12665. #define QUADSPI_DCR_CKMODE_Pos (0U)
  12666. #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
  12667. #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
  12668. #define QUADSPI_DCR_CSHT_Pos (8U)
  12669. #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
  12670. #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
  12671. #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
  12672. #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
  12673. #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
  12674. #define QUADSPI_DCR_FSIZE_Pos (16U)
  12675. #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
  12676. #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
  12677. #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
  12678. #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
  12679. #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
  12680. #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
  12681. #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
  12682. /****************** Bit definition for QUADSPI_SR register *******************/
  12683. #define QUADSPI_SR_TEF_Pos (0U)
  12684. #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
  12685. #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
  12686. #define QUADSPI_SR_TCF_Pos (1U)
  12687. #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
  12688. #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
  12689. #define QUADSPI_SR_FTF_Pos (2U)
  12690. #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
  12691. #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
  12692. #define QUADSPI_SR_SMF_Pos (3U)
  12693. #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
  12694. #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
  12695. #define QUADSPI_SR_TOF_Pos (4U)
  12696. #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
  12697. #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
  12698. #define QUADSPI_SR_BUSY_Pos (5U)
  12699. #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
  12700. #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
  12701. #define QUADSPI_SR_FLEVEL_Pos (8U)
  12702. #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
  12703. #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
  12704. #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
  12705. #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
  12706. #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
  12707. #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
  12708. #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
  12709. #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
  12710. /****************** Bit definition for QUADSPI_FCR register ******************/
  12711. #define QUADSPI_FCR_CTEF_Pos (0U)
  12712. #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
  12713. #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
  12714. #define QUADSPI_FCR_CTCF_Pos (1U)
  12715. #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
  12716. #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
  12717. #define QUADSPI_FCR_CSMF_Pos (3U)
  12718. #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
  12719. #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
  12720. #define QUADSPI_FCR_CTOF_Pos (4U)
  12721. #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
  12722. #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
  12723. /****************** Bit definition for QUADSPI_DLR register ******************/
  12724. #define QUADSPI_DLR_DL_Pos (0U)
  12725. #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
  12726. #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
  12727. /****************** Bit definition for QUADSPI_CCR register ******************/
  12728. #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
  12729. #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
  12730. #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
  12731. #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
  12732. #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
  12733. #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
  12734. #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
  12735. #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
  12736. #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
  12737. #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
  12738. #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
  12739. #define QUADSPI_CCR_IMODE_Pos (8U)
  12740. #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
  12741. #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
  12742. #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
  12743. #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
  12744. #define QUADSPI_CCR_ADMODE_Pos (10U)
  12745. #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
  12746. #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
  12747. #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
  12748. #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
  12749. #define QUADSPI_CCR_ADSIZE_Pos (12U)
  12750. #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
  12751. #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
  12752. #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
  12753. #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
  12754. #define QUADSPI_CCR_ABMODE_Pos (14U)
  12755. #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
  12756. #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
  12757. #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
  12758. #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
  12759. #define QUADSPI_CCR_ABSIZE_Pos (16U)
  12760. #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
  12761. #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
  12762. #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
  12763. #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
  12764. #define QUADSPI_CCR_DCYC_Pos (18U)
  12765. #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
  12766. #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
  12767. #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
  12768. #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
  12769. #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
  12770. #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
  12771. #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
  12772. #define QUADSPI_CCR_DMODE_Pos (24U)
  12773. #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
  12774. #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
  12775. #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
  12776. #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
  12777. #define QUADSPI_CCR_FMODE_Pos (26U)
  12778. #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
  12779. #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
  12780. #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
  12781. #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
  12782. #define QUADSPI_CCR_SIOO_Pos (28U)
  12783. #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
  12784. #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
  12785. #define QUADSPI_CCR_DHHC_Pos (30U)
  12786. #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
  12787. #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
  12788. #define QUADSPI_CCR_DDRM_Pos (31U)
  12789. #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
  12790. #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
  12791. /****************** Bit definition for QUADSPI_AR register *******************/
  12792. #define QUADSPI_AR_ADDRESS_Pos (0U)
  12793. #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
  12794. #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
  12795. /****************** Bit definition for QUADSPI_ABR register ******************/
  12796. #define QUADSPI_ABR_ALTERNATE_Pos (0U)
  12797. #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
  12798. #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
  12799. /****************** Bit definition for QUADSPI_DR register *******************/
  12800. #define QUADSPI_DR_DATA_Pos (0U)
  12801. #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
  12802. #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
  12803. /****************** Bit definition for QUADSPI_PSMKR register ****************/
  12804. #define QUADSPI_PSMKR_MASK_Pos (0U)
  12805. #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
  12806. #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
  12807. /****************** Bit definition for QUADSPI_PSMAR register ****************/
  12808. #define QUADSPI_PSMAR_MATCH_Pos (0U)
  12809. #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
  12810. #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
  12811. /****************** Bit definition for QUADSPI_PIR register *****************/
  12812. #define QUADSPI_PIR_INTERVAL_Pos (0U)
  12813. #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
  12814. #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
  12815. /****************** Bit definition for QUADSPI_LPTR register *****************/
  12816. #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
  12817. #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
  12818. #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
  12819. /******************************************************************************/
  12820. /* */
  12821. /* Reset and Clock Control */
  12822. /* */
  12823. /******************************************************************************/
  12824. /******************** Bit definition for RCC_CR register ********************/
  12825. #define RCC_CR_HSION_Pos (0U)
  12826. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  12827. #define RCC_CR_HSION RCC_CR_HSION_Msk
  12828. #define RCC_CR_HSIRDY_Pos (1U)
  12829. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  12830. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
  12831. #define RCC_CR_HSITRIM_Pos (3U)
  12832. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  12833. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
  12834. #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  12835. #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  12836. #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  12837. #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  12838. #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  12839. #define RCC_CR_HSICAL_Pos (8U)
  12840. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  12841. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
  12842. #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  12843. #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  12844. #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  12845. #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  12846. #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  12847. #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  12848. #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  12849. #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  12850. #define RCC_CR_HSEON_Pos (16U)
  12851. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  12852. #define RCC_CR_HSEON RCC_CR_HSEON_Msk
  12853. #define RCC_CR_HSERDY_Pos (17U)
  12854. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  12855. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
  12856. #define RCC_CR_HSEBYP_Pos (18U)
  12857. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  12858. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
  12859. #define RCC_CR_CSSON_Pos (19U)
  12860. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  12861. #define RCC_CR_CSSON RCC_CR_CSSON_Msk
  12862. #define RCC_CR_PLLON_Pos (24U)
  12863. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  12864. #define RCC_CR_PLLON RCC_CR_PLLON_Msk
  12865. #define RCC_CR_PLLRDY_Pos (25U)
  12866. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  12867. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
  12868. /*
  12869. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  12870. */
  12871. #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
  12872. #define RCC_CR_PLLI2SON_Pos (26U)
  12873. #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
  12874. #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
  12875. #define RCC_CR_PLLI2SRDY_Pos (27U)
  12876. #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
  12877. #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
  12878. /*
  12879. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  12880. */
  12881. #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
  12882. #define RCC_CR_PLLSAION_Pos (28U)
  12883. #define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
  12884. #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
  12885. #define RCC_CR_PLLSAIRDY_Pos (29U)
  12886. #define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
  12887. #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
  12888. /******************** Bit definition for RCC_PLLCFGR register ***************/
  12889. #define RCC_PLLCFGR_PLLM_Pos (0U)
  12890. #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
  12891. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  12892. #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
  12893. #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
  12894. #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
  12895. #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
  12896. #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  12897. #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  12898. #define RCC_PLLCFGR_PLLN_Pos (6U)
  12899. #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
  12900. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  12901. #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
  12902. #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
  12903. #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  12904. #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  12905. #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  12906. #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  12907. #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  12908. #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  12909. #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  12910. #define RCC_PLLCFGR_PLLP_Pos (16U)
  12911. #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
  12912. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  12913. #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
  12914. #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  12915. #define RCC_PLLCFGR_PLLSRC_Pos (22U)
  12916. #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
  12917. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  12918. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
  12919. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
  12920. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
  12921. #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
  12922. #define RCC_PLLCFGR_PLLQ_Pos (24U)
  12923. #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
  12924. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  12925. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
  12926. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  12927. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  12928. #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  12929. #define RCC_PLLCFGR_PLLR_Pos (28U)
  12930. #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
  12931. #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
  12932. #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
  12933. #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
  12934. #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
  12935. /******************** Bit definition for RCC_CFGR register ******************/
  12936. /*!< SW configuration */
  12937. #define RCC_CFGR_SW_Pos (0U)
  12938. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  12939. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  12940. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  12941. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  12942. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  12943. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  12944. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  12945. /*!< SWS configuration */
  12946. #define RCC_CFGR_SWS_Pos (2U)
  12947. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  12948. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  12949. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  12950. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  12951. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  12952. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  12953. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  12954. /*!< HPRE configuration */
  12955. #define RCC_CFGR_HPRE_Pos (4U)
  12956. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  12957. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  12958. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  12959. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  12960. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  12961. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  12962. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  12963. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  12964. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  12965. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  12966. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  12967. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  12968. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  12969. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  12970. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  12971. /*!< PPRE1 configuration */
  12972. #define RCC_CFGR_PPRE1_Pos (10U)
  12973. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
  12974. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  12975. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  12976. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
  12977. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
  12978. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  12979. #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
  12980. #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
  12981. #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
  12982. #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
  12983. /*!< PPRE2 configuration */
  12984. #define RCC_CFGR_PPRE2_Pos (13U)
  12985. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
  12986. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  12987. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  12988. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
  12989. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
  12990. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  12991. #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
  12992. #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
  12993. #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
  12994. #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
  12995. /*!< RTCPRE configuration */
  12996. #define RCC_CFGR_RTCPRE_Pos (16U)
  12997. #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
  12998. #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
  12999. #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
  13000. #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
  13001. #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
  13002. #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
  13003. #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
  13004. /*!< MCO1 configuration */
  13005. #define RCC_CFGR_MCO1_Pos (21U)
  13006. #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
  13007. #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
  13008. #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
  13009. #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
  13010. #define RCC_CFGR_I2SSRC_Pos (23U)
  13011. #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
  13012. #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
  13013. #define RCC_CFGR_MCO1PRE_Pos (24U)
  13014. #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
  13015. #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
  13016. #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
  13017. #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
  13018. #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
  13019. #define RCC_CFGR_MCO2PRE_Pos (27U)
  13020. #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
  13021. #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
  13022. #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
  13023. #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
  13024. #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
  13025. #define RCC_CFGR_MCO2_Pos (30U)
  13026. #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
  13027. #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
  13028. #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
  13029. #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
  13030. /******************** Bit definition for RCC_CIR register *******************/
  13031. #define RCC_CIR_LSIRDYF_Pos (0U)
  13032. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  13033. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
  13034. #define RCC_CIR_LSERDYF_Pos (1U)
  13035. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  13036. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
  13037. #define RCC_CIR_HSIRDYF_Pos (2U)
  13038. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  13039. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
  13040. #define RCC_CIR_HSERDYF_Pos (3U)
  13041. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  13042. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
  13043. #define RCC_CIR_PLLRDYF_Pos (4U)
  13044. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  13045. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
  13046. #define RCC_CIR_PLLI2SRDYF_Pos (5U)
  13047. #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
  13048. #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
  13049. #define RCC_CIR_PLLSAIRDYF_Pos (6U)
  13050. #define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
  13051. #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
  13052. #define RCC_CIR_CSSF_Pos (7U)
  13053. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  13054. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
  13055. #define RCC_CIR_LSIRDYIE_Pos (8U)
  13056. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  13057. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
  13058. #define RCC_CIR_LSERDYIE_Pos (9U)
  13059. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  13060. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
  13061. #define RCC_CIR_HSIRDYIE_Pos (10U)
  13062. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  13063. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
  13064. #define RCC_CIR_HSERDYIE_Pos (11U)
  13065. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  13066. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
  13067. #define RCC_CIR_PLLRDYIE_Pos (12U)
  13068. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  13069. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
  13070. #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
  13071. #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
  13072. #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
  13073. #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
  13074. #define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
  13075. #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
  13076. #define RCC_CIR_LSIRDYC_Pos (16U)
  13077. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  13078. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
  13079. #define RCC_CIR_LSERDYC_Pos (17U)
  13080. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  13081. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
  13082. #define RCC_CIR_HSIRDYC_Pos (18U)
  13083. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  13084. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
  13085. #define RCC_CIR_HSERDYC_Pos (19U)
  13086. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  13087. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
  13088. #define RCC_CIR_PLLRDYC_Pos (20U)
  13089. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  13090. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
  13091. #define RCC_CIR_PLLI2SRDYC_Pos (21U)
  13092. #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
  13093. #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
  13094. #define RCC_CIR_PLLSAIRDYC_Pos (22U)
  13095. #define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
  13096. #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
  13097. #define RCC_CIR_CSSC_Pos (23U)
  13098. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  13099. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
  13100. /******************** Bit definition for RCC_AHB1RSTR register **************/
  13101. #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
  13102. #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  13103. #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
  13104. #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
  13105. #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  13106. #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
  13107. #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
  13108. #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  13109. #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
  13110. #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
  13111. #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
  13112. #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
  13113. #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
  13114. #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
  13115. #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
  13116. #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
  13117. #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
  13118. #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
  13119. #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
  13120. #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
  13121. #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
  13122. #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
  13123. #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  13124. #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
  13125. #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
  13126. #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
  13127. #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
  13128. #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
  13129. #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
  13130. #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
  13131. #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
  13132. #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
  13133. #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
  13134. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  13135. #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  13136. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  13137. #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
  13138. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
  13139. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  13140. #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
  13141. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
  13142. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  13143. #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
  13144. #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
  13145. #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
  13146. #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
  13147. #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
  13148. #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
  13149. #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
  13150. #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
  13151. #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
  13152. /******************** Bit definition for RCC_AHB2RSTR register **************/
  13153. #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
  13154. #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
  13155. #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
  13156. #define RCC_AHB2RSTR_RNGRST_Pos (6U)
  13157. #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
  13158. #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
  13159. #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
  13160. #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
  13161. #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
  13162. /******************** Bit definition for RCC_AHB3RSTR register **************/
  13163. #define RCC_AHB3RSTR_FMCRST_Pos (0U)
  13164. #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
  13165. #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
  13166. #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
  13167. #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
  13168. #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
  13169. /******************** Bit definition for RCC_APB1RSTR register **************/
  13170. #define RCC_APB1RSTR_TIM2RST_Pos (0U)
  13171. #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
  13172. #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
  13173. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  13174. #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  13175. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
  13176. #define RCC_APB1RSTR_TIM4RST_Pos (2U)
  13177. #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
  13178. #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
  13179. #define RCC_APB1RSTR_TIM5RST_Pos (3U)
  13180. #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
  13181. #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
  13182. #define RCC_APB1RSTR_TIM6RST_Pos (4U)
  13183. #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
  13184. #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
  13185. #define RCC_APB1RSTR_TIM7RST_Pos (5U)
  13186. #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
  13187. #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
  13188. #define RCC_APB1RSTR_TIM12RST_Pos (6U)
  13189. #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
  13190. #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
  13191. #define RCC_APB1RSTR_TIM13RST_Pos (7U)
  13192. #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
  13193. #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
  13194. #define RCC_APB1RSTR_TIM14RST_Pos (8U)
  13195. #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
  13196. #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
  13197. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  13198. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  13199. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
  13200. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  13201. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  13202. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
  13203. #define RCC_APB1RSTR_SPI3RST_Pos (15U)
  13204. #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
  13205. #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
  13206. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  13207. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  13208. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
  13209. #define RCC_APB1RSTR_USART3RST_Pos (18U)
  13210. #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
  13211. #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
  13212. #define RCC_APB1RSTR_UART4RST_Pos (19U)
  13213. #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
  13214. #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
  13215. #define RCC_APB1RSTR_UART5RST_Pos (20U)
  13216. #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
  13217. #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
  13218. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  13219. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  13220. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
  13221. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  13222. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  13223. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
  13224. #define RCC_APB1RSTR_I2C3RST_Pos (23U)
  13225. #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
  13226. #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
  13227. #define RCC_APB1RSTR_CAN1RST_Pos (25U)
  13228. #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
  13229. #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
  13230. #define RCC_APB1RSTR_CAN2RST_Pos (26U)
  13231. #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
  13232. #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
  13233. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  13234. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  13235. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
  13236. #define RCC_APB1RSTR_DACRST_Pos (29U)
  13237. #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
  13238. #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
  13239. #define RCC_APB1RSTR_UART7RST_Pos (30U)
  13240. #define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
  13241. #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
  13242. #define RCC_APB1RSTR_UART8RST_Pos (31U)
  13243. #define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
  13244. #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
  13245. /******************** Bit definition for RCC_APB2RSTR register **************/
  13246. #define RCC_APB2RSTR_TIM1RST_Pos (0U)
  13247. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
  13248. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  13249. #define RCC_APB2RSTR_TIM8RST_Pos (1U)
  13250. #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
  13251. #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
  13252. #define RCC_APB2RSTR_USART1RST_Pos (4U)
  13253. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
  13254. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  13255. #define RCC_APB2RSTR_USART6RST_Pos (5U)
  13256. #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
  13257. #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
  13258. #define RCC_APB2RSTR_ADCRST_Pos (8U)
  13259. #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
  13260. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
  13261. #define RCC_APB2RSTR_SDIORST_Pos (11U)
  13262. #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
  13263. #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
  13264. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  13265. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  13266. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  13267. #define RCC_APB2RSTR_SPI4RST_Pos (13U)
  13268. #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
  13269. #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
  13270. #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
  13271. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
  13272. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  13273. #define RCC_APB2RSTR_TIM9RST_Pos (16U)
  13274. #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
  13275. #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
  13276. #define RCC_APB2RSTR_TIM10RST_Pos (17U)
  13277. #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
  13278. #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
  13279. #define RCC_APB2RSTR_TIM11RST_Pos (18U)
  13280. #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
  13281. #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
  13282. #define RCC_APB2RSTR_SPI5RST_Pos (20U)
  13283. #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
  13284. #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
  13285. #define RCC_APB2RSTR_SPI6RST_Pos (21U)
  13286. #define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
  13287. #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
  13288. #define RCC_APB2RSTR_SAI1RST_Pos (22U)
  13289. #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
  13290. #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
  13291. #define RCC_APB2RSTR_LTDCRST_Pos (26U)
  13292. #define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
  13293. #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
  13294. #define RCC_APB2RSTR_DSIRST_Pos (27U)
  13295. #define RCC_APB2RSTR_DSIRST_Msk (0x1UL << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
  13296. #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
  13297. /* Old SPI1RST bit definition, maintained for legacy purpose */
  13298. #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
  13299. /******************** Bit definition for RCC_AHB1ENR register ***************/
  13300. #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
  13301. #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  13302. #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
  13303. #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
  13304. #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  13305. #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
  13306. #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
  13307. #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  13308. #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
  13309. #define RCC_AHB1ENR_GPIODEN_Pos (3U)
  13310. #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
  13311. #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
  13312. #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
  13313. #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
  13314. #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
  13315. #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
  13316. #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
  13317. #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
  13318. #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
  13319. #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
  13320. #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
  13321. #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
  13322. #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  13323. #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
  13324. #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
  13325. #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
  13326. #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
  13327. #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
  13328. #define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
  13329. #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
  13330. #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
  13331. #define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
  13332. #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
  13333. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  13334. #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  13335. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  13336. #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
  13337. #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
  13338. #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
  13339. #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
  13340. #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
  13341. #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
  13342. #define RCC_AHB1ENR_DMA1EN_Pos (21U)
  13343. #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
  13344. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  13345. #define RCC_AHB1ENR_DMA2EN_Pos (22U)
  13346. #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
  13347. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  13348. #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
  13349. #define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
  13350. #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
  13351. #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
  13352. #define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
  13353. #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
  13354. #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
  13355. #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
  13356. #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
  13357. #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
  13358. #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
  13359. #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
  13360. #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
  13361. #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
  13362. #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
  13363. #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
  13364. #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
  13365. #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
  13366. #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
  13367. #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
  13368. #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
  13369. /******************** Bit definition for RCC_AHB2ENR register ***************/
  13370. /*
  13371. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  13372. */
  13373. #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
  13374. #define RCC_AHB2ENR_DCMIEN_Pos (0U)
  13375. #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
  13376. #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
  13377. #define RCC_AHB2ENR_RNGEN_Pos (6U)
  13378. #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
  13379. #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
  13380. #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
  13381. #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
  13382. #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
  13383. /******************** Bit definition for RCC_AHB3ENR register ***************/
  13384. /*
  13385. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  13386. */
  13387. #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
  13388. #define RCC_AHB3ENR_FMCEN_Pos (0U)
  13389. #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
  13390. #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
  13391. #define RCC_AHB3ENR_QSPIEN_Pos (1U)
  13392. #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
  13393. #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
  13394. /******************** Bit definition for RCC_APB1ENR register ***************/
  13395. #define RCC_APB1ENR_TIM2EN_Pos (0U)
  13396. #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
  13397. #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
  13398. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  13399. #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  13400. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
  13401. #define RCC_APB1ENR_TIM4EN_Pos (2U)
  13402. #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
  13403. #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
  13404. #define RCC_APB1ENR_TIM5EN_Pos (3U)
  13405. #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
  13406. #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
  13407. #define RCC_APB1ENR_TIM6EN_Pos (4U)
  13408. #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
  13409. #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
  13410. #define RCC_APB1ENR_TIM7EN_Pos (5U)
  13411. #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
  13412. #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
  13413. #define RCC_APB1ENR_TIM12EN_Pos (6U)
  13414. #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
  13415. #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
  13416. #define RCC_APB1ENR_TIM13EN_Pos (7U)
  13417. #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
  13418. #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
  13419. #define RCC_APB1ENR_TIM14EN_Pos (8U)
  13420. #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
  13421. #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
  13422. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  13423. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  13424. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
  13425. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  13426. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  13427. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
  13428. #define RCC_APB1ENR_SPI3EN_Pos (15U)
  13429. #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
  13430. #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
  13431. #define RCC_APB1ENR_USART2EN_Pos (17U)
  13432. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  13433. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
  13434. #define RCC_APB1ENR_USART3EN_Pos (18U)
  13435. #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
  13436. #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
  13437. #define RCC_APB1ENR_UART4EN_Pos (19U)
  13438. #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
  13439. #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
  13440. #define RCC_APB1ENR_UART5EN_Pos (20U)
  13441. #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
  13442. #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
  13443. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  13444. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  13445. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
  13446. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  13447. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  13448. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
  13449. #define RCC_APB1ENR_I2C3EN_Pos (23U)
  13450. #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
  13451. #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
  13452. #define RCC_APB1ENR_CAN1EN_Pos (25U)
  13453. #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
  13454. #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
  13455. #define RCC_APB1ENR_CAN2EN_Pos (26U)
  13456. #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
  13457. #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
  13458. #define RCC_APB1ENR_PWREN_Pos (28U)
  13459. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  13460. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
  13461. #define RCC_APB1ENR_DACEN_Pos (29U)
  13462. #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
  13463. #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
  13464. #define RCC_APB1ENR_UART7EN_Pos (30U)
  13465. #define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
  13466. #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
  13467. #define RCC_APB1ENR_UART8EN_Pos (31U)
  13468. #define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
  13469. #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
  13470. /******************** Bit definition for RCC_APB2ENR register ***************/
  13471. #define RCC_APB2ENR_TIM1EN_Pos (0U)
  13472. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
  13473. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  13474. #define RCC_APB2ENR_TIM8EN_Pos (1U)
  13475. #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
  13476. #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
  13477. #define RCC_APB2ENR_USART1EN_Pos (4U)
  13478. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
  13479. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  13480. #define RCC_APB2ENR_USART6EN_Pos (5U)
  13481. #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
  13482. #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
  13483. #define RCC_APB2ENR_ADC1EN_Pos (8U)
  13484. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
  13485. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
  13486. #define RCC_APB2ENR_ADC2EN_Pos (9U)
  13487. #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
  13488. #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
  13489. #define RCC_APB2ENR_ADC3EN_Pos (10U)
  13490. #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
  13491. #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
  13492. #define RCC_APB2ENR_SDIOEN_Pos (11U)
  13493. #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
  13494. #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
  13495. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  13496. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  13497. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  13498. #define RCC_APB2ENR_SPI4EN_Pos (13U)
  13499. #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
  13500. #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
  13501. #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
  13502. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
  13503. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  13504. #define RCC_APB2ENR_TIM9EN_Pos (16U)
  13505. #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
  13506. #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
  13507. #define RCC_APB2ENR_TIM10EN_Pos (17U)
  13508. #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
  13509. #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
  13510. #define RCC_APB2ENR_TIM11EN_Pos (18U)
  13511. #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
  13512. #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
  13513. #define RCC_APB2ENR_SPI5EN_Pos (20U)
  13514. #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
  13515. #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
  13516. #define RCC_APB2ENR_SPI6EN_Pos (21U)
  13517. #define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
  13518. #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
  13519. #define RCC_APB2ENR_SAI1EN_Pos (22U)
  13520. #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
  13521. #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
  13522. #define RCC_APB2ENR_LTDCEN_Pos (26U)
  13523. #define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
  13524. #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
  13525. #define RCC_APB2ENR_DSIEN_Pos (27U)
  13526. #define RCC_APB2ENR_DSIEN_Msk (0x1UL << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
  13527. #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
  13528. /******************** Bit definition for RCC_AHB1LPENR register *************/
  13529. #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
  13530. #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
  13531. #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
  13532. #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
  13533. #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
  13534. #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
  13535. #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
  13536. #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
  13537. #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
  13538. #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
  13539. #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
  13540. #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
  13541. #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
  13542. #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
  13543. #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
  13544. #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
  13545. #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
  13546. #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
  13547. #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
  13548. #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
  13549. #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
  13550. #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
  13551. #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
  13552. #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
  13553. #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
  13554. #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
  13555. #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
  13556. #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
  13557. #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
  13558. #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
  13559. #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
  13560. #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
  13561. #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
  13562. #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
  13563. #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
  13564. #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
  13565. #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
  13566. #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
  13567. #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
  13568. #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
  13569. #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
  13570. #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
  13571. #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
  13572. #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
  13573. #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
  13574. #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
  13575. #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
  13576. #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
  13577. #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
  13578. #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
  13579. #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
  13580. #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
  13581. #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
  13582. #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
  13583. #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
  13584. #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
  13585. #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
  13586. #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
  13587. #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
  13588. #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
  13589. #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
  13590. #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
  13591. #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
  13592. #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
  13593. #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
  13594. #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
  13595. #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
  13596. #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
  13597. #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
  13598. #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
  13599. #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
  13600. #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
  13601. #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
  13602. #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
  13603. #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
  13604. #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
  13605. #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
  13606. #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
  13607. /******************** Bit definition for RCC_AHB2LPENR register *************/
  13608. #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
  13609. #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
  13610. #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
  13611. #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
  13612. #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
  13613. #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
  13614. #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
  13615. #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
  13616. #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
  13617. /******************** Bit definition for RCC_AHB3LPENR register *************/
  13618. #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
  13619. #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
  13620. #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
  13621. #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
  13622. #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
  13623. #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
  13624. /******************** Bit definition for RCC_APB1LPENR register *************/
  13625. #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
  13626. #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
  13627. #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
  13628. #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
  13629. #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
  13630. #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
  13631. #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
  13632. #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
  13633. #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
  13634. #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
  13635. #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
  13636. #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
  13637. #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
  13638. #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
  13639. #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
  13640. #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
  13641. #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
  13642. #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
  13643. #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
  13644. #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
  13645. #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
  13646. #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
  13647. #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
  13648. #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
  13649. #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
  13650. #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
  13651. #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
  13652. #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
  13653. #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
  13654. #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
  13655. #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
  13656. #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
  13657. #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
  13658. #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
  13659. #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
  13660. #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
  13661. #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
  13662. #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
  13663. #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
  13664. #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
  13665. #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
  13666. #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
  13667. #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
  13668. #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
  13669. #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
  13670. #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
  13671. #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
  13672. #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
  13673. #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
  13674. #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
  13675. #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
  13676. #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
  13677. #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
  13678. #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
  13679. #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
  13680. #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
  13681. #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
  13682. #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
  13683. #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
  13684. #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
  13685. #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
  13686. #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
  13687. #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
  13688. #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
  13689. #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
  13690. #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
  13691. #define RCC_APB1LPENR_DACLPEN_Pos (29U)
  13692. #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
  13693. #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
  13694. #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
  13695. #define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
  13696. #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
  13697. #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
  13698. #define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
  13699. #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
  13700. /******************** Bit definition for RCC_APB2LPENR register *************/
  13701. #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
  13702. #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
  13703. #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
  13704. #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
  13705. #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
  13706. #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
  13707. #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
  13708. #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
  13709. #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
  13710. #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
  13711. #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
  13712. #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
  13713. #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
  13714. #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
  13715. #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
  13716. #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
  13717. #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
  13718. #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
  13719. #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
  13720. #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
  13721. #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
  13722. #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
  13723. #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
  13724. #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
  13725. #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
  13726. #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
  13727. #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
  13728. #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
  13729. #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
  13730. #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
  13731. #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
  13732. #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
  13733. #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
  13734. #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
  13735. #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
  13736. #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
  13737. #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
  13738. #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
  13739. #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
  13740. #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
  13741. #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
  13742. #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
  13743. #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
  13744. #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
  13745. #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
  13746. #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
  13747. #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
  13748. #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
  13749. #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
  13750. #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
  13751. #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
  13752. #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
  13753. #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
  13754. #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
  13755. #define RCC_APB2LPENR_DSILPEN_Pos (27U)
  13756. #define RCC_APB2LPENR_DSILPEN_Msk (0x1UL << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
  13757. #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
  13758. /******************** Bit definition for RCC_BDCR register ******************/
  13759. #define RCC_BDCR_LSEON_Pos (0U)
  13760. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  13761. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  13762. #define RCC_BDCR_LSERDY_Pos (1U)
  13763. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  13764. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  13765. #define RCC_BDCR_LSEBYP_Pos (2U)
  13766. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  13767. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  13768. #define RCC_BDCR_LSEMOD_Pos (3U)
  13769. #define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
  13770. #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
  13771. #define RCC_BDCR_RTCSEL_Pos (8U)
  13772. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  13773. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  13774. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  13775. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  13776. #define RCC_BDCR_RTCEN_Pos (15U)
  13777. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  13778. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  13779. #define RCC_BDCR_BDRST_Pos (16U)
  13780. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  13781. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  13782. /******************** Bit definition for RCC_CSR register *******************/
  13783. #define RCC_CSR_LSION_Pos (0U)
  13784. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  13785. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  13786. #define RCC_CSR_LSIRDY_Pos (1U)
  13787. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  13788. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  13789. #define RCC_CSR_RMVF_Pos (24U)
  13790. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  13791. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  13792. #define RCC_CSR_BORRSTF_Pos (25U)
  13793. #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
  13794. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  13795. #define RCC_CSR_PINRSTF_Pos (26U)
  13796. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  13797. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  13798. #define RCC_CSR_PORRSTF_Pos (27U)
  13799. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  13800. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
  13801. #define RCC_CSR_SFTRSTF_Pos (28U)
  13802. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  13803. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  13804. #define RCC_CSR_IWDGRSTF_Pos (29U)
  13805. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  13806. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  13807. #define RCC_CSR_WWDGRSTF_Pos (30U)
  13808. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  13809. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  13810. #define RCC_CSR_LPWRRSTF_Pos (31U)
  13811. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  13812. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  13813. /* Legacy defines */
  13814. #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
  13815. #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
  13816. /******************** Bit definition for RCC_SSCGR register *****************/
  13817. #define RCC_SSCGR_MODPER_Pos (0U)
  13818. #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
  13819. #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
  13820. #define RCC_SSCGR_INCSTEP_Pos (13U)
  13821. #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
  13822. #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
  13823. #define RCC_SSCGR_SPREADSEL_Pos (30U)
  13824. #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
  13825. #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
  13826. #define RCC_SSCGR_SSCGEN_Pos (31U)
  13827. #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
  13828. #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
  13829. /******************** Bit definition for RCC_PLLI2SCFGR register ************/
  13830. #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
  13831. #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
  13832. #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
  13833. #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
  13834. #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
  13835. #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
  13836. #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
  13837. #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
  13838. #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
  13839. #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
  13840. #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
  13841. #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
  13842. #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
  13843. #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
  13844. #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
  13845. #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
  13846. #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
  13847. #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
  13848. #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
  13849. #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
  13850. #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
  13851. #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
  13852. #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
  13853. #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
  13854. #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
  13855. /******************** Bit definition for RCC_PLLSAICFGR register ************/
  13856. #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
  13857. #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
  13858. #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
  13859. #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
  13860. #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
  13861. #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
  13862. #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
  13863. #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
  13864. #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
  13865. #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
  13866. #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
  13867. #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
  13868. #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
  13869. #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
  13870. #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
  13871. #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
  13872. #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
  13873. #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
  13874. #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
  13875. #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
  13876. #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
  13877. #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
  13878. #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
  13879. #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
  13880. #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
  13881. #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
  13882. #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
  13883. #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
  13884. #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
  13885. #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
  13886. /******************** Bit definition for RCC_DCKCFGR register ***************/
  13887. #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
  13888. #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
  13889. #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
  13890. #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
  13891. #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
  13892. #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
  13893. #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
  13894. #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
  13895. #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
  13896. #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
  13897. #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
  13898. #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
  13899. #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
  13900. #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
  13901. #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
  13902. #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
  13903. #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
  13904. #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
  13905. #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
  13906. #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
  13907. #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
  13908. #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
  13909. #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
  13910. #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
  13911. #define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
  13912. #define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
  13913. #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
  13914. #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
  13915. #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
  13916. #define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
  13917. #define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
  13918. #define RCC_DCKCFGR_TIMPRE_Pos (24U)
  13919. #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
  13920. #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
  13921. #define RCC_DCKCFGR_CK48MSEL_Pos (27U)
  13922. #define RCC_DCKCFGR_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */
  13923. #define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
  13924. #define RCC_DCKCFGR_SDIOSEL_Pos (28U)
  13925. #define RCC_DCKCFGR_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */
  13926. #define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
  13927. #define RCC_DCKCFGR_DSISEL_Pos (29U)
  13928. #define RCC_DCKCFGR_DSISEL_Msk (0x1UL << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */
  13929. #define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
  13930. /******************************************************************************/
  13931. /* */
  13932. /* RNG */
  13933. /* */
  13934. /******************************************************************************/
  13935. /******************** Bits definition for RNG_CR register *******************/
  13936. #define RNG_CR_RNGEN_Pos (2U)
  13937. #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
  13938. #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
  13939. #define RNG_CR_IE_Pos (3U)
  13940. #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
  13941. #define RNG_CR_IE RNG_CR_IE_Msk
  13942. /******************** Bits definition for RNG_SR register *******************/
  13943. #define RNG_SR_DRDY_Pos (0U)
  13944. #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
  13945. #define RNG_SR_DRDY RNG_SR_DRDY_Msk
  13946. #define RNG_SR_CECS_Pos (1U)
  13947. #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
  13948. #define RNG_SR_CECS RNG_SR_CECS_Msk
  13949. #define RNG_SR_SECS_Pos (2U)
  13950. #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
  13951. #define RNG_SR_SECS RNG_SR_SECS_Msk
  13952. #define RNG_SR_CEIS_Pos (5U)
  13953. #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
  13954. #define RNG_SR_CEIS RNG_SR_CEIS_Msk
  13955. #define RNG_SR_SEIS_Pos (6U)
  13956. #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
  13957. #define RNG_SR_SEIS RNG_SR_SEIS_Msk
  13958. /******************************************************************************/
  13959. /* */
  13960. /* Real-Time Clock (RTC) */
  13961. /* */
  13962. /******************************************************************************/
  13963. /*
  13964. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  13965. */
  13966. #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
  13967. #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
  13968. /******************** Bits definition for RTC_TR register *******************/
  13969. #define RTC_TR_PM_Pos (22U)
  13970. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  13971. #define RTC_TR_PM RTC_TR_PM_Msk
  13972. #define RTC_TR_HT_Pos (20U)
  13973. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  13974. #define RTC_TR_HT RTC_TR_HT_Msk
  13975. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  13976. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  13977. #define RTC_TR_HU_Pos (16U)
  13978. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  13979. #define RTC_TR_HU RTC_TR_HU_Msk
  13980. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  13981. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  13982. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  13983. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  13984. #define RTC_TR_MNT_Pos (12U)
  13985. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  13986. #define RTC_TR_MNT RTC_TR_MNT_Msk
  13987. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  13988. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  13989. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  13990. #define RTC_TR_MNU_Pos (8U)
  13991. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  13992. #define RTC_TR_MNU RTC_TR_MNU_Msk
  13993. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  13994. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  13995. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  13996. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  13997. #define RTC_TR_ST_Pos (4U)
  13998. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  13999. #define RTC_TR_ST RTC_TR_ST_Msk
  14000. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  14001. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  14002. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  14003. #define RTC_TR_SU_Pos (0U)
  14004. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  14005. #define RTC_TR_SU RTC_TR_SU_Msk
  14006. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  14007. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  14008. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  14009. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  14010. /******************** Bits definition for RTC_DR register *******************/
  14011. #define RTC_DR_YT_Pos (20U)
  14012. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  14013. #define RTC_DR_YT RTC_DR_YT_Msk
  14014. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  14015. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  14016. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  14017. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  14018. #define RTC_DR_YU_Pos (16U)
  14019. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  14020. #define RTC_DR_YU RTC_DR_YU_Msk
  14021. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  14022. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  14023. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  14024. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  14025. #define RTC_DR_WDU_Pos (13U)
  14026. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  14027. #define RTC_DR_WDU RTC_DR_WDU_Msk
  14028. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  14029. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  14030. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  14031. #define RTC_DR_MT_Pos (12U)
  14032. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  14033. #define RTC_DR_MT RTC_DR_MT_Msk
  14034. #define RTC_DR_MU_Pos (8U)
  14035. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  14036. #define RTC_DR_MU RTC_DR_MU_Msk
  14037. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  14038. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  14039. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  14040. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  14041. #define RTC_DR_DT_Pos (4U)
  14042. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  14043. #define RTC_DR_DT RTC_DR_DT_Msk
  14044. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  14045. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  14046. #define RTC_DR_DU_Pos (0U)
  14047. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  14048. #define RTC_DR_DU RTC_DR_DU_Msk
  14049. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  14050. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  14051. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  14052. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  14053. /******************** Bits definition for RTC_CR register *******************/
  14054. #define RTC_CR_COE_Pos (23U)
  14055. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  14056. #define RTC_CR_COE RTC_CR_COE_Msk
  14057. #define RTC_CR_OSEL_Pos (21U)
  14058. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  14059. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  14060. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  14061. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  14062. #define RTC_CR_POL_Pos (20U)
  14063. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  14064. #define RTC_CR_POL RTC_CR_POL_Msk
  14065. #define RTC_CR_COSEL_Pos (19U)
  14066. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  14067. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  14068. #define RTC_CR_BKP_Pos (18U)
  14069. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  14070. #define RTC_CR_BKP RTC_CR_BKP_Msk
  14071. #define RTC_CR_SUB1H_Pos (17U)
  14072. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  14073. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  14074. #define RTC_CR_ADD1H_Pos (16U)
  14075. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  14076. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  14077. #define RTC_CR_TSIE_Pos (15U)
  14078. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  14079. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  14080. #define RTC_CR_WUTIE_Pos (14U)
  14081. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  14082. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  14083. #define RTC_CR_ALRBIE_Pos (13U)
  14084. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  14085. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  14086. #define RTC_CR_ALRAIE_Pos (12U)
  14087. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  14088. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  14089. #define RTC_CR_TSE_Pos (11U)
  14090. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  14091. #define RTC_CR_TSE RTC_CR_TSE_Msk
  14092. #define RTC_CR_WUTE_Pos (10U)
  14093. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  14094. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  14095. #define RTC_CR_ALRBE_Pos (9U)
  14096. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  14097. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  14098. #define RTC_CR_ALRAE_Pos (8U)
  14099. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  14100. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  14101. #define RTC_CR_DCE_Pos (7U)
  14102. #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */
  14103. #define RTC_CR_DCE RTC_CR_DCE_Msk
  14104. #define RTC_CR_FMT_Pos (6U)
  14105. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  14106. #define RTC_CR_FMT RTC_CR_FMT_Msk
  14107. #define RTC_CR_BYPSHAD_Pos (5U)
  14108. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  14109. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  14110. #define RTC_CR_REFCKON_Pos (4U)
  14111. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  14112. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  14113. #define RTC_CR_TSEDGE_Pos (3U)
  14114. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  14115. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  14116. #define RTC_CR_WUCKSEL_Pos (0U)
  14117. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  14118. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  14119. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  14120. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  14121. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  14122. /* Legacy defines */
  14123. #define RTC_CR_BCK RTC_CR_BKP
  14124. /******************** Bits definition for RTC_ISR register ******************/
  14125. #define RTC_ISR_RECALPF_Pos (16U)
  14126. #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  14127. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  14128. #define RTC_ISR_TAMP1F_Pos (13U)
  14129. #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  14130. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  14131. #define RTC_ISR_TAMP2F_Pos (14U)
  14132. #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  14133. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  14134. #define RTC_ISR_TSOVF_Pos (12U)
  14135. #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  14136. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  14137. #define RTC_ISR_TSF_Pos (11U)
  14138. #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  14139. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  14140. #define RTC_ISR_WUTF_Pos (10U)
  14141. #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  14142. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  14143. #define RTC_ISR_ALRBF_Pos (9U)
  14144. #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  14145. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  14146. #define RTC_ISR_ALRAF_Pos (8U)
  14147. #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  14148. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  14149. #define RTC_ISR_INIT_Pos (7U)
  14150. #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  14151. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  14152. #define RTC_ISR_INITF_Pos (6U)
  14153. #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  14154. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  14155. #define RTC_ISR_RSF_Pos (5U)
  14156. #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  14157. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  14158. #define RTC_ISR_INITS_Pos (4U)
  14159. #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  14160. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  14161. #define RTC_ISR_SHPF_Pos (3U)
  14162. #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  14163. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  14164. #define RTC_ISR_WUTWF_Pos (2U)
  14165. #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  14166. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  14167. #define RTC_ISR_ALRBWF_Pos (1U)
  14168. #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  14169. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  14170. #define RTC_ISR_ALRAWF_Pos (0U)
  14171. #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  14172. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  14173. /******************** Bits definition for RTC_PRER register *****************/
  14174. #define RTC_PRER_PREDIV_A_Pos (16U)
  14175. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  14176. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  14177. #define RTC_PRER_PREDIV_S_Pos (0U)
  14178. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  14179. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  14180. /******************** Bits definition for RTC_WUTR register *****************/
  14181. #define RTC_WUTR_WUT_Pos (0U)
  14182. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  14183. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  14184. /******************** Bits definition for RTC_CALIBR register ***************/
  14185. #define RTC_CALIBR_DCS_Pos (7U)
  14186. #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
  14187. #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
  14188. #define RTC_CALIBR_DC_Pos (0U)
  14189. #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
  14190. #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
  14191. /******************** Bits definition for RTC_ALRMAR register ***************/
  14192. #define RTC_ALRMAR_MSK4_Pos (31U)
  14193. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  14194. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  14195. #define RTC_ALRMAR_WDSEL_Pos (30U)
  14196. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  14197. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  14198. #define RTC_ALRMAR_DT_Pos (28U)
  14199. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  14200. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  14201. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  14202. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  14203. #define RTC_ALRMAR_DU_Pos (24U)
  14204. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  14205. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  14206. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  14207. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  14208. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  14209. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  14210. #define RTC_ALRMAR_MSK3_Pos (23U)
  14211. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  14212. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  14213. #define RTC_ALRMAR_PM_Pos (22U)
  14214. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  14215. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  14216. #define RTC_ALRMAR_HT_Pos (20U)
  14217. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  14218. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  14219. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  14220. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  14221. #define RTC_ALRMAR_HU_Pos (16U)
  14222. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  14223. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  14224. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  14225. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  14226. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  14227. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  14228. #define RTC_ALRMAR_MSK2_Pos (15U)
  14229. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  14230. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  14231. #define RTC_ALRMAR_MNT_Pos (12U)
  14232. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  14233. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  14234. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  14235. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  14236. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  14237. #define RTC_ALRMAR_MNU_Pos (8U)
  14238. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  14239. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  14240. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  14241. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  14242. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  14243. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  14244. #define RTC_ALRMAR_MSK1_Pos (7U)
  14245. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  14246. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  14247. #define RTC_ALRMAR_ST_Pos (4U)
  14248. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  14249. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  14250. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  14251. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  14252. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  14253. #define RTC_ALRMAR_SU_Pos (0U)
  14254. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  14255. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  14256. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  14257. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  14258. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  14259. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  14260. /******************** Bits definition for RTC_ALRMBR register ***************/
  14261. #define RTC_ALRMBR_MSK4_Pos (31U)
  14262. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  14263. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  14264. #define RTC_ALRMBR_WDSEL_Pos (30U)
  14265. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  14266. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  14267. #define RTC_ALRMBR_DT_Pos (28U)
  14268. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  14269. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  14270. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  14271. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  14272. #define RTC_ALRMBR_DU_Pos (24U)
  14273. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  14274. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  14275. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  14276. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  14277. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  14278. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  14279. #define RTC_ALRMBR_MSK3_Pos (23U)
  14280. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  14281. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  14282. #define RTC_ALRMBR_PM_Pos (22U)
  14283. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  14284. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  14285. #define RTC_ALRMBR_HT_Pos (20U)
  14286. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  14287. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  14288. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  14289. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  14290. #define RTC_ALRMBR_HU_Pos (16U)
  14291. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  14292. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  14293. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  14294. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  14295. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  14296. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  14297. #define RTC_ALRMBR_MSK2_Pos (15U)
  14298. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  14299. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  14300. #define RTC_ALRMBR_MNT_Pos (12U)
  14301. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  14302. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  14303. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  14304. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  14305. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  14306. #define RTC_ALRMBR_MNU_Pos (8U)
  14307. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  14308. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  14309. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  14310. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  14311. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  14312. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  14313. #define RTC_ALRMBR_MSK1_Pos (7U)
  14314. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  14315. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  14316. #define RTC_ALRMBR_ST_Pos (4U)
  14317. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  14318. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  14319. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  14320. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  14321. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  14322. #define RTC_ALRMBR_SU_Pos (0U)
  14323. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  14324. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  14325. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  14326. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  14327. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  14328. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  14329. /******************** Bits definition for RTC_WPR register ******************/
  14330. #define RTC_WPR_KEY_Pos (0U)
  14331. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  14332. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  14333. /******************** Bits definition for RTC_SSR register ******************/
  14334. #define RTC_SSR_SS_Pos (0U)
  14335. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  14336. #define RTC_SSR_SS RTC_SSR_SS_Msk
  14337. /******************** Bits definition for RTC_SHIFTR register ***************/
  14338. #define RTC_SHIFTR_SUBFS_Pos (0U)
  14339. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  14340. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  14341. #define RTC_SHIFTR_ADD1S_Pos (31U)
  14342. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  14343. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  14344. /******************** Bits definition for RTC_TSTR register *****************/
  14345. #define RTC_TSTR_PM_Pos (22U)
  14346. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  14347. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  14348. #define RTC_TSTR_HT_Pos (20U)
  14349. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  14350. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  14351. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  14352. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  14353. #define RTC_TSTR_HU_Pos (16U)
  14354. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  14355. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  14356. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  14357. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  14358. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  14359. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  14360. #define RTC_TSTR_MNT_Pos (12U)
  14361. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  14362. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  14363. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  14364. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  14365. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  14366. #define RTC_TSTR_MNU_Pos (8U)
  14367. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  14368. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  14369. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  14370. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  14371. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  14372. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  14373. #define RTC_TSTR_ST_Pos (4U)
  14374. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  14375. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  14376. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  14377. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  14378. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  14379. #define RTC_TSTR_SU_Pos (0U)
  14380. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  14381. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  14382. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  14383. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  14384. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  14385. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  14386. /******************** Bits definition for RTC_TSDR register *****************/
  14387. #define RTC_TSDR_WDU_Pos (13U)
  14388. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  14389. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  14390. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  14391. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  14392. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  14393. #define RTC_TSDR_MT_Pos (12U)
  14394. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  14395. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  14396. #define RTC_TSDR_MU_Pos (8U)
  14397. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  14398. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  14399. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  14400. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  14401. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  14402. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  14403. #define RTC_TSDR_DT_Pos (4U)
  14404. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  14405. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  14406. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  14407. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  14408. #define RTC_TSDR_DU_Pos (0U)
  14409. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  14410. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  14411. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  14412. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  14413. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  14414. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  14415. /******************** Bits definition for RTC_TSSSR register ****************/
  14416. #define RTC_TSSSR_SS_Pos (0U)
  14417. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  14418. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  14419. /******************** Bits definition for RTC_CAL register *****************/
  14420. #define RTC_CALR_CALP_Pos (15U)
  14421. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  14422. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  14423. #define RTC_CALR_CALW8_Pos (14U)
  14424. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  14425. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  14426. #define RTC_CALR_CALW16_Pos (13U)
  14427. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  14428. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  14429. #define RTC_CALR_CALM_Pos (0U)
  14430. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  14431. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  14432. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  14433. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  14434. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  14435. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  14436. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  14437. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  14438. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  14439. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  14440. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  14441. /******************** Bits definition for RTC_TAFCR register ****************/
  14442. #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
  14443. #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
  14444. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
  14445. #define RTC_TAFCR_TSINSEL_Pos (17U)
  14446. #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
  14447. #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
  14448. #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
  14449. #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
  14450. #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
  14451. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  14452. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  14453. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  14454. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  14455. #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  14456. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  14457. #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  14458. #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  14459. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  14460. #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  14461. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  14462. #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  14463. #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  14464. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  14465. #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  14466. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  14467. #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  14468. #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  14469. #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  14470. #define RTC_TAFCR_TAMPTS_Pos (7U)
  14471. #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  14472. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  14473. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  14474. #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  14475. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  14476. #define RTC_TAFCR_TAMP2E_Pos (3U)
  14477. #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  14478. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  14479. #define RTC_TAFCR_TAMPIE_Pos (2U)
  14480. #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  14481. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  14482. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  14483. #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  14484. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  14485. #define RTC_TAFCR_TAMP1E_Pos (0U)
  14486. #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  14487. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  14488. /* Legacy defines */
  14489. #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
  14490. /******************** Bits definition for RTC_ALRMASSR register *************/
  14491. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  14492. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  14493. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  14494. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  14495. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  14496. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  14497. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  14498. #define RTC_ALRMASSR_SS_Pos (0U)
  14499. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  14500. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  14501. /******************** Bits definition for RTC_ALRMBSSR register *************/
  14502. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  14503. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  14504. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  14505. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  14506. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  14507. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  14508. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  14509. #define RTC_ALRMBSSR_SS_Pos (0U)
  14510. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  14511. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  14512. /******************** Bits definition for RTC_BKP0R register ****************/
  14513. #define RTC_BKP0R_Pos (0U)
  14514. #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  14515. #define RTC_BKP0R RTC_BKP0R_Msk
  14516. /******************** Bits definition for RTC_BKP1R register ****************/
  14517. #define RTC_BKP1R_Pos (0U)
  14518. #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  14519. #define RTC_BKP1R RTC_BKP1R_Msk
  14520. /******************** Bits definition for RTC_BKP2R register ****************/
  14521. #define RTC_BKP2R_Pos (0U)
  14522. #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  14523. #define RTC_BKP2R RTC_BKP2R_Msk
  14524. /******************** Bits definition for RTC_BKP3R register ****************/
  14525. #define RTC_BKP3R_Pos (0U)
  14526. #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  14527. #define RTC_BKP3R RTC_BKP3R_Msk
  14528. /******************** Bits definition for RTC_BKP4R register ****************/
  14529. #define RTC_BKP4R_Pos (0U)
  14530. #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  14531. #define RTC_BKP4R RTC_BKP4R_Msk
  14532. /******************** Bits definition for RTC_BKP5R register ****************/
  14533. #define RTC_BKP5R_Pos (0U)
  14534. #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  14535. #define RTC_BKP5R RTC_BKP5R_Msk
  14536. /******************** Bits definition for RTC_BKP6R register ****************/
  14537. #define RTC_BKP6R_Pos (0U)
  14538. #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  14539. #define RTC_BKP6R RTC_BKP6R_Msk
  14540. /******************** Bits definition for RTC_BKP7R register ****************/
  14541. #define RTC_BKP7R_Pos (0U)
  14542. #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  14543. #define RTC_BKP7R RTC_BKP7R_Msk
  14544. /******************** Bits definition for RTC_BKP8R register ****************/
  14545. #define RTC_BKP8R_Pos (0U)
  14546. #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  14547. #define RTC_BKP8R RTC_BKP8R_Msk
  14548. /******************** Bits definition for RTC_BKP9R register ****************/
  14549. #define RTC_BKP9R_Pos (0U)
  14550. #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  14551. #define RTC_BKP9R RTC_BKP9R_Msk
  14552. /******************** Bits definition for RTC_BKP10R register ***************/
  14553. #define RTC_BKP10R_Pos (0U)
  14554. #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  14555. #define RTC_BKP10R RTC_BKP10R_Msk
  14556. /******************** Bits definition for RTC_BKP11R register ***************/
  14557. #define RTC_BKP11R_Pos (0U)
  14558. #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  14559. #define RTC_BKP11R RTC_BKP11R_Msk
  14560. /******************** Bits definition for RTC_BKP12R register ***************/
  14561. #define RTC_BKP12R_Pos (0U)
  14562. #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  14563. #define RTC_BKP12R RTC_BKP12R_Msk
  14564. /******************** Bits definition for RTC_BKP13R register ***************/
  14565. #define RTC_BKP13R_Pos (0U)
  14566. #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  14567. #define RTC_BKP13R RTC_BKP13R_Msk
  14568. /******************** Bits definition for RTC_BKP14R register ***************/
  14569. #define RTC_BKP14R_Pos (0U)
  14570. #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  14571. #define RTC_BKP14R RTC_BKP14R_Msk
  14572. /******************** Bits definition for RTC_BKP15R register ***************/
  14573. #define RTC_BKP15R_Pos (0U)
  14574. #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  14575. #define RTC_BKP15R RTC_BKP15R_Msk
  14576. /******************** Bits definition for RTC_BKP16R register ***************/
  14577. #define RTC_BKP16R_Pos (0U)
  14578. #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  14579. #define RTC_BKP16R RTC_BKP16R_Msk
  14580. /******************** Bits definition for RTC_BKP17R register ***************/
  14581. #define RTC_BKP17R_Pos (0U)
  14582. #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  14583. #define RTC_BKP17R RTC_BKP17R_Msk
  14584. /******************** Bits definition for RTC_BKP18R register ***************/
  14585. #define RTC_BKP18R_Pos (0U)
  14586. #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  14587. #define RTC_BKP18R RTC_BKP18R_Msk
  14588. /******************** Bits definition for RTC_BKP19R register ***************/
  14589. #define RTC_BKP19R_Pos (0U)
  14590. #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  14591. #define RTC_BKP19R RTC_BKP19R_Msk
  14592. /******************** Number of backup registers ******************************/
  14593. #define RTC_BKP_NUMBER 0x000000014U
  14594. /******************************************************************************/
  14595. /* */
  14596. /* Serial Audio Interface */
  14597. /* */
  14598. /******************************************************************************/
  14599. /******************** Bit definition for SAI_GCR register *******************/
  14600. #define SAI_GCR_SYNCIN_Pos (0U)
  14601. #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
  14602. #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
  14603. #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
  14604. #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
  14605. #define SAI_GCR_SYNCOUT_Pos (4U)
  14606. #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
  14607. #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
  14608. #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
  14609. #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
  14610. /******************* Bit definition for SAI_xCR1 register *******************/
  14611. #define SAI_xCR1_MODE_Pos (0U)
  14612. #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
  14613. #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
  14614. #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
  14615. #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
  14616. #define SAI_xCR1_PRTCFG_Pos (2U)
  14617. #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
  14618. #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
  14619. #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
  14620. #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
  14621. #define SAI_xCR1_DS_Pos (5U)
  14622. #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
  14623. #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
  14624. #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
  14625. #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
  14626. #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
  14627. #define SAI_xCR1_LSBFIRST_Pos (8U)
  14628. #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
  14629. #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
  14630. #define SAI_xCR1_CKSTR_Pos (9U)
  14631. #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
  14632. #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
  14633. #define SAI_xCR1_SYNCEN_Pos (10U)
  14634. #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
  14635. #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
  14636. #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
  14637. #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
  14638. #define SAI_xCR1_MONO_Pos (12U)
  14639. #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
  14640. #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
  14641. #define SAI_xCR1_OUTDRIV_Pos (13U)
  14642. #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
  14643. #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
  14644. #define SAI_xCR1_SAIEN_Pos (16U)
  14645. #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
  14646. #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
  14647. #define SAI_xCR1_DMAEN_Pos (17U)
  14648. #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
  14649. #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
  14650. #define SAI_xCR1_NODIV_Pos (19U)
  14651. #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
  14652. #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
  14653. #define SAI_xCR1_MCKDIV_Pos (20U)
  14654. #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
  14655. #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
  14656. #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
  14657. #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
  14658. #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
  14659. #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
  14660. /******************* Bit definition for SAI_xCR2 register *******************/
  14661. #define SAI_xCR2_FTH_Pos (0U)
  14662. #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
  14663. #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
  14664. #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
  14665. #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
  14666. #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
  14667. #define SAI_xCR2_FFLUSH_Pos (3U)
  14668. #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
  14669. #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
  14670. #define SAI_xCR2_TRIS_Pos (4U)
  14671. #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
  14672. #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
  14673. #define SAI_xCR2_MUTE_Pos (5U)
  14674. #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
  14675. #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
  14676. #define SAI_xCR2_MUTEVAL_Pos (6U)
  14677. #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
  14678. #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
  14679. #define SAI_xCR2_MUTECNT_Pos (7U)
  14680. #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
  14681. #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
  14682. #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
  14683. #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
  14684. #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
  14685. #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
  14686. #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
  14687. #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
  14688. #define SAI_xCR2_CPL_Pos (13U)
  14689. #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
  14690. #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
  14691. #define SAI_xCR2_COMP_Pos (14U)
  14692. #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
  14693. #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
  14694. #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
  14695. #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
  14696. /****************** Bit definition for SAI_xFRCR register *******************/
  14697. #define SAI_xFRCR_FRL_Pos (0U)
  14698. #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
  14699. #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
  14700. #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
  14701. #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
  14702. #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
  14703. #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
  14704. #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
  14705. #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
  14706. #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
  14707. #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
  14708. #define SAI_xFRCR_FSALL_Pos (8U)
  14709. #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
  14710. #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
  14711. #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
  14712. #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
  14713. #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
  14714. #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
  14715. #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
  14716. #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
  14717. #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
  14718. #define SAI_xFRCR_FSDEF_Pos (16U)
  14719. #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
  14720. #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
  14721. #define SAI_xFRCR_FSPOL_Pos (17U)
  14722. #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
  14723. #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
  14724. #define SAI_xFRCR_FSOFF_Pos (18U)
  14725. #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
  14726. #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
  14727. /* Legacy defines */
  14728. #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
  14729. /****************** Bit definition for SAI_xSLOTR register *******************/
  14730. #define SAI_xSLOTR_FBOFF_Pos (0U)
  14731. #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
  14732. #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
  14733. #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
  14734. #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
  14735. #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
  14736. #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
  14737. #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
  14738. #define SAI_xSLOTR_SLOTSZ_Pos (6U)
  14739. #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
  14740. #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
  14741. #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
  14742. #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
  14743. #define SAI_xSLOTR_NBSLOT_Pos (8U)
  14744. #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
  14745. #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
  14746. #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
  14747. #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
  14748. #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
  14749. #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
  14750. #define SAI_xSLOTR_SLOTEN_Pos (16U)
  14751. #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
  14752. #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
  14753. /******************* Bit definition for SAI_xIMR register *******************/
  14754. #define SAI_xIMR_OVRUDRIE_Pos (0U)
  14755. #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
  14756. #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
  14757. #define SAI_xIMR_MUTEDETIE_Pos (1U)
  14758. #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
  14759. #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
  14760. #define SAI_xIMR_WCKCFGIE_Pos (2U)
  14761. #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
  14762. #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
  14763. #define SAI_xIMR_FREQIE_Pos (3U)
  14764. #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
  14765. #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
  14766. #define SAI_xIMR_CNRDYIE_Pos (4U)
  14767. #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
  14768. #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
  14769. #define SAI_xIMR_AFSDETIE_Pos (5U)
  14770. #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
  14771. #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
  14772. #define SAI_xIMR_LFSDETIE_Pos (6U)
  14773. #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
  14774. #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
  14775. /******************** Bit definition for SAI_xSR register *******************/
  14776. #define SAI_xSR_OVRUDR_Pos (0U)
  14777. #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
  14778. #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
  14779. #define SAI_xSR_MUTEDET_Pos (1U)
  14780. #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
  14781. #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
  14782. #define SAI_xSR_WCKCFG_Pos (2U)
  14783. #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
  14784. #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
  14785. #define SAI_xSR_FREQ_Pos (3U)
  14786. #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
  14787. #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
  14788. #define SAI_xSR_CNRDY_Pos (4U)
  14789. #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
  14790. #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
  14791. #define SAI_xSR_AFSDET_Pos (5U)
  14792. #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
  14793. #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
  14794. #define SAI_xSR_LFSDET_Pos (6U)
  14795. #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
  14796. #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
  14797. #define SAI_xSR_FLVL_Pos (16U)
  14798. #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
  14799. #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
  14800. #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
  14801. #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
  14802. #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
  14803. /****************** Bit definition for SAI_xCLRFR register ******************/
  14804. #define SAI_xCLRFR_COVRUDR_Pos (0U)
  14805. #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
  14806. #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
  14807. #define SAI_xCLRFR_CMUTEDET_Pos (1U)
  14808. #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
  14809. #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
  14810. #define SAI_xCLRFR_CWCKCFG_Pos (2U)
  14811. #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
  14812. #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
  14813. #define SAI_xCLRFR_CFREQ_Pos (3U)
  14814. #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
  14815. #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
  14816. #define SAI_xCLRFR_CCNRDY_Pos (4U)
  14817. #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
  14818. #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
  14819. #define SAI_xCLRFR_CAFSDET_Pos (5U)
  14820. #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
  14821. #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
  14822. #define SAI_xCLRFR_CLFSDET_Pos (6U)
  14823. #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
  14824. #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
  14825. /****************** Bit definition for SAI_xDR register ******************/
  14826. #define SAI_xDR_DATA_Pos (0U)
  14827. #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
  14828. #define SAI_xDR_DATA SAI_xDR_DATA_Msk
  14829. /******************************************************************************/
  14830. /* */
  14831. /* SD host Interface */
  14832. /* */
  14833. /******************************************************************************/
  14834. /****************** Bit definition for SDIO_POWER register ******************/
  14835. #define SDIO_POWER_PWRCTRL_Pos (0U)
  14836. #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
  14837. #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
  14838. #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
  14839. #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
  14840. /****************** Bit definition for SDIO_CLKCR register ******************/
  14841. #define SDIO_CLKCR_CLKDIV_Pos (0U)
  14842. #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
  14843. #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
  14844. #define SDIO_CLKCR_CLKEN_Pos (8U)
  14845. #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
  14846. #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
  14847. #define SDIO_CLKCR_PWRSAV_Pos (9U)
  14848. #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
  14849. #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
  14850. #define SDIO_CLKCR_BYPASS_Pos (10U)
  14851. #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
  14852. #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
  14853. #define SDIO_CLKCR_WIDBUS_Pos (11U)
  14854. #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
  14855. #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
  14856. #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
  14857. #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
  14858. #define SDIO_CLKCR_NEGEDGE_Pos (13U)
  14859. #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
  14860. #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
  14861. #define SDIO_CLKCR_HWFC_EN_Pos (14U)
  14862. #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
  14863. #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
  14864. /******************* Bit definition for SDIO_ARG register *******************/
  14865. #define SDIO_ARG_CMDARG_Pos (0U)
  14866. #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
  14867. #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
  14868. /******************* Bit definition for SDIO_CMD register *******************/
  14869. #define SDIO_CMD_CMDINDEX_Pos (0U)
  14870. #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
  14871. #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
  14872. #define SDIO_CMD_WAITRESP_Pos (6U)
  14873. #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
  14874. #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
  14875. #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
  14876. #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
  14877. #define SDIO_CMD_WAITINT_Pos (8U)
  14878. #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
  14879. #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
  14880. #define SDIO_CMD_WAITPEND_Pos (9U)
  14881. #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
  14882. #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
  14883. #define SDIO_CMD_CPSMEN_Pos (10U)
  14884. #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
  14885. #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
  14886. #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
  14887. #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
  14888. #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
  14889. /***************** Bit definition for SDIO_RESPCMD register *****************/
  14890. #define SDIO_RESPCMD_RESPCMD_Pos (0U)
  14891. #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
  14892. #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
  14893. /****************** Bit definition for SDIO_RESP0 register ******************/
  14894. #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
  14895. #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
  14896. #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
  14897. /****************** Bit definition for SDIO_RESP1 register ******************/
  14898. #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
  14899. #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
  14900. #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
  14901. /****************** Bit definition for SDIO_RESP2 register ******************/
  14902. #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
  14903. #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
  14904. #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
  14905. /****************** Bit definition for SDIO_RESP3 register ******************/
  14906. #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
  14907. #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
  14908. #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
  14909. /****************** Bit definition for SDIO_RESP4 register ******************/
  14910. #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
  14911. #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
  14912. #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
  14913. /****************** Bit definition for SDIO_DTIMER register *****************/
  14914. #define SDIO_DTIMER_DATATIME_Pos (0U)
  14915. #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
  14916. #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
  14917. /****************** Bit definition for SDIO_DLEN register *******************/
  14918. #define SDIO_DLEN_DATALENGTH_Pos (0U)
  14919. #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
  14920. #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
  14921. /****************** Bit definition for SDIO_DCTRL register ******************/
  14922. #define SDIO_DCTRL_DTEN_Pos (0U)
  14923. #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
  14924. #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
  14925. #define SDIO_DCTRL_DTDIR_Pos (1U)
  14926. #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
  14927. #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
  14928. #define SDIO_DCTRL_DTMODE_Pos (2U)
  14929. #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
  14930. #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
  14931. #define SDIO_DCTRL_DMAEN_Pos (3U)
  14932. #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
  14933. #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
  14934. #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
  14935. #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
  14936. #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
  14937. #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
  14938. #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
  14939. #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
  14940. #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
  14941. #define SDIO_DCTRL_RWSTART_Pos (8U)
  14942. #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
  14943. #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
  14944. #define SDIO_DCTRL_RWSTOP_Pos (9U)
  14945. #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
  14946. #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
  14947. #define SDIO_DCTRL_RWMOD_Pos (10U)
  14948. #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
  14949. #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
  14950. #define SDIO_DCTRL_SDIOEN_Pos (11U)
  14951. #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
  14952. #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
  14953. /****************** Bit definition for SDIO_DCOUNT register *****************/
  14954. #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
  14955. #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
  14956. #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
  14957. /****************** Bit definition for SDIO_STA register ********************/
  14958. #define SDIO_STA_CCRCFAIL_Pos (0U)
  14959. #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
  14960. #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
  14961. #define SDIO_STA_DCRCFAIL_Pos (1U)
  14962. #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
  14963. #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
  14964. #define SDIO_STA_CTIMEOUT_Pos (2U)
  14965. #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
  14966. #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
  14967. #define SDIO_STA_DTIMEOUT_Pos (3U)
  14968. #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
  14969. #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
  14970. #define SDIO_STA_TXUNDERR_Pos (4U)
  14971. #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
  14972. #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
  14973. #define SDIO_STA_RXOVERR_Pos (5U)
  14974. #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
  14975. #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
  14976. #define SDIO_STA_CMDREND_Pos (6U)
  14977. #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
  14978. #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
  14979. #define SDIO_STA_CMDSENT_Pos (7U)
  14980. #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
  14981. #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
  14982. #define SDIO_STA_DATAEND_Pos (8U)
  14983. #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
  14984. #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
  14985. #define SDIO_STA_DBCKEND_Pos (10U)
  14986. #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
  14987. #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
  14988. #define SDIO_STA_CMDACT_Pos (11U)
  14989. #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
  14990. #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
  14991. #define SDIO_STA_TXACT_Pos (12U)
  14992. #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
  14993. #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
  14994. #define SDIO_STA_RXACT_Pos (13U)
  14995. #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
  14996. #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
  14997. #define SDIO_STA_TXFIFOHE_Pos (14U)
  14998. #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
  14999. #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
  15000. #define SDIO_STA_RXFIFOHF_Pos (15U)
  15001. #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
  15002. #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
  15003. #define SDIO_STA_TXFIFOF_Pos (16U)
  15004. #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
  15005. #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
  15006. #define SDIO_STA_RXFIFOF_Pos (17U)
  15007. #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
  15008. #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
  15009. #define SDIO_STA_TXFIFOE_Pos (18U)
  15010. #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
  15011. #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
  15012. #define SDIO_STA_RXFIFOE_Pos (19U)
  15013. #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
  15014. #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
  15015. #define SDIO_STA_TXDAVL_Pos (20U)
  15016. #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
  15017. #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
  15018. #define SDIO_STA_RXDAVL_Pos (21U)
  15019. #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
  15020. #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
  15021. #define SDIO_STA_SDIOIT_Pos (22U)
  15022. #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
  15023. #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
  15024. /******************* Bit definition for SDIO_ICR register *******************/
  15025. #define SDIO_ICR_CCRCFAILC_Pos (0U)
  15026. #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
  15027. #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
  15028. #define SDIO_ICR_DCRCFAILC_Pos (1U)
  15029. #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
  15030. #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
  15031. #define SDIO_ICR_CTIMEOUTC_Pos (2U)
  15032. #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
  15033. #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
  15034. #define SDIO_ICR_DTIMEOUTC_Pos (3U)
  15035. #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
  15036. #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
  15037. #define SDIO_ICR_TXUNDERRC_Pos (4U)
  15038. #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
  15039. #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
  15040. #define SDIO_ICR_RXOVERRC_Pos (5U)
  15041. #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
  15042. #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
  15043. #define SDIO_ICR_CMDRENDC_Pos (6U)
  15044. #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
  15045. #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
  15046. #define SDIO_ICR_CMDSENTC_Pos (7U)
  15047. #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
  15048. #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
  15049. #define SDIO_ICR_DATAENDC_Pos (8U)
  15050. #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
  15051. #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
  15052. #define SDIO_ICR_DBCKENDC_Pos (10U)
  15053. #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
  15054. #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
  15055. #define SDIO_ICR_SDIOITC_Pos (22U)
  15056. #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
  15057. #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
  15058. /****************** Bit definition for SDIO_MASK register *******************/
  15059. #define SDIO_MASK_CCRCFAILIE_Pos (0U)
  15060. #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
  15061. #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
  15062. #define SDIO_MASK_DCRCFAILIE_Pos (1U)
  15063. #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
  15064. #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
  15065. #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
  15066. #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
  15067. #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
  15068. #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
  15069. #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
  15070. #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
  15071. #define SDIO_MASK_TXUNDERRIE_Pos (4U)
  15072. #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
  15073. #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
  15074. #define SDIO_MASK_RXOVERRIE_Pos (5U)
  15075. #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
  15076. #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
  15077. #define SDIO_MASK_CMDRENDIE_Pos (6U)
  15078. #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
  15079. #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
  15080. #define SDIO_MASK_CMDSENTIE_Pos (7U)
  15081. #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
  15082. #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
  15083. #define SDIO_MASK_DATAENDIE_Pos (8U)
  15084. #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
  15085. #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
  15086. #define SDIO_MASK_DBCKENDIE_Pos (10U)
  15087. #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
  15088. #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
  15089. #define SDIO_MASK_CMDACTIE_Pos (11U)
  15090. #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
  15091. #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
  15092. #define SDIO_MASK_TXACTIE_Pos (12U)
  15093. #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
  15094. #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
  15095. #define SDIO_MASK_RXACTIE_Pos (13U)
  15096. #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
  15097. #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
  15098. #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
  15099. #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
  15100. #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
  15101. #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
  15102. #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
  15103. #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
  15104. #define SDIO_MASK_TXFIFOFIE_Pos (16U)
  15105. #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
  15106. #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
  15107. #define SDIO_MASK_RXFIFOFIE_Pos (17U)
  15108. #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
  15109. #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
  15110. #define SDIO_MASK_TXFIFOEIE_Pos (18U)
  15111. #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
  15112. #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
  15113. #define SDIO_MASK_RXFIFOEIE_Pos (19U)
  15114. #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
  15115. #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
  15116. #define SDIO_MASK_TXDAVLIE_Pos (20U)
  15117. #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
  15118. #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
  15119. #define SDIO_MASK_RXDAVLIE_Pos (21U)
  15120. #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
  15121. #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
  15122. #define SDIO_MASK_SDIOITIE_Pos (22U)
  15123. #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
  15124. #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
  15125. /***************** Bit definition for SDIO_FIFOCNT register *****************/
  15126. #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
  15127. #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
  15128. #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
  15129. /****************** Bit definition for SDIO_FIFO register *******************/
  15130. #define SDIO_FIFO_FIFODATA_Pos (0U)
  15131. #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
  15132. #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
  15133. /******************************************************************************/
  15134. /* */
  15135. /* Serial Peripheral Interface */
  15136. /* */
  15137. /******************************************************************************/
  15138. #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
  15139. /******************* Bit definition for SPI_CR1 register ********************/
  15140. #define SPI_CR1_CPHA_Pos (0U)
  15141. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  15142. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  15143. #define SPI_CR1_CPOL_Pos (1U)
  15144. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  15145. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  15146. #define SPI_CR1_MSTR_Pos (2U)
  15147. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  15148. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  15149. #define SPI_CR1_BR_Pos (3U)
  15150. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  15151. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  15152. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  15153. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  15154. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  15155. #define SPI_CR1_SPE_Pos (6U)
  15156. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  15157. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  15158. #define SPI_CR1_LSBFIRST_Pos (7U)
  15159. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  15160. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  15161. #define SPI_CR1_SSI_Pos (8U)
  15162. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  15163. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  15164. #define SPI_CR1_SSM_Pos (9U)
  15165. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  15166. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  15167. #define SPI_CR1_RXONLY_Pos (10U)
  15168. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  15169. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  15170. #define SPI_CR1_DFF_Pos (11U)
  15171. #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
  15172. #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
  15173. #define SPI_CR1_CRCNEXT_Pos (12U)
  15174. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  15175. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  15176. #define SPI_CR1_CRCEN_Pos (13U)
  15177. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  15178. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  15179. #define SPI_CR1_BIDIOE_Pos (14U)
  15180. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  15181. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  15182. #define SPI_CR1_BIDIMODE_Pos (15U)
  15183. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  15184. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  15185. /******************* Bit definition for SPI_CR2 register ********************/
  15186. #define SPI_CR2_RXDMAEN_Pos (0U)
  15187. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  15188. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
  15189. #define SPI_CR2_TXDMAEN_Pos (1U)
  15190. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  15191. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
  15192. #define SPI_CR2_SSOE_Pos (2U)
  15193. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  15194. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
  15195. #define SPI_CR2_FRF_Pos (4U)
  15196. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  15197. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
  15198. #define SPI_CR2_ERRIE_Pos (5U)
  15199. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  15200. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
  15201. #define SPI_CR2_RXNEIE_Pos (6U)
  15202. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  15203. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
  15204. #define SPI_CR2_TXEIE_Pos (7U)
  15205. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  15206. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
  15207. /******************** Bit definition for SPI_SR register ********************/
  15208. #define SPI_SR_RXNE_Pos (0U)
  15209. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  15210. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
  15211. #define SPI_SR_TXE_Pos (1U)
  15212. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  15213. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
  15214. #define SPI_SR_CHSIDE_Pos (2U)
  15215. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  15216. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
  15217. #define SPI_SR_UDR_Pos (3U)
  15218. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  15219. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
  15220. #define SPI_SR_CRCERR_Pos (4U)
  15221. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  15222. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
  15223. #define SPI_SR_MODF_Pos (5U)
  15224. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  15225. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
  15226. #define SPI_SR_OVR_Pos (6U)
  15227. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  15228. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
  15229. #define SPI_SR_BSY_Pos (7U)
  15230. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  15231. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
  15232. #define SPI_SR_FRE_Pos (8U)
  15233. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  15234. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
  15235. /******************** Bit definition for SPI_DR register ********************/
  15236. #define SPI_DR_DR_Pos (0U)
  15237. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  15238. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  15239. /******************* Bit definition for SPI_CRCPR register ******************/
  15240. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  15241. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  15242. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  15243. /****************** Bit definition for SPI_RXCRCR register ******************/
  15244. #define SPI_RXCRCR_RXCRC_Pos (0U)
  15245. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  15246. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  15247. /****************** Bit definition for SPI_TXCRCR register ******************/
  15248. #define SPI_TXCRCR_TXCRC_Pos (0U)
  15249. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  15250. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  15251. /****************** Bit definition for SPI_I2SCFGR register *****************/
  15252. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  15253. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  15254. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  15255. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  15256. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  15257. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  15258. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  15259. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  15260. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  15261. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  15262. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  15263. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  15264. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  15265. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  15266. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  15267. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  15268. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  15269. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  15270. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  15271. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  15272. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  15273. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  15274. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  15275. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  15276. #define SPI_I2SCFGR_I2SE_Pos (10U)
  15277. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  15278. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  15279. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  15280. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  15281. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  15282. #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
  15283. #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
  15284. #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
  15285. /****************** Bit definition for SPI_I2SPR register *******************/
  15286. #define SPI_I2SPR_I2SDIV_Pos (0U)
  15287. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  15288. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  15289. #define SPI_I2SPR_ODD_Pos (8U)
  15290. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  15291. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  15292. #define SPI_I2SPR_MCKOE_Pos (9U)
  15293. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  15294. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  15295. /******************************************************************************/
  15296. /* */
  15297. /* SYSCFG */
  15298. /* */
  15299. /******************************************************************************/
  15300. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  15301. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  15302. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
  15303. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  15304. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  15305. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  15306. #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
  15307. #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
  15308. #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
  15309. #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
  15310. #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
  15311. #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
  15312. #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
  15313. #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
  15314. /* Legacy Defines */
  15315. #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
  15316. /****************** Bit definition for SYSCFG_PMC register ******************/
  15317. #define SYSCFG_PMC_ADCxDC2_Pos (16U)
  15318. #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
  15319. #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
  15320. #define SYSCFG_PMC_ADC1DC2_Pos (16U)
  15321. #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
  15322. #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  15323. #define SYSCFG_PMC_ADC2DC2_Pos (17U)
  15324. #define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
  15325. #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  15326. #define SYSCFG_PMC_ADC3DC2_Pos (18U)
  15327. #define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
  15328. #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  15329. #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
  15330. #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
  15331. #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
  15332. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  15333. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  15334. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  15335. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  15336. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  15337. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  15338. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  15339. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  15340. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  15341. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  15342. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  15343. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  15344. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  15345. /**
  15346. * @brief EXTI0 configuration
  15347. */
  15348. #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
  15349. #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
  15350. #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
  15351. #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
  15352. #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
  15353. #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
  15354. #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
  15355. #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
  15356. #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
  15357. #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
  15358. #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
  15359. /**
  15360. * @brief EXTI1 configuration
  15361. */
  15362. #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
  15363. #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
  15364. #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
  15365. #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
  15366. #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
  15367. #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
  15368. #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
  15369. #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
  15370. #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
  15371. #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
  15372. #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
  15373. /**
  15374. * @brief EXTI2 configuration
  15375. */
  15376. #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
  15377. #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
  15378. #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
  15379. #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
  15380. #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
  15381. #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
  15382. #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
  15383. #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
  15384. #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
  15385. #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
  15386. #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
  15387. /**
  15388. * @brief EXTI3 configuration
  15389. */
  15390. #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
  15391. #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
  15392. #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
  15393. #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
  15394. #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
  15395. #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
  15396. #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
  15397. #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
  15398. #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
  15399. #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
  15400. #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
  15401. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  15402. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  15403. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  15404. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  15405. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  15406. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  15407. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  15408. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  15409. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  15410. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  15411. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  15412. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  15413. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  15414. /**
  15415. * @brief EXTI4 configuration
  15416. */
  15417. #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
  15418. #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
  15419. #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
  15420. #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
  15421. #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
  15422. #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
  15423. #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
  15424. #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
  15425. #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
  15426. #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
  15427. #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
  15428. /**
  15429. * @brief EXTI5 configuration
  15430. */
  15431. #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
  15432. #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
  15433. #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
  15434. #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
  15435. #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
  15436. #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
  15437. #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
  15438. #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
  15439. #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
  15440. #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
  15441. #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
  15442. /**
  15443. * @brief EXTI6 configuration
  15444. */
  15445. #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
  15446. #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
  15447. #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
  15448. #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
  15449. #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
  15450. #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
  15451. #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
  15452. #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
  15453. #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
  15454. #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
  15455. #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
  15456. /**
  15457. * @brief EXTI7 configuration
  15458. */
  15459. #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
  15460. #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
  15461. #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
  15462. #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
  15463. #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
  15464. #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
  15465. #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
  15466. #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
  15467. #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
  15468. #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
  15469. #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
  15470. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  15471. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  15472. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  15473. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  15474. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  15475. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  15476. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  15477. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  15478. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  15479. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  15480. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  15481. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  15482. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  15483. /**
  15484. * @brief EXTI8 configuration
  15485. */
  15486. #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
  15487. #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
  15488. #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
  15489. #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
  15490. #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
  15491. #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
  15492. #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
  15493. #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
  15494. #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
  15495. #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
  15496. /**
  15497. * @brief EXTI9 configuration
  15498. */
  15499. #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
  15500. #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
  15501. #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
  15502. #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
  15503. #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
  15504. #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
  15505. #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
  15506. #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
  15507. #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
  15508. #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
  15509. /**
  15510. * @brief EXTI10 configuration
  15511. */
  15512. #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
  15513. #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
  15514. #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
  15515. #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
  15516. #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
  15517. #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
  15518. #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
  15519. #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
  15520. #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
  15521. #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
  15522. /**
  15523. * @brief EXTI11 configuration
  15524. */
  15525. #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
  15526. #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
  15527. #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
  15528. #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
  15529. #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
  15530. #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
  15531. #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
  15532. #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
  15533. #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
  15534. #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
  15535. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  15536. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  15537. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  15538. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  15539. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  15540. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  15541. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  15542. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  15543. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  15544. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  15545. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  15546. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  15547. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  15548. /**
  15549. * @brief EXTI12 configuration
  15550. */
  15551. #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
  15552. #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
  15553. #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
  15554. #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
  15555. #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
  15556. #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
  15557. #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
  15558. #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
  15559. #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
  15560. #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
  15561. /**
  15562. * @brief EXTI13 configuration
  15563. */
  15564. #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
  15565. #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
  15566. #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
  15567. #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
  15568. #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
  15569. #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
  15570. #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
  15571. #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
  15572. #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
  15573. #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
  15574. /**
  15575. * @brief EXTI14 configuration
  15576. */
  15577. #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
  15578. #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
  15579. #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
  15580. #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
  15581. #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
  15582. #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
  15583. #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
  15584. #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
  15585. #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
  15586. #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
  15587. /**
  15588. * @brief EXTI15 configuration
  15589. */
  15590. #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
  15591. #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
  15592. #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
  15593. #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
  15594. #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
  15595. #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
  15596. #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
  15597. #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
  15598. #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
  15599. #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
  15600. /****************** Bit definition for SYSCFG_CMPCR register ****************/
  15601. #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
  15602. #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
  15603. #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
  15604. #define SYSCFG_CMPCR_READY_Pos (8U)
  15605. #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
  15606. #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
  15607. /******************************************************************************/
  15608. /* */
  15609. /* TIM */
  15610. /* */
  15611. /******************************************************************************/
  15612. /******************* Bit definition for TIM_CR1 register ********************/
  15613. #define TIM_CR1_CEN_Pos (0U)
  15614. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  15615. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  15616. #define TIM_CR1_UDIS_Pos (1U)
  15617. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  15618. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  15619. #define TIM_CR1_URS_Pos (2U)
  15620. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  15621. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  15622. #define TIM_CR1_OPM_Pos (3U)
  15623. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  15624. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  15625. #define TIM_CR1_DIR_Pos (4U)
  15626. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  15627. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  15628. #define TIM_CR1_CMS_Pos (5U)
  15629. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  15630. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  15631. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
  15632. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
  15633. #define TIM_CR1_ARPE_Pos (7U)
  15634. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  15635. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  15636. #define TIM_CR1_CKD_Pos (8U)
  15637. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  15638. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  15639. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
  15640. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
  15641. /******************* Bit definition for TIM_CR2 register ********************/
  15642. #define TIM_CR2_CCPC_Pos (0U)
  15643. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  15644. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  15645. #define TIM_CR2_CCUS_Pos (2U)
  15646. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  15647. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  15648. #define TIM_CR2_CCDS_Pos (3U)
  15649. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  15650. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  15651. #define TIM_CR2_MMS_Pos (4U)
  15652. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  15653. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  15654. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
  15655. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
  15656. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
  15657. #define TIM_CR2_TI1S_Pos (7U)
  15658. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  15659. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  15660. #define TIM_CR2_OIS1_Pos (8U)
  15661. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  15662. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  15663. #define TIM_CR2_OIS1N_Pos (9U)
  15664. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  15665. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  15666. #define TIM_CR2_OIS2_Pos (10U)
  15667. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  15668. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  15669. #define TIM_CR2_OIS2N_Pos (11U)
  15670. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  15671. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  15672. #define TIM_CR2_OIS3_Pos (12U)
  15673. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  15674. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  15675. #define TIM_CR2_OIS3N_Pos (13U)
  15676. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  15677. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  15678. #define TIM_CR2_OIS4_Pos (14U)
  15679. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  15680. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  15681. /******************* Bit definition for TIM_SMCR register *******************/
  15682. #define TIM_SMCR_SMS_Pos (0U)
  15683. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  15684. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  15685. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
  15686. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
  15687. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
  15688. #define TIM_SMCR_TS_Pos (4U)
  15689. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  15690. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  15691. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
  15692. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
  15693. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
  15694. #define TIM_SMCR_MSM_Pos (7U)
  15695. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  15696. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  15697. #define TIM_SMCR_ETF_Pos (8U)
  15698. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  15699. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  15700. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
  15701. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
  15702. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
  15703. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
  15704. #define TIM_SMCR_ETPS_Pos (12U)
  15705. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  15706. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  15707. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
  15708. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
  15709. #define TIM_SMCR_ECE_Pos (14U)
  15710. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  15711. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  15712. #define TIM_SMCR_ETP_Pos (15U)
  15713. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  15714. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  15715. /******************* Bit definition for TIM_DIER register *******************/
  15716. #define TIM_DIER_UIE_Pos (0U)
  15717. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  15718. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  15719. #define TIM_DIER_CC1IE_Pos (1U)
  15720. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  15721. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  15722. #define TIM_DIER_CC2IE_Pos (2U)
  15723. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  15724. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  15725. #define TIM_DIER_CC3IE_Pos (3U)
  15726. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  15727. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  15728. #define TIM_DIER_CC4IE_Pos (4U)
  15729. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  15730. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  15731. #define TIM_DIER_COMIE_Pos (5U)
  15732. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  15733. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  15734. #define TIM_DIER_TIE_Pos (6U)
  15735. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  15736. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  15737. #define TIM_DIER_BIE_Pos (7U)
  15738. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  15739. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  15740. #define TIM_DIER_UDE_Pos (8U)
  15741. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  15742. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  15743. #define TIM_DIER_CC1DE_Pos (9U)
  15744. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  15745. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  15746. #define TIM_DIER_CC2DE_Pos (10U)
  15747. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  15748. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  15749. #define TIM_DIER_CC3DE_Pos (11U)
  15750. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  15751. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  15752. #define TIM_DIER_CC4DE_Pos (12U)
  15753. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  15754. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  15755. #define TIM_DIER_COMDE_Pos (13U)
  15756. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  15757. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  15758. #define TIM_DIER_TDE_Pos (14U)
  15759. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  15760. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  15761. /******************** Bit definition for TIM_SR register ********************/
  15762. #define TIM_SR_UIF_Pos (0U)
  15763. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  15764. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  15765. #define TIM_SR_CC1IF_Pos (1U)
  15766. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  15767. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  15768. #define TIM_SR_CC2IF_Pos (2U)
  15769. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  15770. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  15771. #define TIM_SR_CC3IF_Pos (3U)
  15772. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  15773. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  15774. #define TIM_SR_CC4IF_Pos (4U)
  15775. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  15776. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  15777. #define TIM_SR_COMIF_Pos (5U)
  15778. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  15779. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  15780. #define TIM_SR_TIF_Pos (6U)
  15781. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  15782. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  15783. #define TIM_SR_BIF_Pos (7U)
  15784. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  15785. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  15786. #define TIM_SR_CC1OF_Pos (9U)
  15787. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  15788. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  15789. #define TIM_SR_CC2OF_Pos (10U)
  15790. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  15791. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  15792. #define TIM_SR_CC3OF_Pos (11U)
  15793. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  15794. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  15795. #define TIM_SR_CC4OF_Pos (12U)
  15796. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  15797. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  15798. /******************* Bit definition for TIM_EGR register ********************/
  15799. #define TIM_EGR_UG_Pos (0U)
  15800. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  15801. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  15802. #define TIM_EGR_CC1G_Pos (1U)
  15803. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  15804. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  15805. #define TIM_EGR_CC2G_Pos (2U)
  15806. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  15807. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  15808. #define TIM_EGR_CC3G_Pos (3U)
  15809. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  15810. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  15811. #define TIM_EGR_CC4G_Pos (4U)
  15812. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  15813. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  15814. #define TIM_EGR_COMG_Pos (5U)
  15815. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  15816. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  15817. #define TIM_EGR_TG_Pos (6U)
  15818. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  15819. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  15820. #define TIM_EGR_BG_Pos (7U)
  15821. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  15822. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  15823. /****************** Bit definition for TIM_CCMR1 register *******************/
  15824. #define TIM_CCMR1_CC1S_Pos (0U)
  15825. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  15826. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  15827. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
  15828. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
  15829. #define TIM_CCMR1_OC1FE_Pos (2U)
  15830. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  15831. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  15832. #define TIM_CCMR1_OC1PE_Pos (3U)
  15833. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  15834. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  15835. #define TIM_CCMR1_OC1M_Pos (4U)
  15836. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  15837. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  15838. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
  15839. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
  15840. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
  15841. #define TIM_CCMR1_OC1CE_Pos (7U)
  15842. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  15843. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  15844. #define TIM_CCMR1_CC2S_Pos (8U)
  15845. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  15846. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  15847. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
  15848. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
  15849. #define TIM_CCMR1_OC2FE_Pos (10U)
  15850. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  15851. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  15852. #define TIM_CCMR1_OC2PE_Pos (11U)
  15853. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  15854. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  15855. #define TIM_CCMR1_OC2M_Pos (12U)
  15856. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  15857. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  15858. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
  15859. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
  15860. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
  15861. #define TIM_CCMR1_OC2CE_Pos (15U)
  15862. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  15863. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  15864. /*----------------------------------------------------------------------------*/
  15865. #define TIM_CCMR1_IC1PSC_Pos (2U)
  15866. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  15867. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  15868. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
  15869. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
  15870. #define TIM_CCMR1_IC1F_Pos (4U)
  15871. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  15872. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  15873. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
  15874. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
  15875. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
  15876. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
  15877. #define TIM_CCMR1_IC2PSC_Pos (10U)
  15878. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  15879. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  15880. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
  15881. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
  15882. #define TIM_CCMR1_IC2F_Pos (12U)
  15883. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  15884. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  15885. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
  15886. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
  15887. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
  15888. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
  15889. /****************** Bit definition for TIM_CCMR2 register *******************/
  15890. #define TIM_CCMR2_CC3S_Pos (0U)
  15891. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  15892. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  15893. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
  15894. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
  15895. #define TIM_CCMR2_OC3FE_Pos (2U)
  15896. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  15897. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  15898. #define TIM_CCMR2_OC3PE_Pos (3U)
  15899. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  15900. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  15901. #define TIM_CCMR2_OC3M_Pos (4U)
  15902. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  15903. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  15904. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
  15905. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
  15906. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
  15907. #define TIM_CCMR2_OC3CE_Pos (7U)
  15908. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  15909. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  15910. #define TIM_CCMR2_CC4S_Pos (8U)
  15911. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  15912. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  15913. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
  15914. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
  15915. #define TIM_CCMR2_OC4FE_Pos (10U)
  15916. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  15917. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  15918. #define TIM_CCMR2_OC4PE_Pos (11U)
  15919. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  15920. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  15921. #define TIM_CCMR2_OC4M_Pos (12U)
  15922. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  15923. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  15924. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
  15925. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
  15926. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
  15927. #define TIM_CCMR2_OC4CE_Pos (15U)
  15928. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  15929. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  15930. /*----------------------------------------------------------------------------*/
  15931. #define TIM_CCMR2_IC3PSC_Pos (2U)
  15932. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  15933. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  15934. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
  15935. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
  15936. #define TIM_CCMR2_IC3F_Pos (4U)
  15937. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  15938. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  15939. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
  15940. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
  15941. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
  15942. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
  15943. #define TIM_CCMR2_IC4PSC_Pos (10U)
  15944. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  15945. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  15946. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
  15947. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
  15948. #define TIM_CCMR2_IC4F_Pos (12U)
  15949. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  15950. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  15951. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
  15952. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
  15953. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
  15954. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
  15955. /******************* Bit definition for TIM_CCER register *******************/
  15956. #define TIM_CCER_CC1E_Pos (0U)
  15957. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  15958. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  15959. #define TIM_CCER_CC1P_Pos (1U)
  15960. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  15961. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  15962. #define TIM_CCER_CC1NE_Pos (2U)
  15963. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  15964. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  15965. #define TIM_CCER_CC1NP_Pos (3U)
  15966. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  15967. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  15968. #define TIM_CCER_CC2E_Pos (4U)
  15969. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  15970. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  15971. #define TIM_CCER_CC2P_Pos (5U)
  15972. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  15973. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  15974. #define TIM_CCER_CC2NE_Pos (6U)
  15975. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  15976. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  15977. #define TIM_CCER_CC2NP_Pos (7U)
  15978. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  15979. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  15980. #define TIM_CCER_CC3E_Pos (8U)
  15981. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  15982. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  15983. #define TIM_CCER_CC3P_Pos (9U)
  15984. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  15985. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  15986. #define TIM_CCER_CC3NE_Pos (10U)
  15987. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  15988. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  15989. #define TIM_CCER_CC3NP_Pos (11U)
  15990. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  15991. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  15992. #define TIM_CCER_CC4E_Pos (12U)
  15993. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  15994. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  15995. #define TIM_CCER_CC4P_Pos (13U)
  15996. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  15997. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  15998. #define TIM_CCER_CC4NP_Pos (15U)
  15999. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  16000. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  16001. /******************* Bit definition for TIM_CNT register ********************/
  16002. #define TIM_CNT_CNT_Pos (0U)
  16003. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  16004. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  16005. /******************* Bit definition for TIM_PSC register ********************/
  16006. #define TIM_PSC_PSC_Pos (0U)
  16007. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  16008. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  16009. /******************* Bit definition for TIM_ARR register ********************/
  16010. #define TIM_ARR_ARR_Pos (0U)
  16011. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  16012. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  16013. /******************* Bit definition for TIM_RCR register ********************/
  16014. #define TIM_RCR_REP_Pos (0U)
  16015. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  16016. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  16017. /******************* Bit definition for TIM_CCR1 register *******************/
  16018. #define TIM_CCR1_CCR1_Pos (0U)
  16019. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  16020. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  16021. /******************* Bit definition for TIM_CCR2 register *******************/
  16022. #define TIM_CCR2_CCR2_Pos (0U)
  16023. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  16024. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  16025. /******************* Bit definition for TIM_CCR3 register *******************/
  16026. #define TIM_CCR3_CCR3_Pos (0U)
  16027. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  16028. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  16029. /******************* Bit definition for TIM_CCR4 register *******************/
  16030. #define TIM_CCR4_CCR4_Pos (0U)
  16031. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  16032. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  16033. /******************* Bit definition for TIM_BDTR register *******************/
  16034. #define TIM_BDTR_DTG_Pos (0U)
  16035. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  16036. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  16037. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
  16038. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
  16039. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
  16040. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
  16041. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
  16042. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
  16043. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
  16044. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
  16045. #define TIM_BDTR_LOCK_Pos (8U)
  16046. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  16047. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  16048. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
  16049. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
  16050. #define TIM_BDTR_OSSI_Pos (10U)
  16051. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  16052. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  16053. #define TIM_BDTR_OSSR_Pos (11U)
  16054. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  16055. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  16056. #define TIM_BDTR_BKE_Pos (12U)
  16057. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  16058. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  16059. #define TIM_BDTR_BKP_Pos (13U)
  16060. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  16061. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  16062. #define TIM_BDTR_AOE_Pos (14U)
  16063. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  16064. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  16065. #define TIM_BDTR_MOE_Pos (15U)
  16066. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  16067. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  16068. /******************* Bit definition for TIM_DCR register ********************/
  16069. #define TIM_DCR_DBA_Pos (0U)
  16070. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  16071. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  16072. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
  16073. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
  16074. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
  16075. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
  16076. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
  16077. #define TIM_DCR_DBL_Pos (8U)
  16078. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  16079. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  16080. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
  16081. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
  16082. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
  16083. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
  16084. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
  16085. /******************* Bit definition for TIM_DMAR register *******************/
  16086. #define TIM_DMAR_DMAB_Pos (0U)
  16087. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  16088. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  16089. /******************* Bit definition for TIM_OR register *********************/
  16090. #define TIM_OR_TI1_RMP_Pos (0U)
  16091. #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  16092. #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
  16093. #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  16094. #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  16095. #define TIM_OR_TI4_RMP_Pos (6U)
  16096. #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
  16097. #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
  16098. #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
  16099. #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
  16100. #define TIM_OR_ITR1_RMP_Pos (10U)
  16101. #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
  16102. #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
  16103. #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
  16104. #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
  16105. /******************************************************************************/
  16106. /* */
  16107. /* Universal Synchronous Asynchronous Receiver Transmitter */
  16108. /* */
  16109. /******************************************************************************/
  16110. /******************* Bit definition for USART_SR register *******************/
  16111. #define USART_SR_PE_Pos (0U)
  16112. #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
  16113. #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
  16114. #define USART_SR_FE_Pos (1U)
  16115. #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
  16116. #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
  16117. #define USART_SR_NE_Pos (2U)
  16118. #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
  16119. #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
  16120. #define USART_SR_ORE_Pos (3U)
  16121. #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
  16122. #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
  16123. #define USART_SR_IDLE_Pos (4U)
  16124. #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
  16125. #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
  16126. #define USART_SR_RXNE_Pos (5U)
  16127. #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
  16128. #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
  16129. #define USART_SR_TC_Pos (6U)
  16130. #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
  16131. #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
  16132. #define USART_SR_TXE_Pos (7U)
  16133. #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
  16134. #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
  16135. #define USART_SR_LBD_Pos (8U)
  16136. #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
  16137. #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
  16138. #define USART_SR_CTS_Pos (9U)
  16139. #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
  16140. #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
  16141. /******************* Bit definition for USART_DR register *******************/
  16142. #define USART_DR_DR_Pos (0U)
  16143. #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
  16144. #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
  16145. /****************** Bit definition for USART_BRR register *******************/
  16146. #define USART_BRR_DIV_Fraction_Pos (0U)
  16147. #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
  16148. #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
  16149. #define USART_BRR_DIV_Mantissa_Pos (4U)
  16150. #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
  16151. #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
  16152. /****************** Bit definition for USART_CR1 register *******************/
  16153. #define USART_CR1_SBK_Pos (0U)
  16154. #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
  16155. #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
  16156. #define USART_CR1_RWU_Pos (1U)
  16157. #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
  16158. #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
  16159. #define USART_CR1_RE_Pos (2U)
  16160. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  16161. #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
  16162. #define USART_CR1_TE_Pos (3U)
  16163. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  16164. #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
  16165. #define USART_CR1_IDLEIE_Pos (4U)
  16166. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  16167. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
  16168. #define USART_CR1_RXNEIE_Pos (5U)
  16169. #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  16170. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
  16171. #define USART_CR1_TCIE_Pos (6U)
  16172. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  16173. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
  16174. #define USART_CR1_TXEIE_Pos (7U)
  16175. #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  16176. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
  16177. #define USART_CR1_PEIE_Pos (8U)
  16178. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  16179. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
  16180. #define USART_CR1_PS_Pos (9U)
  16181. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  16182. #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
  16183. #define USART_CR1_PCE_Pos (10U)
  16184. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  16185. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
  16186. #define USART_CR1_WAKE_Pos (11U)
  16187. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  16188. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
  16189. #define USART_CR1_M_Pos (12U)
  16190. #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
  16191. #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
  16192. #define USART_CR1_UE_Pos (13U)
  16193. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
  16194. #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
  16195. #define USART_CR1_OVER8_Pos (15U)
  16196. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  16197. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
  16198. /****************** Bit definition for USART_CR2 register *******************/
  16199. #define USART_CR2_ADD_Pos (0U)
  16200. #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
  16201. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
  16202. #define USART_CR2_LBDL_Pos (5U)
  16203. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  16204. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
  16205. #define USART_CR2_LBDIE_Pos (6U)
  16206. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  16207. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
  16208. #define USART_CR2_LBCL_Pos (8U)
  16209. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  16210. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
  16211. #define USART_CR2_CPHA_Pos (9U)
  16212. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  16213. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
  16214. #define USART_CR2_CPOL_Pos (10U)
  16215. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  16216. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
  16217. #define USART_CR2_CLKEN_Pos (11U)
  16218. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  16219. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
  16220. #define USART_CR2_STOP_Pos (12U)
  16221. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  16222. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
  16223. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
  16224. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
  16225. #define USART_CR2_LINEN_Pos (14U)
  16226. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  16227. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
  16228. /****************** Bit definition for USART_CR3 register *******************/
  16229. #define USART_CR3_EIE_Pos (0U)
  16230. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  16231. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
  16232. #define USART_CR3_IREN_Pos (1U)
  16233. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  16234. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
  16235. #define USART_CR3_IRLP_Pos (2U)
  16236. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  16237. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
  16238. #define USART_CR3_HDSEL_Pos (3U)
  16239. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  16240. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
  16241. #define USART_CR3_NACK_Pos (4U)
  16242. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  16243. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
  16244. #define USART_CR3_SCEN_Pos (5U)
  16245. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  16246. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
  16247. #define USART_CR3_DMAR_Pos (6U)
  16248. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  16249. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
  16250. #define USART_CR3_DMAT_Pos (7U)
  16251. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  16252. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
  16253. #define USART_CR3_RTSE_Pos (8U)
  16254. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  16255. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
  16256. #define USART_CR3_CTSE_Pos (9U)
  16257. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  16258. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
  16259. #define USART_CR3_CTSIE_Pos (10U)
  16260. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  16261. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
  16262. #define USART_CR3_ONEBIT_Pos (11U)
  16263. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  16264. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
  16265. /****************** Bit definition for USART_GTPR register ******************/
  16266. #define USART_GTPR_PSC_Pos (0U)
  16267. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  16268. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
  16269. #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
  16270. #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
  16271. #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
  16272. #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
  16273. #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
  16274. #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
  16275. #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
  16276. #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
  16277. #define USART_GTPR_GT_Pos (8U)
  16278. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  16279. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
  16280. /******************************************************************************/
  16281. /* */
  16282. /* Window WATCHDOG */
  16283. /* */
  16284. /******************************************************************************/
  16285. /******************* Bit definition for WWDG_CR register ********************/
  16286. #define WWDG_CR_T_Pos (0U)
  16287. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  16288. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  16289. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
  16290. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
  16291. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
  16292. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
  16293. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
  16294. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
  16295. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
  16296. /* Legacy defines */
  16297. #define WWDG_CR_T0 WWDG_CR_T_0
  16298. #define WWDG_CR_T1 WWDG_CR_T_1
  16299. #define WWDG_CR_T2 WWDG_CR_T_2
  16300. #define WWDG_CR_T3 WWDG_CR_T_3
  16301. #define WWDG_CR_T4 WWDG_CR_T_4
  16302. #define WWDG_CR_T5 WWDG_CR_T_5
  16303. #define WWDG_CR_T6 WWDG_CR_T_6
  16304. #define WWDG_CR_WDGA_Pos (7U)
  16305. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  16306. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  16307. /******************* Bit definition for WWDG_CFR register *******************/
  16308. #define WWDG_CFR_W_Pos (0U)
  16309. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  16310. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  16311. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
  16312. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
  16313. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
  16314. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
  16315. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
  16316. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
  16317. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
  16318. /* Legacy defines */
  16319. #define WWDG_CFR_W0 WWDG_CFR_W_0
  16320. #define WWDG_CFR_W1 WWDG_CFR_W_1
  16321. #define WWDG_CFR_W2 WWDG_CFR_W_2
  16322. #define WWDG_CFR_W3 WWDG_CFR_W_3
  16323. #define WWDG_CFR_W4 WWDG_CFR_W_4
  16324. #define WWDG_CFR_W5 WWDG_CFR_W_5
  16325. #define WWDG_CFR_W6 WWDG_CFR_W_6
  16326. #define WWDG_CFR_WDGTB_Pos (7U)
  16327. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  16328. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  16329. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
  16330. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
  16331. /* Legacy defines */
  16332. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  16333. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  16334. #define WWDG_CFR_EWI_Pos (9U)
  16335. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  16336. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  16337. /******************* Bit definition for WWDG_SR register ********************/
  16338. #define WWDG_SR_EWIF_Pos (0U)
  16339. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  16340. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  16341. /******************************************************************************/
  16342. /* */
  16343. /* DBG */
  16344. /* */
  16345. /******************************************************************************/
  16346. /******************** Bit definition for DBGMCU_IDCODE register *************/
  16347. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  16348. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  16349. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  16350. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  16351. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  16352. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  16353. /******************** Bit definition for DBGMCU_CR register *****************/
  16354. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  16355. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  16356. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  16357. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  16358. #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  16359. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  16360. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  16361. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  16362. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  16363. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  16364. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  16365. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  16366. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  16367. #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  16368. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  16369. #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  16370. #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  16371. /******************** Bit definition for DBGMCU_APB1_FZ register ************/
  16372. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
  16373. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  16374. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
  16375. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
  16376. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  16377. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
  16378. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
  16379. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
  16380. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
  16381. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
  16382. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
  16383. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
  16384. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
  16385. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
  16386. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
  16387. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
  16388. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
  16389. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
  16390. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
  16391. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
  16392. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
  16393. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
  16394. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
  16395. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
  16396. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
  16397. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
  16398. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
  16399. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  16400. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  16401. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
  16402. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  16403. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  16404. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
  16405. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  16406. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  16407. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
  16408. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  16409. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  16410. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
  16411. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
  16412. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
  16413. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
  16414. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
  16415. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
  16416. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
  16417. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
  16418. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
  16419. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
  16420. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
  16421. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
  16422. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
  16423. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
  16424. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
  16425. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
  16426. /* Old IWDGSTOP bit definition, maintained for legacy purpose */
  16427. #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
  16428. /******************** Bit definition for DBGMCU_APB2_FZ register ************/
  16429. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
  16430. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
  16431. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
  16432. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
  16433. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
  16434. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
  16435. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
  16436. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
  16437. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
  16438. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
  16439. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
  16440. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
  16441. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
  16442. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
  16443. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
  16444. /******************************************************************************/
  16445. /* */
  16446. /* Ethernet MAC Registers bits definitions */
  16447. /* */
  16448. /******************************************************************************/
  16449. /* Bit definition for Ethernet MAC Control Register register */
  16450. #define ETH_MACCR_WD_Pos (23U)
  16451. #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
  16452. #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
  16453. #define ETH_MACCR_JD_Pos (22U)
  16454. #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
  16455. #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
  16456. #define ETH_MACCR_IFG_Pos (17U)
  16457. #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
  16458. #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
  16459. #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
  16460. #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
  16461. #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
  16462. #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
  16463. #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
  16464. #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
  16465. #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
  16466. #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
  16467. #define ETH_MACCR_CSD_Pos (16U)
  16468. #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
  16469. #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
  16470. #define ETH_MACCR_FES_Pos (14U)
  16471. #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
  16472. #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
  16473. #define ETH_MACCR_ROD_Pos (13U)
  16474. #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
  16475. #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
  16476. #define ETH_MACCR_LM_Pos (12U)
  16477. #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
  16478. #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
  16479. #define ETH_MACCR_DM_Pos (11U)
  16480. #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
  16481. #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
  16482. #define ETH_MACCR_IPCO_Pos (10U)
  16483. #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
  16484. #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
  16485. #define ETH_MACCR_RD_Pos (9U)
  16486. #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
  16487. #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
  16488. #define ETH_MACCR_APCS_Pos (7U)
  16489. #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
  16490. #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
  16491. #define ETH_MACCR_BL_Pos (5U)
  16492. #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
  16493. #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
  16494. a transmission attempt during retries after a collision: 0 =< r <2^k */
  16495. #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
  16496. #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
  16497. #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
  16498. #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
  16499. #define ETH_MACCR_DC_Pos (4U)
  16500. #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
  16501. #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
  16502. #define ETH_MACCR_TE_Pos (3U)
  16503. #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
  16504. #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
  16505. #define ETH_MACCR_RE_Pos (2U)
  16506. #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
  16507. #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
  16508. /* Bit definition for Ethernet MAC Frame Filter Register */
  16509. #define ETH_MACFFR_RA_Pos (31U)
  16510. #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
  16511. #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
  16512. #define ETH_MACFFR_HPF_Pos (10U)
  16513. #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
  16514. #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
  16515. #define ETH_MACFFR_SAF_Pos (9U)
  16516. #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
  16517. #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
  16518. #define ETH_MACFFR_SAIF_Pos (8U)
  16519. #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
  16520. #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
  16521. #define ETH_MACFFR_PCF_Pos (6U)
  16522. #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
  16523. #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
  16524. #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
  16525. #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
  16526. #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
  16527. #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
  16528. #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
  16529. #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
  16530. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
  16531. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
  16532. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
  16533. #define ETH_MACFFR_BFD_Pos (5U)
  16534. #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
  16535. #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
  16536. #define ETH_MACFFR_PAM_Pos (4U)
  16537. #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
  16538. #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
  16539. #define ETH_MACFFR_DAIF_Pos (3U)
  16540. #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
  16541. #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
  16542. #define ETH_MACFFR_HM_Pos (2U)
  16543. #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
  16544. #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
  16545. #define ETH_MACFFR_HU_Pos (1U)
  16546. #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
  16547. #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
  16548. #define ETH_MACFFR_PM_Pos (0U)
  16549. #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
  16550. #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
  16551. /* Bit definition for Ethernet MAC Hash Table High Register */
  16552. #define ETH_MACHTHR_HTH_Pos (0U)
  16553. #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
  16554. #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
  16555. /* Bit definition for Ethernet MAC Hash Table Low Register */
  16556. #define ETH_MACHTLR_HTL_Pos (0U)
  16557. #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
  16558. #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
  16559. /* Bit definition for Ethernet MAC MII Address Register */
  16560. #define ETH_MACMIIAR_PA_Pos (11U)
  16561. #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
  16562. #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
  16563. #define ETH_MACMIIAR_MR_Pos (6U)
  16564. #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
  16565. #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
  16566. #define ETH_MACMIIAR_CR_Pos (2U)
  16567. #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
  16568. #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
  16569. #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
  16570. #define ETH_MACMIIAR_CR_Div62_Pos (2U)
  16571. #define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
  16572. #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
  16573. #define ETH_MACMIIAR_CR_Div16_Pos (3U)
  16574. #define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
  16575. #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
  16576. #define ETH_MACMIIAR_CR_Div26_Pos (2U)
  16577. #define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
  16578. #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
  16579. #define ETH_MACMIIAR_CR_Div102_Pos (4U)
  16580. #define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
  16581. #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
  16582. #define ETH_MACMIIAR_MW_Pos (1U)
  16583. #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
  16584. #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
  16585. #define ETH_MACMIIAR_MB_Pos (0U)
  16586. #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
  16587. #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
  16588. /* Bit definition for Ethernet MAC MII Data Register */
  16589. #define ETH_MACMIIDR_MD_Pos (0U)
  16590. #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
  16591. #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
  16592. /* Bit definition for Ethernet MAC Flow Control Register */
  16593. #define ETH_MACFCR_PT_Pos (16U)
  16594. #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
  16595. #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
  16596. #define ETH_MACFCR_ZQPD_Pos (7U)
  16597. #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
  16598. #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
  16599. #define ETH_MACFCR_PLT_Pos (4U)
  16600. #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
  16601. #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
  16602. #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
  16603. #define ETH_MACFCR_PLT_Minus28_Pos (4U)
  16604. #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
  16605. #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
  16606. #define ETH_MACFCR_PLT_Minus144_Pos (5U)
  16607. #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
  16608. #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
  16609. #define ETH_MACFCR_PLT_Minus256_Pos (4U)
  16610. #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
  16611. #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
  16612. #define ETH_MACFCR_UPFD_Pos (3U)
  16613. #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
  16614. #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
  16615. #define ETH_MACFCR_RFCE_Pos (2U)
  16616. #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
  16617. #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
  16618. #define ETH_MACFCR_TFCE_Pos (1U)
  16619. #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
  16620. #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
  16621. #define ETH_MACFCR_FCBBPA_Pos (0U)
  16622. #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
  16623. #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
  16624. /* Bit definition for Ethernet MAC VLAN Tag Register */
  16625. #define ETH_MACVLANTR_VLANTC_Pos (16U)
  16626. #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
  16627. #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
  16628. #define ETH_MACVLANTR_VLANTI_Pos (0U)
  16629. #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
  16630. #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
  16631. /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
  16632. #define ETH_MACRWUFFR_D_Pos (0U)
  16633. #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
  16634. #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
  16635. /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
  16636. Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
  16637. /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
  16638. Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
  16639. Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
  16640. Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
  16641. Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
  16642. RSVD - Filter1 Command - RSVD - Filter0 Command
  16643. Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
  16644. Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
  16645. Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
  16646. /* Bit definition for Ethernet MAC PMT Control and Status Register */
  16647. #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
  16648. #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
  16649. #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
  16650. #define ETH_MACPMTCSR_GU_Pos (9U)
  16651. #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
  16652. #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
  16653. #define ETH_MACPMTCSR_WFR_Pos (6U)
  16654. #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
  16655. #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
  16656. #define ETH_MACPMTCSR_MPR_Pos (5U)
  16657. #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
  16658. #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
  16659. #define ETH_MACPMTCSR_WFE_Pos (2U)
  16660. #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
  16661. #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
  16662. #define ETH_MACPMTCSR_MPE_Pos (1U)
  16663. #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
  16664. #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
  16665. #define ETH_MACPMTCSR_PD_Pos (0U)
  16666. #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
  16667. #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
  16668. /* Bit definition for Ethernet MAC debug Register */
  16669. #define ETH_MACDBGR_TFF_Pos (25U)
  16670. #define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
  16671. #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
  16672. #define ETH_MACDBGR_TFNE_Pos (24U)
  16673. #define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
  16674. #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
  16675. #define ETH_MACDBGR_TFWA_Pos (22U)
  16676. #define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
  16677. #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
  16678. #define ETH_MACDBGR_TFRS_Pos (20U)
  16679. #define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
  16680. #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
  16681. #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
  16682. #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
  16683. #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
  16684. #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
  16685. #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
  16686. #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
  16687. #define ETH_MACDBGR_TFRS_READ_Pos (20U)
  16688. #define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
  16689. #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
  16690. #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
  16691. #define ETH_MACDBGR_MTP_Pos (19U)
  16692. #define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
  16693. #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
  16694. #define ETH_MACDBGR_MTFCS_Pos (17U)
  16695. #define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
  16696. #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
  16697. #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
  16698. #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
  16699. #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
  16700. #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
  16701. #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
  16702. #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
  16703. #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
  16704. #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
  16705. #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
  16706. #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
  16707. #define ETH_MACDBGR_MMTEA_Pos (16U)
  16708. #define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
  16709. #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
  16710. #define ETH_MACDBGR_RFFL_Pos (8U)
  16711. #define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
  16712. #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
  16713. #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
  16714. #define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
  16715. #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
  16716. #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
  16717. #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
  16718. #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
  16719. #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
  16720. #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
  16721. #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
  16722. #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
  16723. #define ETH_MACDBGR_RFRCS_Pos (5U)
  16724. #define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
  16725. #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
  16726. #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
  16727. #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
  16728. #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
  16729. #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
  16730. #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
  16731. #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
  16732. #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
  16733. #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
  16734. #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
  16735. #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
  16736. #define ETH_MACDBGR_RFWRA_Pos (4U)
  16737. #define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
  16738. #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
  16739. #define ETH_MACDBGR_MSFRWCS_Pos (1U)
  16740. #define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
  16741. #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
  16742. #define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
  16743. #define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
  16744. #define ETH_MACDBGR_MMRPEA_Pos (0U)
  16745. #define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
  16746. #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
  16747. /* Bit definition for Ethernet MAC Status Register */
  16748. #define ETH_MACSR_TSTS_Pos (9U)
  16749. #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
  16750. #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
  16751. #define ETH_MACSR_MMCTS_Pos (6U)
  16752. #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
  16753. #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
  16754. #define ETH_MACSR_MMMCRS_Pos (5U)
  16755. #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
  16756. #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
  16757. #define ETH_MACSR_MMCS_Pos (4U)
  16758. #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
  16759. #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
  16760. #define ETH_MACSR_PMTS_Pos (3U)
  16761. #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
  16762. #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
  16763. /* Bit definition for Ethernet MAC Interrupt Mask Register */
  16764. #define ETH_MACIMR_TSTIM_Pos (9U)
  16765. #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
  16766. #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
  16767. #define ETH_MACIMR_PMTIM_Pos (3U)
  16768. #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
  16769. #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
  16770. /* Bit definition for Ethernet MAC Address0 High Register */
  16771. #define ETH_MACA0HR_MACA0H_Pos (0U)
  16772. #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
  16773. #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
  16774. /* Bit definition for Ethernet MAC Address0 Low Register */
  16775. #define ETH_MACA0LR_MACA0L_Pos (0U)
  16776. #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
  16777. #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
  16778. /* Bit definition for Ethernet MAC Address1 High Register */
  16779. #define ETH_MACA1HR_AE_Pos (31U)
  16780. #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
  16781. #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
  16782. #define ETH_MACA1HR_SA_Pos (30U)
  16783. #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
  16784. #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
  16785. #define ETH_MACA1HR_MBC_Pos (24U)
  16786. #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
  16787. #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
  16788. #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  16789. #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  16790. #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  16791. #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  16792. #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  16793. #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
  16794. #define ETH_MACA1HR_MACA1H_Pos (0U)
  16795. #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
  16796. #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
  16797. /* Bit definition for Ethernet MAC Address1 Low Register */
  16798. #define ETH_MACA1LR_MACA1L_Pos (0U)
  16799. #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
  16800. #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
  16801. /* Bit definition for Ethernet MAC Address2 High Register */
  16802. #define ETH_MACA2HR_AE_Pos (31U)
  16803. #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
  16804. #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
  16805. #define ETH_MACA2HR_SA_Pos (30U)
  16806. #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
  16807. #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
  16808. #define ETH_MACA2HR_MBC_Pos (24U)
  16809. #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
  16810. #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
  16811. #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  16812. #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  16813. #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  16814. #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  16815. #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  16816. #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
  16817. #define ETH_MACA2HR_MACA2H_Pos (0U)
  16818. #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
  16819. #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
  16820. /* Bit definition for Ethernet MAC Address2 Low Register */
  16821. #define ETH_MACA2LR_MACA2L_Pos (0U)
  16822. #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
  16823. #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
  16824. /* Bit definition for Ethernet MAC Address3 High Register */
  16825. #define ETH_MACA3HR_AE_Pos (31U)
  16826. #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
  16827. #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
  16828. #define ETH_MACA3HR_SA_Pos (30U)
  16829. #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
  16830. #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
  16831. #define ETH_MACA3HR_MBC_Pos (24U)
  16832. #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
  16833. #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
  16834. #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  16835. #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  16836. #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  16837. #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  16838. #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  16839. #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
  16840. #define ETH_MACA3HR_MACA3H_Pos (0U)
  16841. #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
  16842. #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
  16843. /* Bit definition for Ethernet MAC Address3 Low Register */
  16844. #define ETH_MACA3LR_MACA3L_Pos (0U)
  16845. #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
  16846. #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
  16847. /******************************************************************************/
  16848. /* Ethernet MMC Registers bits definition */
  16849. /******************************************************************************/
  16850. /* Bit definition for Ethernet MMC Contol Register */
  16851. #define ETH_MMCCR_MCFHP_Pos (5U)
  16852. #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
  16853. #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
  16854. #define ETH_MMCCR_MCP_Pos (4U)
  16855. #define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
  16856. #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
  16857. #define ETH_MMCCR_MCF_Pos (3U)
  16858. #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
  16859. #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
  16860. #define ETH_MMCCR_ROR_Pos (2U)
  16861. #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
  16862. #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
  16863. #define ETH_MMCCR_CSR_Pos (1U)
  16864. #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
  16865. #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
  16866. #define ETH_MMCCR_CR_Pos (0U)
  16867. #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
  16868. #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
  16869. /* Bit definition for Ethernet MMC Receive Interrupt Register */
  16870. #define ETH_MMCRIR_RGUFS_Pos (17U)
  16871. #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
  16872. #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
  16873. #define ETH_MMCRIR_RFAES_Pos (6U)
  16874. #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
  16875. #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
  16876. #define ETH_MMCRIR_RFCES_Pos (5U)
  16877. #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
  16878. #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
  16879. /* Bit definition for Ethernet MMC Transmit Interrupt Register */
  16880. #define ETH_MMCTIR_TGFS_Pos (21U)
  16881. #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
  16882. #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
  16883. #define ETH_MMCTIR_TGFMSCS_Pos (15U)
  16884. #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
  16885. #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
  16886. #define ETH_MMCTIR_TGFSCS_Pos (14U)
  16887. #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
  16888. #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
  16889. /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
  16890. #define ETH_MMCRIMR_RGUFM_Pos (17U)
  16891. #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
  16892. #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
  16893. #define ETH_MMCRIMR_RFAEM_Pos (6U)
  16894. #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
  16895. #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
  16896. #define ETH_MMCRIMR_RFCEM_Pos (5U)
  16897. #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
  16898. #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
  16899. /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
  16900. #define ETH_MMCTIMR_TGFM_Pos (21U)
  16901. #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
  16902. #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
  16903. #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
  16904. #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
  16905. #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
  16906. #define ETH_MMCTIMR_TGFSCM_Pos (14U)
  16907. #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
  16908. #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
  16909. /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
  16910. #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
  16911. #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
  16912. #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
  16913. /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
  16914. #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
  16915. #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
  16916. #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
  16917. /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
  16918. #define ETH_MMCTGFCR_TGFC_Pos (0U)
  16919. #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
  16920. #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
  16921. /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
  16922. #define ETH_MMCRFCECR_RFCEC_Pos (0U)
  16923. #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
  16924. #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
  16925. /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
  16926. #define ETH_MMCRFAECR_RFAEC_Pos (0U)
  16927. #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
  16928. #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
  16929. /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
  16930. #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
  16931. #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
  16932. #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
  16933. /******************************************************************************/
  16934. /* Ethernet PTP Registers bits definition */
  16935. /******************************************************************************/
  16936. /* Bit definition for Ethernet PTP Time Stamp Contol Register */
  16937. #define ETH_PTPTSCR_TSCNT_Pos (16U)
  16938. #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
  16939. #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
  16940. #define ETH_PTPTSSR_TSSMRME_Pos (15U)
  16941. #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
  16942. #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
  16943. #define ETH_PTPTSSR_TSSEME_Pos (14U)
  16944. #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
  16945. #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
  16946. #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
  16947. #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
  16948. #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
  16949. #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
  16950. #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
  16951. #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
  16952. #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
  16953. #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
  16954. #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
  16955. #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
  16956. #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
  16957. #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
  16958. #define ETH_PTPTSSR_TSSSR_Pos (9U)
  16959. #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
  16960. #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
  16961. #define ETH_PTPTSSR_TSSARFE_Pos (8U)
  16962. #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
  16963. #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
  16964. #define ETH_PTPTSCR_TSARU_Pos (5U)
  16965. #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
  16966. #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
  16967. #define ETH_PTPTSCR_TSITE_Pos (4U)
  16968. #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
  16969. #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
  16970. #define ETH_PTPTSCR_TSSTU_Pos (3U)
  16971. #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
  16972. #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
  16973. #define ETH_PTPTSCR_TSSTI_Pos (2U)
  16974. #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
  16975. #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
  16976. #define ETH_PTPTSCR_TSFCU_Pos (1U)
  16977. #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
  16978. #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
  16979. #define ETH_PTPTSCR_TSE_Pos (0U)
  16980. #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
  16981. #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
  16982. /* Bit definition for Ethernet PTP Sub-Second Increment Register */
  16983. #define ETH_PTPSSIR_STSSI_Pos (0U)
  16984. #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
  16985. #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
  16986. /* Bit definition for Ethernet PTP Time Stamp High Register */
  16987. #define ETH_PTPTSHR_STS_Pos (0U)
  16988. #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
  16989. #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
  16990. /* Bit definition for Ethernet PTP Time Stamp Low Register */
  16991. #define ETH_PTPTSLR_STPNS_Pos (31U)
  16992. #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
  16993. #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
  16994. #define ETH_PTPTSLR_STSS_Pos (0U)
  16995. #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
  16996. #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
  16997. /* Bit definition for Ethernet PTP Time Stamp High Update Register */
  16998. #define ETH_PTPTSHUR_TSUS_Pos (0U)
  16999. #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
  17000. #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
  17001. /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
  17002. #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
  17003. #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
  17004. #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
  17005. #define ETH_PTPTSLUR_TSUSS_Pos (0U)
  17006. #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
  17007. #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
  17008. /* Bit definition for Ethernet PTP Time Stamp Addend Register */
  17009. #define ETH_PTPTSAR_TSA_Pos (0U)
  17010. #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
  17011. #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
  17012. /* Bit definition for Ethernet PTP Target Time High Register */
  17013. #define ETH_PTPTTHR_TTSH_Pos (0U)
  17014. #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
  17015. #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
  17016. /* Bit definition for Ethernet PTP Target Time Low Register */
  17017. #define ETH_PTPTTLR_TTSL_Pos (0U)
  17018. #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
  17019. #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
  17020. /* Bit definition for Ethernet PTP Time Stamp Status Register */
  17021. #define ETH_PTPTSSR_TSTTR_Pos (5U)
  17022. #define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
  17023. #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
  17024. #define ETH_PTPTSSR_TSSO_Pos (4U)
  17025. #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
  17026. #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
  17027. /******************************************************************************/
  17028. /* Ethernet DMA Registers bits definition */
  17029. /******************************************************************************/
  17030. /* Bit definition for Ethernet DMA Bus Mode Register */
  17031. #define ETH_DMABMR_AAB_Pos (25U)
  17032. #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
  17033. #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
  17034. #define ETH_DMABMR_FPM_Pos (24U)
  17035. #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
  17036. #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
  17037. #define ETH_DMABMR_USP_Pos (23U)
  17038. #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
  17039. #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
  17040. #define ETH_DMABMR_RDP_Pos (17U)
  17041. #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
  17042. #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
  17043. #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
  17044. #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
  17045. #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
  17046. #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
  17047. #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
  17048. #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
  17049. #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
  17050. #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
  17051. #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
  17052. #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
  17053. #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
  17054. #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
  17055. #define ETH_DMABMR_FB_Pos (16U)
  17056. #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
  17057. #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
  17058. #define ETH_DMABMR_RTPR_Pos (14U)
  17059. #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
  17060. #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
  17061. #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
  17062. #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
  17063. #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
  17064. #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
  17065. #define ETH_DMABMR_PBL_Pos (8U)
  17066. #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
  17067. #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
  17068. #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
  17069. #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
  17070. #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
  17071. #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
  17072. #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
  17073. #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
  17074. #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
  17075. #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
  17076. #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
  17077. #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
  17078. #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
  17079. #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
  17080. #define ETH_DMABMR_EDE_Pos (7U)
  17081. #define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
  17082. #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
  17083. #define ETH_DMABMR_DSL_Pos (2U)
  17084. #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
  17085. #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
  17086. #define ETH_DMABMR_DA_Pos (1U)
  17087. #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
  17088. #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
  17089. #define ETH_DMABMR_SR_Pos (0U)
  17090. #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
  17091. #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
  17092. /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
  17093. #define ETH_DMATPDR_TPD_Pos (0U)
  17094. #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
  17095. #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
  17096. /* Bit definition for Ethernet DMA Receive Poll Demand Register */
  17097. #define ETH_DMARPDR_RPD_Pos (0U)
  17098. #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
  17099. #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
  17100. /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
  17101. #define ETH_DMARDLAR_SRL_Pos (0U)
  17102. #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
  17103. #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
  17104. /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
  17105. #define ETH_DMATDLAR_STL_Pos (0U)
  17106. #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
  17107. #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
  17108. /* Bit definition for Ethernet DMA Status Register */
  17109. #define ETH_DMASR_TSTS_Pos (29U)
  17110. #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
  17111. #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
  17112. #define ETH_DMASR_PMTS_Pos (28U)
  17113. #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
  17114. #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
  17115. #define ETH_DMASR_MMCS_Pos (27U)
  17116. #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
  17117. #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
  17118. #define ETH_DMASR_EBS_Pos (23U)
  17119. #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
  17120. #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
  17121. /* combination with EBS[2:0] for GetFlagStatus function */
  17122. #define ETH_DMASR_EBS_DescAccess_Pos (25U)
  17123. #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
  17124. #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
  17125. #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
  17126. #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
  17127. #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
  17128. #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
  17129. #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
  17130. #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
  17131. #define ETH_DMASR_TPS_Pos (20U)
  17132. #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
  17133. #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
  17134. #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
  17135. #define ETH_DMASR_TPS_Fetching_Pos (20U)
  17136. #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
  17137. #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
  17138. #define ETH_DMASR_TPS_Waiting_Pos (21U)
  17139. #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
  17140. #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
  17141. #define ETH_DMASR_TPS_Reading_Pos (20U)
  17142. #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
  17143. #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
  17144. #define ETH_DMASR_TPS_Suspended_Pos (21U)
  17145. #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
  17146. #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
  17147. #define ETH_DMASR_TPS_Closing_Pos (20U)
  17148. #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
  17149. #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
  17150. #define ETH_DMASR_RPS_Pos (17U)
  17151. #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
  17152. #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
  17153. #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
  17154. #define ETH_DMASR_RPS_Fetching_Pos (17U)
  17155. #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
  17156. #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
  17157. #define ETH_DMASR_RPS_Waiting_Pos (17U)
  17158. #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
  17159. #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
  17160. #define ETH_DMASR_RPS_Suspended_Pos (19U)
  17161. #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
  17162. #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
  17163. #define ETH_DMASR_RPS_Closing_Pos (17U)
  17164. #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
  17165. #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
  17166. #define ETH_DMASR_RPS_Queuing_Pos (17U)
  17167. #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
  17168. #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
  17169. #define ETH_DMASR_NIS_Pos (16U)
  17170. #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
  17171. #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
  17172. #define ETH_DMASR_AIS_Pos (15U)
  17173. #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
  17174. #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
  17175. #define ETH_DMASR_ERS_Pos (14U)
  17176. #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
  17177. #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
  17178. #define ETH_DMASR_FBES_Pos (13U)
  17179. #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
  17180. #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
  17181. #define ETH_DMASR_ETS_Pos (10U)
  17182. #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
  17183. #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
  17184. #define ETH_DMASR_RWTS_Pos (9U)
  17185. #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
  17186. #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
  17187. #define ETH_DMASR_RPSS_Pos (8U)
  17188. #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
  17189. #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
  17190. #define ETH_DMASR_RBUS_Pos (7U)
  17191. #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
  17192. #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
  17193. #define ETH_DMASR_RS_Pos (6U)
  17194. #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
  17195. #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
  17196. #define ETH_DMASR_TUS_Pos (5U)
  17197. #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
  17198. #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
  17199. #define ETH_DMASR_ROS_Pos (4U)
  17200. #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
  17201. #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
  17202. #define ETH_DMASR_TJTS_Pos (3U)
  17203. #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
  17204. #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
  17205. #define ETH_DMASR_TBUS_Pos (2U)
  17206. #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
  17207. #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
  17208. #define ETH_DMASR_TPSS_Pos (1U)
  17209. #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
  17210. #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
  17211. #define ETH_DMASR_TS_Pos (0U)
  17212. #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
  17213. #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
  17214. /* Bit definition for Ethernet DMA Operation Mode Register */
  17215. #define ETH_DMAOMR_DTCEFD_Pos (26U)
  17216. #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
  17217. #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
  17218. #define ETH_DMAOMR_RSF_Pos (25U)
  17219. #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
  17220. #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
  17221. #define ETH_DMAOMR_DFRF_Pos (24U)
  17222. #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
  17223. #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
  17224. #define ETH_DMAOMR_TSF_Pos (21U)
  17225. #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
  17226. #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
  17227. #define ETH_DMAOMR_FTF_Pos (20U)
  17228. #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
  17229. #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
  17230. #define ETH_DMAOMR_TTC_Pos (14U)
  17231. #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
  17232. #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
  17233. #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
  17234. #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
  17235. #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
  17236. #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
  17237. #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
  17238. #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
  17239. #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
  17240. #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
  17241. #define ETH_DMAOMR_ST_Pos (13U)
  17242. #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
  17243. #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
  17244. #define ETH_DMAOMR_FEF_Pos (7U)
  17245. #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
  17246. #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
  17247. #define ETH_DMAOMR_FUGF_Pos (6U)
  17248. #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
  17249. #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
  17250. #define ETH_DMAOMR_RTC_Pos (3U)
  17251. #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
  17252. #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
  17253. #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
  17254. #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
  17255. #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
  17256. #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
  17257. #define ETH_DMAOMR_OSF_Pos (2U)
  17258. #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
  17259. #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
  17260. #define ETH_DMAOMR_SR_Pos (1U)
  17261. #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
  17262. #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
  17263. /* Bit definition for Ethernet DMA Interrupt Enable Register */
  17264. #define ETH_DMAIER_NISE_Pos (16U)
  17265. #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
  17266. #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
  17267. #define ETH_DMAIER_AISE_Pos (15U)
  17268. #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
  17269. #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
  17270. #define ETH_DMAIER_ERIE_Pos (14U)
  17271. #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
  17272. #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
  17273. #define ETH_DMAIER_FBEIE_Pos (13U)
  17274. #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
  17275. #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
  17276. #define ETH_DMAIER_ETIE_Pos (10U)
  17277. #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
  17278. #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
  17279. #define ETH_DMAIER_RWTIE_Pos (9U)
  17280. #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
  17281. #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
  17282. #define ETH_DMAIER_RPSIE_Pos (8U)
  17283. #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
  17284. #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
  17285. #define ETH_DMAIER_RBUIE_Pos (7U)
  17286. #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
  17287. #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
  17288. #define ETH_DMAIER_RIE_Pos (6U)
  17289. #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
  17290. #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
  17291. #define ETH_DMAIER_TUIE_Pos (5U)
  17292. #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
  17293. #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
  17294. #define ETH_DMAIER_ROIE_Pos (4U)
  17295. #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
  17296. #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
  17297. #define ETH_DMAIER_TJTIE_Pos (3U)
  17298. #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
  17299. #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
  17300. #define ETH_DMAIER_TBUIE_Pos (2U)
  17301. #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
  17302. #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
  17303. #define ETH_DMAIER_TPSIE_Pos (1U)
  17304. #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
  17305. #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
  17306. #define ETH_DMAIER_TIE_Pos (0U)
  17307. #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
  17308. #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
  17309. /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
  17310. #define ETH_DMAMFBOCR_OFOC_Pos (28U)
  17311. #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
  17312. #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
  17313. #define ETH_DMAMFBOCR_MFA_Pos (17U)
  17314. #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
  17315. #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
  17316. #define ETH_DMAMFBOCR_OMFC_Pos (16U)
  17317. #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
  17318. #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
  17319. #define ETH_DMAMFBOCR_MFC_Pos (0U)
  17320. #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
  17321. #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
  17322. /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
  17323. #define ETH_DMACHTDR_HTDAP_Pos (0U)
  17324. #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
  17325. #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
  17326. /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
  17327. #define ETH_DMACHRDR_HRDAP_Pos (0U)
  17328. #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
  17329. #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
  17330. /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
  17331. #define ETH_DMACHTBAR_HTBAP_Pos (0U)
  17332. #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
  17333. #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
  17334. /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
  17335. #define ETH_DMACHRBAR_HRBAP_Pos (0U)
  17336. #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
  17337. #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
  17338. /******************************************************************************/
  17339. /* */
  17340. /* USB_OTG */
  17341. /* */
  17342. /******************************************************************************/
  17343. /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
  17344. #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
  17345. #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
  17346. #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
  17347. #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
  17348. #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
  17349. #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
  17350. #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
  17351. #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
  17352. #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
  17353. #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
  17354. #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
  17355. #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
  17356. #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
  17357. #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
  17358. #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
  17359. #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
  17360. #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
  17361. #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
  17362. #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
  17363. #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
  17364. #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
  17365. #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
  17366. #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
  17367. #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
  17368. #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
  17369. #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
  17370. #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
  17371. #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
  17372. #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
  17373. #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
  17374. #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
  17375. #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
  17376. #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
  17377. #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
  17378. #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
  17379. #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
  17380. #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
  17381. #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
  17382. #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
  17383. #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
  17384. #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
  17385. #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
  17386. #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
  17387. #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
  17388. #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
  17389. #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
  17390. #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
  17391. #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
  17392. #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
  17393. #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
  17394. #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
  17395. #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
  17396. #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
  17397. #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
  17398. /******************** Bit definition forUSB_OTG_HCFG register ********************/
  17399. #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
  17400. #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
  17401. #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
  17402. #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
  17403. #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
  17404. #define USB_OTG_HCFG_FSLSS_Pos (2U)
  17405. #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
  17406. #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
  17407. /******************** Bit definition for USB_OTG_DCFG register ********************/
  17408. #define USB_OTG_DCFG_DSPD_Pos (0U)
  17409. #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
  17410. #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
  17411. #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
  17412. #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
  17413. #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
  17414. #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
  17415. #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
  17416. #define USB_OTG_DCFG_DAD_Pos (4U)
  17417. #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
  17418. #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
  17419. #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
  17420. #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
  17421. #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
  17422. #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
  17423. #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
  17424. #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
  17425. #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
  17426. #define USB_OTG_DCFG_PFIVL_Pos (11U)
  17427. #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
  17428. #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
  17429. #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
  17430. #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
  17431. #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
  17432. #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
  17433. #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
  17434. #define USB_OTG_DCFG_ERRATIM_Pos (15U)
  17435. #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
  17436. #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
  17437. #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
  17438. #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
  17439. #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
  17440. #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
  17441. #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
  17442. /******************** Bit definition for USB_OTG_PCGCR register ********************/
  17443. #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
  17444. #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
  17445. #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
  17446. #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
  17447. #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
  17448. #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
  17449. #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
  17450. #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
  17451. #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
  17452. /******************** Bit definition for USB_OTG_GOTGINT register ********************/
  17453. #define USB_OTG_GOTGINT_SEDET_Pos (2U)
  17454. #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
  17455. #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
  17456. #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
  17457. #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
  17458. #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
  17459. #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
  17460. #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
  17461. #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
  17462. #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
  17463. #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
  17464. #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
  17465. #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
  17466. #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
  17467. #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
  17468. #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
  17469. #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
  17470. #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
  17471. #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
  17472. #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
  17473. #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
  17474. /******************** Bit definition for USB_OTG_DCTL register ********************/
  17475. #define USB_OTG_DCTL_RWUSIG_Pos (0U)
  17476. #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
  17477. #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
  17478. #define USB_OTG_DCTL_SDIS_Pos (1U)
  17479. #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
  17480. #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
  17481. #define USB_OTG_DCTL_GINSTS_Pos (2U)
  17482. #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
  17483. #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
  17484. #define USB_OTG_DCTL_GONSTS_Pos (3U)
  17485. #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
  17486. #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
  17487. #define USB_OTG_DCTL_TCTL_Pos (4U)
  17488. #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
  17489. #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
  17490. #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
  17491. #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
  17492. #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
  17493. #define USB_OTG_DCTL_SGINAK_Pos (7U)
  17494. #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
  17495. #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
  17496. #define USB_OTG_DCTL_CGINAK_Pos (8U)
  17497. #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
  17498. #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
  17499. #define USB_OTG_DCTL_SGONAK_Pos (9U)
  17500. #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
  17501. #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
  17502. #define USB_OTG_DCTL_CGONAK_Pos (10U)
  17503. #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
  17504. #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
  17505. #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
  17506. #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
  17507. #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
  17508. /******************** Bit definition for USB_OTG_HFIR register ********************/
  17509. #define USB_OTG_HFIR_FRIVL_Pos (0U)
  17510. #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
  17511. #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
  17512. /******************** Bit definition for USB_OTG_HFNUM register ********************/
  17513. #define USB_OTG_HFNUM_FRNUM_Pos (0U)
  17514. #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
  17515. #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
  17516. #define USB_OTG_HFNUM_FTREM_Pos (16U)
  17517. #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
  17518. #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
  17519. /******************** Bit definition for USB_OTG_DSTS register ********************/
  17520. #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
  17521. #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
  17522. #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
  17523. #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
  17524. #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
  17525. #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
  17526. #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
  17527. #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
  17528. #define USB_OTG_DSTS_EERR_Pos (3U)
  17529. #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
  17530. #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
  17531. #define USB_OTG_DSTS_FNSOF_Pos (8U)
  17532. #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
  17533. #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
  17534. /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
  17535. #define USB_OTG_GAHBCFG_GINT_Pos (0U)
  17536. #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
  17537. #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
  17538. #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
  17539. #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
  17540. #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
  17541. #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
  17542. #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
  17543. #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
  17544. #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
  17545. #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
  17546. #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
  17547. #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
  17548. #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
  17549. #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
  17550. #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
  17551. #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
  17552. #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
  17553. #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
  17554. #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
  17555. /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
  17556. #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
  17557. #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
  17558. #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
  17559. #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
  17560. #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
  17561. #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
  17562. #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
  17563. #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
  17564. #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
  17565. #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
  17566. #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
  17567. #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
  17568. #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
  17569. #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
  17570. #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
  17571. #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
  17572. #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
  17573. #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
  17574. #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
  17575. #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
  17576. #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
  17577. #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
  17578. #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
  17579. #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
  17580. #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
  17581. #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
  17582. #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
  17583. #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
  17584. #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
  17585. #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
  17586. #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
  17587. #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
  17588. #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
  17589. #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
  17590. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
  17591. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
  17592. #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
  17593. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
  17594. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
  17595. #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
  17596. #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
  17597. #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
  17598. #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
  17599. #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
  17600. #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
  17601. #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
  17602. #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
  17603. #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
  17604. #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
  17605. #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
  17606. #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
  17607. #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
  17608. #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
  17609. #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
  17610. #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
  17611. #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
  17612. #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
  17613. #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
  17614. #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
  17615. #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
  17616. #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
  17617. /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
  17618. #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
  17619. #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
  17620. #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
  17621. #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
  17622. #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
  17623. #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
  17624. #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
  17625. #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
  17626. #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
  17627. #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
  17628. #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
  17629. #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
  17630. #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
  17631. #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
  17632. #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
  17633. #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
  17634. #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
  17635. #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
  17636. #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
  17637. #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
  17638. #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
  17639. #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
  17640. #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
  17641. #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
  17642. #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
  17643. #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
  17644. #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
  17645. #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
  17646. #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
  17647. /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
  17648. #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
  17649. #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  17650. #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  17651. #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
  17652. #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
  17653. #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  17654. #define USB_OTG_DIEPMSK_TOM_Pos (3U)
  17655. #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
  17656. #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  17657. #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
  17658. #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
  17659. #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  17660. #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
  17661. #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
  17662. #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  17663. #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
  17664. #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
  17665. #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  17666. #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
  17667. #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
  17668. #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
  17669. #define USB_OTG_DIEPMSK_BIM_Pos (9U)
  17670. #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
  17671. #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
  17672. /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
  17673. #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
  17674. #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
  17675. #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
  17676. #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
  17677. #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
  17678. #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
  17679. #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
  17680. #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
  17681. #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
  17682. #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
  17683. #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
  17684. #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
  17685. #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
  17686. #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
  17687. #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
  17688. #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
  17689. #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
  17690. #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
  17691. #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
  17692. #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
  17693. #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
  17694. #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
  17695. #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
  17696. #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
  17697. #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
  17698. /******************** Bit definition for USB_OTG_HAINT register ********************/
  17699. #define USB_OTG_HAINT_HAINT_Pos (0U)
  17700. #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
  17701. #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
  17702. /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
  17703. #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
  17704. #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  17705. #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  17706. #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
  17707. #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
  17708. #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  17709. #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
  17710. #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
  17711. #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
  17712. #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
  17713. #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
  17714. #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
  17715. #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
  17716. #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
  17717. #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
  17718. #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
  17719. #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
  17720. #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
  17721. #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
  17722. #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
  17723. #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
  17724. #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
  17725. #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
  17726. #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
  17727. #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
  17728. #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
  17729. #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
  17730. #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
  17731. #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
  17732. #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
  17733. #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
  17734. #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
  17735. #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
  17736. #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
  17737. #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
  17738. #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
  17739. /******************** Bit definition for USB_OTG_GINTSTS register ********************/
  17740. #define USB_OTG_GINTSTS_CMOD_Pos (0U)
  17741. #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
  17742. #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
  17743. #define USB_OTG_GINTSTS_MMIS_Pos (1U)
  17744. #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
  17745. #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
  17746. #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
  17747. #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
  17748. #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
  17749. #define USB_OTG_GINTSTS_SOF_Pos (3U)
  17750. #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
  17751. #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
  17752. #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
  17753. #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
  17754. #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
  17755. #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
  17756. #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
  17757. #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
  17758. #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
  17759. #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
  17760. #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
  17761. #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
  17762. #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
  17763. #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
  17764. #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
  17765. #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
  17766. #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
  17767. #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
  17768. #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
  17769. #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
  17770. #define USB_OTG_GINTSTS_USBRST_Pos (12U)
  17771. #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
  17772. #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
  17773. #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
  17774. #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
  17775. #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
  17776. #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
  17777. #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
  17778. #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
  17779. #define USB_OTG_GINTSTS_EOPF_Pos (15U)
  17780. #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
  17781. #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
  17782. #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
  17783. #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
  17784. #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
  17785. #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
  17786. #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
  17787. #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
  17788. #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
  17789. #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
  17790. #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
  17791. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
  17792. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
  17793. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
  17794. #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
  17795. #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
  17796. #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
  17797. #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
  17798. #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
  17799. #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
  17800. #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
  17801. #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
  17802. #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
  17803. #define USB_OTG_GINTSTS_HCINT_Pos (25U)
  17804. #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
  17805. #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
  17806. #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
  17807. #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
  17808. #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
  17809. #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
  17810. #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
  17811. #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
  17812. #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
  17813. #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
  17814. #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
  17815. #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
  17816. #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
  17817. #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
  17818. #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
  17819. #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
  17820. #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
  17821. #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
  17822. #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
  17823. #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
  17824. /******************** Bit definition for USB_OTG_GINTMSK register ********************/
  17825. #define USB_OTG_GINTMSK_MMISM_Pos (1U)
  17826. #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
  17827. #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
  17828. #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
  17829. #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
  17830. #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
  17831. #define USB_OTG_GINTMSK_SOFM_Pos (3U)
  17832. #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
  17833. #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
  17834. #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
  17835. #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
  17836. #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
  17837. #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
  17838. #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
  17839. #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
  17840. #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
  17841. #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
  17842. #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
  17843. #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
  17844. #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
  17845. #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
  17846. #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
  17847. #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
  17848. #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
  17849. #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
  17850. #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
  17851. #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
  17852. #define USB_OTG_GINTMSK_USBRST_Pos (12U)
  17853. #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
  17854. #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
  17855. #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
  17856. #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
  17857. #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
  17858. #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
  17859. #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
  17860. #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
  17861. #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
  17862. #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
  17863. #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
  17864. #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
  17865. #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
  17866. #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
  17867. #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
  17868. #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
  17869. #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
  17870. #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
  17871. #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
  17872. #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
  17873. #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
  17874. #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
  17875. #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
  17876. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
  17877. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
  17878. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
  17879. #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
  17880. #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
  17881. #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
  17882. #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
  17883. #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
  17884. #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
  17885. #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
  17886. #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
  17887. #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
  17888. #define USB_OTG_GINTMSK_HCIM_Pos (25U)
  17889. #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
  17890. #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
  17891. #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
  17892. #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
  17893. #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
  17894. #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
  17895. #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
  17896. #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
  17897. #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
  17898. #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
  17899. #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
  17900. #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
  17901. #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
  17902. #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
  17903. #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
  17904. #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
  17905. #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
  17906. #define USB_OTG_GINTMSK_WUIM_Pos (31U)
  17907. #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
  17908. #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
  17909. /******************** Bit definition for USB_OTG_DAINT register ********************/
  17910. #define USB_OTG_DAINT_IEPINT_Pos (0U)
  17911. #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
  17912. #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
  17913. #define USB_OTG_DAINT_OEPINT_Pos (16U)
  17914. #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
  17915. #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
  17916. /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
  17917. #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
  17918. #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
  17919. #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
  17920. /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
  17921. #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
  17922. #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
  17923. #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
  17924. #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
  17925. #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
  17926. #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
  17927. #define USB_OTG_GRXSTSP_DPID_Pos (15U)
  17928. #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
  17929. #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
  17930. #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
  17931. #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
  17932. #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
  17933. /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
  17934. #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
  17935. #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
  17936. #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
  17937. #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
  17938. #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
  17939. #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
  17940. /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
  17941. #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
  17942. #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
  17943. #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
  17944. /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
  17945. #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
  17946. #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
  17947. #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
  17948. /******************** Bit definition for OTG register ********************/
  17949. #define USB_OTG_NPTXFSA_Pos (0U)
  17950. #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
  17951. #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
  17952. #define USB_OTG_NPTXFD_Pos (16U)
  17953. #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
  17954. #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
  17955. #define USB_OTG_TX0FSA_Pos (0U)
  17956. #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
  17957. #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
  17958. #define USB_OTG_TX0FD_Pos (16U)
  17959. #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
  17960. #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
  17961. /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
  17962. #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
  17963. #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
  17964. #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
  17965. /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
  17966. #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
  17967. #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
  17968. #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
  17969. #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
  17970. #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
  17971. #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
  17972. #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
  17973. #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
  17974. #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
  17975. #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
  17976. #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
  17977. #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
  17978. #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
  17979. #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
  17980. #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
  17981. #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
  17982. #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
  17983. #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
  17984. #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
  17985. #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
  17986. #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
  17987. #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
  17988. #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
  17989. #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
  17990. /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
  17991. #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
  17992. #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
  17993. #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
  17994. #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
  17995. #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
  17996. #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
  17997. #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
  17998. #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
  17999. #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
  18000. #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
  18001. #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
  18002. #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
  18003. #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
  18004. #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
  18005. #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
  18006. #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
  18007. #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
  18008. #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
  18009. #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
  18010. #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
  18011. #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
  18012. #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
  18013. #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
  18014. #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
  18015. #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
  18016. #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
  18017. #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
  18018. #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
  18019. #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
  18020. #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
  18021. #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
  18022. #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
  18023. #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
  18024. #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
  18025. #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
  18026. #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
  18027. /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
  18028. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
  18029. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
  18030. #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
  18031. /******************** Bit definition for USB_OTG_DEACHINT register ********************/
  18032. #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
  18033. #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
  18034. #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
  18035. #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
  18036. #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
  18037. #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
  18038. /******************** Bit definition for USB_OTG_GCCFG register ********************/
  18039. #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
  18040. #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
  18041. #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
  18042. #define USB_OTG_GCCFG_VBDEN_Pos (21U)
  18043. #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
  18044. #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
  18045. /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
  18046. #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
  18047. #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
  18048. #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
  18049. #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
  18050. #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
  18051. #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
  18052. /******************** Bit definition for USB_OTG_CID register ********************/
  18053. #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
  18054. #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
  18055. #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
  18056. /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
  18057. #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
  18058. #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
  18059. #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
  18060. #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
  18061. #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
  18062. #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
  18063. #define USB_OTG_GLPMCFG_BESL_Pos (2U)
  18064. #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
  18065. #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
  18066. #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
  18067. #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
  18068. #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
  18069. #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
  18070. #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
  18071. #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
  18072. #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
  18073. #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
  18074. #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
  18075. #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
  18076. #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
  18077. #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
  18078. #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
  18079. #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
  18080. #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
  18081. #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
  18082. #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
  18083. #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
  18084. #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
  18085. #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
  18086. #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
  18087. #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
  18088. #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
  18089. #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
  18090. #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
  18091. #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
  18092. #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
  18093. #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
  18094. #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
  18095. #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
  18096. #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
  18097. #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
  18098. #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
  18099. #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
  18100. #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
  18101. #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
  18102. /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
  18103. #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
  18104. #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  18105. #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  18106. #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
  18107. #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  18108. #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  18109. #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
  18110. #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  18111. #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  18112. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
  18113. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  18114. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  18115. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
  18116. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  18117. #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  18118. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
  18119. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  18120. #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  18121. #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
  18122. #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  18123. #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
  18124. #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
  18125. #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  18126. #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  18127. #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
  18128. #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  18129. #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  18130. /******************** Bit definition for USB_OTG_HPRT register ********************/
  18131. #define USB_OTG_HPRT_PCSTS_Pos (0U)
  18132. #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
  18133. #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
  18134. #define USB_OTG_HPRT_PCDET_Pos (1U)
  18135. #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
  18136. #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
  18137. #define USB_OTG_HPRT_PENA_Pos (2U)
  18138. #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
  18139. #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
  18140. #define USB_OTG_HPRT_PENCHNG_Pos (3U)
  18141. #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
  18142. #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
  18143. #define USB_OTG_HPRT_POCA_Pos (4U)
  18144. #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
  18145. #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
  18146. #define USB_OTG_HPRT_POCCHNG_Pos (5U)
  18147. #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
  18148. #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
  18149. #define USB_OTG_HPRT_PRES_Pos (6U)
  18150. #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
  18151. #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
  18152. #define USB_OTG_HPRT_PSUSP_Pos (7U)
  18153. #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
  18154. #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
  18155. #define USB_OTG_HPRT_PRST_Pos (8U)
  18156. #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
  18157. #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
  18158. #define USB_OTG_HPRT_PLSTS_Pos (10U)
  18159. #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
  18160. #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
  18161. #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
  18162. #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
  18163. #define USB_OTG_HPRT_PPWR_Pos (12U)
  18164. #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
  18165. #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
  18166. #define USB_OTG_HPRT_PTCTL_Pos (13U)
  18167. #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
  18168. #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
  18169. #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
  18170. #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
  18171. #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
  18172. #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
  18173. #define USB_OTG_HPRT_PSPD_Pos (17U)
  18174. #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
  18175. #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
  18176. #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
  18177. #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
  18178. /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
  18179. #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
  18180. #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  18181. #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  18182. #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
  18183. #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  18184. #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  18185. #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
  18186. #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  18187. #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
  18188. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
  18189. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  18190. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  18191. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
  18192. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  18193. #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  18194. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
  18195. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  18196. #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  18197. #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
  18198. #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  18199. #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
  18200. #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
  18201. #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  18202. #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  18203. #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
  18204. #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
  18205. #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
  18206. #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
  18207. #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  18208. #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  18209. #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
  18210. #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
  18211. #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
  18212. /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
  18213. #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
  18214. #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
  18215. #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
  18216. #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
  18217. #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
  18218. #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
  18219. /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
  18220. #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
  18221. #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  18222. #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
  18223. #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
  18224. #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  18225. #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
  18226. #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
  18227. #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
  18228. #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
  18229. #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
  18230. #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  18231. #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
  18232. #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
  18233. #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  18234. #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
  18235. #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  18236. #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  18237. #define USB_OTG_DIEPCTL_STALL_Pos (21U)
  18238. #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
  18239. #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
  18240. #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
  18241. #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
  18242. #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
  18243. #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
  18244. #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
  18245. #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
  18246. #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
  18247. #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
  18248. #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
  18249. #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
  18250. #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
  18251. #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
  18252. #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
  18253. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
  18254. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  18255. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  18256. #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
  18257. #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  18258. #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
  18259. #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
  18260. #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  18261. #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
  18262. #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
  18263. #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
  18264. #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
  18265. /******************** Bit definition for USB_OTG_HCCHAR register ********************/
  18266. #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
  18267. #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
  18268. #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
  18269. #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
  18270. #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
  18271. #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
  18272. #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
  18273. #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
  18274. #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
  18275. #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
  18276. #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
  18277. #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
  18278. #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
  18279. #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
  18280. #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
  18281. #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
  18282. #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
  18283. #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
  18284. #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
  18285. #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
  18286. #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
  18287. #define USB_OTG_HCCHAR_MC_Pos (20U)
  18288. #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
  18289. #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
  18290. #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
  18291. #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
  18292. #define USB_OTG_HCCHAR_DAD_Pos (22U)
  18293. #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
  18294. #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
  18295. #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
  18296. #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
  18297. #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
  18298. #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
  18299. #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
  18300. #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
  18301. #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
  18302. #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
  18303. #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
  18304. #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
  18305. #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
  18306. #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
  18307. #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
  18308. #define USB_OTG_HCCHAR_CHENA_Pos (31U)
  18309. #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
  18310. #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
  18311. /******************** Bit definition for USB_OTG_HCSPLT register ********************/
  18312. #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
  18313. #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
  18314. #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
  18315. #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
  18316. #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
  18317. #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
  18318. #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
  18319. #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
  18320. #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
  18321. #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
  18322. #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
  18323. #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
  18324. #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
  18325. #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
  18326. #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
  18327. #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
  18328. #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
  18329. #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
  18330. #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
  18331. #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
  18332. #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
  18333. #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
  18334. #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
  18335. #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
  18336. #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
  18337. #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
  18338. #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
  18339. #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
  18340. #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
  18341. #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
  18342. #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
  18343. /******************** Bit definition for USB_OTG_HCINT register ********************/
  18344. #define USB_OTG_HCINT_XFRC_Pos (0U)
  18345. #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
  18346. #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
  18347. #define USB_OTG_HCINT_CHH_Pos (1U)
  18348. #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
  18349. #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
  18350. #define USB_OTG_HCINT_AHBERR_Pos (2U)
  18351. #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
  18352. #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
  18353. #define USB_OTG_HCINT_STALL_Pos (3U)
  18354. #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
  18355. #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
  18356. #define USB_OTG_HCINT_NAK_Pos (4U)
  18357. #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
  18358. #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
  18359. #define USB_OTG_HCINT_ACK_Pos (5U)
  18360. #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
  18361. #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
  18362. #define USB_OTG_HCINT_NYET_Pos (6U)
  18363. #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
  18364. #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
  18365. #define USB_OTG_HCINT_TXERR_Pos (7U)
  18366. #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
  18367. #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
  18368. #define USB_OTG_HCINT_BBERR_Pos (8U)
  18369. #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
  18370. #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
  18371. #define USB_OTG_HCINT_FRMOR_Pos (9U)
  18372. #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
  18373. #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
  18374. #define USB_OTG_HCINT_DTERR_Pos (10U)
  18375. #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
  18376. #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
  18377. /******************** Bit definition for USB_OTG_DIEPINT register ********************/
  18378. #define USB_OTG_DIEPINT_XFRC_Pos (0U)
  18379. #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
  18380. #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  18381. #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
  18382. #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
  18383. #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  18384. #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
  18385. #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
  18386. #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
  18387. #define USB_OTG_DIEPINT_TOC_Pos (3U)
  18388. #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
  18389. #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
  18390. #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
  18391. #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
  18392. #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
  18393. #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
  18394. #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
  18395. #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
  18396. #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
  18397. #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
  18398. #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
  18399. #define USB_OTG_DIEPINT_TXFE_Pos (7U)
  18400. #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
  18401. #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
  18402. #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
  18403. #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
  18404. #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
  18405. #define USB_OTG_DIEPINT_BNA_Pos (9U)
  18406. #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
  18407. #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
  18408. #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
  18409. #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
  18410. #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
  18411. #define USB_OTG_DIEPINT_BERR_Pos (12U)
  18412. #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
  18413. #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
  18414. #define USB_OTG_DIEPINT_NAK_Pos (13U)
  18415. #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
  18416. #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
  18417. /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
  18418. #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
  18419. #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
  18420. #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
  18421. #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
  18422. #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
  18423. #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
  18424. #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
  18425. #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
  18426. #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
  18427. #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
  18428. #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
  18429. #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
  18430. #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
  18431. #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
  18432. #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
  18433. #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
  18434. #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
  18435. #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
  18436. #define USB_OTG_HCINTMSK_NYET_Pos (6U)
  18437. #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
  18438. #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
  18439. #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
  18440. #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
  18441. #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
  18442. #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
  18443. #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
  18444. #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
  18445. #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
  18446. #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
  18447. #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
  18448. #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
  18449. #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
  18450. #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
  18451. /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
  18452. #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
  18453. #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  18454. #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  18455. #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
  18456. #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  18457. #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
  18458. #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
  18459. #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
  18460. #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
  18461. /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
  18462. #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
  18463. #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  18464. #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
  18465. #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
  18466. #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  18467. #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
  18468. #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
  18469. #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
  18470. #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
  18471. #define USB_OTG_HCTSIZ_DPID_Pos (29U)
  18472. #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
  18473. #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
  18474. #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
  18475. #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
  18476. /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
  18477. #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
  18478. #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  18479. #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
  18480. /******************** Bit definition for USB_OTG_HCDMA register ********************/
  18481. #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
  18482. #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  18483. #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
  18484. /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
  18485. #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
  18486. #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
  18487. #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
  18488. /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
  18489. #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
  18490. #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
  18491. #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
  18492. #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
  18493. #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
  18494. #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
  18495. /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
  18496. #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
  18497. #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  18498. #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
  18499. #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
  18500. #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  18501. #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
  18502. #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
  18503. #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  18504. #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
  18505. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
  18506. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  18507. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  18508. #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
  18509. #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  18510. #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
  18511. #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
  18512. #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  18513. #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
  18514. #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  18515. #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  18516. #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
  18517. #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
  18518. #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
  18519. #define USB_OTG_DOEPCTL_STALL_Pos (21U)
  18520. #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
  18521. #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
  18522. #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
  18523. #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
  18524. #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
  18525. #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
  18526. #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
  18527. #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
  18528. #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
  18529. #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  18530. #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
  18531. #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
  18532. #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
  18533. #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
  18534. /******************** Bit definition for USB_OTG_DOEPINT register ********************/
  18535. #define USB_OTG_DOEPINT_XFRC_Pos (0U)
  18536. #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
  18537. #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  18538. #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
  18539. #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
  18540. #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  18541. #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
  18542. #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
  18543. #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
  18544. #define USB_OTG_DOEPINT_STUP_Pos (3U)
  18545. #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
  18546. #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
  18547. #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
  18548. #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
  18549. #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
  18550. #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
  18551. #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
  18552. #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
  18553. #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
  18554. #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
  18555. #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
  18556. #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
  18557. #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
  18558. #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
  18559. #define USB_OTG_DOEPINT_NAK_Pos (13U)
  18560. #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
  18561. #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
  18562. #define USB_OTG_DOEPINT_NYET_Pos (14U)
  18563. #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
  18564. #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
  18565. #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
  18566. #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
  18567. #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
  18568. /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
  18569. #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
  18570. #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  18571. #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  18572. #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
  18573. #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  18574. #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
  18575. #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
  18576. #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
  18577. #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
  18578. #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
  18579. #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
  18580. /******************** Bit definition for PCGCCTL register ********************/
  18581. #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
  18582. #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
  18583. #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
  18584. #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
  18585. #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
  18586. #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
  18587. #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
  18588. #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
  18589. #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
  18590. /* Legacy define */
  18591. /******************** Bit definition for OTG register ********************/
  18592. #define USB_OTG_CHNUM_Pos (0U)
  18593. #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
  18594. #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
  18595. #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
  18596. #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
  18597. #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
  18598. #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
  18599. #define USB_OTG_BCNT_Pos (4U)
  18600. #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
  18601. #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
  18602. #define USB_OTG_DPID_Pos (15U)
  18603. #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
  18604. #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
  18605. #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
  18606. #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
  18607. #define USB_OTG_PKTSTS_Pos (17U)
  18608. #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
  18609. #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
  18610. #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
  18611. #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
  18612. #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
  18613. #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
  18614. #define USB_OTG_EPNUM_Pos (0U)
  18615. #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
  18616. #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
  18617. #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
  18618. #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
  18619. #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
  18620. #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
  18621. #define USB_OTG_FRMNUM_Pos (21U)
  18622. #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
  18623. #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
  18624. #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
  18625. #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
  18626. #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
  18627. #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
  18628. /**
  18629. * @}
  18630. */
  18631. /**
  18632. * @}
  18633. */
  18634. /** @addtogroup Exported_macros
  18635. * @{
  18636. */
  18637. /******************************* ADC Instances ********************************/
  18638. #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
  18639. ((INSTANCE) == ADC2) || \
  18640. ((INSTANCE) == ADC3))
  18641. #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  18642. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
  18643. /******************************* CAN Instances ********************************/
  18644. #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
  18645. ((INSTANCE) == CAN2))
  18646. /******************************* CRC Instances ********************************/
  18647. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  18648. /******************************* DAC Instances ********************************/
  18649. #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
  18650. /******************************* DCMI Instances *******************************/
  18651. #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
  18652. /******************************* DMA2D Instances *******************************/
  18653. #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
  18654. /******************************** DMA Instances *******************************/
  18655. #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
  18656. ((INSTANCE) == DMA1_Stream1) || \
  18657. ((INSTANCE) == DMA1_Stream2) || \
  18658. ((INSTANCE) == DMA1_Stream3) || \
  18659. ((INSTANCE) == DMA1_Stream4) || \
  18660. ((INSTANCE) == DMA1_Stream5) || \
  18661. ((INSTANCE) == DMA1_Stream6) || \
  18662. ((INSTANCE) == DMA1_Stream7) || \
  18663. ((INSTANCE) == DMA2_Stream0) || \
  18664. ((INSTANCE) == DMA2_Stream1) || \
  18665. ((INSTANCE) == DMA2_Stream2) || \
  18666. ((INSTANCE) == DMA2_Stream3) || \
  18667. ((INSTANCE) == DMA2_Stream4) || \
  18668. ((INSTANCE) == DMA2_Stream5) || \
  18669. ((INSTANCE) == DMA2_Stream6) || \
  18670. ((INSTANCE) == DMA2_Stream7))
  18671. /******************************* GPIO Instances *******************************/
  18672. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  18673. ((INSTANCE) == GPIOB) || \
  18674. ((INSTANCE) == GPIOC) || \
  18675. ((INSTANCE) == GPIOD) || \
  18676. ((INSTANCE) == GPIOE) || \
  18677. ((INSTANCE) == GPIOF) || \
  18678. ((INSTANCE) == GPIOG) || \
  18679. ((INSTANCE) == GPIOH) || \
  18680. ((INSTANCE) == GPIOI) || \
  18681. ((INSTANCE) == GPIOJ) || \
  18682. ((INSTANCE) == GPIOK))
  18683. /******************************** I2C Instances *******************************/
  18684. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  18685. ((INSTANCE) == I2C2) || \
  18686. ((INSTANCE) == I2C3))
  18687. /******************************* SMBUS Instances ******************************/
  18688. #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
  18689. /******************************** I2S Instances *******************************/
  18690. #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
  18691. ((INSTANCE) == SPI3))
  18692. /*************************** I2S Extended Instances ***************************/
  18693. #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
  18694. ((INSTANCE) == I2S3ext))
  18695. /* Legacy Defines */
  18696. #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
  18697. /****************************** LTDC Instances ********************************/
  18698. #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
  18699. /******************************* RNG Instances ********************************/
  18700. #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
  18701. /****************************** RTC Instances *********************************/
  18702. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  18703. /******************************* SAI Instances ********************************/
  18704. #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
  18705. ((PERIPH) == SAI1_Block_B))
  18706. /* Legacy define */
  18707. #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
  18708. /******************************** SPI Instances *******************************/
  18709. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  18710. ((INSTANCE) == SPI2) || \
  18711. ((INSTANCE) == SPI3) || \
  18712. ((INSTANCE) == SPI4) || \
  18713. ((INSTANCE) == SPI5) || \
  18714. ((INSTANCE) == SPI6))
  18715. /****************** TIM Instances : All supported instances *******************/
  18716. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18717. ((INSTANCE) == TIM2) || \
  18718. ((INSTANCE) == TIM3) || \
  18719. ((INSTANCE) == TIM4) || \
  18720. ((INSTANCE) == TIM5) || \
  18721. ((INSTANCE) == TIM6) || \
  18722. ((INSTANCE) == TIM7) || \
  18723. ((INSTANCE) == TIM8) || \
  18724. ((INSTANCE) == TIM9) || \
  18725. ((INSTANCE) == TIM10)|| \
  18726. ((INSTANCE) == TIM11)|| \
  18727. ((INSTANCE) == TIM12)|| \
  18728. ((INSTANCE) == TIM13)|| \
  18729. ((INSTANCE) == TIM14))
  18730. /****************** TIM Instances : supporting synchronization ****************/
  18731. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  18732. /************* TIM Instances : at least 1 capture/compare channel *************/
  18733. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18734. ((INSTANCE) == TIM2) || \
  18735. ((INSTANCE) == TIM3) || \
  18736. ((INSTANCE) == TIM4) || \
  18737. ((INSTANCE) == TIM5) || \
  18738. ((INSTANCE) == TIM8) || \
  18739. ((INSTANCE) == TIM9) || \
  18740. ((INSTANCE) == TIM10) || \
  18741. ((INSTANCE) == TIM11) || \
  18742. ((INSTANCE) == TIM12) || \
  18743. ((INSTANCE) == TIM13) || \
  18744. ((INSTANCE) == TIM14))
  18745. /************ TIM Instances : at least 2 capture/compare channels *************/
  18746. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18747. ((INSTANCE) == TIM2) || \
  18748. ((INSTANCE) == TIM3) || \
  18749. ((INSTANCE) == TIM4) || \
  18750. ((INSTANCE) == TIM5) || \
  18751. ((INSTANCE) == TIM8) || \
  18752. ((INSTANCE) == TIM9) || \
  18753. ((INSTANCE) == TIM12))
  18754. /************ TIM Instances : at least 3 capture/compare channels *************/
  18755. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18756. ((INSTANCE) == TIM2) || \
  18757. ((INSTANCE) == TIM3) || \
  18758. ((INSTANCE) == TIM4) || \
  18759. ((INSTANCE) == TIM5) || \
  18760. ((INSTANCE) == TIM8))
  18761. /************ TIM Instances : at least 4 capture/compare channels *************/
  18762. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18763. ((INSTANCE) == TIM2) || \
  18764. ((INSTANCE) == TIM3) || \
  18765. ((INSTANCE) == TIM4) || \
  18766. ((INSTANCE) == TIM5) || \
  18767. ((INSTANCE) == TIM8))
  18768. /******************** TIM Instances : Advanced-control timers *****************/
  18769. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18770. ((INSTANCE) == TIM8))
  18771. /******************* TIM Instances : Timer input XOR function *****************/
  18772. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18773. ((INSTANCE) == TIM2) || \
  18774. ((INSTANCE) == TIM3) || \
  18775. ((INSTANCE) == TIM4) || \
  18776. ((INSTANCE) == TIM5) || \
  18777. ((INSTANCE) == TIM8))
  18778. /****************** TIM Instances : DMA requests generation (UDE) *************/
  18779. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18780. ((INSTANCE) == TIM2) || \
  18781. ((INSTANCE) == TIM3) || \
  18782. ((INSTANCE) == TIM4) || \
  18783. ((INSTANCE) == TIM5) || \
  18784. ((INSTANCE) == TIM6) || \
  18785. ((INSTANCE) == TIM7) || \
  18786. ((INSTANCE) == TIM8))
  18787. /************ TIM Instances : DMA requests generation (CCxDE) *****************/
  18788. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18789. ((INSTANCE) == TIM2) || \
  18790. ((INSTANCE) == TIM3) || \
  18791. ((INSTANCE) == TIM4) || \
  18792. ((INSTANCE) == TIM5) || \
  18793. ((INSTANCE) == TIM8))
  18794. /************ TIM Instances : DMA requests generation (COMDE) *****************/
  18795. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18796. ((INSTANCE) == TIM2) || \
  18797. ((INSTANCE) == TIM3) || \
  18798. ((INSTANCE) == TIM4) || \
  18799. ((INSTANCE) == TIM5) || \
  18800. ((INSTANCE) == TIM8))
  18801. /******************** TIM Instances : DMA burst feature ***********************/
  18802. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18803. ((INSTANCE) == TIM2) || \
  18804. ((INSTANCE) == TIM3) || \
  18805. ((INSTANCE) == TIM4) || \
  18806. ((INSTANCE) == TIM5) || \
  18807. ((INSTANCE) == TIM8))
  18808. /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
  18809. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18810. ((INSTANCE) == TIM2) || \
  18811. ((INSTANCE) == TIM3) || \
  18812. ((INSTANCE) == TIM4) || \
  18813. ((INSTANCE) == TIM5) || \
  18814. ((INSTANCE) == TIM6) || \
  18815. ((INSTANCE) == TIM7) || \
  18816. ((INSTANCE) == TIM8))
  18817. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  18818. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18819. ((INSTANCE) == TIM2) || \
  18820. ((INSTANCE) == TIM3) || \
  18821. ((INSTANCE) == TIM4) || \
  18822. ((INSTANCE) == TIM5) || \
  18823. ((INSTANCE) == TIM8) || \
  18824. ((INSTANCE) == TIM9) || \
  18825. ((INSTANCE) == TIM12))
  18826. /********************** TIM Instances : 32 bit Counter ************************/
  18827. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
  18828. ((INSTANCE) == TIM5))
  18829. /***************** TIM Instances : external trigger input availabe ************/
  18830. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18831. ((INSTANCE) == TIM2) || \
  18832. ((INSTANCE) == TIM3) || \
  18833. ((INSTANCE) == TIM4) || \
  18834. ((INSTANCE) == TIM5) || \
  18835. ((INSTANCE) == TIM8))
  18836. /****************** TIM Instances : remapping capability **********************/
  18837. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
  18838. ((INSTANCE) == TIM5) || \
  18839. ((INSTANCE) == TIM11))
  18840. /******************* TIM Instances : output(s) available **********************/
  18841. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  18842. ((((INSTANCE) == TIM1) && \
  18843. (((CHANNEL) == TIM_CHANNEL_1) || \
  18844. ((CHANNEL) == TIM_CHANNEL_2) || \
  18845. ((CHANNEL) == TIM_CHANNEL_3) || \
  18846. ((CHANNEL) == TIM_CHANNEL_4))) \
  18847. || \
  18848. (((INSTANCE) == TIM2) && \
  18849. (((CHANNEL) == TIM_CHANNEL_1) || \
  18850. ((CHANNEL) == TIM_CHANNEL_2) || \
  18851. ((CHANNEL) == TIM_CHANNEL_3) || \
  18852. ((CHANNEL) == TIM_CHANNEL_4))) \
  18853. || \
  18854. (((INSTANCE) == TIM3) && \
  18855. (((CHANNEL) == TIM_CHANNEL_1) || \
  18856. ((CHANNEL) == TIM_CHANNEL_2) || \
  18857. ((CHANNEL) == TIM_CHANNEL_3) || \
  18858. ((CHANNEL) == TIM_CHANNEL_4))) \
  18859. || \
  18860. (((INSTANCE) == TIM4) && \
  18861. (((CHANNEL) == TIM_CHANNEL_1) || \
  18862. ((CHANNEL) == TIM_CHANNEL_2) || \
  18863. ((CHANNEL) == TIM_CHANNEL_3) || \
  18864. ((CHANNEL) == TIM_CHANNEL_4))) \
  18865. || \
  18866. (((INSTANCE) == TIM5) && \
  18867. (((CHANNEL) == TIM_CHANNEL_1) || \
  18868. ((CHANNEL) == TIM_CHANNEL_2) || \
  18869. ((CHANNEL) == TIM_CHANNEL_3) || \
  18870. ((CHANNEL) == TIM_CHANNEL_4))) \
  18871. || \
  18872. (((INSTANCE) == TIM8) && \
  18873. (((CHANNEL) == TIM_CHANNEL_1) || \
  18874. ((CHANNEL) == TIM_CHANNEL_2) || \
  18875. ((CHANNEL) == TIM_CHANNEL_3) || \
  18876. ((CHANNEL) == TIM_CHANNEL_4))) \
  18877. || \
  18878. (((INSTANCE) == TIM9) && \
  18879. (((CHANNEL) == TIM_CHANNEL_1) || \
  18880. ((CHANNEL) == TIM_CHANNEL_2))) \
  18881. || \
  18882. (((INSTANCE) == TIM10) && \
  18883. (((CHANNEL) == TIM_CHANNEL_1))) \
  18884. || \
  18885. (((INSTANCE) == TIM11) && \
  18886. (((CHANNEL) == TIM_CHANNEL_1))) \
  18887. || \
  18888. (((INSTANCE) == TIM12) && \
  18889. (((CHANNEL) == TIM_CHANNEL_1) || \
  18890. ((CHANNEL) == TIM_CHANNEL_2))) \
  18891. || \
  18892. (((INSTANCE) == TIM13) && \
  18893. (((CHANNEL) == TIM_CHANNEL_1))) \
  18894. || \
  18895. (((INSTANCE) == TIM14) && \
  18896. (((CHANNEL) == TIM_CHANNEL_1))))
  18897. /************ TIM Instances : complementary output(s) available ***************/
  18898. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  18899. ((((INSTANCE) == TIM1) && \
  18900. (((CHANNEL) == TIM_CHANNEL_1) || \
  18901. ((CHANNEL) == TIM_CHANNEL_2) || \
  18902. ((CHANNEL) == TIM_CHANNEL_3))) \
  18903. || \
  18904. (((INSTANCE) == TIM8) && \
  18905. (((CHANNEL) == TIM_CHANNEL_1) || \
  18906. ((CHANNEL) == TIM_CHANNEL_2) || \
  18907. ((CHANNEL) == TIM_CHANNEL_3))))
  18908. /****************** TIM Instances : supporting counting mode selection ********/
  18909. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18910. ((INSTANCE) == TIM2) || \
  18911. ((INSTANCE) == TIM3) || \
  18912. ((INSTANCE) == TIM4) || \
  18913. ((INSTANCE) == TIM5) || \
  18914. ((INSTANCE) == TIM8))
  18915. /****************** TIM Instances : supporting clock division *****************/
  18916. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18917. ((INSTANCE) == TIM2) || \
  18918. ((INSTANCE) == TIM3) || \
  18919. ((INSTANCE) == TIM4) || \
  18920. ((INSTANCE) == TIM5) || \
  18921. ((INSTANCE) == TIM8) || \
  18922. ((INSTANCE) == TIM9) || \
  18923. ((INSTANCE) == TIM10)|| \
  18924. ((INSTANCE) == TIM11)|| \
  18925. ((INSTANCE) == TIM12)|| \
  18926. ((INSTANCE) == TIM13)|| \
  18927. ((INSTANCE) == TIM14))
  18928. /****************** TIM Instances : supporting commutation event generation ***/
  18929. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
  18930. ((INSTANCE) == TIM8))
  18931. /****************** TIM Instances : supporting OCxREF clear *******************/
  18932. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18933. ((INSTANCE) == TIM2) || \
  18934. ((INSTANCE) == TIM3) || \
  18935. ((INSTANCE) == TIM4) || \
  18936. ((INSTANCE) == TIM5) || \
  18937. ((INSTANCE) == TIM8))
  18938. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  18939. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18940. ((INSTANCE) == TIM2) || \
  18941. ((INSTANCE) == TIM3) || \
  18942. ((INSTANCE) == TIM4) || \
  18943. ((INSTANCE) == TIM5) || \
  18944. ((INSTANCE) == TIM8) || \
  18945. ((INSTANCE) == TIM9) || \
  18946. ((INSTANCE) == TIM12))
  18947. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  18948. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18949. ((INSTANCE) == TIM2) || \
  18950. ((INSTANCE) == TIM3) || \
  18951. ((INSTANCE) == TIM4) || \
  18952. ((INSTANCE) == TIM5) || \
  18953. ((INSTANCE) == TIM8))
  18954. /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
  18955. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18956. ((INSTANCE) == TIM2) || \
  18957. ((INSTANCE) == TIM3) || \
  18958. ((INSTANCE) == TIM4) || \
  18959. ((INSTANCE) == TIM5) || \
  18960. ((INSTANCE) == TIM8) || \
  18961. ((INSTANCE) == TIM9) || \
  18962. ((INSTANCE) == TIM12))
  18963. /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
  18964. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18965. ((INSTANCE) == TIM2) || \
  18966. ((INSTANCE) == TIM3) || \
  18967. ((INSTANCE) == TIM4) || \
  18968. ((INSTANCE) == TIM5) || \
  18969. ((INSTANCE) == TIM8) || \
  18970. ((INSTANCE) == TIM9) || \
  18971. ((INSTANCE) == TIM12))
  18972. /****************** TIM Instances : supporting repetition counter *************/
  18973. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18974. ((INSTANCE) == TIM8))
  18975. /****************** TIM Instances : supporting encoder interface **************/
  18976. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18977. ((INSTANCE) == TIM2) || \
  18978. ((INSTANCE) == TIM3) || \
  18979. ((INSTANCE) == TIM4) || \
  18980. ((INSTANCE) == TIM5) || \
  18981. ((INSTANCE) == TIM8) || \
  18982. ((INSTANCE) == TIM9) || \
  18983. ((INSTANCE) == TIM12))
  18984. /****************** TIM Instances : supporting Hall sensor interface **********/
  18985. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18986. ((INSTANCE) == TIM2) || \
  18987. ((INSTANCE) == TIM3) || \
  18988. ((INSTANCE) == TIM4) || \
  18989. ((INSTANCE) == TIM5) || \
  18990. ((INSTANCE) == TIM8))
  18991. /****************** TIM Instances : supporting the break function *************/
  18992. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  18993. ((INSTANCE) == TIM8))
  18994. /******************** USART Instances : Synchronous mode **********************/
  18995. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  18996. ((INSTANCE) == USART2) || \
  18997. ((INSTANCE) == USART3) || \
  18998. ((INSTANCE) == USART6))
  18999. /******************** UART Instances : Half-Duplex mode **********************/
  19000. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  19001. ((INSTANCE) == USART2) || \
  19002. ((INSTANCE) == USART3) || \
  19003. ((INSTANCE) == UART4) || \
  19004. ((INSTANCE) == UART5) || \
  19005. ((INSTANCE) == USART6) || \
  19006. ((INSTANCE) == UART7) || \
  19007. ((INSTANCE) == UART8))
  19008. /* Legacy defines */
  19009. #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  19010. /****************** UART Instances : Hardware Flow control ********************/
  19011. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  19012. ((INSTANCE) == USART2) || \
  19013. ((INSTANCE) == USART3) || \
  19014. ((INSTANCE) == USART6))
  19015. /******************** UART Instances : LIN mode **********************/
  19016. #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  19017. /********************* UART Instances : Smart card mode ***********************/
  19018. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  19019. ((INSTANCE) == USART2) || \
  19020. ((INSTANCE) == USART3) || \
  19021. ((INSTANCE) == USART6))
  19022. /*********************** UART Instances : IRDA mode ***************************/
  19023. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  19024. ((INSTANCE) == USART2) || \
  19025. ((INSTANCE) == USART3) || \
  19026. ((INSTANCE) == UART4) || \
  19027. ((INSTANCE) == UART5) || \
  19028. ((INSTANCE) == USART6) || \
  19029. ((INSTANCE) == UART7) || \
  19030. ((INSTANCE) == UART8))
  19031. /*********************** PCD Instances ****************************************/
  19032. #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
  19033. ((INSTANCE) == USB_OTG_HS))
  19034. /*********************** HCD Instances ****************************************/
  19035. #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
  19036. ((INSTANCE) == USB_OTG_HS))
  19037. /****************************** SDIO Instances ********************************/
  19038. #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
  19039. /****************************** IWDG Instances ********************************/
  19040. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  19041. /****************************** WWDG Instances ********************************/
  19042. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  19043. /****************************** QSPI Instances ********************************/
  19044. #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
  19045. /****************************** USB Exported Constants ************************/
  19046. #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
  19047. #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
  19048. #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
  19049. #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
  19050. #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
  19051. #define USB_OTG_HS_MAX_IN_ENDPOINTS 9U /* Including EP0 */
  19052. #define USB_OTG_HS_MAX_OUT_ENDPOINTS 9U /* Including EP0 */
  19053. #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
  19054. /*
  19055. * @brief Specific devices reset values definitions
  19056. */
  19057. #define RCC_PLLCFGR_RST_VALUE 0x24003010U
  19058. #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
  19059. #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
  19060. #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
  19061. #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
  19062. #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
  19063. #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  19064. #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
  19065. #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  19066. #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  19067. #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  19068. #define RCC_PLLN_MIN_VALUE 50U
  19069. #define RCC_PLLN_MAX_VALUE 432U
  19070. #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  19071. #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  19072. #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  19073. #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
  19074. #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
  19075. #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  19076. #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  19077. #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
  19078. #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
  19079. #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
  19080. #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  19081. #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  19082. #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
  19083. /******************************************************************************/
  19084. /* For a painless codes migration between the STM32F4xx device product */
  19085. /* lines, the aliases defined below are put in place to overcome the */
  19086. /* differences in the interrupt handlers and IRQn definitions. */
  19087. /* No need to update developed interrupt code when moving across */
  19088. /* product lines within the same STM32F4 Family */
  19089. /******************************************************************************/
  19090. /* Aliases for __IRQn */
  19091. #define FSMC_IRQn FMC_IRQn
  19092. /* Aliases for __IRQHandler */
  19093. #define FSMC_IRQHandler FMC_IRQHandler
  19094. /**
  19095. * @}
  19096. */
  19097. /**
  19098. * @}
  19099. */
  19100. /**
  19101. * @}
  19102. */
  19103. #ifdef __cplusplus
  19104. }
  19105. #endif /* __cplusplus */
  19106. #endif /* __STM32F469xx_H */
  19107. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/