stm32f413xx.h 1.3 MB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f413xx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32F413xx Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - peripherals registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32f413xx
  45. * @{
  46. */
  47. #ifndef __STM32F413xx_H
  48. #define __STM32F413xx_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
  59. #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 1U /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32F4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  77. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  78. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  79. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  80. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  81. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  82. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  83. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  84. /****** STM32 specific Interrupt Numbers **********************************************************************/
  85. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  86. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  87. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  88. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  89. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  90. RCC_IRQn = 5, /*!< RCC global Interrupt */
  91. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  92. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  93. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  94. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  95. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  96. DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
  97. DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
  98. DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
  99. DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
  100. DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
  101. DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
  102. DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
  103. ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
  104. CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
  105. CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
  106. CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
  107. CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
  108. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  109. TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
  110. TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
  111. TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
  112. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  113. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  114. TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
  115. TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
  116. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  117. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  118. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  119. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  120. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  121. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  122. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  123. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  124. USART3_IRQn = 39, /*!< USART3 global Interrupt */
  125. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  126. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  127. OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
  128. TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
  129. TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
  130. TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
  131. TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
  132. DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
  133. SDIO_IRQn = 49, /*!< SDIO global Interrupt */
  134. TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
  135. SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
  136. UART4_IRQn = 52, /*!< UART4 global Interrupt */
  137. UART5_IRQn = 53, /*!< UART5 global Interrupt */
  138. TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
  139. TIM7_IRQn = 55, /*!< TIM7 global interrupt */
  140. DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
  141. DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
  142. DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
  143. DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
  144. DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
  145. DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
  146. DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
  147. CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
  148. CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
  149. CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
  150. CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
  151. OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
  152. DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
  153. DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
  154. DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
  155. USART6_IRQn = 71, /*!< USART6 global interrupt */
  156. I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
  157. I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
  158. CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
  159. CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
  160. CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
  161. CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
  162. RNG_IRQn = 80, /*!< RNG global Interrupt */
  163. FPU_IRQn = 81, /*!< FPU global interrupt */
  164. UART7_IRQn = 82, /*!< UART7 global interrupt */
  165. UART8_IRQn = 83, /*!< UART8 global interrupt */
  166. SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
  167. SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
  168. SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
  169. UART9_IRQn = 88, /*!< UART9 global Interrupt */
  170. UART10_IRQn = 89, /*!< UART10 global Interrupt */
  171. QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
  172. FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
  173. FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
  174. LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
  175. DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
  176. DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
  177. DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
  178. DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
  179. } IRQn_Type;
  180. /**
  181. * @}
  182. */
  183. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  184. #include "system_stm32f4xx.h"
  185. #include <stdint.h>
  186. /** @addtogroup Peripheral_registers_structures
  187. * @{
  188. */
  189. /**
  190. * @brief Analog to Digital Converter
  191. */
  192. typedef struct
  193. {
  194. __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
  195. __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
  196. __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
  197. __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
  198. __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
  199. __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  200. __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  201. __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  202. __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  203. __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
  204. __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
  205. __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
  206. __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
  207. __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
  208. __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
  209. __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
  210. __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
  211. __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
  212. __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
  213. __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
  214. } ADC_TypeDef;
  215. typedef struct
  216. {
  217. __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
  218. __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
  219. __IO uint32_t CDR; /*!< ADC common regular data register for dual
  220. AND triple modes, Address offset: ADC1 base address + 0x308 */
  221. } ADC_Common_TypeDef;
  222. /**
  223. * @brief Controller Area Network TxMailBox
  224. */
  225. typedef struct
  226. {
  227. __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
  228. __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
  229. __IO uint32_t TDLR; /*!< CAN mailbox data low register */
  230. __IO uint32_t TDHR; /*!< CAN mailbox data high register */
  231. } CAN_TxMailBox_TypeDef;
  232. /**
  233. * @brief Controller Area Network FIFOMailBox
  234. */
  235. typedef struct
  236. {
  237. __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
  238. __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
  239. __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
  240. __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
  241. } CAN_FIFOMailBox_TypeDef;
  242. /**
  243. * @brief Controller Area Network FilterRegister
  244. */
  245. typedef struct
  246. {
  247. __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
  248. __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
  249. } CAN_FilterRegister_TypeDef;
  250. /**
  251. * @brief Controller Area Network
  252. */
  253. typedef struct
  254. {
  255. __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
  256. __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
  257. __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
  258. __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
  259. __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
  260. __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
  261. __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
  262. __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
  263. uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
  264. CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
  265. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
  266. uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
  267. __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
  268. __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
  269. uint32_t RESERVED2; /*!< Reserved, 0x208 */
  270. __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
  271. uint32_t RESERVED3; /*!< Reserved, 0x210 */
  272. __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
  273. uint32_t RESERVED4; /*!< Reserved, 0x218 */
  274. __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
  275. uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
  276. CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
  277. } CAN_TypeDef;
  278. /**
  279. * @brief CRC calculation unit
  280. */
  281. typedef struct
  282. {
  283. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  284. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  285. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  286. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  287. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  288. } CRC_TypeDef;
  289. /**
  290. * @brief DFSDM module registers
  291. */
  292. typedef struct
  293. {
  294. __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
  295. __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
  296. __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
  297. __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
  298. __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
  299. __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
  300. __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
  301. __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
  302. __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
  303. __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
  304. __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
  305. __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
  306. __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
  307. __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
  308. __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
  309. } DFSDM_Filter_TypeDef;
  310. /**
  311. * @brief DFSDM channel configuration registers
  312. */
  313. typedef struct
  314. {
  315. __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
  316. __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
  317. __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
  318. short circuit detector register, Address offset: 0x08 */
  319. __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
  320. __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
  321. } DFSDM_Channel_TypeDef;
  322. /**
  323. * @brief Digital to Analog Converter
  324. */
  325. typedef struct
  326. {
  327. __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
  328. __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
  329. __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  330. __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
  331. __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
  332. __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  333. __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
  334. __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
  335. __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
  336. __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
  337. __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
  338. __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
  339. __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
  340. __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
  341. } DAC_TypeDef;
  342. /**
  343. * @brief Debug MCU
  344. */
  345. typedef struct
  346. {
  347. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  348. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  349. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  350. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  351. }DBGMCU_TypeDef;
  352. /**
  353. * @brief DMA Controller
  354. */
  355. typedef struct
  356. {
  357. __IO uint32_t CR; /*!< DMA stream x configuration register */
  358. __IO uint32_t NDTR; /*!< DMA stream x number of data register */
  359. __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
  360. __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
  361. __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
  362. __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
  363. } DMA_Stream_TypeDef;
  364. typedef struct
  365. {
  366. __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
  367. __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
  368. __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
  369. __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
  370. } DMA_TypeDef;
  371. /**
  372. * @brief External Interrupt/Event Controller
  373. */
  374. typedef struct
  375. {
  376. __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
  377. __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
  378. __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
  379. __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
  380. __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
  381. __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
  382. } EXTI_TypeDef;
  383. /**
  384. * @brief FLASH Registers
  385. */
  386. typedef struct
  387. {
  388. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  389. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
  390. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
  391. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
  392. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
  393. __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
  394. __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
  395. } FLASH_TypeDef;
  396. /**
  397. * @brief Flexible Static Memory Controller
  398. */
  399. typedef struct
  400. {
  401. __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
  402. } FSMC_Bank1_TypeDef;
  403. /**
  404. * @brief Flexible Static Memory Controller Bank1E
  405. */
  406. typedef struct
  407. {
  408. __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
  409. } FSMC_Bank1E_TypeDef;
  410. /**
  411. * @brief General Purpose I/O
  412. */
  413. typedef struct
  414. {
  415. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  416. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  417. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  418. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  419. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  420. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  421. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  422. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  423. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  424. } GPIO_TypeDef;
  425. /**
  426. * @brief System configuration controller
  427. */
  428. typedef struct
  429. {
  430. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  431. __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
  432. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  433. uint32_t RESERVED; /*!< Reserved, 0x18 */
  434. __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
  435. __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
  436. uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
  437. __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
  438. __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
  439. } SYSCFG_TypeDef;
  440. /**
  441. * @brief Inter-integrated Circuit Interface
  442. */
  443. typedef struct
  444. {
  445. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  446. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  447. __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
  448. __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
  449. __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
  450. __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
  451. __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
  452. __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
  453. __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
  454. __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
  455. } I2C_TypeDef;
  456. /**
  457. * @brief Inter-integrated Circuit Interface
  458. */
  459. typedef struct
  460. {
  461. __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
  462. __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
  463. __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
  464. __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
  465. __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
  466. __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
  467. __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
  468. __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
  469. __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
  470. __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
  471. __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
  472. } FMPI2C_TypeDef;
  473. /**
  474. * @brief Independent WATCHDOG
  475. */
  476. typedef struct
  477. {
  478. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  479. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  480. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  481. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  482. } IWDG_TypeDef;
  483. /**
  484. * @brief Power Control
  485. */
  486. typedef struct
  487. {
  488. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  489. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  490. } PWR_TypeDef;
  491. /**
  492. * @brief Reset and Clock Control
  493. */
  494. typedef struct
  495. {
  496. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  497. __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
  498. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  499. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
  500. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
  501. __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
  502. __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
  503. uint32_t RESERVED0; /*!< Reserved, 0x1C */
  504. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
  505. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
  506. uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
  507. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
  508. __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
  509. __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
  510. uint32_t RESERVED2; /*!< Reserved, 0x3C */
  511. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
  512. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
  513. uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
  514. __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  515. __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
  516. __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
  517. uint32_t RESERVED4; /*!< Reserved, 0x5C */
  518. __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  519. __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  520. uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
  521. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
  522. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
  523. uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
  524. __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
  525. __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
  526. uint32_t RESERVED7; /*!< Reserved, 0x84 */
  527. __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
  528. __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
  529. __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
  530. } RCC_TypeDef;
  531. /**
  532. * @brief Real-Time Clock
  533. */
  534. typedef struct
  535. {
  536. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  537. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  538. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  539. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  540. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  541. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  542. __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
  543. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  544. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  545. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  546. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  547. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  548. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  549. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  550. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  551. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  552. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  553. __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
  554. __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
  555. uint32_t RESERVED7; /*!< Reserved, 0x4C */
  556. __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
  557. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  558. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  559. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  560. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  561. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  562. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  563. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  564. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  565. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  566. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  567. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  568. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  569. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  570. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  571. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  572. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  573. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  574. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  575. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  576. } RTC_TypeDef;
  577. /**
  578. * @brief Serial Audio Interface
  579. */
  580. typedef struct
  581. {
  582. __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
  583. } SAI_TypeDef;
  584. typedef struct
  585. {
  586. __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
  587. __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
  588. __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
  589. __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
  590. __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
  591. __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
  592. __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
  593. __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
  594. } SAI_Block_TypeDef;
  595. /**
  596. * @brief SD host Interface
  597. */
  598. typedef struct
  599. {
  600. __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
  601. __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
  602. __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
  603. __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
  604. __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
  605. __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
  606. __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
  607. __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
  608. __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
  609. __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
  610. __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
  611. __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
  612. __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
  613. __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
  614. __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
  615. __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
  616. uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
  617. __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
  618. uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
  619. __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
  620. } SDIO_TypeDef;
  621. /**
  622. * @brief Serial Peripheral Interface
  623. */
  624. typedef struct
  625. {
  626. __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
  627. __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
  628. __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
  629. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  630. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  631. __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
  632. __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
  633. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  634. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  635. } SPI_TypeDef;
  636. /**
  637. * @brief QUAD Serial Peripheral Interface
  638. */
  639. typedef struct
  640. {
  641. __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
  642. __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
  643. __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
  644. __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
  645. __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
  646. __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
  647. __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
  648. __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
  649. __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
  650. __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
  651. __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
  652. __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
  653. __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
  654. } QUADSPI_TypeDef;
  655. /**
  656. * @brief TIM
  657. */
  658. typedef struct
  659. {
  660. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  661. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  662. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  663. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  664. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  665. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  666. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  667. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  668. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  669. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  670. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  671. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  672. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  673. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  674. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  675. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  676. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  677. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  678. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  679. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  680. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  681. } TIM_TypeDef;
  682. /**
  683. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  684. */
  685. typedef struct
  686. {
  687. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  688. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  689. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  690. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  691. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  692. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  693. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  694. } USART_TypeDef;
  695. /**
  696. * @brief Window WATCHDOG
  697. */
  698. typedef struct
  699. {
  700. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  701. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  702. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  703. } WWDG_TypeDef;
  704. /**
  705. * @brief RNG
  706. */
  707. typedef struct
  708. {
  709. __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
  710. __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
  711. __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
  712. } RNG_TypeDef;
  713. /**
  714. * @brief USB_OTG_Core_Registers
  715. */
  716. typedef struct
  717. {
  718. __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
  719. __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
  720. __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
  721. __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
  722. __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
  723. __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
  724. __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
  725. __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
  726. __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
  727. __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
  728. __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
  729. __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
  730. uint32_t Reserved30[2]; /*!< Reserved 030h */
  731. __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
  732. __IO uint32_t CID; /*!< User ID Register 03Ch */
  733. uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
  734. __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
  735. uint32_t Reserved6; /*!< Reserved 050h */
  736. __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
  737. uint32_t Reserved; /*!< Reserved 058h */
  738. __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
  739. uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
  740. __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
  741. __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
  742. } USB_OTG_GlobalTypeDef;
  743. /**
  744. * @brief USB_OTG_device_Registers
  745. */
  746. typedef struct
  747. {
  748. __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
  749. __IO uint32_t DCTL; /*!< dev Control Register 804h */
  750. __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
  751. uint32_t Reserved0C; /*!< Reserved 80Ch */
  752. __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
  753. __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
  754. __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
  755. __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
  756. uint32_t Reserved20; /*!< Reserved 820h */
  757. uint32_t Reserved9; /*!< Reserved 824h */
  758. __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
  759. __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
  760. __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
  761. __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
  762. __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
  763. __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
  764. uint32_t Reserved40; /*!< dedicated EP mask 840h */
  765. __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
  766. uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
  767. __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
  768. } USB_OTG_DeviceTypeDef;
  769. /**
  770. * @brief USB_OTG_IN_Endpoint-Specific_Register
  771. */
  772. typedef struct
  773. {
  774. __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
  775. uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
  776. __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
  777. uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
  778. __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
  779. __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
  780. __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
  781. uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
  782. } USB_OTG_INEndpointTypeDef;
  783. /**
  784. * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  785. */
  786. typedef struct
  787. {
  788. __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
  789. uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
  790. __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
  791. uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
  792. __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
  793. __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
  794. uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
  795. } USB_OTG_OUTEndpointTypeDef;
  796. /**
  797. * @brief USB_OTG_Host_Mode_Register_Structures
  798. */
  799. typedef struct
  800. {
  801. __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
  802. __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
  803. __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
  804. uint32_t Reserved40C; /*!< Reserved 40Ch */
  805. __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
  806. __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
  807. __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
  808. } USB_OTG_HostTypeDef;
  809. /**
  810. * @brief USB_OTG_Host_Channel_Specific_Registers
  811. */
  812. typedef struct
  813. {
  814. __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
  815. __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
  816. __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
  817. __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
  818. __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
  819. __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
  820. uint32_t Reserved[2]; /*!< Reserved */
  821. } USB_OTG_HostChannelTypeDef;
  822. /**
  823. * @brief LPTIMER
  824. */
  825. typedef struct
  826. {
  827. __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
  828. __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
  829. __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
  830. __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
  831. __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
  832. __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
  833. __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
  834. __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
  835. __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
  836. } LPTIM_TypeDef;
  837. /**
  838. * @}
  839. */
  840. /** @addtogroup Peripheral_memory_map
  841. * @{
  842. */
  843. #define FLASH_BASE 0x08000000UL /*!< FLASH (up to 1.5 MB) base address in the alias region */
  844. #define SRAM1_BASE 0x20000000UL /*!< SRAM1(256 KB) base address in the alias region */
  845. #define SRAM2_BASE 0x20040000UL /*!< SRAM2(64 KB) base address in the alias region */
  846. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  847. #define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */
  848. #define QSPI_R_BASE 0xA0001000UL /*!< QuadSPI registers base address */
  849. #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(256 KB) base address in the bit-band region */
  850. #define SRAM2_BB_BASE 0x22800000UL /*!< SRAM2(64 KB) base address in the bit-band region */
  851. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  852. #define FLASH_END 0x0817FFFFUL /*!< FLASH end address */
  853. #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
  854. #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
  855. /* Legacy defines */
  856. #define SRAM_BASE SRAM1_BASE
  857. #define SRAM_BB_BASE SRAM1_BB_BASE
  858. /*!< Peripheral memory map */
  859. #define APB1PERIPH_BASE PERIPH_BASE
  860. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  861. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  862. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
  863. /*!< APB1 peripherals */
  864. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
  865. #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
  866. #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
  867. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
  868. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
  869. #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
  870. #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
  871. #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
  872. #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
  873. #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
  874. #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
  875. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
  876. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
  877. #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
  878. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
  879. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
  880. #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
  881. #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
  882. #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
  883. #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
  884. #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
  885. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
  886. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
  887. #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
  888. #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
  889. #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
  890. #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
  891. #define CAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
  892. #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
  893. #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
  894. #define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
  895. #define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
  896. /*!< APB2 peripherals */
  897. #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
  898. #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
  899. #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
  900. #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
  901. #define UART9_BASE (APB2PERIPH_BASE + 0x1800UL)
  902. #define UART10_BASE (APB2PERIPH_BASE + 0x1C00UL)
  903. #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
  904. #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
  905. /* Legacy define */
  906. #define ADC_BASE ADC1_COMMON_BASE
  907. #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
  908. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
  909. #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
  910. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
  911. #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
  912. #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
  913. #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
  914. #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
  915. #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
  916. #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
  917. #define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400UL)
  918. #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
  919. #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
  920. #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
  921. #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
  922. #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
  923. #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
  924. #define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
  925. #define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
  926. #define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40UL)
  927. #define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60UL)
  928. #define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80UL)
  929. #define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0UL)
  930. #define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0UL)
  931. #define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0UL)
  932. #define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100UL)
  933. #define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180UL)
  934. #define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200UL)
  935. #define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280UL)
  936. #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
  937. #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
  938. #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
  939. /*!< AHB1 peripherals */
  940. #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
  941. #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
  942. #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
  943. #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
  944. #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
  945. #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
  946. #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
  947. #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
  948. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
  949. #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
  950. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
  951. #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
  952. #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
  953. #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
  954. #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
  955. #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
  956. #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
  957. #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
  958. #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
  959. #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
  960. #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
  961. #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
  962. #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
  963. #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
  964. #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
  965. #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
  966. #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
  967. #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
  968. #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
  969. /*!< AHB2 peripherals */
  970. #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
  971. /*!< FSMC Bankx registers base address */
  972. #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
  973. #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
  974. /*!< Debug MCU registers base address */
  975. #define DBGMCU_BASE 0xE0042000UL
  976. /*!< USB registers base address */
  977. #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
  978. #define USB_OTG_GLOBAL_BASE 0x000UL
  979. #define USB_OTG_DEVICE_BASE 0x800UL
  980. #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
  981. #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
  982. #define USB_OTG_EP_REG_SIZE 0x20UL
  983. #define USB_OTG_HOST_BASE 0x400UL
  984. #define USB_OTG_HOST_PORT_BASE 0x440UL
  985. #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
  986. #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
  987. #define USB_OTG_PCGCCTL_BASE 0xE00UL
  988. #define USB_OTG_FIFO_BASE 0x1000UL
  989. #define USB_OTG_FIFO_SIZE 0x1000UL
  990. #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
  991. #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
  992. #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
  993. /**
  994. * @}
  995. */
  996. /** @addtogroup Peripheral_declaration
  997. * @{
  998. */
  999. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  1000. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  1001. #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
  1002. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  1003. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  1004. #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
  1005. #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
  1006. #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
  1007. #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
  1008. #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
  1009. #define RTC ((RTC_TypeDef *) RTC_BASE)
  1010. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  1011. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  1012. #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
  1013. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  1014. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  1015. #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
  1016. #define USART2 ((USART_TypeDef *) USART2_BASE)
  1017. #define USART3 ((USART_TypeDef *) USART3_BASE)
  1018. #define UART4 ((USART_TypeDef *) UART4_BASE)
  1019. #define UART5 ((USART_TypeDef *) UART5_BASE)
  1020. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  1021. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  1022. #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
  1023. #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
  1024. #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
  1025. #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
  1026. #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
  1027. #define PWR ((PWR_TypeDef *) PWR_BASE)
  1028. #define DAC1 ((DAC_TypeDef *) DAC_BASE)
  1029. #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
  1030. #define UART7 ((USART_TypeDef *) UART7_BASE)
  1031. #define UART8 ((USART_TypeDef *) UART8_BASE)
  1032. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  1033. #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
  1034. #define USART1 ((USART_TypeDef *) USART1_BASE)
  1035. #define USART6 ((USART_TypeDef *) USART6_BASE)
  1036. #define UART9 ((USART_TypeDef *) UART9_BASE)
  1037. #define UART10 ((USART_TypeDef *) UART10_BASE)
  1038. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  1039. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
  1040. /* Legacy define */
  1041. #define ADC ADC1_COMMON
  1042. #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
  1043. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  1044. #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
  1045. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  1046. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  1047. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  1048. #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
  1049. #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
  1050. #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
  1051. #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
  1052. #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
  1053. #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
  1054. #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
  1055. #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
  1056. #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
  1057. #define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
  1058. #define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
  1059. #define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
  1060. #define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
  1061. #define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
  1062. #define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
  1063. #define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
  1064. #define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
  1065. #define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
  1066. #define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
  1067. #define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
  1068. #define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
  1069. #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
  1070. #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
  1071. #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
  1072. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  1073. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  1074. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  1075. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  1076. #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
  1077. #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
  1078. #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
  1079. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  1080. #define CRC ((CRC_TypeDef *) CRC_BASE)
  1081. #define RCC ((RCC_TypeDef *) RCC_BASE)
  1082. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  1083. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  1084. #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  1085. #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
  1086. #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
  1087. #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
  1088. #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
  1089. #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
  1090. #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
  1091. #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
  1092. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  1093. #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
  1094. #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
  1095. #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
  1096. #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
  1097. #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
  1098. #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
  1099. #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
  1100. #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
  1101. #define RNG ((RNG_TypeDef *) RNG_BASE)
  1102. #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
  1103. #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
  1104. #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
  1105. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  1106. #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
  1107. /**
  1108. * @}
  1109. */
  1110. /** @addtogroup Exported_constants
  1111. * @{
  1112. */
  1113. /** @addtogroup Peripheral_Registers_Bits_Definition
  1114. * @{
  1115. */
  1116. /******************************************************************************/
  1117. /* Peripheral Registers_Bits_Definition */
  1118. /******************************************************************************/
  1119. /******************************************************************************/
  1120. /* */
  1121. /* Analog to Digital Converter */
  1122. /* */
  1123. /******************************************************************************/
  1124. /******************** Bit definition for ADC_SR register ********************/
  1125. #define ADC_SR_AWD_Pos (0U)
  1126. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  1127. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
  1128. #define ADC_SR_EOC_Pos (1U)
  1129. #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
  1130. #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
  1131. #define ADC_SR_JEOC_Pos (2U)
  1132. #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
  1133. #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
  1134. #define ADC_SR_JSTRT_Pos (3U)
  1135. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  1136. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
  1137. #define ADC_SR_STRT_Pos (4U)
  1138. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  1139. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
  1140. #define ADC_SR_OVR_Pos (5U)
  1141. #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
  1142. #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
  1143. /******************* Bit definition for ADC_CR1 register ********************/
  1144. #define ADC_CR1_AWDCH_Pos (0U)
  1145. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  1146. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
  1147. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  1148. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  1149. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  1150. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  1151. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  1152. #define ADC_CR1_EOCIE_Pos (5U)
  1153. #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
  1154. #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
  1155. #define ADC_CR1_AWDIE_Pos (6U)
  1156. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  1157. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
  1158. #define ADC_CR1_JEOCIE_Pos (7U)
  1159. #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
  1160. #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
  1161. #define ADC_CR1_SCAN_Pos (8U)
  1162. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  1163. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
  1164. #define ADC_CR1_AWDSGL_Pos (9U)
  1165. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  1166. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
  1167. #define ADC_CR1_JAUTO_Pos (10U)
  1168. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  1169. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
  1170. #define ADC_CR1_DISCEN_Pos (11U)
  1171. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  1172. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
  1173. #define ADC_CR1_JDISCEN_Pos (12U)
  1174. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  1175. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
  1176. #define ADC_CR1_DISCNUM_Pos (13U)
  1177. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  1178. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
  1179. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  1180. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  1181. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  1182. #define ADC_CR1_JAWDEN_Pos (22U)
  1183. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  1184. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
  1185. #define ADC_CR1_AWDEN_Pos (23U)
  1186. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  1187. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
  1188. #define ADC_CR1_RES_Pos (24U)
  1189. #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
  1190. #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
  1191. #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
  1192. #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
  1193. #define ADC_CR1_OVRIE_Pos (26U)
  1194. #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
  1195. #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
  1196. /******************* Bit definition for ADC_CR2 register ********************/
  1197. #define ADC_CR2_ADON_Pos (0U)
  1198. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  1199. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
  1200. #define ADC_CR2_CONT_Pos (1U)
  1201. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  1202. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
  1203. #define ADC_CR2_DMA_Pos (8U)
  1204. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  1205. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
  1206. #define ADC_CR2_DDS_Pos (9U)
  1207. #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
  1208. #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
  1209. #define ADC_CR2_EOCS_Pos (10U)
  1210. #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
  1211. #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
  1212. #define ADC_CR2_ALIGN_Pos (11U)
  1213. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  1214. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
  1215. #define ADC_CR2_JEXTSEL_Pos (16U)
  1216. #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
  1217. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
  1218. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
  1219. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
  1220. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
  1221. #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
  1222. #define ADC_CR2_JEXTEN_Pos (20U)
  1223. #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
  1224. #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
  1225. #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
  1226. #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
  1227. #define ADC_CR2_JSWSTART_Pos (22U)
  1228. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
  1229. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
  1230. #define ADC_CR2_EXTSEL_Pos (24U)
  1231. #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
  1232. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
  1233. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
  1234. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
  1235. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
  1236. #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
  1237. #define ADC_CR2_EXTEN_Pos (28U)
  1238. #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
  1239. #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
  1240. #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
  1241. #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
  1242. #define ADC_CR2_SWSTART_Pos (30U)
  1243. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
  1244. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
  1245. /****************** Bit definition for ADC_SMPR1 register *******************/
  1246. #define ADC_SMPR1_SMP10_Pos (0U)
  1247. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  1248. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
  1249. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  1250. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  1251. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  1252. #define ADC_SMPR1_SMP11_Pos (3U)
  1253. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  1254. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
  1255. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  1256. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  1257. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  1258. #define ADC_SMPR1_SMP12_Pos (6U)
  1259. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  1260. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
  1261. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  1262. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  1263. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  1264. #define ADC_SMPR1_SMP13_Pos (9U)
  1265. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  1266. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
  1267. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  1268. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  1269. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  1270. #define ADC_SMPR1_SMP14_Pos (12U)
  1271. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  1272. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
  1273. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  1274. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  1275. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  1276. #define ADC_SMPR1_SMP15_Pos (15U)
  1277. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  1278. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
  1279. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  1280. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  1281. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  1282. #define ADC_SMPR1_SMP16_Pos (18U)
  1283. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  1284. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
  1285. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  1286. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  1287. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  1288. #define ADC_SMPR1_SMP17_Pos (21U)
  1289. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  1290. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
  1291. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  1292. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  1293. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  1294. #define ADC_SMPR1_SMP18_Pos (24U)
  1295. #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
  1296. #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
  1297. #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
  1298. #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
  1299. #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
  1300. /****************** Bit definition for ADC_SMPR2 register *******************/
  1301. #define ADC_SMPR2_SMP0_Pos (0U)
  1302. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  1303. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
  1304. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  1305. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  1306. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  1307. #define ADC_SMPR2_SMP1_Pos (3U)
  1308. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  1309. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
  1310. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  1311. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  1312. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  1313. #define ADC_SMPR2_SMP2_Pos (6U)
  1314. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  1315. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
  1316. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  1317. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  1318. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  1319. #define ADC_SMPR2_SMP3_Pos (9U)
  1320. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  1321. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
  1322. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  1323. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  1324. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  1325. #define ADC_SMPR2_SMP4_Pos (12U)
  1326. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  1327. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
  1328. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  1329. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  1330. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  1331. #define ADC_SMPR2_SMP5_Pos (15U)
  1332. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  1333. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
  1334. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  1335. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  1336. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  1337. #define ADC_SMPR2_SMP6_Pos (18U)
  1338. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  1339. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
  1340. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  1341. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  1342. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  1343. #define ADC_SMPR2_SMP7_Pos (21U)
  1344. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  1345. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
  1346. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  1347. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  1348. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  1349. #define ADC_SMPR2_SMP8_Pos (24U)
  1350. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  1351. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
  1352. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  1353. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  1354. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  1355. #define ADC_SMPR2_SMP9_Pos (27U)
  1356. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  1357. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
  1358. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  1359. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  1360. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  1361. /****************** Bit definition for ADC_JOFR1 register *******************/
  1362. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  1363. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  1364. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
  1365. /****************** Bit definition for ADC_JOFR2 register *******************/
  1366. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  1367. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  1368. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
  1369. /****************** Bit definition for ADC_JOFR3 register *******************/
  1370. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  1371. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  1372. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
  1373. /****************** Bit definition for ADC_JOFR4 register *******************/
  1374. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  1375. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  1376. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
  1377. /******************* Bit definition for ADC_HTR register ********************/
  1378. #define ADC_HTR_HT_Pos (0U)
  1379. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  1380. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
  1381. /******************* Bit definition for ADC_LTR register ********************/
  1382. #define ADC_LTR_LT_Pos (0U)
  1383. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  1384. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
  1385. /******************* Bit definition for ADC_SQR1 register *******************/
  1386. #define ADC_SQR1_SQ13_Pos (0U)
  1387. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  1388. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
  1389. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  1390. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  1391. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  1392. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  1393. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  1394. #define ADC_SQR1_SQ14_Pos (5U)
  1395. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  1396. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
  1397. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  1398. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  1399. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  1400. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  1401. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  1402. #define ADC_SQR1_SQ15_Pos (10U)
  1403. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  1404. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
  1405. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  1406. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  1407. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  1408. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  1409. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  1410. #define ADC_SQR1_SQ16_Pos (15U)
  1411. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  1412. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
  1413. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  1414. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  1415. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  1416. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  1417. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  1418. #define ADC_SQR1_L_Pos (20U)
  1419. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  1420. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
  1421. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  1422. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  1423. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  1424. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  1425. /******************* Bit definition for ADC_SQR2 register *******************/
  1426. #define ADC_SQR2_SQ7_Pos (0U)
  1427. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  1428. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
  1429. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  1430. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  1431. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  1432. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  1433. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  1434. #define ADC_SQR2_SQ8_Pos (5U)
  1435. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  1436. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
  1437. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  1438. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  1439. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  1440. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  1441. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  1442. #define ADC_SQR2_SQ9_Pos (10U)
  1443. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  1444. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
  1445. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  1446. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  1447. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  1448. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  1449. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  1450. #define ADC_SQR2_SQ10_Pos (15U)
  1451. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  1452. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
  1453. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  1454. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  1455. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  1456. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  1457. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  1458. #define ADC_SQR2_SQ11_Pos (20U)
  1459. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  1460. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
  1461. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  1462. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  1463. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  1464. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  1465. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  1466. #define ADC_SQR2_SQ12_Pos (25U)
  1467. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  1468. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
  1469. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  1470. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  1471. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  1472. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  1473. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  1474. /******************* Bit definition for ADC_SQR3 register *******************/
  1475. #define ADC_SQR3_SQ1_Pos (0U)
  1476. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  1477. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
  1478. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  1479. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  1480. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  1481. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  1482. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  1483. #define ADC_SQR3_SQ2_Pos (5U)
  1484. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  1485. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
  1486. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  1487. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  1488. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  1489. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  1490. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  1491. #define ADC_SQR3_SQ3_Pos (10U)
  1492. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  1493. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
  1494. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  1495. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  1496. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  1497. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  1498. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  1499. #define ADC_SQR3_SQ4_Pos (15U)
  1500. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  1501. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
  1502. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  1503. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  1504. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  1505. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  1506. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  1507. #define ADC_SQR3_SQ5_Pos (20U)
  1508. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  1509. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
  1510. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  1511. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  1512. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  1513. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  1514. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  1515. #define ADC_SQR3_SQ6_Pos (25U)
  1516. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  1517. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
  1518. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  1519. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  1520. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  1521. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  1522. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  1523. /******************* Bit definition for ADC_JSQR register *******************/
  1524. #define ADC_JSQR_JSQ1_Pos (0U)
  1525. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  1526. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
  1527. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  1528. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  1529. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  1530. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  1531. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  1532. #define ADC_JSQR_JSQ2_Pos (5U)
  1533. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  1534. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1535. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  1536. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  1537. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  1538. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  1539. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  1540. #define ADC_JSQR_JSQ3_Pos (10U)
  1541. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  1542. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1543. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  1544. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  1545. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  1546. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  1547. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  1548. #define ADC_JSQR_JSQ4_Pos (15U)
  1549. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  1550. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
  1551. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  1552. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  1553. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  1554. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  1555. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  1556. #define ADC_JSQR_JL_Pos (20U)
  1557. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  1558. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
  1559. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  1560. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  1561. /******************* Bit definition for ADC_JDR1 register *******************/
  1562. #define ADC_JDR1_JDATA_Pos (0U)
  1563. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1564. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
  1565. /******************* Bit definition for ADC_JDR2 register *******************/
  1566. #define ADC_JDR2_JDATA_Pos (0U)
  1567. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1568. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
  1569. /******************* Bit definition for ADC_JDR3 register *******************/
  1570. #define ADC_JDR3_JDATA_Pos (0U)
  1571. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1572. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
  1573. /******************* Bit definition for ADC_JDR4 register *******************/
  1574. #define ADC_JDR4_JDATA_Pos (0U)
  1575. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1576. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
  1577. /******************** Bit definition for ADC_DR register ********************/
  1578. #define ADC_DR_DATA_Pos (0U)
  1579. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1580. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
  1581. #define ADC_DR_ADC2DATA_Pos (16U)
  1582. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  1583. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
  1584. /******************* Bit definition for ADC_CSR register ********************/
  1585. #define ADC_CSR_AWD1_Pos (0U)
  1586. #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
  1587. #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
  1588. #define ADC_CSR_EOC1_Pos (1U)
  1589. #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
  1590. #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
  1591. #define ADC_CSR_JEOC1_Pos (2U)
  1592. #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
  1593. #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
  1594. #define ADC_CSR_JSTRT1_Pos (3U)
  1595. #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
  1596. #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
  1597. #define ADC_CSR_STRT1_Pos (4U)
  1598. #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
  1599. #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
  1600. #define ADC_CSR_OVR1_Pos (5U)
  1601. #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
  1602. #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
  1603. /* Legacy defines */
  1604. #define ADC_CSR_DOVR1 ADC_CSR_OVR1
  1605. /******************* Bit definition for ADC_CCR register ********************/
  1606. #define ADC_CCR_MULTI_Pos (0U)
  1607. #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
  1608. #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
  1609. #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
  1610. #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
  1611. #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
  1612. #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
  1613. #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
  1614. #define ADC_CCR_DELAY_Pos (8U)
  1615. #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
  1616. #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
  1617. #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
  1618. #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
  1619. #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
  1620. #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
  1621. #define ADC_CCR_DDS_Pos (13U)
  1622. #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
  1623. #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
  1624. #define ADC_CCR_DMA_Pos (14U)
  1625. #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
  1626. #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
  1627. #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
  1628. #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
  1629. #define ADC_CCR_ADCPRE_Pos (16U)
  1630. #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
  1631. #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
  1632. #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
  1633. #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
  1634. #define ADC_CCR_VBATE_Pos (22U)
  1635. #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
  1636. #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
  1637. #define ADC_CCR_TSVREFE_Pos (23U)
  1638. #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
  1639. #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
  1640. /******************* Bit definition for ADC_CDR register ********************/
  1641. #define ADC_CDR_DATA1_Pos (0U)
  1642. #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
  1643. #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
  1644. #define ADC_CDR_DATA2_Pos (16U)
  1645. #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
  1646. #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
  1647. /* Legacy defines */
  1648. #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
  1649. #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
  1650. /******************************************************************************/
  1651. /* */
  1652. /* Controller Area Network */
  1653. /* */
  1654. /******************************************************************************/
  1655. /*!<CAN control and status registers */
  1656. /******************* Bit definition for CAN_MCR register ********************/
  1657. #define CAN_MCR_INRQ_Pos (0U)
  1658. #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
  1659. #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
  1660. #define CAN_MCR_SLEEP_Pos (1U)
  1661. #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
  1662. #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
  1663. #define CAN_MCR_TXFP_Pos (2U)
  1664. #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
  1665. #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
  1666. #define CAN_MCR_RFLM_Pos (3U)
  1667. #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
  1668. #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
  1669. #define CAN_MCR_NART_Pos (4U)
  1670. #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
  1671. #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
  1672. #define CAN_MCR_AWUM_Pos (5U)
  1673. #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
  1674. #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
  1675. #define CAN_MCR_ABOM_Pos (6U)
  1676. #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
  1677. #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
  1678. #define CAN_MCR_TTCM_Pos (7U)
  1679. #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
  1680. #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
  1681. #define CAN_MCR_RESET_Pos (15U)
  1682. #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
  1683. #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
  1684. #define CAN_MCR_DBF_Pos (16U)
  1685. #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
  1686. #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
  1687. /******************* Bit definition for CAN_MSR register ********************/
  1688. #define CAN_MSR_INAK_Pos (0U)
  1689. #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
  1690. #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
  1691. #define CAN_MSR_SLAK_Pos (1U)
  1692. #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
  1693. #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
  1694. #define CAN_MSR_ERRI_Pos (2U)
  1695. #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
  1696. #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
  1697. #define CAN_MSR_WKUI_Pos (3U)
  1698. #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
  1699. #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
  1700. #define CAN_MSR_SLAKI_Pos (4U)
  1701. #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
  1702. #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
  1703. #define CAN_MSR_TXM_Pos (8U)
  1704. #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
  1705. #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
  1706. #define CAN_MSR_RXM_Pos (9U)
  1707. #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
  1708. #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
  1709. #define CAN_MSR_SAMP_Pos (10U)
  1710. #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
  1711. #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
  1712. #define CAN_MSR_RX_Pos (11U)
  1713. #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
  1714. #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
  1715. /******************* Bit definition for CAN_TSR register ********************/
  1716. #define CAN_TSR_RQCP0_Pos (0U)
  1717. #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
  1718. #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
  1719. #define CAN_TSR_TXOK0_Pos (1U)
  1720. #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
  1721. #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
  1722. #define CAN_TSR_ALST0_Pos (2U)
  1723. #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
  1724. #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
  1725. #define CAN_TSR_TERR0_Pos (3U)
  1726. #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
  1727. #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
  1728. #define CAN_TSR_ABRQ0_Pos (7U)
  1729. #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
  1730. #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
  1731. #define CAN_TSR_RQCP1_Pos (8U)
  1732. #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
  1733. #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
  1734. #define CAN_TSR_TXOK1_Pos (9U)
  1735. #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
  1736. #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
  1737. #define CAN_TSR_ALST1_Pos (10U)
  1738. #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
  1739. #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
  1740. #define CAN_TSR_TERR1_Pos (11U)
  1741. #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
  1742. #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
  1743. #define CAN_TSR_ABRQ1_Pos (15U)
  1744. #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
  1745. #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
  1746. #define CAN_TSR_RQCP2_Pos (16U)
  1747. #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
  1748. #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
  1749. #define CAN_TSR_TXOK2_Pos (17U)
  1750. #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
  1751. #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
  1752. #define CAN_TSR_ALST2_Pos (18U)
  1753. #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
  1754. #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
  1755. #define CAN_TSR_TERR2_Pos (19U)
  1756. #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
  1757. #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
  1758. #define CAN_TSR_ABRQ2_Pos (23U)
  1759. #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
  1760. #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
  1761. #define CAN_TSR_CODE_Pos (24U)
  1762. #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
  1763. #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
  1764. #define CAN_TSR_TME_Pos (26U)
  1765. #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
  1766. #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
  1767. #define CAN_TSR_TME0_Pos (26U)
  1768. #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
  1769. #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
  1770. #define CAN_TSR_TME1_Pos (27U)
  1771. #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
  1772. #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
  1773. #define CAN_TSR_TME2_Pos (28U)
  1774. #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
  1775. #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
  1776. #define CAN_TSR_LOW_Pos (29U)
  1777. #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
  1778. #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
  1779. #define CAN_TSR_LOW0_Pos (29U)
  1780. #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
  1781. #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
  1782. #define CAN_TSR_LOW1_Pos (30U)
  1783. #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
  1784. #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
  1785. #define CAN_TSR_LOW2_Pos (31U)
  1786. #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
  1787. #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
  1788. /******************* Bit definition for CAN_RF0R register *******************/
  1789. #define CAN_RF0R_FMP0_Pos (0U)
  1790. #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
  1791. #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
  1792. #define CAN_RF0R_FULL0_Pos (3U)
  1793. #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
  1794. #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
  1795. #define CAN_RF0R_FOVR0_Pos (4U)
  1796. #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
  1797. #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
  1798. #define CAN_RF0R_RFOM0_Pos (5U)
  1799. #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
  1800. #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
  1801. /******************* Bit definition for CAN_RF1R register *******************/
  1802. #define CAN_RF1R_FMP1_Pos (0U)
  1803. #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
  1804. #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
  1805. #define CAN_RF1R_FULL1_Pos (3U)
  1806. #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
  1807. #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
  1808. #define CAN_RF1R_FOVR1_Pos (4U)
  1809. #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
  1810. #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
  1811. #define CAN_RF1R_RFOM1_Pos (5U)
  1812. #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
  1813. #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
  1814. /******************** Bit definition for CAN_IER register *******************/
  1815. #define CAN_IER_TMEIE_Pos (0U)
  1816. #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
  1817. #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
  1818. #define CAN_IER_FMPIE0_Pos (1U)
  1819. #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
  1820. #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
  1821. #define CAN_IER_FFIE0_Pos (2U)
  1822. #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
  1823. #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
  1824. #define CAN_IER_FOVIE0_Pos (3U)
  1825. #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
  1826. #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
  1827. #define CAN_IER_FMPIE1_Pos (4U)
  1828. #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
  1829. #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
  1830. #define CAN_IER_FFIE1_Pos (5U)
  1831. #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
  1832. #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
  1833. #define CAN_IER_FOVIE1_Pos (6U)
  1834. #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
  1835. #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
  1836. #define CAN_IER_EWGIE_Pos (8U)
  1837. #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
  1838. #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
  1839. #define CAN_IER_EPVIE_Pos (9U)
  1840. #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
  1841. #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
  1842. #define CAN_IER_BOFIE_Pos (10U)
  1843. #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
  1844. #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
  1845. #define CAN_IER_LECIE_Pos (11U)
  1846. #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
  1847. #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
  1848. #define CAN_IER_ERRIE_Pos (15U)
  1849. #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
  1850. #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
  1851. #define CAN_IER_WKUIE_Pos (16U)
  1852. #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
  1853. #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
  1854. #define CAN_IER_SLKIE_Pos (17U)
  1855. #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
  1856. #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
  1857. #define CAN_IER_EWGIE_Pos (8U)
  1858. /******************** Bit definition for CAN_ESR register *******************/
  1859. #define CAN_ESR_EWGF_Pos (0U)
  1860. #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
  1861. #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
  1862. #define CAN_ESR_EPVF_Pos (1U)
  1863. #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
  1864. #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
  1865. #define CAN_ESR_BOFF_Pos (2U)
  1866. #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
  1867. #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
  1868. #define CAN_ESR_LEC_Pos (4U)
  1869. #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
  1870. #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
  1871. #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
  1872. #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
  1873. #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
  1874. #define CAN_ESR_TEC_Pos (16U)
  1875. #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
  1876. #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
  1877. #define CAN_ESR_REC_Pos (24U)
  1878. #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
  1879. #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
  1880. /******************* Bit definition for CAN_BTR register ********************/
  1881. #define CAN_BTR_BRP_Pos (0U)
  1882. #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
  1883. #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
  1884. #define CAN_BTR_TS1_Pos (16U)
  1885. #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
  1886. #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
  1887. #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
  1888. #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
  1889. #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
  1890. #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
  1891. #define CAN_BTR_TS2_Pos (20U)
  1892. #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
  1893. #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
  1894. #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
  1895. #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
  1896. #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
  1897. #define CAN_BTR_SJW_Pos (24U)
  1898. #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
  1899. #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
  1900. #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
  1901. #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
  1902. #define CAN_BTR_LBKM_Pos (30U)
  1903. #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
  1904. #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
  1905. #define CAN_BTR_SILM_Pos (31U)
  1906. #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
  1907. #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
  1908. /*!<Mailbox registers */
  1909. /****************** Bit definition for CAN_TI0R register ********************/
  1910. #define CAN_TI0R_TXRQ_Pos (0U)
  1911. #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
  1912. #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
  1913. #define CAN_TI0R_RTR_Pos (1U)
  1914. #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
  1915. #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
  1916. #define CAN_TI0R_IDE_Pos (2U)
  1917. #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
  1918. #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
  1919. #define CAN_TI0R_EXID_Pos (3U)
  1920. #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
  1921. #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
  1922. #define CAN_TI0R_STID_Pos (21U)
  1923. #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
  1924. #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  1925. /****************** Bit definition for CAN_TDT0R register *******************/
  1926. #define CAN_TDT0R_DLC_Pos (0U)
  1927. #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
  1928. #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
  1929. #define CAN_TDT0R_TGT_Pos (8U)
  1930. #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
  1931. #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
  1932. #define CAN_TDT0R_TIME_Pos (16U)
  1933. #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  1934. #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
  1935. /****************** Bit definition for CAN_TDL0R register *******************/
  1936. #define CAN_TDL0R_DATA0_Pos (0U)
  1937. #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
  1938. #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
  1939. #define CAN_TDL0R_DATA1_Pos (8U)
  1940. #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  1941. #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
  1942. #define CAN_TDL0R_DATA2_Pos (16U)
  1943. #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  1944. #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
  1945. #define CAN_TDL0R_DATA3_Pos (24U)
  1946. #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
  1947. #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
  1948. /****************** Bit definition for CAN_TDH0R register *******************/
  1949. #define CAN_TDH0R_DATA4_Pos (0U)
  1950. #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
  1951. #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
  1952. #define CAN_TDH0R_DATA5_Pos (8U)
  1953. #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  1954. #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
  1955. #define CAN_TDH0R_DATA6_Pos (16U)
  1956. #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  1957. #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
  1958. #define CAN_TDH0R_DATA7_Pos (24U)
  1959. #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
  1960. #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
  1961. /******************* Bit definition for CAN_TI1R register *******************/
  1962. #define CAN_TI1R_TXRQ_Pos (0U)
  1963. #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
  1964. #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
  1965. #define CAN_TI1R_RTR_Pos (1U)
  1966. #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
  1967. #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
  1968. #define CAN_TI1R_IDE_Pos (2U)
  1969. #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
  1970. #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
  1971. #define CAN_TI1R_EXID_Pos (3U)
  1972. #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
  1973. #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
  1974. #define CAN_TI1R_STID_Pos (21U)
  1975. #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
  1976. #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  1977. /******************* Bit definition for CAN_TDT1R register ******************/
  1978. #define CAN_TDT1R_DLC_Pos (0U)
  1979. #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
  1980. #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
  1981. #define CAN_TDT1R_TGT_Pos (8U)
  1982. #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
  1983. #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
  1984. #define CAN_TDT1R_TIME_Pos (16U)
  1985. #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  1986. #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
  1987. /******************* Bit definition for CAN_TDL1R register ******************/
  1988. #define CAN_TDL1R_DATA0_Pos (0U)
  1989. #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
  1990. #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
  1991. #define CAN_TDL1R_DATA1_Pos (8U)
  1992. #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  1993. #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
  1994. #define CAN_TDL1R_DATA2_Pos (16U)
  1995. #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  1996. #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
  1997. #define CAN_TDL1R_DATA3_Pos (24U)
  1998. #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
  1999. #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
  2000. /******************* Bit definition for CAN_TDH1R register ******************/
  2001. #define CAN_TDH1R_DATA4_Pos (0U)
  2002. #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
  2003. #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
  2004. #define CAN_TDH1R_DATA5_Pos (8U)
  2005. #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2006. #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
  2007. #define CAN_TDH1R_DATA6_Pos (16U)
  2008. #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2009. #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
  2010. #define CAN_TDH1R_DATA7_Pos (24U)
  2011. #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2012. #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
  2013. /******************* Bit definition for CAN_TI2R register *******************/
  2014. #define CAN_TI2R_TXRQ_Pos (0U)
  2015. #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
  2016. #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2017. #define CAN_TI2R_RTR_Pos (1U)
  2018. #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
  2019. #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
  2020. #define CAN_TI2R_IDE_Pos (2U)
  2021. #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
  2022. #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
  2023. #define CAN_TI2R_EXID_Pos (3U)
  2024. #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
  2025. #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
  2026. #define CAN_TI2R_STID_Pos (21U)
  2027. #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
  2028. #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2029. /******************* Bit definition for CAN_TDT2R register ******************/
  2030. #define CAN_TDT2R_DLC_Pos (0U)
  2031. #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
  2032. #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
  2033. #define CAN_TDT2R_TGT_Pos (8U)
  2034. #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
  2035. #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
  2036. #define CAN_TDT2R_TIME_Pos (16U)
  2037. #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
  2038. #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
  2039. /******************* Bit definition for CAN_TDL2R register ******************/
  2040. #define CAN_TDL2R_DATA0_Pos (0U)
  2041. #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
  2042. #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
  2043. #define CAN_TDL2R_DATA1_Pos (8U)
  2044. #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
  2045. #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
  2046. #define CAN_TDL2R_DATA2_Pos (16U)
  2047. #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
  2048. #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
  2049. #define CAN_TDL2R_DATA3_Pos (24U)
  2050. #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
  2051. #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
  2052. /******************* Bit definition for CAN_TDH2R register ******************/
  2053. #define CAN_TDH2R_DATA4_Pos (0U)
  2054. #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
  2055. #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
  2056. #define CAN_TDH2R_DATA5_Pos (8U)
  2057. #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
  2058. #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
  2059. #define CAN_TDH2R_DATA6_Pos (16U)
  2060. #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
  2061. #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
  2062. #define CAN_TDH2R_DATA7_Pos (24U)
  2063. #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
  2064. #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
  2065. /******************* Bit definition for CAN_RI0R register *******************/
  2066. #define CAN_RI0R_RTR_Pos (1U)
  2067. #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
  2068. #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
  2069. #define CAN_RI0R_IDE_Pos (2U)
  2070. #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
  2071. #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
  2072. #define CAN_RI0R_EXID_Pos (3U)
  2073. #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2074. #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
  2075. #define CAN_RI0R_STID_Pos (21U)
  2076. #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
  2077. #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2078. /******************* Bit definition for CAN_RDT0R register ******************/
  2079. #define CAN_RDT0R_DLC_Pos (0U)
  2080. #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
  2081. #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
  2082. #define CAN_RDT0R_FMI_Pos (8U)
  2083. #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
  2084. #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
  2085. #define CAN_RDT0R_TIME_Pos (16U)
  2086. #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2087. #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
  2088. /******************* Bit definition for CAN_RDL0R register ******************/
  2089. #define CAN_RDL0R_DATA0_Pos (0U)
  2090. #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
  2091. #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
  2092. #define CAN_RDL0R_DATA1_Pos (8U)
  2093. #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2094. #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
  2095. #define CAN_RDL0R_DATA2_Pos (16U)
  2096. #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2097. #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
  2098. #define CAN_RDL0R_DATA3_Pos (24U)
  2099. #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2100. #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
  2101. /******************* Bit definition for CAN_RDH0R register ******************/
  2102. #define CAN_RDH0R_DATA4_Pos (0U)
  2103. #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
  2104. #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
  2105. #define CAN_RDH0R_DATA5_Pos (8U)
  2106. #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2107. #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
  2108. #define CAN_RDH0R_DATA6_Pos (16U)
  2109. #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2110. #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
  2111. #define CAN_RDH0R_DATA7_Pos (24U)
  2112. #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2113. #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
  2114. /******************* Bit definition for CAN_RI1R register *******************/
  2115. #define CAN_RI1R_RTR_Pos (1U)
  2116. #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
  2117. #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
  2118. #define CAN_RI1R_IDE_Pos (2U)
  2119. #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
  2120. #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
  2121. #define CAN_RI1R_EXID_Pos (3U)
  2122. #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2123. #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
  2124. #define CAN_RI1R_STID_Pos (21U)
  2125. #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
  2126. #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2127. /******************* Bit definition for CAN_RDT1R register ******************/
  2128. #define CAN_RDT1R_DLC_Pos (0U)
  2129. #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
  2130. #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
  2131. #define CAN_RDT1R_FMI_Pos (8U)
  2132. #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
  2133. #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
  2134. #define CAN_RDT1R_TIME_Pos (16U)
  2135. #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2136. #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
  2137. /******************* Bit definition for CAN_RDL1R register ******************/
  2138. #define CAN_RDL1R_DATA0_Pos (0U)
  2139. #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
  2140. #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
  2141. #define CAN_RDL1R_DATA1_Pos (8U)
  2142. #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2143. #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
  2144. #define CAN_RDL1R_DATA2_Pos (16U)
  2145. #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2146. #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
  2147. #define CAN_RDL1R_DATA3_Pos (24U)
  2148. #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2149. #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
  2150. /******************* Bit definition for CAN_RDH1R register ******************/
  2151. #define CAN_RDH1R_DATA4_Pos (0U)
  2152. #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
  2153. #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
  2154. #define CAN_RDH1R_DATA5_Pos (8U)
  2155. #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2156. #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
  2157. #define CAN_RDH1R_DATA6_Pos (16U)
  2158. #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2159. #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
  2160. #define CAN_RDH1R_DATA7_Pos (24U)
  2161. #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2162. #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
  2163. /*!<CAN filter registers */
  2164. /******************* Bit definition for CAN_FMR register ********************/
  2165. #define CAN_FMR_FINIT_Pos (0U)
  2166. #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
  2167. #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
  2168. #define CAN_FMR_CAN2SB_Pos (8U)
  2169. #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
  2170. #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
  2171. /******************* Bit definition for CAN_FM1R register *******************/
  2172. #define CAN_FM1R_FBM_Pos (0U)
  2173. #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
  2174. #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
  2175. #define CAN_FM1R_FBM0_Pos (0U)
  2176. #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
  2177. #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
  2178. #define CAN_FM1R_FBM1_Pos (1U)
  2179. #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
  2180. #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
  2181. #define CAN_FM1R_FBM2_Pos (2U)
  2182. #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
  2183. #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
  2184. #define CAN_FM1R_FBM3_Pos (3U)
  2185. #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
  2186. #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
  2187. #define CAN_FM1R_FBM4_Pos (4U)
  2188. #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
  2189. #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
  2190. #define CAN_FM1R_FBM5_Pos (5U)
  2191. #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
  2192. #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
  2193. #define CAN_FM1R_FBM6_Pos (6U)
  2194. #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
  2195. #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
  2196. #define CAN_FM1R_FBM7_Pos (7U)
  2197. #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
  2198. #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
  2199. #define CAN_FM1R_FBM8_Pos (8U)
  2200. #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
  2201. #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
  2202. #define CAN_FM1R_FBM9_Pos (9U)
  2203. #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
  2204. #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
  2205. #define CAN_FM1R_FBM10_Pos (10U)
  2206. #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
  2207. #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
  2208. #define CAN_FM1R_FBM11_Pos (11U)
  2209. #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
  2210. #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
  2211. #define CAN_FM1R_FBM12_Pos (12U)
  2212. #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
  2213. #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
  2214. #define CAN_FM1R_FBM13_Pos (13U)
  2215. #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
  2216. #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
  2217. #define CAN_FM1R_FBM14_Pos (14U)
  2218. #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
  2219. #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
  2220. #define CAN_FM1R_FBM15_Pos (15U)
  2221. #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
  2222. #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
  2223. #define CAN_FM1R_FBM16_Pos (16U)
  2224. #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
  2225. #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
  2226. #define CAN_FM1R_FBM17_Pos (17U)
  2227. #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
  2228. #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
  2229. #define CAN_FM1R_FBM18_Pos (18U)
  2230. #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
  2231. #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
  2232. #define CAN_FM1R_FBM19_Pos (19U)
  2233. #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
  2234. #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
  2235. #define CAN_FM1R_FBM20_Pos (20U)
  2236. #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
  2237. #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
  2238. #define CAN_FM1R_FBM21_Pos (21U)
  2239. #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
  2240. #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
  2241. #define CAN_FM1R_FBM22_Pos (22U)
  2242. #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
  2243. #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
  2244. #define CAN_FM1R_FBM23_Pos (23U)
  2245. #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
  2246. #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
  2247. #define CAN_FM1R_FBM24_Pos (24U)
  2248. #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
  2249. #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
  2250. #define CAN_FM1R_FBM25_Pos (25U)
  2251. #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
  2252. #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
  2253. #define CAN_FM1R_FBM26_Pos (26U)
  2254. #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
  2255. #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
  2256. #define CAN_FM1R_FBM27_Pos (27U)
  2257. #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
  2258. #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
  2259. /******************* Bit definition for CAN_FS1R register *******************/
  2260. #define CAN_FS1R_FSC_Pos (0U)
  2261. #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
  2262. #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
  2263. #define CAN_FS1R_FSC0_Pos (0U)
  2264. #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
  2265. #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
  2266. #define CAN_FS1R_FSC1_Pos (1U)
  2267. #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
  2268. #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
  2269. #define CAN_FS1R_FSC2_Pos (2U)
  2270. #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
  2271. #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
  2272. #define CAN_FS1R_FSC3_Pos (3U)
  2273. #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
  2274. #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
  2275. #define CAN_FS1R_FSC4_Pos (4U)
  2276. #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
  2277. #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
  2278. #define CAN_FS1R_FSC5_Pos (5U)
  2279. #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
  2280. #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
  2281. #define CAN_FS1R_FSC6_Pos (6U)
  2282. #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
  2283. #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
  2284. #define CAN_FS1R_FSC7_Pos (7U)
  2285. #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
  2286. #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
  2287. #define CAN_FS1R_FSC8_Pos (8U)
  2288. #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
  2289. #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
  2290. #define CAN_FS1R_FSC9_Pos (9U)
  2291. #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
  2292. #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
  2293. #define CAN_FS1R_FSC10_Pos (10U)
  2294. #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
  2295. #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
  2296. #define CAN_FS1R_FSC11_Pos (11U)
  2297. #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
  2298. #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
  2299. #define CAN_FS1R_FSC12_Pos (12U)
  2300. #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
  2301. #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
  2302. #define CAN_FS1R_FSC13_Pos (13U)
  2303. #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
  2304. #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
  2305. #define CAN_FS1R_FSC14_Pos (14U)
  2306. #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
  2307. #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
  2308. #define CAN_FS1R_FSC15_Pos (15U)
  2309. #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
  2310. #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
  2311. #define CAN_FS1R_FSC16_Pos (16U)
  2312. #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
  2313. #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
  2314. #define CAN_FS1R_FSC17_Pos (17U)
  2315. #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
  2316. #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
  2317. #define CAN_FS1R_FSC18_Pos (18U)
  2318. #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
  2319. #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
  2320. #define CAN_FS1R_FSC19_Pos (19U)
  2321. #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
  2322. #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
  2323. #define CAN_FS1R_FSC20_Pos (20U)
  2324. #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
  2325. #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
  2326. #define CAN_FS1R_FSC21_Pos (21U)
  2327. #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
  2328. #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
  2329. #define CAN_FS1R_FSC22_Pos (22U)
  2330. #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
  2331. #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
  2332. #define CAN_FS1R_FSC23_Pos (23U)
  2333. #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
  2334. #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
  2335. #define CAN_FS1R_FSC24_Pos (24U)
  2336. #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
  2337. #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
  2338. #define CAN_FS1R_FSC25_Pos (25U)
  2339. #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
  2340. #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
  2341. #define CAN_FS1R_FSC26_Pos (26U)
  2342. #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
  2343. #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
  2344. #define CAN_FS1R_FSC27_Pos (27U)
  2345. #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
  2346. #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
  2347. /****************** Bit definition for CAN_FFA1R register *******************/
  2348. #define CAN_FFA1R_FFA_Pos (0U)
  2349. #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
  2350. #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
  2351. #define CAN_FFA1R_FFA0_Pos (0U)
  2352. #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
  2353. #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
  2354. #define CAN_FFA1R_FFA1_Pos (1U)
  2355. #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
  2356. #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
  2357. #define CAN_FFA1R_FFA2_Pos (2U)
  2358. #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
  2359. #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
  2360. #define CAN_FFA1R_FFA3_Pos (3U)
  2361. #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
  2362. #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
  2363. #define CAN_FFA1R_FFA4_Pos (4U)
  2364. #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
  2365. #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
  2366. #define CAN_FFA1R_FFA5_Pos (5U)
  2367. #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
  2368. #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
  2369. #define CAN_FFA1R_FFA6_Pos (6U)
  2370. #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
  2371. #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
  2372. #define CAN_FFA1R_FFA7_Pos (7U)
  2373. #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
  2374. #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
  2375. #define CAN_FFA1R_FFA8_Pos (8U)
  2376. #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
  2377. #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
  2378. #define CAN_FFA1R_FFA9_Pos (9U)
  2379. #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
  2380. #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
  2381. #define CAN_FFA1R_FFA10_Pos (10U)
  2382. #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
  2383. #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
  2384. #define CAN_FFA1R_FFA11_Pos (11U)
  2385. #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
  2386. #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
  2387. #define CAN_FFA1R_FFA12_Pos (12U)
  2388. #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
  2389. #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
  2390. #define CAN_FFA1R_FFA13_Pos (13U)
  2391. #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
  2392. #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
  2393. #define CAN_FFA1R_FFA14_Pos (14U)
  2394. #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
  2395. #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
  2396. #define CAN_FFA1R_FFA15_Pos (15U)
  2397. #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
  2398. #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
  2399. #define CAN_FFA1R_FFA16_Pos (16U)
  2400. #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
  2401. #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
  2402. #define CAN_FFA1R_FFA17_Pos (17U)
  2403. #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
  2404. #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
  2405. #define CAN_FFA1R_FFA18_Pos (18U)
  2406. #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
  2407. #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
  2408. #define CAN_FFA1R_FFA19_Pos (19U)
  2409. #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
  2410. #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
  2411. #define CAN_FFA1R_FFA20_Pos (20U)
  2412. #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
  2413. #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
  2414. #define CAN_FFA1R_FFA21_Pos (21U)
  2415. #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
  2416. #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
  2417. #define CAN_FFA1R_FFA22_Pos (22U)
  2418. #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
  2419. #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
  2420. #define CAN_FFA1R_FFA23_Pos (23U)
  2421. #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
  2422. #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
  2423. #define CAN_FFA1R_FFA24_Pos (24U)
  2424. #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
  2425. #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
  2426. #define CAN_FFA1R_FFA25_Pos (25U)
  2427. #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
  2428. #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
  2429. #define CAN_FFA1R_FFA26_Pos (26U)
  2430. #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
  2431. #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
  2432. #define CAN_FFA1R_FFA27_Pos (27U)
  2433. #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
  2434. #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
  2435. /******************* Bit definition for CAN_FA1R register *******************/
  2436. #define CAN_FA1R_FACT_Pos (0U)
  2437. #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
  2438. #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
  2439. #define CAN_FA1R_FACT0_Pos (0U)
  2440. #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
  2441. #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
  2442. #define CAN_FA1R_FACT1_Pos (1U)
  2443. #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
  2444. #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
  2445. #define CAN_FA1R_FACT2_Pos (2U)
  2446. #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
  2447. #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
  2448. #define CAN_FA1R_FACT3_Pos (3U)
  2449. #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
  2450. #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
  2451. #define CAN_FA1R_FACT4_Pos (4U)
  2452. #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
  2453. #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
  2454. #define CAN_FA1R_FACT5_Pos (5U)
  2455. #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
  2456. #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
  2457. #define CAN_FA1R_FACT6_Pos (6U)
  2458. #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
  2459. #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
  2460. #define CAN_FA1R_FACT7_Pos (7U)
  2461. #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
  2462. #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
  2463. #define CAN_FA1R_FACT8_Pos (8U)
  2464. #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
  2465. #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
  2466. #define CAN_FA1R_FACT9_Pos (9U)
  2467. #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
  2468. #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
  2469. #define CAN_FA1R_FACT10_Pos (10U)
  2470. #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
  2471. #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
  2472. #define CAN_FA1R_FACT11_Pos (11U)
  2473. #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
  2474. #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
  2475. #define CAN_FA1R_FACT12_Pos (12U)
  2476. #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
  2477. #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
  2478. #define CAN_FA1R_FACT13_Pos (13U)
  2479. #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
  2480. #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
  2481. #define CAN_FA1R_FACT14_Pos (14U)
  2482. #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
  2483. #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
  2484. #define CAN_FA1R_FACT15_Pos (15U)
  2485. #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
  2486. #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
  2487. #define CAN_FA1R_FACT16_Pos (16U)
  2488. #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
  2489. #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
  2490. #define CAN_FA1R_FACT17_Pos (17U)
  2491. #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
  2492. #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
  2493. #define CAN_FA1R_FACT18_Pos (18U)
  2494. #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
  2495. #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
  2496. #define CAN_FA1R_FACT19_Pos (19U)
  2497. #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
  2498. #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
  2499. #define CAN_FA1R_FACT20_Pos (20U)
  2500. #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
  2501. #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
  2502. #define CAN_FA1R_FACT21_Pos (21U)
  2503. #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
  2504. #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
  2505. #define CAN_FA1R_FACT22_Pos (22U)
  2506. #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
  2507. #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
  2508. #define CAN_FA1R_FACT23_Pos (23U)
  2509. #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
  2510. #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
  2511. #define CAN_FA1R_FACT24_Pos (24U)
  2512. #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
  2513. #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
  2514. #define CAN_FA1R_FACT25_Pos (25U)
  2515. #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
  2516. #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
  2517. #define CAN_FA1R_FACT26_Pos (26U)
  2518. #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
  2519. #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
  2520. #define CAN_FA1R_FACT27_Pos (27U)
  2521. #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
  2522. #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
  2523. /******************* Bit definition for CAN_F0R1 register *******************/
  2524. #define CAN_F0R1_FB0_Pos (0U)
  2525. #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
  2526. #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
  2527. #define CAN_F0R1_FB1_Pos (1U)
  2528. #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
  2529. #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
  2530. #define CAN_F0R1_FB2_Pos (2U)
  2531. #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
  2532. #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
  2533. #define CAN_F0R1_FB3_Pos (3U)
  2534. #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
  2535. #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
  2536. #define CAN_F0R1_FB4_Pos (4U)
  2537. #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
  2538. #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
  2539. #define CAN_F0R1_FB5_Pos (5U)
  2540. #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
  2541. #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
  2542. #define CAN_F0R1_FB6_Pos (6U)
  2543. #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
  2544. #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
  2545. #define CAN_F0R1_FB7_Pos (7U)
  2546. #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
  2547. #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
  2548. #define CAN_F0R1_FB8_Pos (8U)
  2549. #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
  2550. #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
  2551. #define CAN_F0R1_FB9_Pos (9U)
  2552. #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
  2553. #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
  2554. #define CAN_F0R1_FB10_Pos (10U)
  2555. #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
  2556. #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
  2557. #define CAN_F0R1_FB11_Pos (11U)
  2558. #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
  2559. #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
  2560. #define CAN_F0R1_FB12_Pos (12U)
  2561. #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
  2562. #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
  2563. #define CAN_F0R1_FB13_Pos (13U)
  2564. #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
  2565. #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
  2566. #define CAN_F0R1_FB14_Pos (14U)
  2567. #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
  2568. #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
  2569. #define CAN_F0R1_FB15_Pos (15U)
  2570. #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
  2571. #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
  2572. #define CAN_F0R1_FB16_Pos (16U)
  2573. #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
  2574. #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
  2575. #define CAN_F0R1_FB17_Pos (17U)
  2576. #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
  2577. #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
  2578. #define CAN_F0R1_FB18_Pos (18U)
  2579. #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
  2580. #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
  2581. #define CAN_F0R1_FB19_Pos (19U)
  2582. #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
  2583. #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
  2584. #define CAN_F0R1_FB20_Pos (20U)
  2585. #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
  2586. #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
  2587. #define CAN_F0R1_FB21_Pos (21U)
  2588. #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
  2589. #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
  2590. #define CAN_F0R1_FB22_Pos (22U)
  2591. #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
  2592. #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
  2593. #define CAN_F0R1_FB23_Pos (23U)
  2594. #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
  2595. #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
  2596. #define CAN_F0R1_FB24_Pos (24U)
  2597. #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
  2598. #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
  2599. #define CAN_F0R1_FB25_Pos (25U)
  2600. #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
  2601. #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
  2602. #define CAN_F0R1_FB26_Pos (26U)
  2603. #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
  2604. #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
  2605. #define CAN_F0R1_FB27_Pos (27U)
  2606. #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
  2607. #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
  2608. #define CAN_F0R1_FB28_Pos (28U)
  2609. #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
  2610. #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
  2611. #define CAN_F0R1_FB29_Pos (29U)
  2612. #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
  2613. #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
  2614. #define CAN_F0R1_FB30_Pos (30U)
  2615. #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
  2616. #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
  2617. #define CAN_F0R1_FB31_Pos (31U)
  2618. #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
  2619. #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
  2620. /******************* Bit definition for CAN_F1R1 register *******************/
  2621. #define CAN_F1R1_FB0_Pos (0U)
  2622. #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
  2623. #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
  2624. #define CAN_F1R1_FB1_Pos (1U)
  2625. #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
  2626. #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
  2627. #define CAN_F1R1_FB2_Pos (2U)
  2628. #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
  2629. #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
  2630. #define CAN_F1R1_FB3_Pos (3U)
  2631. #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
  2632. #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
  2633. #define CAN_F1R1_FB4_Pos (4U)
  2634. #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
  2635. #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
  2636. #define CAN_F1R1_FB5_Pos (5U)
  2637. #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
  2638. #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
  2639. #define CAN_F1R1_FB6_Pos (6U)
  2640. #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
  2641. #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
  2642. #define CAN_F1R1_FB7_Pos (7U)
  2643. #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
  2644. #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
  2645. #define CAN_F1R1_FB8_Pos (8U)
  2646. #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
  2647. #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
  2648. #define CAN_F1R1_FB9_Pos (9U)
  2649. #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
  2650. #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
  2651. #define CAN_F1R1_FB10_Pos (10U)
  2652. #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
  2653. #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
  2654. #define CAN_F1R1_FB11_Pos (11U)
  2655. #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
  2656. #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
  2657. #define CAN_F1R1_FB12_Pos (12U)
  2658. #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
  2659. #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
  2660. #define CAN_F1R1_FB13_Pos (13U)
  2661. #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
  2662. #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
  2663. #define CAN_F1R1_FB14_Pos (14U)
  2664. #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
  2665. #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
  2666. #define CAN_F1R1_FB15_Pos (15U)
  2667. #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
  2668. #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
  2669. #define CAN_F1R1_FB16_Pos (16U)
  2670. #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
  2671. #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
  2672. #define CAN_F1R1_FB17_Pos (17U)
  2673. #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
  2674. #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
  2675. #define CAN_F1R1_FB18_Pos (18U)
  2676. #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
  2677. #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
  2678. #define CAN_F1R1_FB19_Pos (19U)
  2679. #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
  2680. #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
  2681. #define CAN_F1R1_FB20_Pos (20U)
  2682. #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
  2683. #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
  2684. #define CAN_F1R1_FB21_Pos (21U)
  2685. #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
  2686. #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
  2687. #define CAN_F1R1_FB22_Pos (22U)
  2688. #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
  2689. #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
  2690. #define CAN_F1R1_FB23_Pos (23U)
  2691. #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
  2692. #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
  2693. #define CAN_F1R1_FB24_Pos (24U)
  2694. #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
  2695. #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
  2696. #define CAN_F1R1_FB25_Pos (25U)
  2697. #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
  2698. #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
  2699. #define CAN_F1R1_FB26_Pos (26U)
  2700. #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
  2701. #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
  2702. #define CAN_F1R1_FB27_Pos (27U)
  2703. #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
  2704. #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
  2705. #define CAN_F1R1_FB28_Pos (28U)
  2706. #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
  2707. #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
  2708. #define CAN_F1R1_FB29_Pos (29U)
  2709. #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
  2710. #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
  2711. #define CAN_F1R1_FB30_Pos (30U)
  2712. #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
  2713. #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
  2714. #define CAN_F1R1_FB31_Pos (31U)
  2715. #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
  2716. #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
  2717. /******************* Bit definition for CAN_F2R1 register *******************/
  2718. #define CAN_F2R1_FB0_Pos (0U)
  2719. #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
  2720. #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
  2721. #define CAN_F2R1_FB1_Pos (1U)
  2722. #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
  2723. #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
  2724. #define CAN_F2R1_FB2_Pos (2U)
  2725. #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
  2726. #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
  2727. #define CAN_F2R1_FB3_Pos (3U)
  2728. #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
  2729. #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
  2730. #define CAN_F2R1_FB4_Pos (4U)
  2731. #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
  2732. #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
  2733. #define CAN_F2R1_FB5_Pos (5U)
  2734. #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
  2735. #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
  2736. #define CAN_F2R1_FB6_Pos (6U)
  2737. #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
  2738. #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
  2739. #define CAN_F2R1_FB7_Pos (7U)
  2740. #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
  2741. #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
  2742. #define CAN_F2R1_FB8_Pos (8U)
  2743. #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
  2744. #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
  2745. #define CAN_F2R1_FB9_Pos (9U)
  2746. #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
  2747. #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
  2748. #define CAN_F2R1_FB10_Pos (10U)
  2749. #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
  2750. #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
  2751. #define CAN_F2R1_FB11_Pos (11U)
  2752. #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
  2753. #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
  2754. #define CAN_F2R1_FB12_Pos (12U)
  2755. #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
  2756. #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
  2757. #define CAN_F2R1_FB13_Pos (13U)
  2758. #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
  2759. #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
  2760. #define CAN_F2R1_FB14_Pos (14U)
  2761. #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
  2762. #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
  2763. #define CAN_F2R1_FB15_Pos (15U)
  2764. #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
  2765. #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
  2766. #define CAN_F2R1_FB16_Pos (16U)
  2767. #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
  2768. #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
  2769. #define CAN_F2R1_FB17_Pos (17U)
  2770. #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
  2771. #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
  2772. #define CAN_F2R1_FB18_Pos (18U)
  2773. #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
  2774. #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
  2775. #define CAN_F2R1_FB19_Pos (19U)
  2776. #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
  2777. #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
  2778. #define CAN_F2R1_FB20_Pos (20U)
  2779. #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
  2780. #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
  2781. #define CAN_F2R1_FB21_Pos (21U)
  2782. #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
  2783. #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
  2784. #define CAN_F2R1_FB22_Pos (22U)
  2785. #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
  2786. #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
  2787. #define CAN_F2R1_FB23_Pos (23U)
  2788. #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
  2789. #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
  2790. #define CAN_F2R1_FB24_Pos (24U)
  2791. #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
  2792. #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
  2793. #define CAN_F2R1_FB25_Pos (25U)
  2794. #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
  2795. #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
  2796. #define CAN_F2R1_FB26_Pos (26U)
  2797. #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
  2798. #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
  2799. #define CAN_F2R1_FB27_Pos (27U)
  2800. #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
  2801. #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
  2802. #define CAN_F2R1_FB28_Pos (28U)
  2803. #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
  2804. #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
  2805. #define CAN_F2R1_FB29_Pos (29U)
  2806. #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
  2807. #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
  2808. #define CAN_F2R1_FB30_Pos (30U)
  2809. #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
  2810. #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
  2811. #define CAN_F2R1_FB31_Pos (31U)
  2812. #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
  2813. #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
  2814. /******************* Bit definition for CAN_F3R1 register *******************/
  2815. #define CAN_F3R1_FB0_Pos (0U)
  2816. #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
  2817. #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
  2818. #define CAN_F3R1_FB1_Pos (1U)
  2819. #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
  2820. #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
  2821. #define CAN_F3R1_FB2_Pos (2U)
  2822. #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
  2823. #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
  2824. #define CAN_F3R1_FB3_Pos (3U)
  2825. #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
  2826. #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
  2827. #define CAN_F3R1_FB4_Pos (4U)
  2828. #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
  2829. #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
  2830. #define CAN_F3R1_FB5_Pos (5U)
  2831. #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
  2832. #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
  2833. #define CAN_F3R1_FB6_Pos (6U)
  2834. #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
  2835. #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
  2836. #define CAN_F3R1_FB7_Pos (7U)
  2837. #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
  2838. #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
  2839. #define CAN_F3R1_FB8_Pos (8U)
  2840. #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
  2841. #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
  2842. #define CAN_F3R1_FB9_Pos (9U)
  2843. #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
  2844. #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
  2845. #define CAN_F3R1_FB10_Pos (10U)
  2846. #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
  2847. #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
  2848. #define CAN_F3R1_FB11_Pos (11U)
  2849. #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
  2850. #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
  2851. #define CAN_F3R1_FB12_Pos (12U)
  2852. #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
  2853. #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
  2854. #define CAN_F3R1_FB13_Pos (13U)
  2855. #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
  2856. #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
  2857. #define CAN_F3R1_FB14_Pos (14U)
  2858. #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
  2859. #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
  2860. #define CAN_F3R1_FB15_Pos (15U)
  2861. #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
  2862. #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
  2863. #define CAN_F3R1_FB16_Pos (16U)
  2864. #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
  2865. #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
  2866. #define CAN_F3R1_FB17_Pos (17U)
  2867. #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
  2868. #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
  2869. #define CAN_F3R1_FB18_Pos (18U)
  2870. #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
  2871. #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
  2872. #define CAN_F3R1_FB19_Pos (19U)
  2873. #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
  2874. #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
  2875. #define CAN_F3R1_FB20_Pos (20U)
  2876. #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
  2877. #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
  2878. #define CAN_F3R1_FB21_Pos (21U)
  2879. #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
  2880. #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
  2881. #define CAN_F3R1_FB22_Pos (22U)
  2882. #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
  2883. #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
  2884. #define CAN_F3R1_FB23_Pos (23U)
  2885. #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
  2886. #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
  2887. #define CAN_F3R1_FB24_Pos (24U)
  2888. #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
  2889. #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
  2890. #define CAN_F3R1_FB25_Pos (25U)
  2891. #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
  2892. #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
  2893. #define CAN_F3R1_FB26_Pos (26U)
  2894. #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
  2895. #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
  2896. #define CAN_F3R1_FB27_Pos (27U)
  2897. #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
  2898. #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
  2899. #define CAN_F3R1_FB28_Pos (28U)
  2900. #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
  2901. #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
  2902. #define CAN_F3R1_FB29_Pos (29U)
  2903. #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
  2904. #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
  2905. #define CAN_F3R1_FB30_Pos (30U)
  2906. #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
  2907. #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
  2908. #define CAN_F3R1_FB31_Pos (31U)
  2909. #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
  2910. #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
  2911. /******************* Bit definition for CAN_F4R1 register *******************/
  2912. #define CAN_F4R1_FB0_Pos (0U)
  2913. #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
  2914. #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
  2915. #define CAN_F4R1_FB1_Pos (1U)
  2916. #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
  2917. #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
  2918. #define CAN_F4R1_FB2_Pos (2U)
  2919. #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
  2920. #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
  2921. #define CAN_F4R1_FB3_Pos (3U)
  2922. #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
  2923. #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
  2924. #define CAN_F4R1_FB4_Pos (4U)
  2925. #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
  2926. #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
  2927. #define CAN_F4R1_FB5_Pos (5U)
  2928. #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
  2929. #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
  2930. #define CAN_F4R1_FB6_Pos (6U)
  2931. #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
  2932. #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
  2933. #define CAN_F4R1_FB7_Pos (7U)
  2934. #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
  2935. #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
  2936. #define CAN_F4R1_FB8_Pos (8U)
  2937. #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
  2938. #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
  2939. #define CAN_F4R1_FB9_Pos (9U)
  2940. #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
  2941. #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
  2942. #define CAN_F4R1_FB10_Pos (10U)
  2943. #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
  2944. #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
  2945. #define CAN_F4R1_FB11_Pos (11U)
  2946. #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
  2947. #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
  2948. #define CAN_F4R1_FB12_Pos (12U)
  2949. #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
  2950. #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
  2951. #define CAN_F4R1_FB13_Pos (13U)
  2952. #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
  2953. #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
  2954. #define CAN_F4R1_FB14_Pos (14U)
  2955. #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
  2956. #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
  2957. #define CAN_F4R1_FB15_Pos (15U)
  2958. #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
  2959. #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
  2960. #define CAN_F4R1_FB16_Pos (16U)
  2961. #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
  2962. #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
  2963. #define CAN_F4R1_FB17_Pos (17U)
  2964. #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
  2965. #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
  2966. #define CAN_F4R1_FB18_Pos (18U)
  2967. #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
  2968. #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
  2969. #define CAN_F4R1_FB19_Pos (19U)
  2970. #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
  2971. #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
  2972. #define CAN_F4R1_FB20_Pos (20U)
  2973. #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
  2974. #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
  2975. #define CAN_F4R1_FB21_Pos (21U)
  2976. #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
  2977. #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
  2978. #define CAN_F4R1_FB22_Pos (22U)
  2979. #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
  2980. #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
  2981. #define CAN_F4R1_FB23_Pos (23U)
  2982. #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
  2983. #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
  2984. #define CAN_F4R1_FB24_Pos (24U)
  2985. #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
  2986. #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
  2987. #define CAN_F4R1_FB25_Pos (25U)
  2988. #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
  2989. #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
  2990. #define CAN_F4R1_FB26_Pos (26U)
  2991. #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
  2992. #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
  2993. #define CAN_F4R1_FB27_Pos (27U)
  2994. #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
  2995. #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
  2996. #define CAN_F4R1_FB28_Pos (28U)
  2997. #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
  2998. #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
  2999. #define CAN_F4R1_FB29_Pos (29U)
  3000. #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
  3001. #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
  3002. #define CAN_F4R1_FB30_Pos (30U)
  3003. #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
  3004. #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
  3005. #define CAN_F4R1_FB31_Pos (31U)
  3006. #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
  3007. #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
  3008. /******************* Bit definition for CAN_F5R1 register *******************/
  3009. #define CAN_F5R1_FB0_Pos (0U)
  3010. #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
  3011. #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
  3012. #define CAN_F5R1_FB1_Pos (1U)
  3013. #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
  3014. #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
  3015. #define CAN_F5R1_FB2_Pos (2U)
  3016. #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
  3017. #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
  3018. #define CAN_F5R1_FB3_Pos (3U)
  3019. #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
  3020. #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
  3021. #define CAN_F5R1_FB4_Pos (4U)
  3022. #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
  3023. #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
  3024. #define CAN_F5R1_FB5_Pos (5U)
  3025. #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
  3026. #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
  3027. #define CAN_F5R1_FB6_Pos (6U)
  3028. #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
  3029. #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
  3030. #define CAN_F5R1_FB7_Pos (7U)
  3031. #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
  3032. #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
  3033. #define CAN_F5R1_FB8_Pos (8U)
  3034. #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
  3035. #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
  3036. #define CAN_F5R1_FB9_Pos (9U)
  3037. #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
  3038. #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
  3039. #define CAN_F5R1_FB10_Pos (10U)
  3040. #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
  3041. #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
  3042. #define CAN_F5R1_FB11_Pos (11U)
  3043. #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
  3044. #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
  3045. #define CAN_F5R1_FB12_Pos (12U)
  3046. #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
  3047. #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
  3048. #define CAN_F5R1_FB13_Pos (13U)
  3049. #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
  3050. #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
  3051. #define CAN_F5R1_FB14_Pos (14U)
  3052. #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
  3053. #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
  3054. #define CAN_F5R1_FB15_Pos (15U)
  3055. #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
  3056. #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
  3057. #define CAN_F5R1_FB16_Pos (16U)
  3058. #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
  3059. #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
  3060. #define CAN_F5R1_FB17_Pos (17U)
  3061. #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
  3062. #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
  3063. #define CAN_F5R1_FB18_Pos (18U)
  3064. #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
  3065. #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
  3066. #define CAN_F5R1_FB19_Pos (19U)
  3067. #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
  3068. #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
  3069. #define CAN_F5R1_FB20_Pos (20U)
  3070. #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
  3071. #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
  3072. #define CAN_F5R1_FB21_Pos (21U)
  3073. #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
  3074. #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
  3075. #define CAN_F5R1_FB22_Pos (22U)
  3076. #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
  3077. #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
  3078. #define CAN_F5R1_FB23_Pos (23U)
  3079. #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
  3080. #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
  3081. #define CAN_F5R1_FB24_Pos (24U)
  3082. #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
  3083. #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
  3084. #define CAN_F5R1_FB25_Pos (25U)
  3085. #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
  3086. #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
  3087. #define CAN_F5R1_FB26_Pos (26U)
  3088. #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
  3089. #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
  3090. #define CAN_F5R1_FB27_Pos (27U)
  3091. #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
  3092. #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
  3093. #define CAN_F5R1_FB28_Pos (28U)
  3094. #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
  3095. #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
  3096. #define CAN_F5R1_FB29_Pos (29U)
  3097. #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
  3098. #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
  3099. #define CAN_F5R1_FB30_Pos (30U)
  3100. #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
  3101. #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
  3102. #define CAN_F5R1_FB31_Pos (31U)
  3103. #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
  3104. #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
  3105. /******************* Bit definition for CAN_F6R1 register *******************/
  3106. #define CAN_F6R1_FB0_Pos (0U)
  3107. #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
  3108. #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
  3109. #define CAN_F6R1_FB1_Pos (1U)
  3110. #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
  3111. #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
  3112. #define CAN_F6R1_FB2_Pos (2U)
  3113. #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
  3114. #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
  3115. #define CAN_F6R1_FB3_Pos (3U)
  3116. #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
  3117. #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
  3118. #define CAN_F6R1_FB4_Pos (4U)
  3119. #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
  3120. #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
  3121. #define CAN_F6R1_FB5_Pos (5U)
  3122. #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
  3123. #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
  3124. #define CAN_F6R1_FB6_Pos (6U)
  3125. #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
  3126. #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
  3127. #define CAN_F6R1_FB7_Pos (7U)
  3128. #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
  3129. #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
  3130. #define CAN_F6R1_FB8_Pos (8U)
  3131. #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
  3132. #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
  3133. #define CAN_F6R1_FB9_Pos (9U)
  3134. #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
  3135. #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
  3136. #define CAN_F6R1_FB10_Pos (10U)
  3137. #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
  3138. #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
  3139. #define CAN_F6R1_FB11_Pos (11U)
  3140. #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
  3141. #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
  3142. #define CAN_F6R1_FB12_Pos (12U)
  3143. #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
  3144. #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
  3145. #define CAN_F6R1_FB13_Pos (13U)
  3146. #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
  3147. #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
  3148. #define CAN_F6R1_FB14_Pos (14U)
  3149. #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
  3150. #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
  3151. #define CAN_F6R1_FB15_Pos (15U)
  3152. #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
  3153. #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
  3154. #define CAN_F6R1_FB16_Pos (16U)
  3155. #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
  3156. #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
  3157. #define CAN_F6R1_FB17_Pos (17U)
  3158. #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
  3159. #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
  3160. #define CAN_F6R1_FB18_Pos (18U)
  3161. #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
  3162. #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
  3163. #define CAN_F6R1_FB19_Pos (19U)
  3164. #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
  3165. #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
  3166. #define CAN_F6R1_FB20_Pos (20U)
  3167. #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
  3168. #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
  3169. #define CAN_F6R1_FB21_Pos (21U)
  3170. #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
  3171. #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
  3172. #define CAN_F6R1_FB22_Pos (22U)
  3173. #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
  3174. #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
  3175. #define CAN_F6R1_FB23_Pos (23U)
  3176. #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
  3177. #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
  3178. #define CAN_F6R1_FB24_Pos (24U)
  3179. #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
  3180. #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
  3181. #define CAN_F6R1_FB25_Pos (25U)
  3182. #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
  3183. #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
  3184. #define CAN_F6R1_FB26_Pos (26U)
  3185. #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
  3186. #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
  3187. #define CAN_F6R1_FB27_Pos (27U)
  3188. #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
  3189. #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
  3190. #define CAN_F6R1_FB28_Pos (28U)
  3191. #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
  3192. #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
  3193. #define CAN_F6R1_FB29_Pos (29U)
  3194. #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
  3195. #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
  3196. #define CAN_F6R1_FB30_Pos (30U)
  3197. #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
  3198. #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
  3199. #define CAN_F6R1_FB31_Pos (31U)
  3200. #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
  3201. #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
  3202. /******************* Bit definition for CAN_F7R1 register *******************/
  3203. #define CAN_F7R1_FB0_Pos (0U)
  3204. #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
  3205. #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
  3206. #define CAN_F7R1_FB1_Pos (1U)
  3207. #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
  3208. #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
  3209. #define CAN_F7R1_FB2_Pos (2U)
  3210. #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
  3211. #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
  3212. #define CAN_F7R1_FB3_Pos (3U)
  3213. #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
  3214. #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
  3215. #define CAN_F7R1_FB4_Pos (4U)
  3216. #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
  3217. #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
  3218. #define CAN_F7R1_FB5_Pos (5U)
  3219. #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
  3220. #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
  3221. #define CAN_F7R1_FB6_Pos (6U)
  3222. #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
  3223. #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
  3224. #define CAN_F7R1_FB7_Pos (7U)
  3225. #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
  3226. #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
  3227. #define CAN_F7R1_FB8_Pos (8U)
  3228. #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
  3229. #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
  3230. #define CAN_F7R1_FB9_Pos (9U)
  3231. #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
  3232. #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
  3233. #define CAN_F7R1_FB10_Pos (10U)
  3234. #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
  3235. #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
  3236. #define CAN_F7R1_FB11_Pos (11U)
  3237. #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
  3238. #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
  3239. #define CAN_F7R1_FB12_Pos (12U)
  3240. #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
  3241. #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
  3242. #define CAN_F7R1_FB13_Pos (13U)
  3243. #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
  3244. #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
  3245. #define CAN_F7R1_FB14_Pos (14U)
  3246. #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
  3247. #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
  3248. #define CAN_F7R1_FB15_Pos (15U)
  3249. #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
  3250. #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
  3251. #define CAN_F7R1_FB16_Pos (16U)
  3252. #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
  3253. #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
  3254. #define CAN_F7R1_FB17_Pos (17U)
  3255. #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
  3256. #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
  3257. #define CAN_F7R1_FB18_Pos (18U)
  3258. #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
  3259. #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
  3260. #define CAN_F7R1_FB19_Pos (19U)
  3261. #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
  3262. #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
  3263. #define CAN_F7R1_FB20_Pos (20U)
  3264. #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
  3265. #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
  3266. #define CAN_F7R1_FB21_Pos (21U)
  3267. #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
  3268. #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
  3269. #define CAN_F7R1_FB22_Pos (22U)
  3270. #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
  3271. #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
  3272. #define CAN_F7R1_FB23_Pos (23U)
  3273. #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
  3274. #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
  3275. #define CAN_F7R1_FB24_Pos (24U)
  3276. #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
  3277. #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
  3278. #define CAN_F7R1_FB25_Pos (25U)
  3279. #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
  3280. #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
  3281. #define CAN_F7R1_FB26_Pos (26U)
  3282. #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
  3283. #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
  3284. #define CAN_F7R1_FB27_Pos (27U)
  3285. #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
  3286. #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
  3287. #define CAN_F7R1_FB28_Pos (28U)
  3288. #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
  3289. #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
  3290. #define CAN_F7R1_FB29_Pos (29U)
  3291. #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
  3292. #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
  3293. #define CAN_F7R1_FB30_Pos (30U)
  3294. #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
  3295. #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
  3296. #define CAN_F7R1_FB31_Pos (31U)
  3297. #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
  3298. #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
  3299. /******************* Bit definition for CAN_F8R1 register *******************/
  3300. #define CAN_F8R1_FB0_Pos (0U)
  3301. #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
  3302. #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
  3303. #define CAN_F8R1_FB1_Pos (1U)
  3304. #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
  3305. #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
  3306. #define CAN_F8R1_FB2_Pos (2U)
  3307. #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
  3308. #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
  3309. #define CAN_F8R1_FB3_Pos (3U)
  3310. #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
  3311. #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
  3312. #define CAN_F8R1_FB4_Pos (4U)
  3313. #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
  3314. #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
  3315. #define CAN_F8R1_FB5_Pos (5U)
  3316. #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
  3317. #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
  3318. #define CAN_F8R1_FB6_Pos (6U)
  3319. #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
  3320. #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
  3321. #define CAN_F8R1_FB7_Pos (7U)
  3322. #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
  3323. #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
  3324. #define CAN_F8R1_FB8_Pos (8U)
  3325. #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
  3326. #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
  3327. #define CAN_F8R1_FB9_Pos (9U)
  3328. #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
  3329. #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
  3330. #define CAN_F8R1_FB10_Pos (10U)
  3331. #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
  3332. #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
  3333. #define CAN_F8R1_FB11_Pos (11U)
  3334. #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
  3335. #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
  3336. #define CAN_F8R1_FB12_Pos (12U)
  3337. #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
  3338. #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
  3339. #define CAN_F8R1_FB13_Pos (13U)
  3340. #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
  3341. #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
  3342. #define CAN_F8R1_FB14_Pos (14U)
  3343. #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
  3344. #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
  3345. #define CAN_F8R1_FB15_Pos (15U)
  3346. #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
  3347. #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
  3348. #define CAN_F8R1_FB16_Pos (16U)
  3349. #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
  3350. #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
  3351. #define CAN_F8R1_FB17_Pos (17U)
  3352. #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
  3353. #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
  3354. #define CAN_F8R1_FB18_Pos (18U)
  3355. #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
  3356. #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
  3357. #define CAN_F8R1_FB19_Pos (19U)
  3358. #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
  3359. #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
  3360. #define CAN_F8R1_FB20_Pos (20U)
  3361. #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
  3362. #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
  3363. #define CAN_F8R1_FB21_Pos (21U)
  3364. #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
  3365. #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
  3366. #define CAN_F8R1_FB22_Pos (22U)
  3367. #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
  3368. #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
  3369. #define CAN_F8R1_FB23_Pos (23U)
  3370. #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
  3371. #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
  3372. #define CAN_F8R1_FB24_Pos (24U)
  3373. #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
  3374. #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
  3375. #define CAN_F8R1_FB25_Pos (25U)
  3376. #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
  3377. #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
  3378. #define CAN_F8R1_FB26_Pos (26U)
  3379. #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
  3380. #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
  3381. #define CAN_F8R1_FB27_Pos (27U)
  3382. #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
  3383. #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
  3384. #define CAN_F8R1_FB28_Pos (28U)
  3385. #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
  3386. #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
  3387. #define CAN_F8R1_FB29_Pos (29U)
  3388. #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
  3389. #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
  3390. #define CAN_F8R1_FB30_Pos (30U)
  3391. #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
  3392. #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
  3393. #define CAN_F8R1_FB31_Pos (31U)
  3394. #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
  3395. #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
  3396. /******************* Bit definition for CAN_F9R1 register *******************/
  3397. #define CAN_F9R1_FB0_Pos (0U)
  3398. #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
  3399. #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
  3400. #define CAN_F9R1_FB1_Pos (1U)
  3401. #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
  3402. #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
  3403. #define CAN_F9R1_FB2_Pos (2U)
  3404. #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
  3405. #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
  3406. #define CAN_F9R1_FB3_Pos (3U)
  3407. #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
  3408. #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
  3409. #define CAN_F9R1_FB4_Pos (4U)
  3410. #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
  3411. #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
  3412. #define CAN_F9R1_FB5_Pos (5U)
  3413. #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
  3414. #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
  3415. #define CAN_F9R1_FB6_Pos (6U)
  3416. #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
  3417. #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
  3418. #define CAN_F9R1_FB7_Pos (7U)
  3419. #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
  3420. #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
  3421. #define CAN_F9R1_FB8_Pos (8U)
  3422. #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
  3423. #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
  3424. #define CAN_F9R1_FB9_Pos (9U)
  3425. #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
  3426. #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
  3427. #define CAN_F9R1_FB10_Pos (10U)
  3428. #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
  3429. #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
  3430. #define CAN_F9R1_FB11_Pos (11U)
  3431. #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
  3432. #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
  3433. #define CAN_F9R1_FB12_Pos (12U)
  3434. #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
  3435. #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
  3436. #define CAN_F9R1_FB13_Pos (13U)
  3437. #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
  3438. #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
  3439. #define CAN_F9R1_FB14_Pos (14U)
  3440. #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
  3441. #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
  3442. #define CAN_F9R1_FB15_Pos (15U)
  3443. #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
  3444. #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
  3445. #define CAN_F9R1_FB16_Pos (16U)
  3446. #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
  3447. #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
  3448. #define CAN_F9R1_FB17_Pos (17U)
  3449. #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
  3450. #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
  3451. #define CAN_F9R1_FB18_Pos (18U)
  3452. #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
  3453. #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
  3454. #define CAN_F9R1_FB19_Pos (19U)
  3455. #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
  3456. #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
  3457. #define CAN_F9R1_FB20_Pos (20U)
  3458. #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
  3459. #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
  3460. #define CAN_F9R1_FB21_Pos (21U)
  3461. #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
  3462. #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
  3463. #define CAN_F9R1_FB22_Pos (22U)
  3464. #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
  3465. #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
  3466. #define CAN_F9R1_FB23_Pos (23U)
  3467. #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
  3468. #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
  3469. #define CAN_F9R1_FB24_Pos (24U)
  3470. #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
  3471. #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
  3472. #define CAN_F9R1_FB25_Pos (25U)
  3473. #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
  3474. #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
  3475. #define CAN_F9R1_FB26_Pos (26U)
  3476. #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
  3477. #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
  3478. #define CAN_F9R1_FB27_Pos (27U)
  3479. #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
  3480. #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
  3481. #define CAN_F9R1_FB28_Pos (28U)
  3482. #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
  3483. #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
  3484. #define CAN_F9R1_FB29_Pos (29U)
  3485. #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
  3486. #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
  3487. #define CAN_F9R1_FB30_Pos (30U)
  3488. #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
  3489. #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
  3490. #define CAN_F9R1_FB31_Pos (31U)
  3491. #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
  3492. #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
  3493. /******************* Bit definition for CAN_F10R1 register ******************/
  3494. #define CAN_F10R1_FB0_Pos (0U)
  3495. #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
  3496. #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
  3497. #define CAN_F10R1_FB1_Pos (1U)
  3498. #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
  3499. #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
  3500. #define CAN_F10R1_FB2_Pos (2U)
  3501. #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
  3502. #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
  3503. #define CAN_F10R1_FB3_Pos (3U)
  3504. #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
  3505. #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
  3506. #define CAN_F10R1_FB4_Pos (4U)
  3507. #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
  3508. #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
  3509. #define CAN_F10R1_FB5_Pos (5U)
  3510. #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
  3511. #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
  3512. #define CAN_F10R1_FB6_Pos (6U)
  3513. #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
  3514. #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
  3515. #define CAN_F10R1_FB7_Pos (7U)
  3516. #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
  3517. #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
  3518. #define CAN_F10R1_FB8_Pos (8U)
  3519. #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
  3520. #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
  3521. #define CAN_F10R1_FB9_Pos (9U)
  3522. #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
  3523. #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
  3524. #define CAN_F10R1_FB10_Pos (10U)
  3525. #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
  3526. #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
  3527. #define CAN_F10R1_FB11_Pos (11U)
  3528. #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
  3529. #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
  3530. #define CAN_F10R1_FB12_Pos (12U)
  3531. #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
  3532. #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
  3533. #define CAN_F10R1_FB13_Pos (13U)
  3534. #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
  3535. #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
  3536. #define CAN_F10R1_FB14_Pos (14U)
  3537. #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
  3538. #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
  3539. #define CAN_F10R1_FB15_Pos (15U)
  3540. #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
  3541. #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
  3542. #define CAN_F10R1_FB16_Pos (16U)
  3543. #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
  3544. #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
  3545. #define CAN_F10R1_FB17_Pos (17U)
  3546. #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
  3547. #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
  3548. #define CAN_F10R1_FB18_Pos (18U)
  3549. #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
  3550. #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
  3551. #define CAN_F10R1_FB19_Pos (19U)
  3552. #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
  3553. #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
  3554. #define CAN_F10R1_FB20_Pos (20U)
  3555. #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
  3556. #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
  3557. #define CAN_F10R1_FB21_Pos (21U)
  3558. #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
  3559. #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
  3560. #define CAN_F10R1_FB22_Pos (22U)
  3561. #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
  3562. #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
  3563. #define CAN_F10R1_FB23_Pos (23U)
  3564. #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
  3565. #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
  3566. #define CAN_F10R1_FB24_Pos (24U)
  3567. #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
  3568. #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
  3569. #define CAN_F10R1_FB25_Pos (25U)
  3570. #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
  3571. #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
  3572. #define CAN_F10R1_FB26_Pos (26U)
  3573. #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
  3574. #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
  3575. #define CAN_F10R1_FB27_Pos (27U)
  3576. #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
  3577. #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
  3578. #define CAN_F10R1_FB28_Pos (28U)
  3579. #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
  3580. #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
  3581. #define CAN_F10R1_FB29_Pos (29U)
  3582. #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
  3583. #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
  3584. #define CAN_F10R1_FB30_Pos (30U)
  3585. #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
  3586. #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
  3587. #define CAN_F10R1_FB31_Pos (31U)
  3588. #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
  3589. #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
  3590. /******************* Bit definition for CAN_F11R1 register ******************/
  3591. #define CAN_F11R1_FB0_Pos (0U)
  3592. #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
  3593. #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
  3594. #define CAN_F11R1_FB1_Pos (1U)
  3595. #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
  3596. #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
  3597. #define CAN_F11R1_FB2_Pos (2U)
  3598. #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
  3599. #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
  3600. #define CAN_F11R1_FB3_Pos (3U)
  3601. #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
  3602. #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
  3603. #define CAN_F11R1_FB4_Pos (4U)
  3604. #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
  3605. #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
  3606. #define CAN_F11R1_FB5_Pos (5U)
  3607. #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
  3608. #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
  3609. #define CAN_F11R1_FB6_Pos (6U)
  3610. #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
  3611. #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
  3612. #define CAN_F11R1_FB7_Pos (7U)
  3613. #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
  3614. #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
  3615. #define CAN_F11R1_FB8_Pos (8U)
  3616. #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
  3617. #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
  3618. #define CAN_F11R1_FB9_Pos (9U)
  3619. #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
  3620. #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
  3621. #define CAN_F11R1_FB10_Pos (10U)
  3622. #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
  3623. #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
  3624. #define CAN_F11R1_FB11_Pos (11U)
  3625. #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
  3626. #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
  3627. #define CAN_F11R1_FB12_Pos (12U)
  3628. #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
  3629. #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
  3630. #define CAN_F11R1_FB13_Pos (13U)
  3631. #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
  3632. #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
  3633. #define CAN_F11R1_FB14_Pos (14U)
  3634. #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
  3635. #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
  3636. #define CAN_F11R1_FB15_Pos (15U)
  3637. #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
  3638. #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
  3639. #define CAN_F11R1_FB16_Pos (16U)
  3640. #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
  3641. #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
  3642. #define CAN_F11R1_FB17_Pos (17U)
  3643. #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
  3644. #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
  3645. #define CAN_F11R1_FB18_Pos (18U)
  3646. #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
  3647. #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
  3648. #define CAN_F11R1_FB19_Pos (19U)
  3649. #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
  3650. #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
  3651. #define CAN_F11R1_FB20_Pos (20U)
  3652. #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
  3653. #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
  3654. #define CAN_F11R1_FB21_Pos (21U)
  3655. #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
  3656. #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
  3657. #define CAN_F11R1_FB22_Pos (22U)
  3658. #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
  3659. #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
  3660. #define CAN_F11R1_FB23_Pos (23U)
  3661. #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
  3662. #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
  3663. #define CAN_F11R1_FB24_Pos (24U)
  3664. #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
  3665. #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
  3666. #define CAN_F11R1_FB25_Pos (25U)
  3667. #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
  3668. #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
  3669. #define CAN_F11R1_FB26_Pos (26U)
  3670. #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
  3671. #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
  3672. #define CAN_F11R1_FB27_Pos (27U)
  3673. #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
  3674. #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
  3675. #define CAN_F11R1_FB28_Pos (28U)
  3676. #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
  3677. #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
  3678. #define CAN_F11R1_FB29_Pos (29U)
  3679. #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
  3680. #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
  3681. #define CAN_F11R1_FB30_Pos (30U)
  3682. #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
  3683. #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
  3684. #define CAN_F11R1_FB31_Pos (31U)
  3685. #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
  3686. #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
  3687. /******************* Bit definition for CAN_F12R1 register ******************/
  3688. #define CAN_F12R1_FB0_Pos (0U)
  3689. #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
  3690. #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
  3691. #define CAN_F12R1_FB1_Pos (1U)
  3692. #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
  3693. #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
  3694. #define CAN_F12R1_FB2_Pos (2U)
  3695. #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
  3696. #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
  3697. #define CAN_F12R1_FB3_Pos (3U)
  3698. #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
  3699. #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
  3700. #define CAN_F12R1_FB4_Pos (4U)
  3701. #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
  3702. #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
  3703. #define CAN_F12R1_FB5_Pos (5U)
  3704. #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
  3705. #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
  3706. #define CAN_F12R1_FB6_Pos (6U)
  3707. #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
  3708. #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
  3709. #define CAN_F12R1_FB7_Pos (7U)
  3710. #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
  3711. #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
  3712. #define CAN_F12R1_FB8_Pos (8U)
  3713. #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
  3714. #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
  3715. #define CAN_F12R1_FB9_Pos (9U)
  3716. #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
  3717. #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
  3718. #define CAN_F12R1_FB10_Pos (10U)
  3719. #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
  3720. #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
  3721. #define CAN_F12R1_FB11_Pos (11U)
  3722. #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
  3723. #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
  3724. #define CAN_F12R1_FB12_Pos (12U)
  3725. #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
  3726. #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
  3727. #define CAN_F12R1_FB13_Pos (13U)
  3728. #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
  3729. #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
  3730. #define CAN_F12R1_FB14_Pos (14U)
  3731. #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
  3732. #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
  3733. #define CAN_F12R1_FB15_Pos (15U)
  3734. #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
  3735. #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
  3736. #define CAN_F12R1_FB16_Pos (16U)
  3737. #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
  3738. #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
  3739. #define CAN_F12R1_FB17_Pos (17U)
  3740. #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
  3741. #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
  3742. #define CAN_F12R1_FB18_Pos (18U)
  3743. #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
  3744. #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
  3745. #define CAN_F12R1_FB19_Pos (19U)
  3746. #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
  3747. #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
  3748. #define CAN_F12R1_FB20_Pos (20U)
  3749. #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
  3750. #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
  3751. #define CAN_F12R1_FB21_Pos (21U)
  3752. #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
  3753. #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
  3754. #define CAN_F12R1_FB22_Pos (22U)
  3755. #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
  3756. #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
  3757. #define CAN_F12R1_FB23_Pos (23U)
  3758. #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
  3759. #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
  3760. #define CAN_F12R1_FB24_Pos (24U)
  3761. #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
  3762. #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
  3763. #define CAN_F12R1_FB25_Pos (25U)
  3764. #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
  3765. #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
  3766. #define CAN_F12R1_FB26_Pos (26U)
  3767. #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
  3768. #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
  3769. #define CAN_F12R1_FB27_Pos (27U)
  3770. #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
  3771. #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
  3772. #define CAN_F12R1_FB28_Pos (28U)
  3773. #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
  3774. #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
  3775. #define CAN_F12R1_FB29_Pos (29U)
  3776. #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
  3777. #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
  3778. #define CAN_F12R1_FB30_Pos (30U)
  3779. #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
  3780. #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
  3781. #define CAN_F12R1_FB31_Pos (31U)
  3782. #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
  3783. #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
  3784. /******************* Bit definition for CAN_F13R1 register ******************/
  3785. #define CAN_F13R1_FB0_Pos (0U)
  3786. #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
  3787. #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
  3788. #define CAN_F13R1_FB1_Pos (1U)
  3789. #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
  3790. #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
  3791. #define CAN_F13R1_FB2_Pos (2U)
  3792. #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
  3793. #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
  3794. #define CAN_F13R1_FB3_Pos (3U)
  3795. #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
  3796. #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
  3797. #define CAN_F13R1_FB4_Pos (4U)
  3798. #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
  3799. #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
  3800. #define CAN_F13R1_FB5_Pos (5U)
  3801. #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
  3802. #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
  3803. #define CAN_F13R1_FB6_Pos (6U)
  3804. #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
  3805. #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
  3806. #define CAN_F13R1_FB7_Pos (7U)
  3807. #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
  3808. #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
  3809. #define CAN_F13R1_FB8_Pos (8U)
  3810. #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
  3811. #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
  3812. #define CAN_F13R1_FB9_Pos (9U)
  3813. #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
  3814. #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
  3815. #define CAN_F13R1_FB10_Pos (10U)
  3816. #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
  3817. #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
  3818. #define CAN_F13R1_FB11_Pos (11U)
  3819. #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
  3820. #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
  3821. #define CAN_F13R1_FB12_Pos (12U)
  3822. #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
  3823. #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
  3824. #define CAN_F13R1_FB13_Pos (13U)
  3825. #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
  3826. #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
  3827. #define CAN_F13R1_FB14_Pos (14U)
  3828. #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
  3829. #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
  3830. #define CAN_F13R1_FB15_Pos (15U)
  3831. #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
  3832. #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
  3833. #define CAN_F13R1_FB16_Pos (16U)
  3834. #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
  3835. #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
  3836. #define CAN_F13R1_FB17_Pos (17U)
  3837. #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
  3838. #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
  3839. #define CAN_F13R1_FB18_Pos (18U)
  3840. #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
  3841. #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
  3842. #define CAN_F13R1_FB19_Pos (19U)
  3843. #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
  3844. #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
  3845. #define CAN_F13R1_FB20_Pos (20U)
  3846. #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
  3847. #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
  3848. #define CAN_F13R1_FB21_Pos (21U)
  3849. #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
  3850. #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
  3851. #define CAN_F13R1_FB22_Pos (22U)
  3852. #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
  3853. #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
  3854. #define CAN_F13R1_FB23_Pos (23U)
  3855. #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
  3856. #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
  3857. #define CAN_F13R1_FB24_Pos (24U)
  3858. #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
  3859. #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
  3860. #define CAN_F13R1_FB25_Pos (25U)
  3861. #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
  3862. #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
  3863. #define CAN_F13R1_FB26_Pos (26U)
  3864. #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
  3865. #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
  3866. #define CAN_F13R1_FB27_Pos (27U)
  3867. #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
  3868. #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
  3869. #define CAN_F13R1_FB28_Pos (28U)
  3870. #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
  3871. #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
  3872. #define CAN_F13R1_FB29_Pos (29U)
  3873. #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
  3874. #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
  3875. #define CAN_F13R1_FB30_Pos (30U)
  3876. #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
  3877. #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
  3878. #define CAN_F13R1_FB31_Pos (31U)
  3879. #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
  3880. #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
  3881. /******************* Bit definition for CAN_F0R2 register *******************/
  3882. #define CAN_F0R2_FB0_Pos (0U)
  3883. #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
  3884. #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
  3885. #define CAN_F0R2_FB1_Pos (1U)
  3886. #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
  3887. #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
  3888. #define CAN_F0R2_FB2_Pos (2U)
  3889. #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
  3890. #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
  3891. #define CAN_F0R2_FB3_Pos (3U)
  3892. #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
  3893. #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
  3894. #define CAN_F0R2_FB4_Pos (4U)
  3895. #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
  3896. #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
  3897. #define CAN_F0R2_FB5_Pos (5U)
  3898. #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
  3899. #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
  3900. #define CAN_F0R2_FB6_Pos (6U)
  3901. #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
  3902. #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
  3903. #define CAN_F0R2_FB7_Pos (7U)
  3904. #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
  3905. #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
  3906. #define CAN_F0R2_FB8_Pos (8U)
  3907. #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
  3908. #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
  3909. #define CAN_F0R2_FB9_Pos (9U)
  3910. #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
  3911. #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
  3912. #define CAN_F0R2_FB10_Pos (10U)
  3913. #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
  3914. #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
  3915. #define CAN_F0R2_FB11_Pos (11U)
  3916. #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
  3917. #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
  3918. #define CAN_F0R2_FB12_Pos (12U)
  3919. #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
  3920. #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
  3921. #define CAN_F0R2_FB13_Pos (13U)
  3922. #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
  3923. #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
  3924. #define CAN_F0R2_FB14_Pos (14U)
  3925. #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
  3926. #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
  3927. #define CAN_F0R2_FB15_Pos (15U)
  3928. #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
  3929. #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
  3930. #define CAN_F0R2_FB16_Pos (16U)
  3931. #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
  3932. #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
  3933. #define CAN_F0R2_FB17_Pos (17U)
  3934. #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
  3935. #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
  3936. #define CAN_F0R2_FB18_Pos (18U)
  3937. #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
  3938. #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
  3939. #define CAN_F0R2_FB19_Pos (19U)
  3940. #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
  3941. #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
  3942. #define CAN_F0R2_FB20_Pos (20U)
  3943. #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
  3944. #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
  3945. #define CAN_F0R2_FB21_Pos (21U)
  3946. #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
  3947. #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
  3948. #define CAN_F0R2_FB22_Pos (22U)
  3949. #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
  3950. #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
  3951. #define CAN_F0R2_FB23_Pos (23U)
  3952. #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
  3953. #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
  3954. #define CAN_F0R2_FB24_Pos (24U)
  3955. #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
  3956. #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
  3957. #define CAN_F0R2_FB25_Pos (25U)
  3958. #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
  3959. #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
  3960. #define CAN_F0R2_FB26_Pos (26U)
  3961. #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
  3962. #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
  3963. #define CAN_F0R2_FB27_Pos (27U)
  3964. #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
  3965. #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
  3966. #define CAN_F0R2_FB28_Pos (28U)
  3967. #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
  3968. #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
  3969. #define CAN_F0R2_FB29_Pos (29U)
  3970. #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
  3971. #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
  3972. #define CAN_F0R2_FB30_Pos (30U)
  3973. #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
  3974. #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
  3975. #define CAN_F0R2_FB31_Pos (31U)
  3976. #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
  3977. #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
  3978. /******************* Bit definition for CAN_F1R2 register *******************/
  3979. #define CAN_F1R2_FB0_Pos (0U)
  3980. #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
  3981. #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
  3982. #define CAN_F1R2_FB1_Pos (1U)
  3983. #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
  3984. #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
  3985. #define CAN_F1R2_FB2_Pos (2U)
  3986. #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
  3987. #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
  3988. #define CAN_F1R2_FB3_Pos (3U)
  3989. #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
  3990. #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
  3991. #define CAN_F1R2_FB4_Pos (4U)
  3992. #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
  3993. #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
  3994. #define CAN_F1R2_FB5_Pos (5U)
  3995. #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
  3996. #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
  3997. #define CAN_F1R2_FB6_Pos (6U)
  3998. #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
  3999. #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
  4000. #define CAN_F1R2_FB7_Pos (7U)
  4001. #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
  4002. #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
  4003. #define CAN_F1R2_FB8_Pos (8U)
  4004. #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
  4005. #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
  4006. #define CAN_F1R2_FB9_Pos (9U)
  4007. #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
  4008. #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
  4009. #define CAN_F1R2_FB10_Pos (10U)
  4010. #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
  4011. #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
  4012. #define CAN_F1R2_FB11_Pos (11U)
  4013. #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
  4014. #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
  4015. #define CAN_F1R2_FB12_Pos (12U)
  4016. #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
  4017. #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
  4018. #define CAN_F1R2_FB13_Pos (13U)
  4019. #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
  4020. #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
  4021. #define CAN_F1R2_FB14_Pos (14U)
  4022. #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
  4023. #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
  4024. #define CAN_F1R2_FB15_Pos (15U)
  4025. #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
  4026. #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
  4027. #define CAN_F1R2_FB16_Pos (16U)
  4028. #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
  4029. #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
  4030. #define CAN_F1R2_FB17_Pos (17U)
  4031. #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
  4032. #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
  4033. #define CAN_F1R2_FB18_Pos (18U)
  4034. #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
  4035. #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
  4036. #define CAN_F1R2_FB19_Pos (19U)
  4037. #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
  4038. #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
  4039. #define CAN_F1R2_FB20_Pos (20U)
  4040. #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
  4041. #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
  4042. #define CAN_F1R2_FB21_Pos (21U)
  4043. #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
  4044. #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
  4045. #define CAN_F1R2_FB22_Pos (22U)
  4046. #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
  4047. #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
  4048. #define CAN_F1R2_FB23_Pos (23U)
  4049. #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
  4050. #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
  4051. #define CAN_F1R2_FB24_Pos (24U)
  4052. #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
  4053. #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
  4054. #define CAN_F1R2_FB25_Pos (25U)
  4055. #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
  4056. #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
  4057. #define CAN_F1R2_FB26_Pos (26U)
  4058. #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
  4059. #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
  4060. #define CAN_F1R2_FB27_Pos (27U)
  4061. #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
  4062. #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
  4063. #define CAN_F1R2_FB28_Pos (28U)
  4064. #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
  4065. #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
  4066. #define CAN_F1R2_FB29_Pos (29U)
  4067. #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
  4068. #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
  4069. #define CAN_F1R2_FB30_Pos (30U)
  4070. #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
  4071. #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
  4072. #define CAN_F1R2_FB31_Pos (31U)
  4073. #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
  4074. #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
  4075. /******************* Bit definition for CAN_F2R2 register *******************/
  4076. #define CAN_F2R2_FB0_Pos (0U)
  4077. #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
  4078. #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
  4079. #define CAN_F2R2_FB1_Pos (1U)
  4080. #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
  4081. #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
  4082. #define CAN_F2R2_FB2_Pos (2U)
  4083. #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
  4084. #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
  4085. #define CAN_F2R2_FB3_Pos (3U)
  4086. #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
  4087. #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
  4088. #define CAN_F2R2_FB4_Pos (4U)
  4089. #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
  4090. #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
  4091. #define CAN_F2R2_FB5_Pos (5U)
  4092. #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
  4093. #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
  4094. #define CAN_F2R2_FB6_Pos (6U)
  4095. #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
  4096. #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
  4097. #define CAN_F2R2_FB7_Pos (7U)
  4098. #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
  4099. #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
  4100. #define CAN_F2R2_FB8_Pos (8U)
  4101. #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
  4102. #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
  4103. #define CAN_F2R2_FB9_Pos (9U)
  4104. #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
  4105. #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
  4106. #define CAN_F2R2_FB10_Pos (10U)
  4107. #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
  4108. #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
  4109. #define CAN_F2R2_FB11_Pos (11U)
  4110. #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
  4111. #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
  4112. #define CAN_F2R2_FB12_Pos (12U)
  4113. #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
  4114. #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
  4115. #define CAN_F2R2_FB13_Pos (13U)
  4116. #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
  4117. #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
  4118. #define CAN_F2R2_FB14_Pos (14U)
  4119. #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
  4120. #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
  4121. #define CAN_F2R2_FB15_Pos (15U)
  4122. #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
  4123. #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
  4124. #define CAN_F2R2_FB16_Pos (16U)
  4125. #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
  4126. #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
  4127. #define CAN_F2R2_FB17_Pos (17U)
  4128. #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
  4129. #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
  4130. #define CAN_F2R2_FB18_Pos (18U)
  4131. #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
  4132. #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
  4133. #define CAN_F2R2_FB19_Pos (19U)
  4134. #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
  4135. #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
  4136. #define CAN_F2R2_FB20_Pos (20U)
  4137. #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
  4138. #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
  4139. #define CAN_F2R2_FB21_Pos (21U)
  4140. #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
  4141. #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
  4142. #define CAN_F2R2_FB22_Pos (22U)
  4143. #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
  4144. #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
  4145. #define CAN_F2R2_FB23_Pos (23U)
  4146. #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
  4147. #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
  4148. #define CAN_F2R2_FB24_Pos (24U)
  4149. #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
  4150. #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
  4151. #define CAN_F2R2_FB25_Pos (25U)
  4152. #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
  4153. #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
  4154. #define CAN_F2R2_FB26_Pos (26U)
  4155. #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
  4156. #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
  4157. #define CAN_F2R2_FB27_Pos (27U)
  4158. #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
  4159. #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
  4160. #define CAN_F2R2_FB28_Pos (28U)
  4161. #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
  4162. #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
  4163. #define CAN_F2R2_FB29_Pos (29U)
  4164. #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
  4165. #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
  4166. #define CAN_F2R2_FB30_Pos (30U)
  4167. #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
  4168. #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
  4169. #define CAN_F2R2_FB31_Pos (31U)
  4170. #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
  4171. #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
  4172. /******************* Bit definition for CAN_F3R2 register *******************/
  4173. #define CAN_F3R2_FB0_Pos (0U)
  4174. #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
  4175. #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
  4176. #define CAN_F3R2_FB1_Pos (1U)
  4177. #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
  4178. #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
  4179. #define CAN_F3R2_FB2_Pos (2U)
  4180. #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
  4181. #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
  4182. #define CAN_F3R2_FB3_Pos (3U)
  4183. #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
  4184. #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
  4185. #define CAN_F3R2_FB4_Pos (4U)
  4186. #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
  4187. #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
  4188. #define CAN_F3R2_FB5_Pos (5U)
  4189. #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
  4190. #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
  4191. #define CAN_F3R2_FB6_Pos (6U)
  4192. #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
  4193. #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
  4194. #define CAN_F3R2_FB7_Pos (7U)
  4195. #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
  4196. #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
  4197. #define CAN_F3R2_FB8_Pos (8U)
  4198. #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
  4199. #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
  4200. #define CAN_F3R2_FB9_Pos (9U)
  4201. #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
  4202. #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
  4203. #define CAN_F3R2_FB10_Pos (10U)
  4204. #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
  4205. #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
  4206. #define CAN_F3R2_FB11_Pos (11U)
  4207. #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
  4208. #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
  4209. #define CAN_F3R2_FB12_Pos (12U)
  4210. #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
  4211. #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
  4212. #define CAN_F3R2_FB13_Pos (13U)
  4213. #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
  4214. #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
  4215. #define CAN_F3R2_FB14_Pos (14U)
  4216. #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
  4217. #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
  4218. #define CAN_F3R2_FB15_Pos (15U)
  4219. #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
  4220. #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
  4221. #define CAN_F3R2_FB16_Pos (16U)
  4222. #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
  4223. #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
  4224. #define CAN_F3R2_FB17_Pos (17U)
  4225. #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
  4226. #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
  4227. #define CAN_F3R2_FB18_Pos (18U)
  4228. #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
  4229. #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
  4230. #define CAN_F3R2_FB19_Pos (19U)
  4231. #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
  4232. #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
  4233. #define CAN_F3R2_FB20_Pos (20U)
  4234. #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
  4235. #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
  4236. #define CAN_F3R2_FB21_Pos (21U)
  4237. #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
  4238. #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
  4239. #define CAN_F3R2_FB22_Pos (22U)
  4240. #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
  4241. #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
  4242. #define CAN_F3R2_FB23_Pos (23U)
  4243. #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
  4244. #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
  4245. #define CAN_F3R2_FB24_Pos (24U)
  4246. #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
  4247. #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
  4248. #define CAN_F3R2_FB25_Pos (25U)
  4249. #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
  4250. #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
  4251. #define CAN_F3R2_FB26_Pos (26U)
  4252. #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
  4253. #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
  4254. #define CAN_F3R2_FB27_Pos (27U)
  4255. #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
  4256. #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
  4257. #define CAN_F3R2_FB28_Pos (28U)
  4258. #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
  4259. #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
  4260. #define CAN_F3R2_FB29_Pos (29U)
  4261. #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
  4262. #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
  4263. #define CAN_F3R2_FB30_Pos (30U)
  4264. #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
  4265. #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
  4266. #define CAN_F3R2_FB31_Pos (31U)
  4267. #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
  4268. #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
  4269. /******************* Bit definition for CAN_F4R2 register *******************/
  4270. #define CAN_F4R2_FB0_Pos (0U)
  4271. #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
  4272. #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
  4273. #define CAN_F4R2_FB1_Pos (1U)
  4274. #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
  4275. #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
  4276. #define CAN_F4R2_FB2_Pos (2U)
  4277. #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
  4278. #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
  4279. #define CAN_F4R2_FB3_Pos (3U)
  4280. #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
  4281. #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
  4282. #define CAN_F4R2_FB4_Pos (4U)
  4283. #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
  4284. #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
  4285. #define CAN_F4R2_FB5_Pos (5U)
  4286. #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
  4287. #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
  4288. #define CAN_F4R2_FB6_Pos (6U)
  4289. #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
  4290. #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
  4291. #define CAN_F4R2_FB7_Pos (7U)
  4292. #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
  4293. #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
  4294. #define CAN_F4R2_FB8_Pos (8U)
  4295. #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
  4296. #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
  4297. #define CAN_F4R2_FB9_Pos (9U)
  4298. #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
  4299. #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
  4300. #define CAN_F4R2_FB10_Pos (10U)
  4301. #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
  4302. #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
  4303. #define CAN_F4R2_FB11_Pos (11U)
  4304. #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
  4305. #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
  4306. #define CAN_F4R2_FB12_Pos (12U)
  4307. #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
  4308. #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
  4309. #define CAN_F4R2_FB13_Pos (13U)
  4310. #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
  4311. #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
  4312. #define CAN_F4R2_FB14_Pos (14U)
  4313. #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
  4314. #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
  4315. #define CAN_F4R2_FB15_Pos (15U)
  4316. #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
  4317. #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
  4318. #define CAN_F4R2_FB16_Pos (16U)
  4319. #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
  4320. #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
  4321. #define CAN_F4R2_FB17_Pos (17U)
  4322. #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
  4323. #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
  4324. #define CAN_F4R2_FB18_Pos (18U)
  4325. #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
  4326. #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
  4327. #define CAN_F4R2_FB19_Pos (19U)
  4328. #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
  4329. #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
  4330. #define CAN_F4R2_FB20_Pos (20U)
  4331. #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
  4332. #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
  4333. #define CAN_F4R2_FB21_Pos (21U)
  4334. #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
  4335. #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
  4336. #define CAN_F4R2_FB22_Pos (22U)
  4337. #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
  4338. #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
  4339. #define CAN_F4R2_FB23_Pos (23U)
  4340. #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
  4341. #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
  4342. #define CAN_F4R2_FB24_Pos (24U)
  4343. #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
  4344. #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
  4345. #define CAN_F4R2_FB25_Pos (25U)
  4346. #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
  4347. #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
  4348. #define CAN_F4R2_FB26_Pos (26U)
  4349. #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
  4350. #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
  4351. #define CAN_F4R2_FB27_Pos (27U)
  4352. #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
  4353. #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
  4354. #define CAN_F4R2_FB28_Pos (28U)
  4355. #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
  4356. #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
  4357. #define CAN_F4R2_FB29_Pos (29U)
  4358. #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
  4359. #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
  4360. #define CAN_F4R2_FB30_Pos (30U)
  4361. #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
  4362. #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
  4363. #define CAN_F4R2_FB31_Pos (31U)
  4364. #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
  4365. #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
  4366. /******************* Bit definition for CAN_F5R2 register *******************/
  4367. #define CAN_F5R2_FB0_Pos (0U)
  4368. #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
  4369. #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
  4370. #define CAN_F5R2_FB1_Pos (1U)
  4371. #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
  4372. #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
  4373. #define CAN_F5R2_FB2_Pos (2U)
  4374. #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
  4375. #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
  4376. #define CAN_F5R2_FB3_Pos (3U)
  4377. #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
  4378. #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
  4379. #define CAN_F5R2_FB4_Pos (4U)
  4380. #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
  4381. #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
  4382. #define CAN_F5R2_FB5_Pos (5U)
  4383. #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
  4384. #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
  4385. #define CAN_F5R2_FB6_Pos (6U)
  4386. #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
  4387. #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
  4388. #define CAN_F5R2_FB7_Pos (7U)
  4389. #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
  4390. #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
  4391. #define CAN_F5R2_FB8_Pos (8U)
  4392. #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
  4393. #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
  4394. #define CAN_F5R2_FB9_Pos (9U)
  4395. #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
  4396. #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
  4397. #define CAN_F5R2_FB10_Pos (10U)
  4398. #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
  4399. #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
  4400. #define CAN_F5R2_FB11_Pos (11U)
  4401. #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
  4402. #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
  4403. #define CAN_F5R2_FB12_Pos (12U)
  4404. #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
  4405. #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
  4406. #define CAN_F5R2_FB13_Pos (13U)
  4407. #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
  4408. #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
  4409. #define CAN_F5R2_FB14_Pos (14U)
  4410. #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
  4411. #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
  4412. #define CAN_F5R2_FB15_Pos (15U)
  4413. #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
  4414. #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
  4415. #define CAN_F5R2_FB16_Pos (16U)
  4416. #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
  4417. #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
  4418. #define CAN_F5R2_FB17_Pos (17U)
  4419. #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
  4420. #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
  4421. #define CAN_F5R2_FB18_Pos (18U)
  4422. #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
  4423. #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
  4424. #define CAN_F5R2_FB19_Pos (19U)
  4425. #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
  4426. #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
  4427. #define CAN_F5R2_FB20_Pos (20U)
  4428. #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
  4429. #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
  4430. #define CAN_F5R2_FB21_Pos (21U)
  4431. #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
  4432. #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
  4433. #define CAN_F5R2_FB22_Pos (22U)
  4434. #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
  4435. #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
  4436. #define CAN_F5R2_FB23_Pos (23U)
  4437. #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
  4438. #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
  4439. #define CAN_F5R2_FB24_Pos (24U)
  4440. #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
  4441. #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
  4442. #define CAN_F5R2_FB25_Pos (25U)
  4443. #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
  4444. #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
  4445. #define CAN_F5R2_FB26_Pos (26U)
  4446. #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
  4447. #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
  4448. #define CAN_F5R2_FB27_Pos (27U)
  4449. #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
  4450. #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
  4451. #define CAN_F5R2_FB28_Pos (28U)
  4452. #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
  4453. #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
  4454. #define CAN_F5R2_FB29_Pos (29U)
  4455. #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
  4456. #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
  4457. #define CAN_F5R2_FB30_Pos (30U)
  4458. #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
  4459. #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
  4460. #define CAN_F5R2_FB31_Pos (31U)
  4461. #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
  4462. #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
  4463. /******************* Bit definition for CAN_F6R2 register *******************/
  4464. #define CAN_F6R2_FB0_Pos (0U)
  4465. #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
  4466. #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
  4467. #define CAN_F6R2_FB1_Pos (1U)
  4468. #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
  4469. #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
  4470. #define CAN_F6R2_FB2_Pos (2U)
  4471. #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
  4472. #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
  4473. #define CAN_F6R2_FB3_Pos (3U)
  4474. #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
  4475. #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
  4476. #define CAN_F6R2_FB4_Pos (4U)
  4477. #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
  4478. #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
  4479. #define CAN_F6R2_FB5_Pos (5U)
  4480. #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
  4481. #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
  4482. #define CAN_F6R2_FB6_Pos (6U)
  4483. #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
  4484. #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
  4485. #define CAN_F6R2_FB7_Pos (7U)
  4486. #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
  4487. #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
  4488. #define CAN_F6R2_FB8_Pos (8U)
  4489. #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
  4490. #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
  4491. #define CAN_F6R2_FB9_Pos (9U)
  4492. #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
  4493. #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
  4494. #define CAN_F6R2_FB10_Pos (10U)
  4495. #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
  4496. #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
  4497. #define CAN_F6R2_FB11_Pos (11U)
  4498. #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
  4499. #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
  4500. #define CAN_F6R2_FB12_Pos (12U)
  4501. #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
  4502. #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
  4503. #define CAN_F6R2_FB13_Pos (13U)
  4504. #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
  4505. #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
  4506. #define CAN_F6R2_FB14_Pos (14U)
  4507. #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
  4508. #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
  4509. #define CAN_F6R2_FB15_Pos (15U)
  4510. #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
  4511. #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
  4512. #define CAN_F6R2_FB16_Pos (16U)
  4513. #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
  4514. #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
  4515. #define CAN_F6R2_FB17_Pos (17U)
  4516. #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
  4517. #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
  4518. #define CAN_F6R2_FB18_Pos (18U)
  4519. #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
  4520. #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
  4521. #define CAN_F6R2_FB19_Pos (19U)
  4522. #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
  4523. #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
  4524. #define CAN_F6R2_FB20_Pos (20U)
  4525. #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
  4526. #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
  4527. #define CAN_F6R2_FB21_Pos (21U)
  4528. #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
  4529. #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
  4530. #define CAN_F6R2_FB22_Pos (22U)
  4531. #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
  4532. #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
  4533. #define CAN_F6R2_FB23_Pos (23U)
  4534. #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
  4535. #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
  4536. #define CAN_F6R2_FB24_Pos (24U)
  4537. #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
  4538. #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
  4539. #define CAN_F6R2_FB25_Pos (25U)
  4540. #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
  4541. #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
  4542. #define CAN_F6R2_FB26_Pos (26U)
  4543. #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
  4544. #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
  4545. #define CAN_F6R2_FB27_Pos (27U)
  4546. #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
  4547. #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
  4548. #define CAN_F6R2_FB28_Pos (28U)
  4549. #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
  4550. #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
  4551. #define CAN_F6R2_FB29_Pos (29U)
  4552. #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
  4553. #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
  4554. #define CAN_F6R2_FB30_Pos (30U)
  4555. #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
  4556. #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
  4557. #define CAN_F6R2_FB31_Pos (31U)
  4558. #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
  4559. #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
  4560. /******************* Bit definition for CAN_F7R2 register *******************/
  4561. #define CAN_F7R2_FB0_Pos (0U)
  4562. #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
  4563. #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
  4564. #define CAN_F7R2_FB1_Pos (1U)
  4565. #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
  4566. #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
  4567. #define CAN_F7R2_FB2_Pos (2U)
  4568. #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
  4569. #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
  4570. #define CAN_F7R2_FB3_Pos (3U)
  4571. #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
  4572. #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
  4573. #define CAN_F7R2_FB4_Pos (4U)
  4574. #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
  4575. #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
  4576. #define CAN_F7R2_FB5_Pos (5U)
  4577. #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
  4578. #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
  4579. #define CAN_F7R2_FB6_Pos (6U)
  4580. #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
  4581. #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
  4582. #define CAN_F7R2_FB7_Pos (7U)
  4583. #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
  4584. #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
  4585. #define CAN_F7R2_FB8_Pos (8U)
  4586. #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
  4587. #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
  4588. #define CAN_F7R2_FB9_Pos (9U)
  4589. #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
  4590. #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
  4591. #define CAN_F7R2_FB10_Pos (10U)
  4592. #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
  4593. #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
  4594. #define CAN_F7R2_FB11_Pos (11U)
  4595. #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
  4596. #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
  4597. #define CAN_F7R2_FB12_Pos (12U)
  4598. #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
  4599. #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
  4600. #define CAN_F7R2_FB13_Pos (13U)
  4601. #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
  4602. #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
  4603. #define CAN_F7R2_FB14_Pos (14U)
  4604. #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
  4605. #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
  4606. #define CAN_F7R2_FB15_Pos (15U)
  4607. #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
  4608. #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
  4609. #define CAN_F7R2_FB16_Pos (16U)
  4610. #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
  4611. #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
  4612. #define CAN_F7R2_FB17_Pos (17U)
  4613. #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
  4614. #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
  4615. #define CAN_F7R2_FB18_Pos (18U)
  4616. #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
  4617. #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
  4618. #define CAN_F7R2_FB19_Pos (19U)
  4619. #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
  4620. #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
  4621. #define CAN_F7R2_FB20_Pos (20U)
  4622. #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
  4623. #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
  4624. #define CAN_F7R2_FB21_Pos (21U)
  4625. #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
  4626. #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
  4627. #define CAN_F7R2_FB22_Pos (22U)
  4628. #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
  4629. #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
  4630. #define CAN_F7R2_FB23_Pos (23U)
  4631. #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
  4632. #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
  4633. #define CAN_F7R2_FB24_Pos (24U)
  4634. #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
  4635. #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
  4636. #define CAN_F7R2_FB25_Pos (25U)
  4637. #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
  4638. #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
  4639. #define CAN_F7R2_FB26_Pos (26U)
  4640. #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
  4641. #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
  4642. #define CAN_F7R2_FB27_Pos (27U)
  4643. #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
  4644. #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
  4645. #define CAN_F7R2_FB28_Pos (28U)
  4646. #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
  4647. #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
  4648. #define CAN_F7R2_FB29_Pos (29U)
  4649. #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
  4650. #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
  4651. #define CAN_F7R2_FB30_Pos (30U)
  4652. #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
  4653. #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
  4654. #define CAN_F7R2_FB31_Pos (31U)
  4655. #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
  4656. #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
  4657. /******************* Bit definition for CAN_F8R2 register *******************/
  4658. #define CAN_F8R2_FB0_Pos (0U)
  4659. #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
  4660. #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
  4661. #define CAN_F8R2_FB1_Pos (1U)
  4662. #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
  4663. #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
  4664. #define CAN_F8R2_FB2_Pos (2U)
  4665. #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
  4666. #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
  4667. #define CAN_F8R2_FB3_Pos (3U)
  4668. #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
  4669. #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
  4670. #define CAN_F8R2_FB4_Pos (4U)
  4671. #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
  4672. #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
  4673. #define CAN_F8R2_FB5_Pos (5U)
  4674. #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
  4675. #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
  4676. #define CAN_F8R2_FB6_Pos (6U)
  4677. #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
  4678. #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
  4679. #define CAN_F8R2_FB7_Pos (7U)
  4680. #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
  4681. #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
  4682. #define CAN_F8R2_FB8_Pos (8U)
  4683. #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
  4684. #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
  4685. #define CAN_F8R2_FB9_Pos (9U)
  4686. #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
  4687. #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
  4688. #define CAN_F8R2_FB10_Pos (10U)
  4689. #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
  4690. #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
  4691. #define CAN_F8R2_FB11_Pos (11U)
  4692. #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
  4693. #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
  4694. #define CAN_F8R2_FB12_Pos (12U)
  4695. #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
  4696. #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
  4697. #define CAN_F8R2_FB13_Pos (13U)
  4698. #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
  4699. #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
  4700. #define CAN_F8R2_FB14_Pos (14U)
  4701. #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
  4702. #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
  4703. #define CAN_F8R2_FB15_Pos (15U)
  4704. #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
  4705. #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
  4706. #define CAN_F8R2_FB16_Pos (16U)
  4707. #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
  4708. #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
  4709. #define CAN_F8R2_FB17_Pos (17U)
  4710. #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
  4711. #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
  4712. #define CAN_F8R2_FB18_Pos (18U)
  4713. #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
  4714. #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
  4715. #define CAN_F8R2_FB19_Pos (19U)
  4716. #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
  4717. #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
  4718. #define CAN_F8R2_FB20_Pos (20U)
  4719. #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
  4720. #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
  4721. #define CAN_F8R2_FB21_Pos (21U)
  4722. #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
  4723. #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
  4724. #define CAN_F8R2_FB22_Pos (22U)
  4725. #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
  4726. #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
  4727. #define CAN_F8R2_FB23_Pos (23U)
  4728. #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
  4729. #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
  4730. #define CAN_F8R2_FB24_Pos (24U)
  4731. #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
  4732. #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
  4733. #define CAN_F8R2_FB25_Pos (25U)
  4734. #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
  4735. #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
  4736. #define CAN_F8R2_FB26_Pos (26U)
  4737. #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
  4738. #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
  4739. #define CAN_F8R2_FB27_Pos (27U)
  4740. #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
  4741. #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
  4742. #define CAN_F8R2_FB28_Pos (28U)
  4743. #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
  4744. #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
  4745. #define CAN_F8R2_FB29_Pos (29U)
  4746. #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
  4747. #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
  4748. #define CAN_F8R2_FB30_Pos (30U)
  4749. #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
  4750. #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
  4751. #define CAN_F8R2_FB31_Pos (31U)
  4752. #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
  4753. #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
  4754. /******************* Bit definition for CAN_F9R2 register *******************/
  4755. #define CAN_F9R2_FB0_Pos (0U)
  4756. #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
  4757. #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
  4758. #define CAN_F9R2_FB1_Pos (1U)
  4759. #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
  4760. #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
  4761. #define CAN_F9R2_FB2_Pos (2U)
  4762. #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
  4763. #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
  4764. #define CAN_F9R2_FB3_Pos (3U)
  4765. #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
  4766. #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
  4767. #define CAN_F9R2_FB4_Pos (4U)
  4768. #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
  4769. #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
  4770. #define CAN_F9R2_FB5_Pos (5U)
  4771. #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
  4772. #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
  4773. #define CAN_F9R2_FB6_Pos (6U)
  4774. #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
  4775. #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
  4776. #define CAN_F9R2_FB7_Pos (7U)
  4777. #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
  4778. #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
  4779. #define CAN_F9R2_FB8_Pos (8U)
  4780. #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
  4781. #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
  4782. #define CAN_F9R2_FB9_Pos (9U)
  4783. #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
  4784. #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
  4785. #define CAN_F9R2_FB10_Pos (10U)
  4786. #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
  4787. #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
  4788. #define CAN_F9R2_FB11_Pos (11U)
  4789. #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
  4790. #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
  4791. #define CAN_F9R2_FB12_Pos (12U)
  4792. #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
  4793. #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
  4794. #define CAN_F9R2_FB13_Pos (13U)
  4795. #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
  4796. #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
  4797. #define CAN_F9R2_FB14_Pos (14U)
  4798. #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
  4799. #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
  4800. #define CAN_F9R2_FB15_Pos (15U)
  4801. #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
  4802. #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
  4803. #define CAN_F9R2_FB16_Pos (16U)
  4804. #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
  4805. #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
  4806. #define CAN_F9R2_FB17_Pos (17U)
  4807. #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
  4808. #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
  4809. #define CAN_F9R2_FB18_Pos (18U)
  4810. #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
  4811. #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
  4812. #define CAN_F9R2_FB19_Pos (19U)
  4813. #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
  4814. #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
  4815. #define CAN_F9R2_FB20_Pos (20U)
  4816. #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
  4817. #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
  4818. #define CAN_F9R2_FB21_Pos (21U)
  4819. #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
  4820. #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
  4821. #define CAN_F9R2_FB22_Pos (22U)
  4822. #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
  4823. #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
  4824. #define CAN_F9R2_FB23_Pos (23U)
  4825. #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
  4826. #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
  4827. #define CAN_F9R2_FB24_Pos (24U)
  4828. #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
  4829. #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
  4830. #define CAN_F9R2_FB25_Pos (25U)
  4831. #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
  4832. #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
  4833. #define CAN_F9R2_FB26_Pos (26U)
  4834. #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
  4835. #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
  4836. #define CAN_F9R2_FB27_Pos (27U)
  4837. #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
  4838. #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
  4839. #define CAN_F9R2_FB28_Pos (28U)
  4840. #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
  4841. #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
  4842. #define CAN_F9R2_FB29_Pos (29U)
  4843. #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
  4844. #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
  4845. #define CAN_F9R2_FB30_Pos (30U)
  4846. #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
  4847. #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
  4848. #define CAN_F9R2_FB31_Pos (31U)
  4849. #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
  4850. #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
  4851. /******************* Bit definition for CAN_F10R2 register ******************/
  4852. #define CAN_F10R2_FB0_Pos (0U)
  4853. #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
  4854. #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
  4855. #define CAN_F10R2_FB1_Pos (1U)
  4856. #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
  4857. #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
  4858. #define CAN_F10R2_FB2_Pos (2U)
  4859. #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
  4860. #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
  4861. #define CAN_F10R2_FB3_Pos (3U)
  4862. #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
  4863. #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
  4864. #define CAN_F10R2_FB4_Pos (4U)
  4865. #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
  4866. #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
  4867. #define CAN_F10R2_FB5_Pos (5U)
  4868. #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
  4869. #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
  4870. #define CAN_F10R2_FB6_Pos (6U)
  4871. #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
  4872. #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
  4873. #define CAN_F10R2_FB7_Pos (7U)
  4874. #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
  4875. #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
  4876. #define CAN_F10R2_FB8_Pos (8U)
  4877. #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
  4878. #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
  4879. #define CAN_F10R2_FB9_Pos (9U)
  4880. #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
  4881. #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
  4882. #define CAN_F10R2_FB10_Pos (10U)
  4883. #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
  4884. #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
  4885. #define CAN_F10R2_FB11_Pos (11U)
  4886. #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
  4887. #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
  4888. #define CAN_F10R2_FB12_Pos (12U)
  4889. #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
  4890. #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
  4891. #define CAN_F10R2_FB13_Pos (13U)
  4892. #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
  4893. #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
  4894. #define CAN_F10R2_FB14_Pos (14U)
  4895. #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
  4896. #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
  4897. #define CAN_F10R2_FB15_Pos (15U)
  4898. #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
  4899. #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
  4900. #define CAN_F10R2_FB16_Pos (16U)
  4901. #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
  4902. #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
  4903. #define CAN_F10R2_FB17_Pos (17U)
  4904. #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
  4905. #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
  4906. #define CAN_F10R2_FB18_Pos (18U)
  4907. #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
  4908. #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
  4909. #define CAN_F10R2_FB19_Pos (19U)
  4910. #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
  4911. #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
  4912. #define CAN_F10R2_FB20_Pos (20U)
  4913. #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
  4914. #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
  4915. #define CAN_F10R2_FB21_Pos (21U)
  4916. #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
  4917. #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
  4918. #define CAN_F10R2_FB22_Pos (22U)
  4919. #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
  4920. #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
  4921. #define CAN_F10R2_FB23_Pos (23U)
  4922. #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
  4923. #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
  4924. #define CAN_F10R2_FB24_Pos (24U)
  4925. #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
  4926. #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
  4927. #define CAN_F10R2_FB25_Pos (25U)
  4928. #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
  4929. #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
  4930. #define CAN_F10R2_FB26_Pos (26U)
  4931. #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
  4932. #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
  4933. #define CAN_F10R2_FB27_Pos (27U)
  4934. #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
  4935. #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
  4936. #define CAN_F10R2_FB28_Pos (28U)
  4937. #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
  4938. #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
  4939. #define CAN_F10R2_FB29_Pos (29U)
  4940. #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
  4941. #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
  4942. #define CAN_F10R2_FB30_Pos (30U)
  4943. #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
  4944. #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
  4945. #define CAN_F10R2_FB31_Pos (31U)
  4946. #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
  4947. #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
  4948. /******************* Bit definition for CAN_F11R2 register ******************/
  4949. #define CAN_F11R2_FB0_Pos (0U)
  4950. #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
  4951. #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
  4952. #define CAN_F11R2_FB1_Pos (1U)
  4953. #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
  4954. #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
  4955. #define CAN_F11R2_FB2_Pos (2U)
  4956. #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
  4957. #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
  4958. #define CAN_F11R2_FB3_Pos (3U)
  4959. #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
  4960. #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
  4961. #define CAN_F11R2_FB4_Pos (4U)
  4962. #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
  4963. #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
  4964. #define CAN_F11R2_FB5_Pos (5U)
  4965. #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
  4966. #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
  4967. #define CAN_F11R2_FB6_Pos (6U)
  4968. #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
  4969. #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
  4970. #define CAN_F11R2_FB7_Pos (7U)
  4971. #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
  4972. #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
  4973. #define CAN_F11R2_FB8_Pos (8U)
  4974. #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
  4975. #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
  4976. #define CAN_F11R2_FB9_Pos (9U)
  4977. #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
  4978. #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
  4979. #define CAN_F11R2_FB10_Pos (10U)
  4980. #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
  4981. #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
  4982. #define CAN_F11R2_FB11_Pos (11U)
  4983. #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
  4984. #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
  4985. #define CAN_F11R2_FB12_Pos (12U)
  4986. #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
  4987. #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
  4988. #define CAN_F11R2_FB13_Pos (13U)
  4989. #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
  4990. #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
  4991. #define CAN_F11R2_FB14_Pos (14U)
  4992. #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
  4993. #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
  4994. #define CAN_F11R2_FB15_Pos (15U)
  4995. #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
  4996. #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
  4997. #define CAN_F11R2_FB16_Pos (16U)
  4998. #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
  4999. #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
  5000. #define CAN_F11R2_FB17_Pos (17U)
  5001. #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
  5002. #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
  5003. #define CAN_F11R2_FB18_Pos (18U)
  5004. #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
  5005. #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
  5006. #define CAN_F11R2_FB19_Pos (19U)
  5007. #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
  5008. #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
  5009. #define CAN_F11R2_FB20_Pos (20U)
  5010. #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
  5011. #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
  5012. #define CAN_F11R2_FB21_Pos (21U)
  5013. #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
  5014. #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
  5015. #define CAN_F11R2_FB22_Pos (22U)
  5016. #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
  5017. #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
  5018. #define CAN_F11R2_FB23_Pos (23U)
  5019. #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
  5020. #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
  5021. #define CAN_F11R2_FB24_Pos (24U)
  5022. #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
  5023. #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
  5024. #define CAN_F11R2_FB25_Pos (25U)
  5025. #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
  5026. #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
  5027. #define CAN_F11R2_FB26_Pos (26U)
  5028. #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
  5029. #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
  5030. #define CAN_F11R2_FB27_Pos (27U)
  5031. #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
  5032. #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
  5033. #define CAN_F11R2_FB28_Pos (28U)
  5034. #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
  5035. #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
  5036. #define CAN_F11R2_FB29_Pos (29U)
  5037. #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
  5038. #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
  5039. #define CAN_F11R2_FB30_Pos (30U)
  5040. #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
  5041. #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
  5042. #define CAN_F11R2_FB31_Pos (31U)
  5043. #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
  5044. #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
  5045. /******************* Bit definition for CAN_F12R2 register ******************/
  5046. #define CAN_F12R2_FB0_Pos (0U)
  5047. #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
  5048. #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
  5049. #define CAN_F12R2_FB1_Pos (1U)
  5050. #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
  5051. #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
  5052. #define CAN_F12R2_FB2_Pos (2U)
  5053. #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
  5054. #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
  5055. #define CAN_F12R2_FB3_Pos (3U)
  5056. #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
  5057. #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
  5058. #define CAN_F12R2_FB4_Pos (4U)
  5059. #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
  5060. #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
  5061. #define CAN_F12R2_FB5_Pos (5U)
  5062. #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
  5063. #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
  5064. #define CAN_F12R2_FB6_Pos (6U)
  5065. #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
  5066. #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
  5067. #define CAN_F12R2_FB7_Pos (7U)
  5068. #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
  5069. #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
  5070. #define CAN_F12R2_FB8_Pos (8U)
  5071. #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
  5072. #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
  5073. #define CAN_F12R2_FB9_Pos (9U)
  5074. #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
  5075. #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
  5076. #define CAN_F12R2_FB10_Pos (10U)
  5077. #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
  5078. #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
  5079. #define CAN_F12R2_FB11_Pos (11U)
  5080. #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
  5081. #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
  5082. #define CAN_F12R2_FB12_Pos (12U)
  5083. #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
  5084. #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
  5085. #define CAN_F12R2_FB13_Pos (13U)
  5086. #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
  5087. #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
  5088. #define CAN_F12R2_FB14_Pos (14U)
  5089. #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
  5090. #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
  5091. #define CAN_F12R2_FB15_Pos (15U)
  5092. #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
  5093. #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
  5094. #define CAN_F12R2_FB16_Pos (16U)
  5095. #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
  5096. #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
  5097. #define CAN_F12R2_FB17_Pos (17U)
  5098. #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
  5099. #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
  5100. #define CAN_F12R2_FB18_Pos (18U)
  5101. #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
  5102. #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
  5103. #define CAN_F12R2_FB19_Pos (19U)
  5104. #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
  5105. #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
  5106. #define CAN_F12R2_FB20_Pos (20U)
  5107. #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
  5108. #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
  5109. #define CAN_F12R2_FB21_Pos (21U)
  5110. #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
  5111. #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
  5112. #define CAN_F12R2_FB22_Pos (22U)
  5113. #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
  5114. #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
  5115. #define CAN_F12R2_FB23_Pos (23U)
  5116. #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
  5117. #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
  5118. #define CAN_F12R2_FB24_Pos (24U)
  5119. #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
  5120. #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
  5121. #define CAN_F12R2_FB25_Pos (25U)
  5122. #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
  5123. #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
  5124. #define CAN_F12R2_FB26_Pos (26U)
  5125. #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
  5126. #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
  5127. #define CAN_F12R2_FB27_Pos (27U)
  5128. #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
  5129. #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
  5130. #define CAN_F12R2_FB28_Pos (28U)
  5131. #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
  5132. #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
  5133. #define CAN_F12R2_FB29_Pos (29U)
  5134. #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
  5135. #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
  5136. #define CAN_F12R2_FB30_Pos (30U)
  5137. #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
  5138. #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
  5139. #define CAN_F12R2_FB31_Pos (31U)
  5140. #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
  5141. #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
  5142. /******************* Bit definition for CAN_F13R2 register ******************/
  5143. #define CAN_F13R2_FB0_Pos (0U)
  5144. #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
  5145. #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
  5146. #define CAN_F13R2_FB1_Pos (1U)
  5147. #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
  5148. #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
  5149. #define CAN_F13R2_FB2_Pos (2U)
  5150. #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
  5151. #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
  5152. #define CAN_F13R2_FB3_Pos (3U)
  5153. #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
  5154. #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
  5155. #define CAN_F13R2_FB4_Pos (4U)
  5156. #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
  5157. #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
  5158. #define CAN_F13R2_FB5_Pos (5U)
  5159. #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
  5160. #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
  5161. #define CAN_F13R2_FB6_Pos (6U)
  5162. #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
  5163. #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
  5164. #define CAN_F13R2_FB7_Pos (7U)
  5165. #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
  5166. #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
  5167. #define CAN_F13R2_FB8_Pos (8U)
  5168. #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
  5169. #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
  5170. #define CAN_F13R2_FB9_Pos (9U)
  5171. #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
  5172. #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
  5173. #define CAN_F13R2_FB10_Pos (10U)
  5174. #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
  5175. #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
  5176. #define CAN_F13R2_FB11_Pos (11U)
  5177. #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
  5178. #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
  5179. #define CAN_F13R2_FB12_Pos (12U)
  5180. #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
  5181. #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
  5182. #define CAN_F13R2_FB13_Pos (13U)
  5183. #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
  5184. #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
  5185. #define CAN_F13R2_FB14_Pos (14U)
  5186. #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
  5187. #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
  5188. #define CAN_F13R2_FB15_Pos (15U)
  5189. #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
  5190. #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
  5191. #define CAN_F13R2_FB16_Pos (16U)
  5192. #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
  5193. #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
  5194. #define CAN_F13R2_FB17_Pos (17U)
  5195. #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
  5196. #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
  5197. #define CAN_F13R2_FB18_Pos (18U)
  5198. #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
  5199. #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
  5200. #define CAN_F13R2_FB19_Pos (19U)
  5201. #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
  5202. #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
  5203. #define CAN_F13R2_FB20_Pos (20U)
  5204. #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
  5205. #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
  5206. #define CAN_F13R2_FB21_Pos (21U)
  5207. #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
  5208. #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
  5209. #define CAN_F13R2_FB22_Pos (22U)
  5210. #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
  5211. #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
  5212. #define CAN_F13R2_FB23_Pos (23U)
  5213. #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
  5214. #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
  5215. #define CAN_F13R2_FB24_Pos (24U)
  5216. #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
  5217. #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
  5218. #define CAN_F13R2_FB25_Pos (25U)
  5219. #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
  5220. #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
  5221. #define CAN_F13R2_FB26_Pos (26U)
  5222. #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
  5223. #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
  5224. #define CAN_F13R2_FB27_Pos (27U)
  5225. #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
  5226. #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
  5227. #define CAN_F13R2_FB28_Pos (28U)
  5228. #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
  5229. #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
  5230. #define CAN_F13R2_FB29_Pos (29U)
  5231. #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
  5232. #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
  5233. #define CAN_F13R2_FB30_Pos (30U)
  5234. #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
  5235. #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
  5236. #define CAN_F13R2_FB31_Pos (31U)
  5237. #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
  5238. #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
  5239. /******************************************************************************/
  5240. /* */
  5241. /* CRC calculation unit */
  5242. /* */
  5243. /******************************************************************************/
  5244. /******************* Bit definition for CRC_DR register *********************/
  5245. #define CRC_DR_DR_Pos (0U)
  5246. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  5247. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  5248. /******************* Bit definition for CRC_IDR register ********************/
  5249. #define CRC_IDR_IDR_Pos (0U)
  5250. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  5251. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  5252. /******************** Bit definition for CRC_CR register ********************/
  5253. #define CRC_CR_RESET_Pos (0U)
  5254. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  5255. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  5256. /******************************************************************************/
  5257. /* */
  5258. /* Digital to Analog Converter */
  5259. /* */
  5260. /******************************************************************************/
  5261. /*
  5262. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  5263. */
  5264. #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
  5265. /******************** Bit definition for DAC_CR register ********************/
  5266. #define DAC_CR_EN1_Pos (0U)
  5267. #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
  5268. #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
  5269. #define DAC_CR_BOFF1_Pos (1U)
  5270. #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
  5271. #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
  5272. #define DAC_CR_TEN1_Pos (2U)
  5273. #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
  5274. #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
  5275. #define DAC_CR_TSEL1_Pos (3U)
  5276. #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
  5277. #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
  5278. #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
  5279. #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
  5280. #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
  5281. #define DAC_CR_WAVE1_Pos (6U)
  5282. #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
  5283. #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  5284. #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
  5285. #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
  5286. #define DAC_CR_MAMP1_Pos (8U)
  5287. #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
  5288. #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  5289. #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
  5290. #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
  5291. #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
  5292. #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
  5293. #define DAC_CR_DMAEN1_Pos (12U)
  5294. #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
  5295. #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
  5296. #define DAC_CR_DMAUDRIE1_Pos (13U)
  5297. #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
  5298. #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
  5299. #define DAC_CR_EN2_Pos (16U)
  5300. #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
  5301. #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
  5302. #define DAC_CR_BOFF2_Pos (17U)
  5303. #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
  5304. #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
  5305. #define DAC_CR_TEN2_Pos (18U)
  5306. #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
  5307. #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
  5308. #define DAC_CR_TSEL2_Pos (19U)
  5309. #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
  5310. #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
  5311. #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
  5312. #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
  5313. #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
  5314. #define DAC_CR_WAVE2_Pos (22U)
  5315. #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
  5316. #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  5317. #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
  5318. #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
  5319. #define DAC_CR_MAMP2_Pos (24U)
  5320. #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
  5321. #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  5322. #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
  5323. #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
  5324. #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
  5325. #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
  5326. #define DAC_CR_DMAEN2_Pos (28U)
  5327. #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
  5328. #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
  5329. #define DAC_CR_DMAUDRIE2_Pos (29U)
  5330. #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
  5331. #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
  5332. /***************** Bit definition for DAC_SWTRIGR register ******************/
  5333. #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
  5334. #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
  5335. #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
  5336. #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
  5337. #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
  5338. #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
  5339. /***************** Bit definition for DAC_DHR12R1 register ******************/
  5340. #define DAC_DHR12R1_DACC1DHR_Pos (0U)
  5341. #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
  5342. #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5343. /***************** Bit definition for DAC_DHR12L1 register ******************/
  5344. #define DAC_DHR12L1_DACC1DHR_Pos (4U)
  5345. #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5346. #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5347. /****************** Bit definition for DAC_DHR8R1 register ******************/
  5348. #define DAC_DHR8R1_DACC1DHR_Pos (0U)
  5349. #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
  5350. #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5351. /***************** Bit definition for DAC_DHR12R2 register ******************/
  5352. #define DAC_DHR12R2_DACC2DHR_Pos (0U)
  5353. #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
  5354. #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5355. /***************** Bit definition for DAC_DHR12L2 register ******************/
  5356. #define DAC_DHR12L2_DACC2DHR_Pos (4U)
  5357. #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
  5358. #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5359. /****************** Bit definition for DAC_DHR8R2 register ******************/
  5360. #define DAC_DHR8R2_DACC2DHR_Pos (0U)
  5361. #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
  5362. #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5363. /***************** Bit definition for DAC_DHR12RD register ******************/
  5364. #define DAC_DHR12RD_DACC1DHR_Pos (0U)
  5365. #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
  5366. #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5367. #define DAC_DHR12RD_DACC2DHR_Pos (16U)
  5368. #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
  5369. #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5370. /***************** Bit definition for DAC_DHR12LD register ******************/
  5371. #define DAC_DHR12LD_DACC1DHR_Pos (4U)
  5372. #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5373. #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5374. #define DAC_DHR12LD_DACC2DHR_Pos (20U)
  5375. #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
  5376. #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5377. /****************** Bit definition for DAC_DHR8RD register ******************/
  5378. #define DAC_DHR8RD_DACC1DHR_Pos (0U)
  5379. #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
  5380. #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5381. #define DAC_DHR8RD_DACC2DHR_Pos (8U)
  5382. #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
  5383. #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5384. /******************* Bit definition for DAC_DOR1 register *******************/
  5385. #define DAC_DOR1_DACC1DOR_Pos (0U)
  5386. #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
  5387. #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
  5388. /******************* Bit definition for DAC_DOR2 register *******************/
  5389. #define DAC_DOR2_DACC2DOR_Pos (0U)
  5390. #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
  5391. #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
  5392. /******************** Bit definition for DAC_SR register ********************/
  5393. #define DAC_SR_DMAUDR1_Pos (13U)
  5394. #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
  5395. #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
  5396. #define DAC_SR_DMAUDR2_Pos (29U)
  5397. #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
  5398. #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
  5399. /******************************************************************************/
  5400. /* */
  5401. /* Digital Filter for Sigma Delta Modulators */
  5402. /* */
  5403. /******************************************************************************/
  5404. /**************** DFSDM channel configuration registers ********************/
  5405. /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
  5406. #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
  5407. #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
  5408. #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
  5409. #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
  5410. #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
  5411. #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
  5412. #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
  5413. #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
  5414. #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
  5415. #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
  5416. #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
  5417. #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
  5418. #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
  5419. #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
  5420. #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
  5421. #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
  5422. #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
  5423. #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
  5424. #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
  5425. #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
  5426. #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
  5427. #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
  5428. #define DFSDM_CHCFGR1_CHEN_Pos (7U)
  5429. #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
  5430. #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
  5431. #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
  5432. #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
  5433. #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
  5434. #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
  5435. #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
  5436. #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
  5437. #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
  5438. #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
  5439. #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
  5440. #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
  5441. #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
  5442. #define DFSDM_CHCFGR1_SITP_Pos (0U)
  5443. #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
  5444. #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
  5445. #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
  5446. #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
  5447. /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
  5448. #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
  5449. #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
  5450. #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
  5451. #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
  5452. #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
  5453. #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
  5454. /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
  5455. #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
  5456. #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
  5457. #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
  5458. #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
  5459. #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
  5460. #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
  5461. #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
  5462. #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
  5463. #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
  5464. #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
  5465. #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
  5466. #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
  5467. #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
  5468. #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
  5469. /**************** Bit definition for DFSDM_CHWDATR register *******************/
  5470. #define DFSDM_CHWDATR_WDATA_Pos (0U)
  5471. #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
  5472. #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
  5473. /**************** Bit definition for DFSDM_CHDATINR register *****************/
  5474. #define DFSDM_CHDATINR_INDAT0_Pos (0U)
  5475. #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
  5476. #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
  5477. #define DFSDM_CHDATINR_INDAT1_Pos (16U)
  5478. #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
  5479. #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
  5480. /************************ DFSDM module registers ****************************/
  5481. /***************** Bit definition for DFSDM_FLTCR1 register *******************/
  5482. #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
  5483. #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
  5484. #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
  5485. #define DFSDM_FLTCR1_FAST_Pos (29U)
  5486. #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
  5487. #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
  5488. #define DFSDM_FLTCR1_RCH_Pos (24U)
  5489. #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
  5490. #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
  5491. #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
  5492. #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
  5493. #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
  5494. #define DFSDM_FLTCR1_RSYNC_Pos (19U)
  5495. #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
  5496. #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
  5497. #define DFSDM_FLTCR1_RCONT_Pos (18U)
  5498. #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
  5499. #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
  5500. #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
  5501. #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
  5502. #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
  5503. #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
  5504. #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
  5505. #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
  5506. #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
  5507. #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
  5508. #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
  5509. #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
  5510. #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
  5511. #define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
  5512. #define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
  5513. #define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
  5514. #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
  5515. #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
  5516. #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
  5517. #define DFSDM_FLTCR1_JSCAN_Pos (4U)
  5518. #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
  5519. #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
  5520. #define DFSDM_FLTCR1_JSYNC_Pos (3U)
  5521. #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
  5522. #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
  5523. #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
  5524. #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
  5525. #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
  5526. #define DFSDM_FLTCR1_DFEN_Pos (0U)
  5527. #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
  5528. #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
  5529. /***************** Bit definition for DFSDM_FLTCR2 register *******************/
  5530. #define DFSDM_FLTCR2_AWDCH_Pos (16U)
  5531. #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
  5532. #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
  5533. #define DFSDM_FLTCR2_EXCH_Pos (8U)
  5534. #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
  5535. #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
  5536. #define DFSDM_FLTCR2_CKABIE_Pos (6U)
  5537. #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
  5538. #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
  5539. #define DFSDM_FLTCR2_SCDIE_Pos (5U)
  5540. #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
  5541. #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
  5542. #define DFSDM_FLTCR2_AWDIE_Pos (4U)
  5543. #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
  5544. #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
  5545. #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
  5546. #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
  5547. #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
  5548. #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
  5549. #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
  5550. #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
  5551. #define DFSDM_FLTCR2_REOCIE_Pos (1U)
  5552. #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
  5553. #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
  5554. #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
  5555. #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
  5556. #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
  5557. /***************** Bit definition for DFSDM_FLTISR register *******************/
  5558. #define DFSDM_FLTISR_SCDF_Pos (24U)
  5559. #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
  5560. #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
  5561. #define DFSDM_FLTISR_CKABF_Pos (16U)
  5562. #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
  5563. #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
  5564. #define DFSDM_FLTISR_RCIP_Pos (14U)
  5565. #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
  5566. #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
  5567. #define DFSDM_FLTISR_JCIP_Pos (13U)
  5568. #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
  5569. #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
  5570. #define DFSDM_FLTISR_AWDF_Pos (4U)
  5571. #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
  5572. #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
  5573. #define DFSDM_FLTISR_ROVRF_Pos (3U)
  5574. #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
  5575. #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
  5576. #define DFSDM_FLTISR_JOVRF_Pos (2U)
  5577. #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
  5578. #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
  5579. #define DFSDM_FLTISR_REOCF_Pos (1U)
  5580. #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
  5581. #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
  5582. #define DFSDM_FLTISR_JEOCF_Pos (0U)
  5583. #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
  5584. #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
  5585. /***************** Bit definition for DFSDM_FLTICR register *******************/
  5586. #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
  5587. #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
  5588. #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
  5589. #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
  5590. #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
  5591. #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
  5592. #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
  5593. #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
  5594. #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
  5595. #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
  5596. #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
  5597. #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
  5598. /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
  5599. #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
  5600. #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
  5601. #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
  5602. /***************** Bit definition for DFSDM_FLTFCR register *******************/
  5603. #define DFSDM_FLTFCR_FORD_Pos (29U)
  5604. #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
  5605. #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
  5606. #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
  5607. #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
  5608. #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
  5609. #define DFSDM_FLTFCR_FOSR_Pos (16U)
  5610. #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
  5611. #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
  5612. #define DFSDM_FLTFCR_IOSR_Pos (0U)
  5613. #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
  5614. #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
  5615. /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
  5616. #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
  5617. #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
  5618. #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
  5619. #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
  5620. #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
  5621. #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
  5622. /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
  5623. #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
  5624. #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
  5625. #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
  5626. #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
  5627. #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
  5628. #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
  5629. #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
  5630. #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
  5631. #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
  5632. /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
  5633. #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
  5634. #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
  5635. #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
  5636. #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
  5637. #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
  5638. #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
  5639. /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
  5640. #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
  5641. #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
  5642. #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
  5643. #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
  5644. #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
  5645. #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
  5646. /*************** Bit definition for DFSDM_FLTAWSR register *******************/
  5647. #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
  5648. #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
  5649. #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
  5650. #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
  5651. #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
  5652. #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
  5653. /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
  5654. #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
  5655. #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
  5656. #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
  5657. #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
  5658. #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
  5659. #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
  5660. /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
  5661. #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
  5662. #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
  5663. #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
  5664. #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
  5665. #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
  5666. #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
  5667. /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
  5668. #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
  5669. #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
  5670. #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
  5671. #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
  5672. #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
  5673. #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
  5674. /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
  5675. #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
  5676. #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
  5677. #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
  5678. /* Legacy Defines */
  5679. #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
  5680. #define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
  5681. #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
  5682. /******************************************************************************/
  5683. /* */
  5684. /* DMA Controller */
  5685. /* */
  5686. /******************************************************************************/
  5687. /******************** Bits definition for DMA_SxCR register *****************/
  5688. #define DMA_SxCR_CHSEL_Pos (25U)
  5689. #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
  5690. #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
  5691. #define DMA_SxCR_CHSEL_0 0x02000000U
  5692. #define DMA_SxCR_CHSEL_1 0x04000000U
  5693. #define DMA_SxCR_CHSEL_2 0x08000000U
  5694. #define DMA_SxCR_CHSEL_3 0x10000000U
  5695. #define DMA_SxCR_MBURST_Pos (23U)
  5696. #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
  5697. #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
  5698. #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
  5699. #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
  5700. #define DMA_SxCR_PBURST_Pos (21U)
  5701. #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
  5702. #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
  5703. #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
  5704. #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
  5705. #define DMA_SxCR_CT_Pos (19U)
  5706. #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
  5707. #define DMA_SxCR_CT DMA_SxCR_CT_Msk
  5708. #define DMA_SxCR_DBM_Pos (18U)
  5709. #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
  5710. #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
  5711. #define DMA_SxCR_PL_Pos (16U)
  5712. #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
  5713. #define DMA_SxCR_PL DMA_SxCR_PL_Msk
  5714. #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
  5715. #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
  5716. #define DMA_SxCR_PINCOS_Pos (15U)
  5717. #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
  5718. #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
  5719. #define DMA_SxCR_MSIZE_Pos (13U)
  5720. #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
  5721. #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
  5722. #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
  5723. #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
  5724. #define DMA_SxCR_PSIZE_Pos (11U)
  5725. #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
  5726. #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
  5727. #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
  5728. #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
  5729. #define DMA_SxCR_MINC_Pos (10U)
  5730. #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
  5731. #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
  5732. #define DMA_SxCR_PINC_Pos (9U)
  5733. #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
  5734. #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
  5735. #define DMA_SxCR_CIRC_Pos (8U)
  5736. #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
  5737. #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
  5738. #define DMA_SxCR_DIR_Pos (6U)
  5739. #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
  5740. #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
  5741. #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
  5742. #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
  5743. #define DMA_SxCR_PFCTRL_Pos (5U)
  5744. #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
  5745. #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
  5746. #define DMA_SxCR_TCIE_Pos (4U)
  5747. #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
  5748. #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
  5749. #define DMA_SxCR_HTIE_Pos (3U)
  5750. #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
  5751. #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
  5752. #define DMA_SxCR_TEIE_Pos (2U)
  5753. #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
  5754. #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
  5755. #define DMA_SxCR_DMEIE_Pos (1U)
  5756. #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
  5757. #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
  5758. #define DMA_SxCR_EN_Pos (0U)
  5759. #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
  5760. #define DMA_SxCR_EN DMA_SxCR_EN_Msk
  5761. /* Legacy defines */
  5762. #define DMA_SxCR_ACK_Pos (20U)
  5763. #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
  5764. #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
  5765. /******************** Bits definition for DMA_SxCNDTR register **************/
  5766. #define DMA_SxNDT_Pos (0U)
  5767. #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
  5768. #define DMA_SxNDT DMA_SxNDT_Msk
  5769. #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
  5770. #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
  5771. #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
  5772. #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
  5773. #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
  5774. #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
  5775. #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
  5776. #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
  5777. #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
  5778. #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
  5779. #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
  5780. #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
  5781. #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
  5782. #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
  5783. #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
  5784. #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
  5785. /******************** Bits definition for DMA_SxFCR register ****************/
  5786. #define DMA_SxFCR_FEIE_Pos (7U)
  5787. #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
  5788. #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
  5789. #define DMA_SxFCR_FS_Pos (3U)
  5790. #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
  5791. #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
  5792. #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
  5793. #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
  5794. #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
  5795. #define DMA_SxFCR_DMDIS_Pos (2U)
  5796. #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
  5797. #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
  5798. #define DMA_SxFCR_FTH_Pos (0U)
  5799. #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
  5800. #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
  5801. #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
  5802. #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
  5803. /******************** Bits definition for DMA_LISR register *****************/
  5804. #define DMA_LISR_TCIF3_Pos (27U)
  5805. #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
  5806. #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
  5807. #define DMA_LISR_HTIF3_Pos (26U)
  5808. #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
  5809. #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
  5810. #define DMA_LISR_TEIF3_Pos (25U)
  5811. #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
  5812. #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
  5813. #define DMA_LISR_DMEIF3_Pos (24U)
  5814. #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
  5815. #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
  5816. #define DMA_LISR_FEIF3_Pos (22U)
  5817. #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
  5818. #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
  5819. #define DMA_LISR_TCIF2_Pos (21U)
  5820. #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
  5821. #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
  5822. #define DMA_LISR_HTIF2_Pos (20U)
  5823. #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
  5824. #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
  5825. #define DMA_LISR_TEIF2_Pos (19U)
  5826. #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
  5827. #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
  5828. #define DMA_LISR_DMEIF2_Pos (18U)
  5829. #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
  5830. #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
  5831. #define DMA_LISR_FEIF2_Pos (16U)
  5832. #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
  5833. #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
  5834. #define DMA_LISR_TCIF1_Pos (11U)
  5835. #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
  5836. #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
  5837. #define DMA_LISR_HTIF1_Pos (10U)
  5838. #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
  5839. #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
  5840. #define DMA_LISR_TEIF1_Pos (9U)
  5841. #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
  5842. #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
  5843. #define DMA_LISR_DMEIF1_Pos (8U)
  5844. #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
  5845. #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
  5846. #define DMA_LISR_FEIF1_Pos (6U)
  5847. #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
  5848. #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
  5849. #define DMA_LISR_TCIF0_Pos (5U)
  5850. #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
  5851. #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
  5852. #define DMA_LISR_HTIF0_Pos (4U)
  5853. #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
  5854. #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
  5855. #define DMA_LISR_TEIF0_Pos (3U)
  5856. #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
  5857. #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
  5858. #define DMA_LISR_DMEIF0_Pos (2U)
  5859. #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
  5860. #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
  5861. #define DMA_LISR_FEIF0_Pos (0U)
  5862. #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
  5863. #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
  5864. /******************** Bits definition for DMA_HISR register *****************/
  5865. #define DMA_HISR_TCIF7_Pos (27U)
  5866. #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
  5867. #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
  5868. #define DMA_HISR_HTIF7_Pos (26U)
  5869. #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
  5870. #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
  5871. #define DMA_HISR_TEIF7_Pos (25U)
  5872. #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
  5873. #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
  5874. #define DMA_HISR_DMEIF7_Pos (24U)
  5875. #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
  5876. #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
  5877. #define DMA_HISR_FEIF7_Pos (22U)
  5878. #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
  5879. #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
  5880. #define DMA_HISR_TCIF6_Pos (21U)
  5881. #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
  5882. #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
  5883. #define DMA_HISR_HTIF6_Pos (20U)
  5884. #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
  5885. #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
  5886. #define DMA_HISR_TEIF6_Pos (19U)
  5887. #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
  5888. #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
  5889. #define DMA_HISR_DMEIF6_Pos (18U)
  5890. #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
  5891. #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
  5892. #define DMA_HISR_FEIF6_Pos (16U)
  5893. #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
  5894. #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
  5895. #define DMA_HISR_TCIF5_Pos (11U)
  5896. #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
  5897. #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
  5898. #define DMA_HISR_HTIF5_Pos (10U)
  5899. #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
  5900. #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
  5901. #define DMA_HISR_TEIF5_Pos (9U)
  5902. #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
  5903. #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
  5904. #define DMA_HISR_DMEIF5_Pos (8U)
  5905. #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
  5906. #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
  5907. #define DMA_HISR_FEIF5_Pos (6U)
  5908. #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
  5909. #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
  5910. #define DMA_HISR_TCIF4_Pos (5U)
  5911. #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
  5912. #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
  5913. #define DMA_HISR_HTIF4_Pos (4U)
  5914. #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
  5915. #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
  5916. #define DMA_HISR_TEIF4_Pos (3U)
  5917. #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
  5918. #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
  5919. #define DMA_HISR_DMEIF4_Pos (2U)
  5920. #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
  5921. #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
  5922. #define DMA_HISR_FEIF4_Pos (0U)
  5923. #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
  5924. #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
  5925. /******************** Bits definition for DMA_LIFCR register ****************/
  5926. #define DMA_LIFCR_CTCIF3_Pos (27U)
  5927. #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
  5928. #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
  5929. #define DMA_LIFCR_CHTIF3_Pos (26U)
  5930. #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
  5931. #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
  5932. #define DMA_LIFCR_CTEIF3_Pos (25U)
  5933. #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
  5934. #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
  5935. #define DMA_LIFCR_CDMEIF3_Pos (24U)
  5936. #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
  5937. #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
  5938. #define DMA_LIFCR_CFEIF3_Pos (22U)
  5939. #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
  5940. #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
  5941. #define DMA_LIFCR_CTCIF2_Pos (21U)
  5942. #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
  5943. #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
  5944. #define DMA_LIFCR_CHTIF2_Pos (20U)
  5945. #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
  5946. #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
  5947. #define DMA_LIFCR_CTEIF2_Pos (19U)
  5948. #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
  5949. #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
  5950. #define DMA_LIFCR_CDMEIF2_Pos (18U)
  5951. #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
  5952. #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
  5953. #define DMA_LIFCR_CFEIF2_Pos (16U)
  5954. #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
  5955. #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
  5956. #define DMA_LIFCR_CTCIF1_Pos (11U)
  5957. #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
  5958. #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
  5959. #define DMA_LIFCR_CHTIF1_Pos (10U)
  5960. #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
  5961. #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
  5962. #define DMA_LIFCR_CTEIF1_Pos (9U)
  5963. #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
  5964. #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
  5965. #define DMA_LIFCR_CDMEIF1_Pos (8U)
  5966. #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
  5967. #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
  5968. #define DMA_LIFCR_CFEIF1_Pos (6U)
  5969. #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
  5970. #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
  5971. #define DMA_LIFCR_CTCIF0_Pos (5U)
  5972. #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
  5973. #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
  5974. #define DMA_LIFCR_CHTIF0_Pos (4U)
  5975. #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
  5976. #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
  5977. #define DMA_LIFCR_CTEIF0_Pos (3U)
  5978. #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
  5979. #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
  5980. #define DMA_LIFCR_CDMEIF0_Pos (2U)
  5981. #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
  5982. #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
  5983. #define DMA_LIFCR_CFEIF0_Pos (0U)
  5984. #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
  5985. #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
  5986. /******************** Bits definition for DMA_HIFCR register ****************/
  5987. #define DMA_HIFCR_CTCIF7_Pos (27U)
  5988. #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
  5989. #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
  5990. #define DMA_HIFCR_CHTIF7_Pos (26U)
  5991. #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
  5992. #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
  5993. #define DMA_HIFCR_CTEIF7_Pos (25U)
  5994. #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
  5995. #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
  5996. #define DMA_HIFCR_CDMEIF7_Pos (24U)
  5997. #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
  5998. #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
  5999. #define DMA_HIFCR_CFEIF7_Pos (22U)
  6000. #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
  6001. #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
  6002. #define DMA_HIFCR_CTCIF6_Pos (21U)
  6003. #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
  6004. #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
  6005. #define DMA_HIFCR_CHTIF6_Pos (20U)
  6006. #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
  6007. #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
  6008. #define DMA_HIFCR_CTEIF6_Pos (19U)
  6009. #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
  6010. #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
  6011. #define DMA_HIFCR_CDMEIF6_Pos (18U)
  6012. #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
  6013. #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
  6014. #define DMA_HIFCR_CFEIF6_Pos (16U)
  6015. #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
  6016. #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
  6017. #define DMA_HIFCR_CTCIF5_Pos (11U)
  6018. #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
  6019. #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
  6020. #define DMA_HIFCR_CHTIF5_Pos (10U)
  6021. #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
  6022. #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
  6023. #define DMA_HIFCR_CTEIF5_Pos (9U)
  6024. #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
  6025. #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
  6026. #define DMA_HIFCR_CDMEIF5_Pos (8U)
  6027. #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
  6028. #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
  6029. #define DMA_HIFCR_CFEIF5_Pos (6U)
  6030. #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
  6031. #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
  6032. #define DMA_HIFCR_CTCIF4_Pos (5U)
  6033. #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
  6034. #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
  6035. #define DMA_HIFCR_CHTIF4_Pos (4U)
  6036. #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
  6037. #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
  6038. #define DMA_HIFCR_CTEIF4_Pos (3U)
  6039. #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
  6040. #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
  6041. #define DMA_HIFCR_CDMEIF4_Pos (2U)
  6042. #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
  6043. #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
  6044. #define DMA_HIFCR_CFEIF4_Pos (0U)
  6045. #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
  6046. #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
  6047. /****************** Bit definition for DMA_SxPAR register ********************/
  6048. #define DMA_SxPAR_PA_Pos (0U)
  6049. #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
  6050. #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
  6051. /****************** Bit definition for DMA_SxM0AR register ********************/
  6052. #define DMA_SxM0AR_M0A_Pos (0U)
  6053. #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
  6054. #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
  6055. /****************** Bit definition for DMA_SxM1AR register ********************/
  6056. #define DMA_SxM1AR_M1A_Pos (0U)
  6057. #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
  6058. #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
  6059. /******************************************************************************/
  6060. /* */
  6061. /* External Interrupt/Event Controller */
  6062. /* */
  6063. /******************************************************************************/
  6064. /******************* Bit definition for EXTI_IMR register *******************/
  6065. #define EXTI_IMR_MR0_Pos (0U)
  6066. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  6067. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  6068. #define EXTI_IMR_MR1_Pos (1U)
  6069. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  6070. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  6071. #define EXTI_IMR_MR2_Pos (2U)
  6072. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  6073. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  6074. #define EXTI_IMR_MR3_Pos (3U)
  6075. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  6076. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  6077. #define EXTI_IMR_MR4_Pos (4U)
  6078. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  6079. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  6080. #define EXTI_IMR_MR5_Pos (5U)
  6081. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  6082. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  6083. #define EXTI_IMR_MR6_Pos (6U)
  6084. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  6085. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  6086. #define EXTI_IMR_MR7_Pos (7U)
  6087. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  6088. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  6089. #define EXTI_IMR_MR8_Pos (8U)
  6090. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  6091. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  6092. #define EXTI_IMR_MR9_Pos (9U)
  6093. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  6094. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  6095. #define EXTI_IMR_MR10_Pos (10U)
  6096. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  6097. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  6098. #define EXTI_IMR_MR11_Pos (11U)
  6099. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  6100. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  6101. #define EXTI_IMR_MR12_Pos (12U)
  6102. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  6103. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  6104. #define EXTI_IMR_MR13_Pos (13U)
  6105. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  6106. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  6107. #define EXTI_IMR_MR14_Pos (14U)
  6108. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  6109. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  6110. #define EXTI_IMR_MR15_Pos (15U)
  6111. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  6112. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  6113. #define EXTI_IMR_MR16_Pos (16U)
  6114. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  6115. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  6116. #define EXTI_IMR_MR17_Pos (17U)
  6117. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  6118. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  6119. #define EXTI_IMR_MR18_Pos (18U)
  6120. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  6121. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  6122. #define EXTI_IMR_MR19_Pos (19U)
  6123. #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  6124. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  6125. #define EXTI_IMR_MR20_Pos (20U)
  6126. #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
  6127. #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
  6128. #define EXTI_IMR_MR21_Pos (21U)
  6129. #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
  6130. #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
  6131. #define EXTI_IMR_MR22_Pos (22U)
  6132. #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
  6133. #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
  6134. #define EXTI_IMR_MR23_Pos (23U)
  6135. #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
  6136. #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
  6137. /* Reference Defines */
  6138. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  6139. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  6140. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  6141. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  6142. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  6143. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  6144. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  6145. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  6146. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  6147. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  6148. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  6149. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  6150. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  6151. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  6152. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  6153. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  6154. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  6155. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  6156. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  6157. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  6158. #define EXTI_IMR_IM20 EXTI_IMR_MR20
  6159. #define EXTI_IMR_IM21 EXTI_IMR_MR21
  6160. #define EXTI_IMR_IM22 EXTI_IMR_MR22
  6161. #define EXTI_IMR_IM23 EXTI_IMR_MR23
  6162. #define EXTI_IMR_IM_Pos (0U)
  6163. #define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
  6164. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  6165. /******************* Bit definition for EXTI_EMR register *******************/
  6166. #define EXTI_EMR_MR0_Pos (0U)
  6167. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  6168. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  6169. #define EXTI_EMR_MR1_Pos (1U)
  6170. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  6171. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  6172. #define EXTI_EMR_MR2_Pos (2U)
  6173. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  6174. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  6175. #define EXTI_EMR_MR3_Pos (3U)
  6176. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  6177. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  6178. #define EXTI_EMR_MR4_Pos (4U)
  6179. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  6180. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  6181. #define EXTI_EMR_MR5_Pos (5U)
  6182. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  6183. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  6184. #define EXTI_EMR_MR6_Pos (6U)
  6185. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  6186. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  6187. #define EXTI_EMR_MR7_Pos (7U)
  6188. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  6189. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  6190. #define EXTI_EMR_MR8_Pos (8U)
  6191. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  6192. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  6193. #define EXTI_EMR_MR9_Pos (9U)
  6194. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  6195. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  6196. #define EXTI_EMR_MR10_Pos (10U)
  6197. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  6198. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  6199. #define EXTI_EMR_MR11_Pos (11U)
  6200. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  6201. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  6202. #define EXTI_EMR_MR12_Pos (12U)
  6203. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  6204. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  6205. #define EXTI_EMR_MR13_Pos (13U)
  6206. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  6207. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  6208. #define EXTI_EMR_MR14_Pos (14U)
  6209. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  6210. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  6211. #define EXTI_EMR_MR15_Pos (15U)
  6212. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  6213. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  6214. #define EXTI_EMR_MR16_Pos (16U)
  6215. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  6216. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  6217. #define EXTI_EMR_MR17_Pos (17U)
  6218. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  6219. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  6220. #define EXTI_EMR_MR18_Pos (18U)
  6221. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  6222. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  6223. #define EXTI_EMR_MR19_Pos (19U)
  6224. #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  6225. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  6226. #define EXTI_EMR_MR20_Pos (20U)
  6227. #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
  6228. #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
  6229. #define EXTI_EMR_MR21_Pos (21U)
  6230. #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
  6231. #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
  6232. #define EXTI_EMR_MR22_Pos (22U)
  6233. #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
  6234. #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
  6235. #define EXTI_EMR_MR23_Pos (23U)
  6236. #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
  6237. #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
  6238. /* Reference Defines */
  6239. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  6240. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  6241. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  6242. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  6243. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  6244. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  6245. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  6246. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  6247. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  6248. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  6249. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  6250. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  6251. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  6252. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  6253. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  6254. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  6255. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  6256. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  6257. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  6258. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  6259. #define EXTI_EMR_EM20 EXTI_EMR_MR20
  6260. #define EXTI_EMR_EM21 EXTI_EMR_MR21
  6261. #define EXTI_EMR_EM22 EXTI_EMR_MR22
  6262. #define EXTI_EMR_EM23 EXTI_EMR_MR23
  6263. /****************** Bit definition for EXTI_RTSR register *******************/
  6264. #define EXTI_RTSR_TR0_Pos (0U)
  6265. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  6266. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  6267. #define EXTI_RTSR_TR1_Pos (1U)
  6268. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  6269. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  6270. #define EXTI_RTSR_TR2_Pos (2U)
  6271. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  6272. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  6273. #define EXTI_RTSR_TR3_Pos (3U)
  6274. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  6275. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  6276. #define EXTI_RTSR_TR4_Pos (4U)
  6277. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  6278. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  6279. #define EXTI_RTSR_TR5_Pos (5U)
  6280. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  6281. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  6282. #define EXTI_RTSR_TR6_Pos (6U)
  6283. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  6284. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  6285. #define EXTI_RTSR_TR7_Pos (7U)
  6286. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  6287. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  6288. #define EXTI_RTSR_TR8_Pos (8U)
  6289. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  6290. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  6291. #define EXTI_RTSR_TR9_Pos (9U)
  6292. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  6293. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  6294. #define EXTI_RTSR_TR10_Pos (10U)
  6295. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  6296. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  6297. #define EXTI_RTSR_TR11_Pos (11U)
  6298. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  6299. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  6300. #define EXTI_RTSR_TR12_Pos (12U)
  6301. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  6302. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  6303. #define EXTI_RTSR_TR13_Pos (13U)
  6304. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  6305. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  6306. #define EXTI_RTSR_TR14_Pos (14U)
  6307. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  6308. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  6309. #define EXTI_RTSR_TR15_Pos (15U)
  6310. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  6311. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  6312. #define EXTI_RTSR_TR16_Pos (16U)
  6313. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  6314. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  6315. #define EXTI_RTSR_TR17_Pos (17U)
  6316. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  6317. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  6318. #define EXTI_RTSR_TR18_Pos (18U)
  6319. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  6320. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  6321. #define EXTI_RTSR_TR19_Pos (19U)
  6322. #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  6323. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  6324. #define EXTI_RTSR_TR20_Pos (20U)
  6325. #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
  6326. #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
  6327. #define EXTI_RTSR_TR21_Pos (21U)
  6328. #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
  6329. #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
  6330. #define EXTI_RTSR_TR22_Pos (22U)
  6331. #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
  6332. #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
  6333. #define EXTI_RTSR_TR23_Pos (23U)
  6334. #define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
  6335. #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
  6336. /****************** Bit definition for EXTI_FTSR register *******************/
  6337. #define EXTI_FTSR_TR0_Pos (0U)
  6338. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  6339. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  6340. #define EXTI_FTSR_TR1_Pos (1U)
  6341. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  6342. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  6343. #define EXTI_FTSR_TR2_Pos (2U)
  6344. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  6345. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  6346. #define EXTI_FTSR_TR3_Pos (3U)
  6347. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  6348. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  6349. #define EXTI_FTSR_TR4_Pos (4U)
  6350. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  6351. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  6352. #define EXTI_FTSR_TR5_Pos (5U)
  6353. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  6354. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  6355. #define EXTI_FTSR_TR6_Pos (6U)
  6356. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  6357. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  6358. #define EXTI_FTSR_TR7_Pos (7U)
  6359. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  6360. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  6361. #define EXTI_FTSR_TR8_Pos (8U)
  6362. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  6363. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  6364. #define EXTI_FTSR_TR9_Pos (9U)
  6365. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  6366. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  6367. #define EXTI_FTSR_TR10_Pos (10U)
  6368. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  6369. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  6370. #define EXTI_FTSR_TR11_Pos (11U)
  6371. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  6372. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  6373. #define EXTI_FTSR_TR12_Pos (12U)
  6374. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  6375. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  6376. #define EXTI_FTSR_TR13_Pos (13U)
  6377. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  6378. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  6379. #define EXTI_FTSR_TR14_Pos (14U)
  6380. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  6381. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  6382. #define EXTI_FTSR_TR15_Pos (15U)
  6383. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  6384. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  6385. #define EXTI_FTSR_TR16_Pos (16U)
  6386. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  6387. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  6388. #define EXTI_FTSR_TR17_Pos (17U)
  6389. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  6390. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  6391. #define EXTI_FTSR_TR18_Pos (18U)
  6392. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  6393. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  6394. #define EXTI_FTSR_TR19_Pos (19U)
  6395. #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  6396. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  6397. #define EXTI_FTSR_TR20_Pos (20U)
  6398. #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
  6399. #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
  6400. #define EXTI_FTSR_TR21_Pos (21U)
  6401. #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
  6402. #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
  6403. #define EXTI_FTSR_TR22_Pos (22U)
  6404. #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
  6405. #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
  6406. #define EXTI_FTSR_TR23_Pos (23U)
  6407. #define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
  6408. #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
  6409. /****************** Bit definition for EXTI_SWIER register ******************/
  6410. #define EXTI_SWIER_SWIER0_Pos (0U)
  6411. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  6412. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  6413. #define EXTI_SWIER_SWIER1_Pos (1U)
  6414. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  6415. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  6416. #define EXTI_SWIER_SWIER2_Pos (2U)
  6417. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  6418. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  6419. #define EXTI_SWIER_SWIER3_Pos (3U)
  6420. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  6421. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  6422. #define EXTI_SWIER_SWIER4_Pos (4U)
  6423. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  6424. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  6425. #define EXTI_SWIER_SWIER5_Pos (5U)
  6426. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  6427. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  6428. #define EXTI_SWIER_SWIER6_Pos (6U)
  6429. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  6430. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  6431. #define EXTI_SWIER_SWIER7_Pos (7U)
  6432. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  6433. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  6434. #define EXTI_SWIER_SWIER8_Pos (8U)
  6435. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  6436. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  6437. #define EXTI_SWIER_SWIER9_Pos (9U)
  6438. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  6439. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  6440. #define EXTI_SWIER_SWIER10_Pos (10U)
  6441. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  6442. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  6443. #define EXTI_SWIER_SWIER11_Pos (11U)
  6444. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  6445. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  6446. #define EXTI_SWIER_SWIER12_Pos (12U)
  6447. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  6448. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  6449. #define EXTI_SWIER_SWIER13_Pos (13U)
  6450. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  6451. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  6452. #define EXTI_SWIER_SWIER14_Pos (14U)
  6453. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  6454. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  6455. #define EXTI_SWIER_SWIER15_Pos (15U)
  6456. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  6457. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  6458. #define EXTI_SWIER_SWIER16_Pos (16U)
  6459. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  6460. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  6461. #define EXTI_SWIER_SWIER17_Pos (17U)
  6462. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  6463. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  6464. #define EXTI_SWIER_SWIER18_Pos (18U)
  6465. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  6466. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  6467. #define EXTI_SWIER_SWIER19_Pos (19U)
  6468. #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  6469. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  6470. #define EXTI_SWIER_SWIER20_Pos (20U)
  6471. #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
  6472. #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
  6473. #define EXTI_SWIER_SWIER21_Pos (21U)
  6474. #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
  6475. #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
  6476. #define EXTI_SWIER_SWIER22_Pos (22U)
  6477. #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
  6478. #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
  6479. #define EXTI_SWIER_SWIER23_Pos (23U)
  6480. #define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
  6481. #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
  6482. /******************* Bit definition for EXTI_PR register ********************/
  6483. #define EXTI_PR_PR0_Pos (0U)
  6484. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  6485. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  6486. #define EXTI_PR_PR1_Pos (1U)
  6487. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  6488. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  6489. #define EXTI_PR_PR2_Pos (2U)
  6490. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  6491. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  6492. #define EXTI_PR_PR3_Pos (3U)
  6493. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  6494. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  6495. #define EXTI_PR_PR4_Pos (4U)
  6496. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  6497. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  6498. #define EXTI_PR_PR5_Pos (5U)
  6499. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  6500. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  6501. #define EXTI_PR_PR6_Pos (6U)
  6502. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  6503. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  6504. #define EXTI_PR_PR7_Pos (7U)
  6505. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  6506. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  6507. #define EXTI_PR_PR8_Pos (8U)
  6508. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  6509. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  6510. #define EXTI_PR_PR9_Pos (9U)
  6511. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  6512. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  6513. #define EXTI_PR_PR10_Pos (10U)
  6514. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  6515. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  6516. #define EXTI_PR_PR11_Pos (11U)
  6517. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  6518. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  6519. #define EXTI_PR_PR12_Pos (12U)
  6520. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  6521. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  6522. #define EXTI_PR_PR13_Pos (13U)
  6523. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  6524. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  6525. #define EXTI_PR_PR14_Pos (14U)
  6526. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  6527. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  6528. #define EXTI_PR_PR15_Pos (15U)
  6529. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  6530. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  6531. #define EXTI_PR_PR16_Pos (16U)
  6532. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  6533. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  6534. #define EXTI_PR_PR17_Pos (17U)
  6535. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  6536. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  6537. #define EXTI_PR_PR18_Pos (18U)
  6538. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  6539. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  6540. #define EXTI_PR_PR19_Pos (19U)
  6541. #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  6542. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
  6543. #define EXTI_PR_PR20_Pos (20U)
  6544. #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
  6545. #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
  6546. #define EXTI_PR_PR21_Pos (21U)
  6547. #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
  6548. #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
  6549. #define EXTI_PR_PR22_Pos (22U)
  6550. #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
  6551. #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
  6552. #define EXTI_PR_PR23_Pos (23U)
  6553. #define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
  6554. #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
  6555. /******************************************************************************/
  6556. /* */
  6557. /* FLASH */
  6558. /* */
  6559. /******************************************************************************/
  6560. /******************* Bits definition for FLASH_ACR register *****************/
  6561. #define FLASH_ACR_LATENCY_Pos (0U)
  6562. #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
  6563. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  6564. #define FLASH_ACR_LATENCY_0WS 0x00000000U
  6565. #define FLASH_ACR_LATENCY_1WS 0x00000001U
  6566. #define FLASH_ACR_LATENCY_2WS 0x00000002U
  6567. #define FLASH_ACR_LATENCY_3WS 0x00000003U
  6568. #define FLASH_ACR_LATENCY_4WS 0x00000004U
  6569. #define FLASH_ACR_LATENCY_5WS 0x00000005U
  6570. #define FLASH_ACR_LATENCY_6WS 0x00000006U
  6571. #define FLASH_ACR_LATENCY_7WS 0x00000007U
  6572. #define FLASH_ACR_PRFTEN_Pos (8U)
  6573. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  6574. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  6575. #define FLASH_ACR_ICEN_Pos (9U)
  6576. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  6577. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  6578. #define FLASH_ACR_DCEN_Pos (10U)
  6579. #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  6580. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  6581. #define FLASH_ACR_ICRST_Pos (11U)
  6582. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  6583. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  6584. #define FLASH_ACR_DCRST_Pos (12U)
  6585. #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  6586. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  6587. #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
  6588. #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
  6589. #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
  6590. #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
  6591. #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
  6592. #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
  6593. /******************* Bits definition for FLASH_SR register ******************/
  6594. #define FLASH_SR_EOP_Pos (0U)
  6595. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  6596. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  6597. #define FLASH_SR_SOP_Pos (1U)
  6598. #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
  6599. #define FLASH_SR_SOP FLASH_SR_SOP_Msk
  6600. #define FLASH_SR_WRPERR_Pos (4U)
  6601. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  6602. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  6603. #define FLASH_SR_PGAERR_Pos (5U)
  6604. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  6605. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  6606. #define FLASH_SR_PGPERR_Pos (6U)
  6607. #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
  6608. #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
  6609. #define FLASH_SR_PGSERR_Pos (7U)
  6610. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  6611. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  6612. #define FLASH_SR_RDERR_Pos (8U)
  6613. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
  6614. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  6615. #define FLASH_SR_BSY_Pos (16U)
  6616. #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  6617. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  6618. /******************* Bits definition for FLASH_CR register ******************/
  6619. #define FLASH_CR_PG_Pos (0U)
  6620. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  6621. #define FLASH_CR_PG FLASH_CR_PG_Msk
  6622. #define FLASH_CR_SER_Pos (1U)
  6623. #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
  6624. #define FLASH_CR_SER FLASH_CR_SER_Msk
  6625. #define FLASH_CR_MER_Pos (2U)
  6626. #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  6627. #define FLASH_CR_MER FLASH_CR_MER_Msk
  6628. #define FLASH_CR_SNB_Pos (3U)
  6629. #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
  6630. #define FLASH_CR_SNB FLASH_CR_SNB_Msk
  6631. #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
  6632. #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
  6633. #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
  6634. #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
  6635. #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
  6636. #define FLASH_CR_PSIZE_Pos (8U)
  6637. #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
  6638. #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
  6639. #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
  6640. #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
  6641. #define FLASH_CR_STRT_Pos (16U)
  6642. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  6643. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  6644. #define FLASH_CR_EOPIE_Pos (24U)
  6645. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  6646. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  6647. #define FLASH_CR_LOCK_Pos (31U)
  6648. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  6649. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  6650. /******************* Bits definition for FLASH_OPTCR register ***************/
  6651. #define FLASH_OPTCR_OPTLOCK_Pos (0U)
  6652. #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
  6653. #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
  6654. #define FLASH_OPTCR_OPTSTRT_Pos (1U)
  6655. #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
  6656. #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
  6657. #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
  6658. #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
  6659. #define FLASH_OPTCR_BOR_LEV_Pos (2U)
  6660. #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
  6661. #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
  6662. #define FLASH_OPTCR_WDG_SW_Pos (5U)
  6663. #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
  6664. #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
  6665. #define FLASH_OPTCR_nRST_STOP_Pos (6U)
  6666. #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
  6667. #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
  6668. #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
  6669. #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
  6670. #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
  6671. #define FLASH_OPTCR_RDP_Pos (8U)
  6672. #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
  6673. #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
  6674. #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
  6675. #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
  6676. #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
  6677. #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
  6678. #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
  6679. #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
  6680. #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
  6681. #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
  6682. #define FLASH_OPTCR_nWRP_Pos (16U)
  6683. #define FLASH_OPTCR_nWRP_Msk (0x7FFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x7FFF0000 */
  6684. #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
  6685. #define FLASH_OPTCR_nWRP_0 0x00010000U
  6686. #define FLASH_OPTCR_nWRP_1 0x00020000U
  6687. #define FLASH_OPTCR_nWRP_2 0x00040000U
  6688. #define FLASH_OPTCR_nWRP_3 0x00080000U
  6689. #define FLASH_OPTCR_nWRP_4 0x00100000U
  6690. #define FLASH_OPTCR_nWRP_5 0x00200000U
  6691. #define FLASH_OPTCR_nWRP_6 0x00400000U
  6692. #define FLASH_OPTCR_nWRP_7 0x00800000U
  6693. #define FLASH_OPTCR_nWRP_8 0x01000000U
  6694. #define FLASH_OPTCR_nWRP_9 0x02000000U
  6695. #define FLASH_OPTCR_nWRP_10 0x04000000U
  6696. #define FLASH_OPTCR_nWRP_11 0x08000000U
  6697. #define FLASH_OPTCR_nWRP_12 0x10000000U
  6698. #define FLASH_OPTCR_nWRP_13 0x20000000U
  6699. #define FLASH_OPTCR_nWRP_14 0x40000000U
  6700. #define FLASH_OPTCR_nWRP_15 0x40000000U
  6701. /****************** Bits definition for FLASH_OPTCR1 register ***************/
  6702. #define FLASH_OPTCR1_nWRP_Pos (16U)
  6703. #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
  6704. #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
  6705. #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
  6706. #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
  6707. #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
  6708. #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
  6709. #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
  6710. #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
  6711. #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
  6712. #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
  6713. #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
  6714. #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
  6715. #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
  6716. #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
  6717. /******************************************************************************/
  6718. /* */
  6719. /* Flexible Static Memory Controller */
  6720. /* */
  6721. /******************************************************************************/
  6722. /****************** Bit definition for FSMC_BCR1 register *******************/
  6723. #define FSMC_BCR1_MBKEN_Pos (0U)
  6724. #define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
  6725. #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
  6726. #define FSMC_BCR1_MUXEN_Pos (1U)
  6727. #define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
  6728. #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6729. #define FSMC_BCR1_MTYP_Pos (2U)
  6730. #define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
  6731. #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6732. #define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
  6733. #define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
  6734. #define FSMC_BCR1_MWID_Pos (4U)
  6735. #define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
  6736. #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  6737. #define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
  6738. #define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
  6739. #define FSMC_BCR1_FACCEN_Pos (6U)
  6740. #define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
  6741. #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
  6742. #define FSMC_BCR1_BURSTEN_Pos (8U)
  6743. #define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
  6744. #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
  6745. #define FSMC_BCR1_WAITPOL_Pos (9U)
  6746. #define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
  6747. #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
  6748. #define FSMC_BCR1_WAITCFG_Pos (11U)
  6749. #define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
  6750. #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
  6751. #define FSMC_BCR1_WREN_Pos (12U)
  6752. #define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
  6753. #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
  6754. #define FSMC_BCR1_WAITEN_Pos (13U)
  6755. #define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
  6756. #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
  6757. #define FSMC_BCR1_EXTMOD_Pos (14U)
  6758. #define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
  6759. #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
  6760. #define FSMC_BCR1_ASYNCWAIT_Pos (15U)
  6761. #define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
  6762. #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
  6763. #define FSMC_BCR1_CPSIZE_Pos (16U)
  6764. #define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
  6765. #define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
  6766. #define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
  6767. #define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
  6768. #define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
  6769. #define FSMC_BCR1_CBURSTRW_Pos (19U)
  6770. #define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
  6771. #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
  6772. #define FSMC_BCR1_CCLKEN_Pos (20U)
  6773. #define FSMC_BCR1_CCLKEN_Msk (0x1UL << FSMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
  6774. #define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
  6775. #define FSMC_BCR1_WFDIS_Pos (21U)
  6776. #define FSMC_BCR1_WFDIS_Msk (0x1UL << FSMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
  6777. #define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
  6778. /****************** Bit definition for FSMC_BCR2 register *******************/
  6779. #define FSMC_BCR2_MBKEN_Pos (0U)
  6780. #define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
  6781. #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
  6782. #define FSMC_BCR2_MUXEN_Pos (1U)
  6783. #define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
  6784. #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6785. #define FSMC_BCR2_MTYP_Pos (2U)
  6786. #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
  6787. #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6788. #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
  6789. #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
  6790. #define FSMC_BCR2_MWID_Pos (4U)
  6791. #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
  6792. #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  6793. #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
  6794. #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
  6795. #define FSMC_BCR2_FACCEN_Pos (6U)
  6796. #define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
  6797. #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
  6798. #define FSMC_BCR2_BURSTEN_Pos (8U)
  6799. #define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
  6800. #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
  6801. #define FSMC_BCR2_WAITPOL_Pos (9U)
  6802. #define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
  6803. #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
  6804. #define FSMC_BCR2_WAITCFG_Pos (11U)
  6805. #define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
  6806. #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
  6807. #define FSMC_BCR2_WREN_Pos (12U)
  6808. #define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
  6809. #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
  6810. #define FSMC_BCR2_WAITEN_Pos (13U)
  6811. #define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
  6812. #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
  6813. #define FSMC_BCR2_EXTMOD_Pos (14U)
  6814. #define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
  6815. #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
  6816. #define FSMC_BCR2_ASYNCWAIT_Pos (15U)
  6817. #define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
  6818. #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
  6819. #define FSMC_BCR2_CPSIZE_Pos (16U)
  6820. #define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
  6821. #define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
  6822. #define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
  6823. #define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
  6824. #define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
  6825. #define FSMC_BCR2_CBURSTRW_Pos (19U)
  6826. #define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
  6827. #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
  6828. /****************** Bit definition for FSMC_BCR3 register *******************/
  6829. #define FSMC_BCR3_MBKEN_Pos (0U)
  6830. #define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
  6831. #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
  6832. #define FSMC_BCR3_MUXEN_Pos (1U)
  6833. #define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
  6834. #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6835. #define FSMC_BCR3_MTYP_Pos (2U)
  6836. #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
  6837. #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6838. #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
  6839. #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
  6840. #define FSMC_BCR3_MWID_Pos (4U)
  6841. #define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
  6842. #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  6843. #define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
  6844. #define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
  6845. #define FSMC_BCR3_FACCEN_Pos (6U)
  6846. #define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
  6847. #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
  6848. #define FSMC_BCR3_BURSTEN_Pos (8U)
  6849. #define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
  6850. #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
  6851. #define FSMC_BCR3_WAITPOL_Pos (9U)
  6852. #define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
  6853. #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
  6854. #define FSMC_BCR3_WAITCFG_Pos (11U)
  6855. #define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
  6856. #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
  6857. #define FSMC_BCR3_WREN_Pos (12U)
  6858. #define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
  6859. #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
  6860. #define FSMC_BCR3_WAITEN_Pos (13U)
  6861. #define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
  6862. #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
  6863. #define FSMC_BCR3_EXTMOD_Pos (14U)
  6864. #define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
  6865. #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
  6866. #define FSMC_BCR3_ASYNCWAIT_Pos (15U)
  6867. #define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
  6868. #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
  6869. #define FSMC_BCR3_CPSIZE_Pos (16U)
  6870. #define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
  6871. #define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
  6872. #define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
  6873. #define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
  6874. #define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
  6875. #define FSMC_BCR3_CBURSTRW_Pos (19U)
  6876. #define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
  6877. #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
  6878. /****************** Bit definition for FSMC_BCR4 register *******************/
  6879. #define FSMC_BCR4_MBKEN_Pos (0U)
  6880. #define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
  6881. #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
  6882. #define FSMC_BCR4_MUXEN_Pos (1U)
  6883. #define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
  6884. #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6885. #define FSMC_BCR4_MTYP_Pos (2U)
  6886. #define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
  6887. #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6888. #define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
  6889. #define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
  6890. #define FSMC_BCR4_MWID_Pos (4U)
  6891. #define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
  6892. #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  6893. #define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
  6894. #define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
  6895. #define FSMC_BCR4_FACCEN_Pos (6U)
  6896. #define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
  6897. #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
  6898. #define FSMC_BCR4_BURSTEN_Pos (8U)
  6899. #define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
  6900. #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
  6901. #define FSMC_BCR4_WAITPOL_Pos (9U)
  6902. #define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
  6903. #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
  6904. #define FSMC_BCR4_WAITCFG_Pos (11U)
  6905. #define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
  6906. #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
  6907. #define FSMC_BCR4_WREN_Pos (12U)
  6908. #define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
  6909. #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
  6910. #define FSMC_BCR4_WAITEN_Pos (13U)
  6911. #define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
  6912. #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
  6913. #define FSMC_BCR4_EXTMOD_Pos (14U)
  6914. #define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
  6915. #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
  6916. #define FSMC_BCR4_ASYNCWAIT_Pos (15U)
  6917. #define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
  6918. #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
  6919. #define FSMC_BCR4_CPSIZE_Pos (16U)
  6920. #define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
  6921. #define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
  6922. #define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
  6923. #define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
  6924. #define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
  6925. #define FSMC_BCR4_CBURSTRW_Pos (19U)
  6926. #define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
  6927. #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
  6928. /****************** Bit definition for FSMC_BTR1 register ******************/
  6929. #define FSMC_BTR1_ADDSET_Pos (0U)
  6930. #define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
  6931. #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  6932. #define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
  6933. #define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
  6934. #define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
  6935. #define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
  6936. #define FSMC_BTR1_ADDHLD_Pos (4U)
  6937. #define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  6938. #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  6939. #define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
  6940. #define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
  6941. #define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
  6942. #define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
  6943. #define FSMC_BTR1_DATAST_Pos (8U)
  6944. #define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
  6945. #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  6946. #define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
  6947. #define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
  6948. #define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
  6949. #define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
  6950. #define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
  6951. #define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
  6952. #define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
  6953. #define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
  6954. #define FSMC_BTR1_BUSTURN_Pos (16U)
  6955. #define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  6956. #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  6957. #define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
  6958. #define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
  6959. #define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
  6960. #define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
  6961. #define FSMC_BTR1_CLKDIV_Pos (20U)
  6962. #define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
  6963. #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  6964. #define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
  6965. #define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
  6966. #define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
  6967. #define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
  6968. #define FSMC_BTR1_DATLAT_Pos (24U)
  6969. #define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
  6970. #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  6971. #define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
  6972. #define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
  6973. #define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
  6974. #define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
  6975. #define FSMC_BTR1_ACCMOD_Pos (28U)
  6976. #define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
  6977. #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  6978. #define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
  6979. #define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
  6980. /****************** Bit definition for FSMC_BTR2 register *******************/
  6981. #define FSMC_BTR2_ADDSET_Pos (0U)
  6982. #define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
  6983. #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  6984. #define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
  6985. #define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
  6986. #define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
  6987. #define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
  6988. #define FSMC_BTR2_ADDHLD_Pos (4U)
  6989. #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  6990. #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  6991. #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
  6992. #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
  6993. #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
  6994. #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
  6995. #define FSMC_BTR2_DATAST_Pos (8U)
  6996. #define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
  6997. #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  6998. #define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
  6999. #define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
  7000. #define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
  7001. #define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
  7002. #define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
  7003. #define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
  7004. #define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
  7005. #define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
  7006. #define FSMC_BTR2_BUSTURN_Pos (16U)
  7007. #define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  7008. #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7009. #define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
  7010. #define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
  7011. #define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
  7012. #define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
  7013. #define FSMC_BTR2_CLKDIV_Pos (20U)
  7014. #define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
  7015. #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7016. #define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
  7017. #define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
  7018. #define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
  7019. #define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
  7020. #define FSMC_BTR2_DATLAT_Pos (24U)
  7021. #define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
  7022. #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7023. #define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
  7024. #define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
  7025. #define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
  7026. #define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
  7027. #define FSMC_BTR2_ACCMOD_Pos (28U)
  7028. #define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
  7029. #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7030. #define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
  7031. #define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
  7032. /******************* Bit definition for FSMC_BTR3 register *******************/
  7033. #define FSMC_BTR3_ADDSET_Pos (0U)
  7034. #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
  7035. #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7036. #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
  7037. #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
  7038. #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
  7039. #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
  7040. #define FSMC_BTR3_ADDHLD_Pos (4U)
  7041. #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  7042. #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7043. #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
  7044. #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
  7045. #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
  7046. #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
  7047. #define FSMC_BTR3_DATAST_Pos (8U)
  7048. #define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
  7049. #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  7050. #define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
  7051. #define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
  7052. #define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
  7053. #define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
  7054. #define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
  7055. #define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
  7056. #define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
  7057. #define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
  7058. #define FSMC_BTR3_BUSTURN_Pos (16U)
  7059. #define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  7060. #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7061. #define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
  7062. #define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
  7063. #define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
  7064. #define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
  7065. #define FSMC_BTR3_CLKDIV_Pos (20U)
  7066. #define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
  7067. #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7068. #define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
  7069. #define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
  7070. #define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
  7071. #define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
  7072. #define FSMC_BTR3_DATLAT_Pos (24U)
  7073. #define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
  7074. #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7075. #define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
  7076. #define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
  7077. #define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
  7078. #define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
  7079. #define FSMC_BTR3_ACCMOD_Pos (28U)
  7080. #define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
  7081. #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7082. #define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
  7083. #define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
  7084. /****************** Bit definition for FSMC_BTR4 register *******************/
  7085. #define FSMC_BTR4_ADDSET_Pos (0U)
  7086. #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
  7087. #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7088. #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
  7089. #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
  7090. #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
  7091. #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
  7092. #define FSMC_BTR4_ADDHLD_Pos (4U)
  7093. #define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  7094. #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7095. #define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
  7096. #define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
  7097. #define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
  7098. #define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
  7099. #define FSMC_BTR4_DATAST_Pos (8U)
  7100. #define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
  7101. #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  7102. #define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
  7103. #define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
  7104. #define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
  7105. #define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
  7106. #define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
  7107. #define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
  7108. #define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
  7109. #define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
  7110. #define FSMC_BTR4_BUSTURN_Pos (16U)
  7111. #define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  7112. #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7113. #define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
  7114. #define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
  7115. #define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
  7116. #define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
  7117. #define FSMC_BTR4_CLKDIV_Pos (20U)
  7118. #define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
  7119. #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7120. #define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
  7121. #define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
  7122. #define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
  7123. #define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
  7124. #define FSMC_BTR4_DATLAT_Pos (24U)
  7125. #define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
  7126. #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7127. #define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
  7128. #define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
  7129. #define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
  7130. #define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
  7131. #define FSMC_BTR4_ACCMOD_Pos (28U)
  7132. #define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
  7133. #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7134. #define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
  7135. #define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
  7136. /****************** Bit definition for FSMC_BWTR1 register ******************/
  7137. #define FSMC_BWTR1_ADDSET_Pos (0U)
  7138. #define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
  7139. #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7140. #define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
  7141. #define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
  7142. #define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
  7143. #define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
  7144. #define FSMC_BWTR1_ADDHLD_Pos (4U)
  7145. #define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  7146. #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7147. #define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
  7148. #define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
  7149. #define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
  7150. #define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
  7151. #define FSMC_BWTR1_DATAST_Pos (8U)
  7152. #define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
  7153. #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  7154. #define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
  7155. #define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
  7156. #define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
  7157. #define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
  7158. #define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
  7159. #define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
  7160. #define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
  7161. #define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
  7162. #define FSMC_BWTR1_BUSTURN_Pos (16U)
  7163. #define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  7164. #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7165. #define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
  7166. #define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
  7167. #define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
  7168. #define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
  7169. #define FSMC_BWTR1_ACCMOD_Pos (28U)
  7170. #define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
  7171. #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7172. #define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
  7173. #define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
  7174. /****************** Bit definition for FSMC_BWTR2 register ******************/
  7175. #define FSMC_BWTR2_ADDSET_Pos (0U)
  7176. #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
  7177. #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7178. #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
  7179. #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
  7180. #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
  7181. #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
  7182. #define FSMC_BWTR2_ADDHLD_Pos (4U)
  7183. #define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  7184. #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7185. #define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
  7186. #define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
  7187. #define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
  7188. #define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
  7189. #define FSMC_BWTR2_DATAST_Pos (8U)
  7190. #define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
  7191. #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  7192. #define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
  7193. #define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
  7194. #define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
  7195. #define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
  7196. #define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
  7197. #define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
  7198. #define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
  7199. #define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
  7200. #define FSMC_BWTR2_BUSTURN_Pos (16U)
  7201. #define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  7202. #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7203. #define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
  7204. #define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
  7205. #define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
  7206. #define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
  7207. #define FSMC_BWTR2_ACCMOD_Pos (28U)
  7208. #define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
  7209. #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7210. #define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
  7211. #define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
  7212. /****************** Bit definition for FSMC_BWTR3 register ******************/
  7213. #define FSMC_BWTR3_ADDSET_Pos (0U)
  7214. #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
  7215. #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7216. #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
  7217. #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
  7218. #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
  7219. #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
  7220. #define FSMC_BWTR3_ADDHLD_Pos (4U)
  7221. #define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  7222. #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7223. #define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
  7224. #define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
  7225. #define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
  7226. #define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
  7227. #define FSMC_BWTR3_DATAST_Pos (8U)
  7228. #define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
  7229. #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
  7230. #define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
  7231. #define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
  7232. #define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
  7233. #define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
  7234. #define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
  7235. #define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
  7236. #define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
  7237. #define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
  7238. #define FSMC_BWTR3_BUSTURN_Pos (16U)
  7239. #define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  7240. #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7241. #define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
  7242. #define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
  7243. #define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
  7244. #define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
  7245. #define FSMC_BWTR3_ACCMOD_Pos (28U)
  7246. #define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
  7247. #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7248. #define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
  7249. #define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
  7250. /****************** Bit definition for FSMC_BWTR4 register ******************/
  7251. #define FSMC_BWTR4_ADDSET_Pos (0U)
  7252. #define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
  7253. #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7254. #define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
  7255. #define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
  7256. #define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
  7257. #define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
  7258. #define FSMC_BWTR4_ADDHLD_Pos (4U)
  7259. #define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  7260. #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7261. #define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
  7262. #define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
  7263. #define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
  7264. #define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
  7265. #define FSMC_BWTR4_DATAST_Pos (8U)
  7266. #define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
  7267. #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7268. #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
  7269. #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
  7270. #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
  7271. #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
  7272. #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
  7273. #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
  7274. #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
  7275. #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
  7276. #define FSMC_BWTR4_BUSTURN_Pos (16U)
  7277. #define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  7278. #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7279. #define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
  7280. #define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
  7281. #define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
  7282. #define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
  7283. #define FSMC_BWTR4_ACCMOD_Pos (28U)
  7284. #define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
  7285. #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7286. #define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
  7287. #define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
  7288. /******************************************************************************/
  7289. /* */
  7290. /* General Purpose I/O */
  7291. /* */
  7292. /******************************************************************************/
  7293. /****************** Bits definition for GPIO_MODER register *****************/
  7294. #define GPIO_MODER_MODER0_Pos (0U)
  7295. #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  7296. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  7297. #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  7298. #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  7299. #define GPIO_MODER_MODER1_Pos (2U)
  7300. #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  7301. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  7302. #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  7303. #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  7304. #define GPIO_MODER_MODER2_Pos (4U)
  7305. #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  7306. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  7307. #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  7308. #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  7309. #define GPIO_MODER_MODER3_Pos (6U)
  7310. #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  7311. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  7312. #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  7313. #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  7314. #define GPIO_MODER_MODER4_Pos (8U)
  7315. #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  7316. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  7317. #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  7318. #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  7319. #define GPIO_MODER_MODER5_Pos (10U)
  7320. #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  7321. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  7322. #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  7323. #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  7324. #define GPIO_MODER_MODER6_Pos (12U)
  7325. #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  7326. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  7327. #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  7328. #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  7329. #define GPIO_MODER_MODER7_Pos (14U)
  7330. #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  7331. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  7332. #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  7333. #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  7334. #define GPIO_MODER_MODER8_Pos (16U)
  7335. #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  7336. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  7337. #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  7338. #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  7339. #define GPIO_MODER_MODER9_Pos (18U)
  7340. #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  7341. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  7342. #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  7343. #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  7344. #define GPIO_MODER_MODER10_Pos (20U)
  7345. #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  7346. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  7347. #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  7348. #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  7349. #define GPIO_MODER_MODER11_Pos (22U)
  7350. #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  7351. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  7352. #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  7353. #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  7354. #define GPIO_MODER_MODER12_Pos (24U)
  7355. #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  7356. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  7357. #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  7358. #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  7359. #define GPIO_MODER_MODER13_Pos (26U)
  7360. #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  7361. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  7362. #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  7363. #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  7364. #define GPIO_MODER_MODER14_Pos (28U)
  7365. #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  7366. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  7367. #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  7368. #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  7369. #define GPIO_MODER_MODER15_Pos (30U)
  7370. #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  7371. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  7372. #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  7373. #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  7374. /****************** Bits definition for GPIO_OTYPER register ****************/
  7375. #define GPIO_OTYPER_OT0_Pos (0U)
  7376. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  7377. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  7378. #define GPIO_OTYPER_OT1_Pos (1U)
  7379. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  7380. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  7381. #define GPIO_OTYPER_OT2_Pos (2U)
  7382. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  7383. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  7384. #define GPIO_OTYPER_OT3_Pos (3U)
  7385. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  7386. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  7387. #define GPIO_OTYPER_OT4_Pos (4U)
  7388. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  7389. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  7390. #define GPIO_OTYPER_OT5_Pos (5U)
  7391. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  7392. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  7393. #define GPIO_OTYPER_OT6_Pos (6U)
  7394. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  7395. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  7396. #define GPIO_OTYPER_OT7_Pos (7U)
  7397. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  7398. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  7399. #define GPIO_OTYPER_OT8_Pos (8U)
  7400. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  7401. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  7402. #define GPIO_OTYPER_OT9_Pos (9U)
  7403. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  7404. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  7405. #define GPIO_OTYPER_OT10_Pos (10U)
  7406. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  7407. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  7408. #define GPIO_OTYPER_OT11_Pos (11U)
  7409. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  7410. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  7411. #define GPIO_OTYPER_OT12_Pos (12U)
  7412. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  7413. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  7414. #define GPIO_OTYPER_OT13_Pos (13U)
  7415. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  7416. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  7417. #define GPIO_OTYPER_OT14_Pos (14U)
  7418. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  7419. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  7420. #define GPIO_OTYPER_OT15_Pos (15U)
  7421. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  7422. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  7423. /* Legacy defines */
  7424. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  7425. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  7426. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  7427. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  7428. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  7429. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  7430. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  7431. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  7432. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  7433. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  7434. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  7435. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  7436. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  7437. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  7438. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  7439. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  7440. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  7441. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  7442. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  7443. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  7444. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  7445. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  7446. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  7447. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  7448. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  7449. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  7450. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  7451. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  7452. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  7453. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  7454. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  7455. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  7456. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  7457. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  7458. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  7459. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  7460. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  7461. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  7462. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  7463. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  7464. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  7465. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  7466. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  7467. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  7468. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  7469. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  7470. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  7471. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  7472. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  7473. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  7474. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  7475. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  7476. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  7477. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  7478. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  7479. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  7480. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  7481. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  7482. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  7483. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  7484. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  7485. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  7486. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  7487. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  7488. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  7489. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  7490. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  7491. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  7492. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  7493. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  7494. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  7495. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  7496. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  7497. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  7498. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  7499. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  7500. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  7501. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  7502. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  7503. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  7504. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  7505. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  7506. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  7507. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  7508. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  7509. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  7510. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  7511. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  7512. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  7513. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  7514. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  7515. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  7516. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  7517. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  7518. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  7519. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  7520. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  7521. /* Legacy defines */
  7522. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  7523. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  7524. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  7525. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  7526. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  7527. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  7528. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  7529. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  7530. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  7531. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  7532. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  7533. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  7534. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  7535. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  7536. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  7537. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  7538. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  7539. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  7540. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  7541. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  7542. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  7543. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  7544. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  7545. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  7546. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  7547. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  7548. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  7549. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  7550. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  7551. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  7552. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  7553. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  7554. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  7555. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  7556. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  7557. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  7558. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  7559. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  7560. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  7561. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  7562. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  7563. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  7564. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  7565. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  7566. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  7567. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  7568. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  7569. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  7570. /****************** Bits definition for GPIO_PUPDR register *****************/
  7571. #define GPIO_PUPDR_PUPD0_Pos (0U)
  7572. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  7573. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  7574. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  7575. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  7576. #define GPIO_PUPDR_PUPD1_Pos (2U)
  7577. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  7578. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  7579. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  7580. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  7581. #define GPIO_PUPDR_PUPD2_Pos (4U)
  7582. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  7583. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  7584. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  7585. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  7586. #define GPIO_PUPDR_PUPD3_Pos (6U)
  7587. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  7588. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  7589. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  7590. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  7591. #define GPIO_PUPDR_PUPD4_Pos (8U)
  7592. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  7593. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  7594. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  7595. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  7596. #define GPIO_PUPDR_PUPD5_Pos (10U)
  7597. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  7598. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  7599. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  7600. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  7601. #define GPIO_PUPDR_PUPD6_Pos (12U)
  7602. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  7603. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  7604. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  7605. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  7606. #define GPIO_PUPDR_PUPD7_Pos (14U)
  7607. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  7608. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  7609. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  7610. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  7611. #define GPIO_PUPDR_PUPD8_Pos (16U)
  7612. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  7613. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  7614. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  7615. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  7616. #define GPIO_PUPDR_PUPD9_Pos (18U)
  7617. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  7618. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  7619. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  7620. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  7621. #define GPIO_PUPDR_PUPD10_Pos (20U)
  7622. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  7623. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  7624. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  7625. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  7626. #define GPIO_PUPDR_PUPD11_Pos (22U)
  7627. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  7628. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  7629. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  7630. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  7631. #define GPIO_PUPDR_PUPD12_Pos (24U)
  7632. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  7633. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  7634. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  7635. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  7636. #define GPIO_PUPDR_PUPD13_Pos (26U)
  7637. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  7638. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  7639. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  7640. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  7641. #define GPIO_PUPDR_PUPD14_Pos (28U)
  7642. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  7643. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  7644. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  7645. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  7646. #define GPIO_PUPDR_PUPD15_Pos (30U)
  7647. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  7648. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  7649. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  7650. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  7651. /* Legacy defines */
  7652. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  7653. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  7654. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  7655. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  7656. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  7657. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  7658. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  7659. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  7660. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  7661. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  7662. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  7663. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  7664. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  7665. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  7666. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  7667. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  7668. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  7669. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  7670. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  7671. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  7672. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  7673. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  7674. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  7675. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  7676. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  7677. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  7678. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  7679. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  7680. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  7681. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  7682. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  7683. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  7684. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  7685. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  7686. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  7687. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  7688. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  7689. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  7690. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  7691. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  7692. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  7693. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  7694. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  7695. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  7696. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  7697. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  7698. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  7699. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  7700. /****************** Bits definition for GPIO_IDR register *******************/
  7701. #define GPIO_IDR_ID0_Pos (0U)
  7702. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  7703. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  7704. #define GPIO_IDR_ID1_Pos (1U)
  7705. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  7706. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  7707. #define GPIO_IDR_ID2_Pos (2U)
  7708. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  7709. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  7710. #define GPIO_IDR_ID3_Pos (3U)
  7711. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  7712. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  7713. #define GPIO_IDR_ID4_Pos (4U)
  7714. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  7715. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  7716. #define GPIO_IDR_ID5_Pos (5U)
  7717. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  7718. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  7719. #define GPIO_IDR_ID6_Pos (6U)
  7720. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  7721. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  7722. #define GPIO_IDR_ID7_Pos (7U)
  7723. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  7724. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  7725. #define GPIO_IDR_ID8_Pos (8U)
  7726. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  7727. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  7728. #define GPIO_IDR_ID9_Pos (9U)
  7729. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  7730. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  7731. #define GPIO_IDR_ID10_Pos (10U)
  7732. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  7733. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  7734. #define GPIO_IDR_ID11_Pos (11U)
  7735. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  7736. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  7737. #define GPIO_IDR_ID12_Pos (12U)
  7738. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  7739. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  7740. #define GPIO_IDR_ID13_Pos (13U)
  7741. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  7742. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  7743. #define GPIO_IDR_ID14_Pos (14U)
  7744. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  7745. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  7746. #define GPIO_IDR_ID15_Pos (15U)
  7747. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  7748. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  7749. /* Legacy defines */
  7750. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  7751. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  7752. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  7753. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  7754. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  7755. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  7756. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  7757. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  7758. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  7759. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  7760. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  7761. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  7762. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  7763. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  7764. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  7765. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  7766. /****************** Bits definition for GPIO_ODR register *******************/
  7767. #define GPIO_ODR_OD0_Pos (0U)
  7768. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  7769. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  7770. #define GPIO_ODR_OD1_Pos (1U)
  7771. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  7772. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  7773. #define GPIO_ODR_OD2_Pos (2U)
  7774. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  7775. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  7776. #define GPIO_ODR_OD3_Pos (3U)
  7777. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  7778. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  7779. #define GPIO_ODR_OD4_Pos (4U)
  7780. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  7781. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  7782. #define GPIO_ODR_OD5_Pos (5U)
  7783. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  7784. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  7785. #define GPIO_ODR_OD6_Pos (6U)
  7786. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  7787. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  7788. #define GPIO_ODR_OD7_Pos (7U)
  7789. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  7790. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  7791. #define GPIO_ODR_OD8_Pos (8U)
  7792. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  7793. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  7794. #define GPIO_ODR_OD9_Pos (9U)
  7795. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  7796. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  7797. #define GPIO_ODR_OD10_Pos (10U)
  7798. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  7799. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  7800. #define GPIO_ODR_OD11_Pos (11U)
  7801. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  7802. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  7803. #define GPIO_ODR_OD12_Pos (12U)
  7804. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  7805. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  7806. #define GPIO_ODR_OD13_Pos (13U)
  7807. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  7808. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  7809. #define GPIO_ODR_OD14_Pos (14U)
  7810. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  7811. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  7812. #define GPIO_ODR_OD15_Pos (15U)
  7813. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  7814. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  7815. /* Legacy defines */
  7816. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  7817. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  7818. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  7819. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  7820. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  7821. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  7822. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  7823. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  7824. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  7825. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  7826. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  7827. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  7828. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  7829. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  7830. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  7831. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  7832. /****************** Bits definition for GPIO_BSRR register ******************/
  7833. #define GPIO_BSRR_BS0_Pos (0U)
  7834. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  7835. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  7836. #define GPIO_BSRR_BS1_Pos (1U)
  7837. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  7838. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  7839. #define GPIO_BSRR_BS2_Pos (2U)
  7840. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  7841. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  7842. #define GPIO_BSRR_BS3_Pos (3U)
  7843. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  7844. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  7845. #define GPIO_BSRR_BS4_Pos (4U)
  7846. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  7847. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  7848. #define GPIO_BSRR_BS5_Pos (5U)
  7849. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  7850. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  7851. #define GPIO_BSRR_BS6_Pos (6U)
  7852. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  7853. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  7854. #define GPIO_BSRR_BS7_Pos (7U)
  7855. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  7856. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  7857. #define GPIO_BSRR_BS8_Pos (8U)
  7858. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  7859. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  7860. #define GPIO_BSRR_BS9_Pos (9U)
  7861. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  7862. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  7863. #define GPIO_BSRR_BS10_Pos (10U)
  7864. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  7865. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  7866. #define GPIO_BSRR_BS11_Pos (11U)
  7867. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  7868. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  7869. #define GPIO_BSRR_BS12_Pos (12U)
  7870. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  7871. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  7872. #define GPIO_BSRR_BS13_Pos (13U)
  7873. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  7874. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  7875. #define GPIO_BSRR_BS14_Pos (14U)
  7876. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  7877. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  7878. #define GPIO_BSRR_BS15_Pos (15U)
  7879. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  7880. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  7881. #define GPIO_BSRR_BR0_Pos (16U)
  7882. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  7883. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  7884. #define GPIO_BSRR_BR1_Pos (17U)
  7885. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  7886. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  7887. #define GPIO_BSRR_BR2_Pos (18U)
  7888. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  7889. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  7890. #define GPIO_BSRR_BR3_Pos (19U)
  7891. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  7892. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  7893. #define GPIO_BSRR_BR4_Pos (20U)
  7894. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  7895. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  7896. #define GPIO_BSRR_BR5_Pos (21U)
  7897. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  7898. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  7899. #define GPIO_BSRR_BR6_Pos (22U)
  7900. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  7901. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  7902. #define GPIO_BSRR_BR7_Pos (23U)
  7903. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  7904. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  7905. #define GPIO_BSRR_BR8_Pos (24U)
  7906. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  7907. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  7908. #define GPIO_BSRR_BR9_Pos (25U)
  7909. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  7910. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  7911. #define GPIO_BSRR_BR10_Pos (26U)
  7912. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  7913. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  7914. #define GPIO_BSRR_BR11_Pos (27U)
  7915. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  7916. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  7917. #define GPIO_BSRR_BR12_Pos (28U)
  7918. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  7919. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  7920. #define GPIO_BSRR_BR13_Pos (29U)
  7921. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  7922. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  7923. #define GPIO_BSRR_BR14_Pos (30U)
  7924. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  7925. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  7926. #define GPIO_BSRR_BR15_Pos (31U)
  7927. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  7928. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  7929. /* Legacy defines */
  7930. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  7931. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  7932. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  7933. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  7934. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  7935. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  7936. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  7937. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  7938. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  7939. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  7940. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  7941. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  7942. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  7943. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  7944. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  7945. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  7946. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  7947. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  7948. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  7949. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  7950. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  7951. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  7952. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  7953. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  7954. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  7955. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  7956. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  7957. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  7958. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  7959. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  7960. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  7961. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  7962. #define GPIO_BRR_BR0 GPIO_BSRR_BR0
  7963. #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
  7964. #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
  7965. #define GPIO_BRR_BR1 GPIO_BSRR_BR1
  7966. #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
  7967. #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
  7968. #define GPIO_BRR_BR2 GPIO_BSRR_BR2
  7969. #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
  7970. #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
  7971. #define GPIO_BRR_BR3 GPIO_BSRR_BR3
  7972. #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
  7973. #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
  7974. #define GPIO_BRR_BR4 GPIO_BSRR_BR4
  7975. #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
  7976. #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
  7977. #define GPIO_BRR_BR5 GPIO_BSRR_BR5
  7978. #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
  7979. #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
  7980. #define GPIO_BRR_BR6 GPIO_BSRR_BR6
  7981. #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
  7982. #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
  7983. #define GPIO_BRR_BR7 GPIO_BSRR_BR7
  7984. #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
  7985. #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
  7986. #define GPIO_BRR_BR8 GPIO_BSRR_BR8
  7987. #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
  7988. #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
  7989. #define GPIO_BRR_BR9 GPIO_BSRR_BR9
  7990. #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
  7991. #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
  7992. #define GPIO_BRR_BR10 GPIO_BSRR_BR10
  7993. #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
  7994. #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
  7995. #define GPIO_BRR_BR11 GPIO_BSRR_BR11
  7996. #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
  7997. #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
  7998. #define GPIO_BRR_BR12 GPIO_BSRR_BR12
  7999. #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
  8000. #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
  8001. #define GPIO_BRR_BR13 GPIO_BSRR_BR13
  8002. #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
  8003. #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
  8004. #define GPIO_BRR_BR14 GPIO_BSRR_BR14
  8005. #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
  8006. #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
  8007. #define GPIO_BRR_BR15 GPIO_BSRR_BR15
  8008. #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
  8009. #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
  8010. /****************** Bit definition for GPIO_LCKR register *********************/
  8011. #define GPIO_LCKR_LCK0_Pos (0U)
  8012. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  8013. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  8014. #define GPIO_LCKR_LCK1_Pos (1U)
  8015. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  8016. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  8017. #define GPIO_LCKR_LCK2_Pos (2U)
  8018. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  8019. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  8020. #define GPIO_LCKR_LCK3_Pos (3U)
  8021. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  8022. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  8023. #define GPIO_LCKR_LCK4_Pos (4U)
  8024. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  8025. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  8026. #define GPIO_LCKR_LCK5_Pos (5U)
  8027. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  8028. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  8029. #define GPIO_LCKR_LCK6_Pos (6U)
  8030. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  8031. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  8032. #define GPIO_LCKR_LCK7_Pos (7U)
  8033. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  8034. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  8035. #define GPIO_LCKR_LCK8_Pos (8U)
  8036. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  8037. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  8038. #define GPIO_LCKR_LCK9_Pos (9U)
  8039. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  8040. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  8041. #define GPIO_LCKR_LCK10_Pos (10U)
  8042. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  8043. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  8044. #define GPIO_LCKR_LCK11_Pos (11U)
  8045. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  8046. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  8047. #define GPIO_LCKR_LCK12_Pos (12U)
  8048. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  8049. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  8050. #define GPIO_LCKR_LCK13_Pos (13U)
  8051. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  8052. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  8053. #define GPIO_LCKR_LCK14_Pos (14U)
  8054. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  8055. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  8056. #define GPIO_LCKR_LCK15_Pos (15U)
  8057. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  8058. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  8059. #define GPIO_LCKR_LCKK_Pos (16U)
  8060. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  8061. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  8062. /****************** Bit definition for GPIO_AFRL register *********************/
  8063. #define GPIO_AFRL_AFSEL0_Pos (0U)
  8064. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  8065. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  8066. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  8067. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  8068. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  8069. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  8070. #define GPIO_AFRL_AFSEL1_Pos (4U)
  8071. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  8072. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  8073. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  8074. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  8075. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  8076. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  8077. #define GPIO_AFRL_AFSEL2_Pos (8U)
  8078. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  8079. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  8080. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  8081. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  8082. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  8083. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  8084. #define GPIO_AFRL_AFSEL3_Pos (12U)
  8085. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  8086. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  8087. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  8088. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  8089. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  8090. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  8091. #define GPIO_AFRL_AFSEL4_Pos (16U)
  8092. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  8093. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  8094. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  8095. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  8096. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  8097. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  8098. #define GPIO_AFRL_AFSEL5_Pos (20U)
  8099. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  8100. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  8101. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  8102. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  8103. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  8104. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  8105. #define GPIO_AFRL_AFSEL6_Pos (24U)
  8106. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  8107. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  8108. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  8109. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  8110. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  8111. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  8112. #define GPIO_AFRL_AFSEL7_Pos (28U)
  8113. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  8114. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  8115. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  8116. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  8117. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  8118. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  8119. /* Legacy defines */
  8120. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  8121. #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
  8122. #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
  8123. #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
  8124. #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
  8125. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  8126. #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
  8127. #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
  8128. #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
  8129. #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
  8130. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  8131. #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
  8132. #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
  8133. #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
  8134. #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
  8135. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  8136. #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
  8137. #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
  8138. #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
  8139. #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
  8140. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  8141. #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
  8142. #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
  8143. #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
  8144. #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
  8145. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  8146. #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
  8147. #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
  8148. #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
  8149. #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
  8150. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  8151. #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
  8152. #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
  8153. #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
  8154. #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
  8155. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  8156. #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
  8157. #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
  8158. #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
  8159. #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
  8160. /****************** Bit definition for GPIO_AFRH register *********************/
  8161. #define GPIO_AFRH_AFSEL8_Pos (0U)
  8162. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  8163. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  8164. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  8165. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  8166. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  8167. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  8168. #define GPIO_AFRH_AFSEL9_Pos (4U)
  8169. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  8170. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  8171. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  8172. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  8173. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  8174. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  8175. #define GPIO_AFRH_AFSEL10_Pos (8U)
  8176. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  8177. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  8178. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  8179. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  8180. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  8181. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  8182. #define GPIO_AFRH_AFSEL11_Pos (12U)
  8183. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  8184. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  8185. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  8186. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  8187. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  8188. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  8189. #define GPIO_AFRH_AFSEL12_Pos (16U)
  8190. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  8191. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  8192. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  8193. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  8194. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  8195. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  8196. #define GPIO_AFRH_AFSEL13_Pos (20U)
  8197. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  8198. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  8199. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  8200. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  8201. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  8202. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  8203. #define GPIO_AFRH_AFSEL14_Pos (24U)
  8204. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  8205. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  8206. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  8207. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  8208. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  8209. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  8210. #define GPIO_AFRH_AFSEL15_Pos (28U)
  8211. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  8212. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  8213. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  8214. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  8215. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  8216. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  8217. /* Legacy defines */
  8218. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  8219. #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
  8220. #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
  8221. #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
  8222. #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
  8223. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  8224. #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
  8225. #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
  8226. #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
  8227. #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
  8228. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  8229. #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
  8230. #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
  8231. #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
  8232. #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
  8233. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  8234. #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
  8235. #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
  8236. #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
  8237. #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
  8238. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  8239. #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
  8240. #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
  8241. #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
  8242. #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
  8243. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  8244. #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
  8245. #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
  8246. #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
  8247. #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
  8248. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  8249. #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
  8250. #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
  8251. #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
  8252. #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
  8253. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  8254. #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
  8255. #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
  8256. #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
  8257. #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
  8258. /******************************************************************************/
  8259. /* */
  8260. /* Inter-integrated Circuit Interface */
  8261. /* */
  8262. /******************************************************************************/
  8263. /******************* Bit definition for I2C_CR1 register ********************/
  8264. #define I2C_CR1_PE_Pos (0U)
  8265. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  8266. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
  8267. #define I2C_CR1_SMBUS_Pos (1U)
  8268. #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
  8269. #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
  8270. #define I2C_CR1_SMBTYPE_Pos (3U)
  8271. #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
  8272. #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
  8273. #define I2C_CR1_ENARP_Pos (4U)
  8274. #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
  8275. #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
  8276. #define I2C_CR1_ENPEC_Pos (5U)
  8277. #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
  8278. #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
  8279. #define I2C_CR1_ENGC_Pos (6U)
  8280. #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
  8281. #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
  8282. #define I2C_CR1_NOSTRETCH_Pos (7U)
  8283. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
  8284. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
  8285. #define I2C_CR1_START_Pos (8U)
  8286. #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
  8287. #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
  8288. #define I2C_CR1_STOP_Pos (9U)
  8289. #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
  8290. #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
  8291. #define I2C_CR1_ACK_Pos (10U)
  8292. #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
  8293. #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
  8294. #define I2C_CR1_POS_Pos (11U)
  8295. #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
  8296. #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
  8297. #define I2C_CR1_PEC_Pos (12U)
  8298. #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
  8299. #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
  8300. #define I2C_CR1_ALERT_Pos (13U)
  8301. #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
  8302. #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
  8303. #define I2C_CR1_SWRST_Pos (15U)
  8304. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
  8305. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
  8306. /******************* Bit definition for I2C_CR2 register ********************/
  8307. #define I2C_CR2_FREQ_Pos (0U)
  8308. #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
  8309. #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
  8310. #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
  8311. #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
  8312. #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
  8313. #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
  8314. #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
  8315. #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
  8316. #define I2C_CR2_ITERREN_Pos (8U)
  8317. #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
  8318. #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
  8319. #define I2C_CR2_ITEVTEN_Pos (9U)
  8320. #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
  8321. #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
  8322. #define I2C_CR2_ITBUFEN_Pos (10U)
  8323. #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
  8324. #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
  8325. #define I2C_CR2_DMAEN_Pos (11U)
  8326. #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
  8327. #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
  8328. #define I2C_CR2_LAST_Pos (12U)
  8329. #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
  8330. #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
  8331. /******************* Bit definition for I2C_OAR1 register *******************/
  8332. #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
  8333. #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
  8334. #define I2C_OAR1_ADD0_Pos (0U)
  8335. #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
  8336. #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
  8337. #define I2C_OAR1_ADD1_Pos (1U)
  8338. #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
  8339. #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
  8340. #define I2C_OAR1_ADD2_Pos (2U)
  8341. #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
  8342. #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
  8343. #define I2C_OAR1_ADD3_Pos (3U)
  8344. #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
  8345. #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
  8346. #define I2C_OAR1_ADD4_Pos (4U)
  8347. #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
  8348. #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
  8349. #define I2C_OAR1_ADD5_Pos (5U)
  8350. #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
  8351. #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
  8352. #define I2C_OAR1_ADD6_Pos (6U)
  8353. #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
  8354. #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
  8355. #define I2C_OAR1_ADD7_Pos (7U)
  8356. #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
  8357. #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
  8358. #define I2C_OAR1_ADD8_Pos (8U)
  8359. #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
  8360. #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
  8361. #define I2C_OAR1_ADD9_Pos (9U)
  8362. #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
  8363. #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
  8364. #define I2C_OAR1_ADDMODE_Pos (15U)
  8365. #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
  8366. #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
  8367. /******************* Bit definition for I2C_OAR2 register *******************/
  8368. #define I2C_OAR2_ENDUAL_Pos (0U)
  8369. #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
  8370. #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
  8371. #define I2C_OAR2_ADD2_Pos (1U)
  8372. #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
  8373. #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
  8374. /******************** Bit definition for I2C_DR register ********************/
  8375. #define I2C_DR_DR_Pos (0U)
  8376. #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
  8377. #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
  8378. /******************* Bit definition for I2C_SR1 register ********************/
  8379. #define I2C_SR1_SB_Pos (0U)
  8380. #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
  8381. #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
  8382. #define I2C_SR1_ADDR_Pos (1U)
  8383. #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
  8384. #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
  8385. #define I2C_SR1_BTF_Pos (2U)
  8386. #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
  8387. #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
  8388. #define I2C_SR1_ADD10_Pos (3U)
  8389. #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
  8390. #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
  8391. #define I2C_SR1_STOPF_Pos (4U)
  8392. #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
  8393. #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
  8394. #define I2C_SR1_RXNE_Pos (6U)
  8395. #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
  8396. #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
  8397. #define I2C_SR1_TXE_Pos (7U)
  8398. #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
  8399. #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
  8400. #define I2C_SR1_BERR_Pos (8U)
  8401. #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
  8402. #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
  8403. #define I2C_SR1_ARLO_Pos (9U)
  8404. #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
  8405. #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
  8406. #define I2C_SR1_AF_Pos (10U)
  8407. #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
  8408. #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
  8409. #define I2C_SR1_OVR_Pos (11U)
  8410. #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
  8411. #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
  8412. #define I2C_SR1_PECERR_Pos (12U)
  8413. #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
  8414. #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
  8415. #define I2C_SR1_TIMEOUT_Pos (14U)
  8416. #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
  8417. #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
  8418. #define I2C_SR1_SMBALERT_Pos (15U)
  8419. #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
  8420. #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
  8421. /******************* Bit definition for I2C_SR2 register ********************/
  8422. #define I2C_SR2_MSL_Pos (0U)
  8423. #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
  8424. #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
  8425. #define I2C_SR2_BUSY_Pos (1U)
  8426. #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
  8427. #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
  8428. #define I2C_SR2_TRA_Pos (2U)
  8429. #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
  8430. #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
  8431. #define I2C_SR2_GENCALL_Pos (4U)
  8432. #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
  8433. #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
  8434. #define I2C_SR2_SMBDEFAULT_Pos (5U)
  8435. #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
  8436. #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
  8437. #define I2C_SR2_SMBHOST_Pos (6U)
  8438. #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
  8439. #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
  8440. #define I2C_SR2_DUALF_Pos (7U)
  8441. #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
  8442. #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
  8443. #define I2C_SR2_PEC_Pos (8U)
  8444. #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
  8445. #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
  8446. /******************* Bit definition for I2C_CCR register ********************/
  8447. #define I2C_CCR_CCR_Pos (0U)
  8448. #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
  8449. #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
  8450. #define I2C_CCR_DUTY_Pos (14U)
  8451. #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
  8452. #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
  8453. #define I2C_CCR_FS_Pos (15U)
  8454. #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
  8455. #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
  8456. /****************** Bit definition for I2C_TRISE register *******************/
  8457. #define I2C_TRISE_TRISE_Pos (0U)
  8458. #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
  8459. #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
  8460. /****************** Bit definition for I2C_FLTR register *******************/
  8461. #define I2C_FLTR_DNF_Pos (0U)
  8462. #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
  8463. #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
  8464. #define I2C_FLTR_ANOFF_Pos (4U)
  8465. #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
  8466. #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
  8467. /******************************************************************************/
  8468. /* */
  8469. /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
  8470. /* */
  8471. /******************************************************************************/
  8472. /******************* Bit definition for I2C_CR1 register *******************/
  8473. #define FMPI2C_CR1_PE_Pos (0U)
  8474. #define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
  8475. #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
  8476. #define FMPI2C_CR1_TXIE_Pos (1U)
  8477. #define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
  8478. #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
  8479. #define FMPI2C_CR1_RXIE_Pos (2U)
  8480. #define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
  8481. #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
  8482. #define FMPI2C_CR1_ADDRIE_Pos (3U)
  8483. #define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
  8484. #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
  8485. #define FMPI2C_CR1_NACKIE_Pos (4U)
  8486. #define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
  8487. #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
  8488. #define FMPI2C_CR1_STOPIE_Pos (5U)
  8489. #define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
  8490. #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
  8491. #define FMPI2C_CR1_TCIE_Pos (6U)
  8492. #define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
  8493. #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
  8494. #define FMPI2C_CR1_ERRIE_Pos (7U)
  8495. #define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
  8496. #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
  8497. #define FMPI2C_CR1_DNF_Pos (8U)
  8498. #define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos) /*!< 0x00000F00 */
  8499. #define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk /*!< Digital noise filter */
  8500. #define FMPI2C_CR1_ANFOFF_Pos (12U)
  8501. #define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
  8502. #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
  8503. #define FMPI2C_CR1_TXDMAEN_Pos (14U)
  8504. #define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
  8505. #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
  8506. #define FMPI2C_CR1_RXDMAEN_Pos (15U)
  8507. #define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
  8508. #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
  8509. #define FMPI2C_CR1_SBC_Pos (16U)
  8510. #define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
  8511. #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
  8512. #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
  8513. #define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
  8514. #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
  8515. #define FMPI2C_CR1_GCEN_Pos (19U)
  8516. #define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
  8517. #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
  8518. #define FMPI2C_CR1_SMBHEN_Pos (20U)
  8519. #define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
  8520. #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
  8521. #define FMPI2C_CR1_SMBDEN_Pos (21U)
  8522. #define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
  8523. #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
  8524. #define FMPI2C_CR1_ALERTEN_Pos (22U)
  8525. #define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
  8526. #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
  8527. #define FMPI2C_CR1_PECEN_Pos (23U)
  8528. #define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
  8529. #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
  8530. /* Legacy Defines */
  8531. #define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
  8532. #define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
  8533. #define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
  8534. /****************** Bit definition for I2C_CR2 register ********************/
  8535. #define FMPI2C_CR2_SADD_Pos (0U)
  8536. #define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
  8537. #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
  8538. #define FMPI2C_CR2_RD_WRN_Pos (10U)
  8539. #define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
  8540. #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
  8541. #define FMPI2C_CR2_ADD10_Pos (11U)
  8542. #define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
  8543. #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
  8544. #define FMPI2C_CR2_HEAD10R_Pos (12U)
  8545. #define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
  8546. #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
  8547. #define FMPI2C_CR2_START_Pos (13U)
  8548. #define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
  8549. #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
  8550. #define FMPI2C_CR2_STOP_Pos (14U)
  8551. #define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
  8552. #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
  8553. #define FMPI2C_CR2_NACK_Pos (15U)
  8554. #define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
  8555. #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
  8556. #define FMPI2C_CR2_NBYTES_Pos (16U)
  8557. #define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
  8558. #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
  8559. #define FMPI2C_CR2_RELOAD_Pos (24U)
  8560. #define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
  8561. #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
  8562. #define FMPI2C_CR2_AUTOEND_Pos (25U)
  8563. #define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
  8564. #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
  8565. #define FMPI2C_CR2_PECBYTE_Pos (26U)
  8566. #define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
  8567. #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
  8568. /******************* Bit definition for I2C_OAR1 register ******************/
  8569. #define FMPI2C_OAR1_OA1_Pos (0U)
  8570. #define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
  8571. #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
  8572. #define FMPI2C_OAR1_OA1MODE_Pos (10U)
  8573. #define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
  8574. #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
  8575. #define FMPI2C_OAR1_OA1EN_Pos (15U)
  8576. #define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
  8577. #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
  8578. /******************* Bit definition for I2C_OAR2 register ******************/
  8579. #define FMPI2C_OAR2_OA2_Pos (1U)
  8580. #define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
  8581. #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
  8582. #define FMPI2C_OAR2_OA2MSK_Pos (8U)
  8583. #define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
  8584. #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
  8585. #define FMPI2C_OAR2_OA2EN_Pos (15U)
  8586. #define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
  8587. #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
  8588. /******************* Bit definition for I2C_TIMINGR register *******************/
  8589. #define FMPI2C_TIMINGR_SCLL_Pos (0U)
  8590. #define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
  8591. #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
  8592. #define FMPI2C_TIMINGR_SCLH_Pos (8U)
  8593. #define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
  8594. #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
  8595. #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
  8596. #define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
  8597. #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
  8598. #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
  8599. #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
  8600. #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
  8601. #define FMPI2C_TIMINGR_PRESC_Pos (28U)
  8602. #define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
  8603. #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
  8604. /******************* Bit definition for I2C_TIMEOUTR register *******************/
  8605. #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
  8606. #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
  8607. #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
  8608. #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
  8609. #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
  8610. #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
  8611. #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
  8612. #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
  8613. #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
  8614. #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
  8615. #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
  8616. #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
  8617. #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
  8618. #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
  8619. #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
  8620. /****************** Bit definition for I2C_ISR register *********************/
  8621. #define FMPI2C_ISR_TXE_Pos (0U)
  8622. #define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
  8623. #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
  8624. #define FMPI2C_ISR_TXIS_Pos (1U)
  8625. #define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
  8626. #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
  8627. #define FMPI2C_ISR_RXNE_Pos (2U)
  8628. #define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
  8629. #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
  8630. #define FMPI2C_ISR_ADDR_Pos (3U)
  8631. #define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
  8632. #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
  8633. #define FMPI2C_ISR_NACKF_Pos (4U)
  8634. #define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
  8635. #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
  8636. #define FMPI2C_ISR_STOPF_Pos (5U)
  8637. #define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
  8638. #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
  8639. #define FMPI2C_ISR_TC_Pos (6U)
  8640. #define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
  8641. #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
  8642. #define FMPI2C_ISR_TCR_Pos (7U)
  8643. #define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
  8644. #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
  8645. #define FMPI2C_ISR_BERR_Pos (8U)
  8646. #define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
  8647. #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
  8648. #define FMPI2C_ISR_ARLO_Pos (9U)
  8649. #define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
  8650. #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
  8651. #define FMPI2C_ISR_OVR_Pos (10U)
  8652. #define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
  8653. #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
  8654. #define FMPI2C_ISR_PECERR_Pos (11U)
  8655. #define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
  8656. #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
  8657. #define FMPI2C_ISR_TIMEOUT_Pos (12U)
  8658. #define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
  8659. #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
  8660. #define FMPI2C_ISR_ALERT_Pos (13U)
  8661. #define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
  8662. #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
  8663. #define FMPI2C_ISR_BUSY_Pos (15U)
  8664. #define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
  8665. #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
  8666. #define FMPI2C_ISR_DIR_Pos (16U)
  8667. #define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
  8668. #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
  8669. #define FMPI2C_ISR_ADDCODE_Pos (17U)
  8670. #define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
  8671. #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
  8672. /****************** Bit definition for I2C_ICR register *********************/
  8673. #define FMPI2C_ICR_ADDRCF_Pos (3U)
  8674. #define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
  8675. #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
  8676. #define FMPI2C_ICR_NACKCF_Pos (4U)
  8677. #define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
  8678. #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
  8679. #define FMPI2C_ICR_STOPCF_Pos (5U)
  8680. #define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
  8681. #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
  8682. #define FMPI2C_ICR_BERRCF_Pos (8U)
  8683. #define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
  8684. #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
  8685. #define FMPI2C_ICR_ARLOCF_Pos (9U)
  8686. #define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
  8687. #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
  8688. #define FMPI2C_ICR_OVRCF_Pos (10U)
  8689. #define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
  8690. #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
  8691. #define FMPI2C_ICR_PECCF_Pos (11U)
  8692. #define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
  8693. #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
  8694. #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
  8695. #define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
  8696. #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
  8697. #define FMPI2C_ICR_ALERTCF_Pos (13U)
  8698. #define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
  8699. #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
  8700. /****************** Bit definition for I2C_PECR register *********************/
  8701. #define FMPI2C_PECR_PEC_Pos (0U)
  8702. #define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
  8703. #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
  8704. /****************** Bit definition for I2C_RXDR register *********************/
  8705. #define FMPI2C_RXDR_RXDATA_Pos (0U)
  8706. #define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
  8707. #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
  8708. /****************** Bit definition for I2C_TXDR register *********************/
  8709. #define FMPI2C_TXDR_TXDATA_Pos (0U)
  8710. #define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
  8711. #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
  8712. /******************************************************************************/
  8713. /* */
  8714. /* Independent WATCHDOG */
  8715. /* */
  8716. /******************************************************************************/
  8717. /******************* Bit definition for IWDG_KR register ********************/
  8718. #define IWDG_KR_KEY_Pos (0U)
  8719. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  8720. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  8721. /******************* Bit definition for IWDG_PR register ********************/
  8722. #define IWDG_PR_PR_Pos (0U)
  8723. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  8724. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  8725. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
  8726. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
  8727. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
  8728. /******************* Bit definition for IWDG_RLR register *******************/
  8729. #define IWDG_RLR_RL_Pos (0U)
  8730. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  8731. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  8732. /******************* Bit definition for IWDG_SR register ********************/
  8733. #define IWDG_SR_PVU_Pos (0U)
  8734. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  8735. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
  8736. #define IWDG_SR_RVU_Pos (1U)
  8737. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  8738. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
  8739. /******************************************************************************/
  8740. /* */
  8741. /* Power Control */
  8742. /* */
  8743. /******************************************************************************/
  8744. /******************** Bit definition for PWR_CR register ********************/
  8745. #define PWR_CR_LPDS_Pos (0U)
  8746. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  8747. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  8748. #define PWR_CR_PDDS_Pos (1U)
  8749. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  8750. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  8751. #define PWR_CR_CWUF_Pos (2U)
  8752. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  8753. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  8754. #define PWR_CR_CSBF_Pos (3U)
  8755. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  8756. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  8757. #define PWR_CR_PVDE_Pos (4U)
  8758. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  8759. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  8760. #define PWR_CR_PLS_Pos (5U)
  8761. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  8762. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  8763. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  8764. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  8765. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  8766. /*!< PVD level configuration */
  8767. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
  8768. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
  8769. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
  8770. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
  8771. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
  8772. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
  8773. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
  8774. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
  8775. #define PWR_CR_DBP_Pos (8U)
  8776. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  8777. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  8778. #define PWR_CR_FPDS_Pos (9U)
  8779. #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
  8780. #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
  8781. #define PWR_CR_LPLVDS_Pos (10U)
  8782. #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
  8783. #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
  8784. #define PWR_CR_MRLVDS_Pos (11U)
  8785. #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
  8786. #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
  8787. #define PWR_CR_ADCDC1_Pos (13U)
  8788. #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
  8789. #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
  8790. #define PWR_CR_VOS_Pos (14U)
  8791. #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
  8792. #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  8793. #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
  8794. #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
  8795. #define PWR_CR_FMSSR_Pos (20U)
  8796. #define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
  8797. #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
  8798. #define PWR_CR_FISSR_Pos (21U)
  8799. #define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
  8800. #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
  8801. /******************* Bit definition for PWR_CSR register ********************/
  8802. #define PWR_CSR_WUF_Pos (0U)
  8803. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  8804. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  8805. #define PWR_CSR_SBF_Pos (1U)
  8806. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  8807. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  8808. #define PWR_CSR_PVDO_Pos (2U)
  8809. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  8810. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  8811. #define PWR_CSR_BRR_Pos (3U)
  8812. #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
  8813. #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
  8814. #define PWR_CSR_EWUP3_Pos (6U)
  8815. #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
  8816. #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
  8817. #define PWR_CSR_EWUP2_Pos (7U)
  8818. #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
  8819. #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
  8820. #define PWR_CSR_EWUP1_Pos (8U)
  8821. #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
  8822. #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
  8823. #define PWR_CSR_BRE_Pos (9U)
  8824. #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
  8825. #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
  8826. #define PWR_CSR_VOSRDY_Pos (14U)
  8827. #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
  8828. #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
  8829. /******************************************************************************/
  8830. /* */
  8831. /* QUADSPI */
  8832. /* */
  8833. /******************************************************************************/
  8834. /***************** Bit definition for QUADSPI_CR register *******************/
  8835. #define QUADSPI_CR_EN_Pos (0U)
  8836. #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
  8837. #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
  8838. #define QUADSPI_CR_ABORT_Pos (1U)
  8839. #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
  8840. #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
  8841. #define QUADSPI_CR_DMAEN_Pos (2U)
  8842. #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
  8843. #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
  8844. #define QUADSPI_CR_TCEN_Pos (3U)
  8845. #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
  8846. #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
  8847. #define QUADSPI_CR_SSHIFT_Pos (4U)
  8848. #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
  8849. #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
  8850. #define QUADSPI_CR_DFM_Pos (6U)
  8851. #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
  8852. #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
  8853. #define QUADSPI_CR_FSEL_Pos (7U)
  8854. #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
  8855. #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
  8856. #define QUADSPI_CR_FTHRES_Pos (8U)
  8857. #define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
  8858. #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
  8859. #define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
  8860. #define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
  8861. #define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
  8862. #define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
  8863. #define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
  8864. #define QUADSPI_CR_TEIE_Pos (16U)
  8865. #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
  8866. #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
  8867. #define QUADSPI_CR_TCIE_Pos (17U)
  8868. #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
  8869. #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
  8870. #define QUADSPI_CR_FTIE_Pos (18U)
  8871. #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
  8872. #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
  8873. #define QUADSPI_CR_SMIE_Pos (19U)
  8874. #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
  8875. #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
  8876. #define QUADSPI_CR_TOIE_Pos (20U)
  8877. #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
  8878. #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
  8879. #define QUADSPI_CR_APMS_Pos (22U)
  8880. #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
  8881. #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
  8882. #define QUADSPI_CR_PMM_Pos (23U)
  8883. #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
  8884. #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
  8885. #define QUADSPI_CR_PRESCALER_Pos (24U)
  8886. #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
  8887. #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
  8888. #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
  8889. #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
  8890. #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
  8891. #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
  8892. #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
  8893. #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
  8894. #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
  8895. #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
  8896. /***************** Bit definition for QUADSPI_DCR register ******************/
  8897. #define QUADSPI_DCR_CKMODE_Pos (0U)
  8898. #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
  8899. #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
  8900. #define QUADSPI_DCR_CSHT_Pos (8U)
  8901. #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
  8902. #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
  8903. #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
  8904. #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
  8905. #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
  8906. #define QUADSPI_DCR_FSIZE_Pos (16U)
  8907. #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
  8908. #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
  8909. #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
  8910. #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
  8911. #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
  8912. #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
  8913. #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
  8914. /****************** Bit definition for QUADSPI_SR register *******************/
  8915. #define QUADSPI_SR_TEF_Pos (0U)
  8916. #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
  8917. #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
  8918. #define QUADSPI_SR_TCF_Pos (1U)
  8919. #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
  8920. #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
  8921. #define QUADSPI_SR_FTF_Pos (2U)
  8922. #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
  8923. #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
  8924. #define QUADSPI_SR_SMF_Pos (3U)
  8925. #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
  8926. #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
  8927. #define QUADSPI_SR_TOF_Pos (4U)
  8928. #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
  8929. #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
  8930. #define QUADSPI_SR_BUSY_Pos (5U)
  8931. #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
  8932. #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
  8933. #define QUADSPI_SR_FLEVEL_Pos (8U)
  8934. #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
  8935. #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
  8936. #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
  8937. #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
  8938. #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
  8939. #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
  8940. #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
  8941. #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
  8942. /****************** Bit definition for QUADSPI_FCR register ******************/
  8943. #define QUADSPI_FCR_CTEF_Pos (0U)
  8944. #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
  8945. #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
  8946. #define QUADSPI_FCR_CTCF_Pos (1U)
  8947. #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
  8948. #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
  8949. #define QUADSPI_FCR_CSMF_Pos (3U)
  8950. #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
  8951. #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
  8952. #define QUADSPI_FCR_CTOF_Pos (4U)
  8953. #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
  8954. #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
  8955. /****************** Bit definition for QUADSPI_DLR register ******************/
  8956. #define QUADSPI_DLR_DL_Pos (0U)
  8957. #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
  8958. #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
  8959. /****************** Bit definition for QUADSPI_CCR register ******************/
  8960. #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
  8961. #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
  8962. #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
  8963. #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
  8964. #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
  8965. #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
  8966. #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
  8967. #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
  8968. #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
  8969. #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
  8970. #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
  8971. #define QUADSPI_CCR_IMODE_Pos (8U)
  8972. #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
  8973. #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
  8974. #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
  8975. #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
  8976. #define QUADSPI_CCR_ADMODE_Pos (10U)
  8977. #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
  8978. #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
  8979. #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
  8980. #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
  8981. #define QUADSPI_CCR_ADSIZE_Pos (12U)
  8982. #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
  8983. #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
  8984. #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
  8985. #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
  8986. #define QUADSPI_CCR_ABMODE_Pos (14U)
  8987. #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
  8988. #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
  8989. #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
  8990. #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
  8991. #define QUADSPI_CCR_ABSIZE_Pos (16U)
  8992. #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
  8993. #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
  8994. #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
  8995. #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
  8996. #define QUADSPI_CCR_DCYC_Pos (18U)
  8997. #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
  8998. #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
  8999. #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
  9000. #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
  9001. #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
  9002. #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
  9003. #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
  9004. #define QUADSPI_CCR_DMODE_Pos (24U)
  9005. #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
  9006. #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
  9007. #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
  9008. #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
  9009. #define QUADSPI_CCR_FMODE_Pos (26U)
  9010. #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
  9011. #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
  9012. #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
  9013. #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
  9014. #define QUADSPI_CCR_SIOO_Pos (28U)
  9015. #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
  9016. #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
  9017. #define QUADSPI_CCR_DHHC_Pos (30U)
  9018. #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
  9019. #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
  9020. #define QUADSPI_CCR_DDRM_Pos (31U)
  9021. #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
  9022. #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
  9023. /****************** Bit definition for QUADSPI_AR register *******************/
  9024. #define QUADSPI_AR_ADDRESS_Pos (0U)
  9025. #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
  9026. #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
  9027. /****************** Bit definition for QUADSPI_ABR register ******************/
  9028. #define QUADSPI_ABR_ALTERNATE_Pos (0U)
  9029. #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
  9030. #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
  9031. /****************** Bit definition for QUADSPI_DR register *******************/
  9032. #define QUADSPI_DR_DATA_Pos (0U)
  9033. #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
  9034. #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
  9035. /****************** Bit definition for QUADSPI_PSMKR register ****************/
  9036. #define QUADSPI_PSMKR_MASK_Pos (0U)
  9037. #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
  9038. #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
  9039. /****************** Bit definition for QUADSPI_PSMAR register ****************/
  9040. #define QUADSPI_PSMAR_MATCH_Pos (0U)
  9041. #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
  9042. #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
  9043. /****************** Bit definition for QUADSPI_PIR register *****************/
  9044. #define QUADSPI_PIR_INTERVAL_Pos (0U)
  9045. #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
  9046. #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
  9047. /****************** Bit definition for QUADSPI_LPTR register *****************/
  9048. #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
  9049. #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
  9050. #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
  9051. /******************************************************************************/
  9052. /* */
  9053. /* Reset and Clock Control */
  9054. /* */
  9055. /******************************************************************************/
  9056. /******************** Bit definition for RCC_CR register ********************/
  9057. #define RCC_CR_HSION_Pos (0U)
  9058. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  9059. #define RCC_CR_HSION RCC_CR_HSION_Msk
  9060. #define RCC_CR_HSIRDY_Pos (1U)
  9061. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  9062. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
  9063. #define RCC_CR_HSITRIM_Pos (3U)
  9064. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  9065. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
  9066. #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  9067. #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  9068. #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  9069. #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  9070. #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  9071. #define RCC_CR_HSICAL_Pos (8U)
  9072. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  9073. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
  9074. #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  9075. #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  9076. #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  9077. #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  9078. #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  9079. #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  9080. #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  9081. #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  9082. #define RCC_CR_HSEON_Pos (16U)
  9083. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  9084. #define RCC_CR_HSEON RCC_CR_HSEON_Msk
  9085. #define RCC_CR_HSERDY_Pos (17U)
  9086. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  9087. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
  9088. #define RCC_CR_HSEBYP_Pos (18U)
  9089. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  9090. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
  9091. #define RCC_CR_CSSON_Pos (19U)
  9092. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  9093. #define RCC_CR_CSSON RCC_CR_CSSON_Msk
  9094. #define RCC_CR_PLLON_Pos (24U)
  9095. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  9096. #define RCC_CR_PLLON RCC_CR_PLLON_Msk
  9097. #define RCC_CR_PLLRDY_Pos (25U)
  9098. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  9099. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
  9100. /*
  9101. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9102. */
  9103. #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
  9104. #define RCC_CR_PLLI2SON_Pos (26U)
  9105. #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
  9106. #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
  9107. #define RCC_CR_PLLI2SRDY_Pos (27U)
  9108. #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
  9109. #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
  9110. /******************** Bit definition for RCC_PLLCFGR register ***************/
  9111. #define RCC_PLLCFGR_PLLM_Pos (0U)
  9112. #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
  9113. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  9114. #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
  9115. #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
  9116. #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
  9117. #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
  9118. #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  9119. #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  9120. #define RCC_PLLCFGR_PLLN_Pos (6U)
  9121. #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
  9122. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  9123. #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
  9124. #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
  9125. #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  9126. #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  9127. #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  9128. #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  9129. #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  9130. #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  9131. #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  9132. #define RCC_PLLCFGR_PLLP_Pos (16U)
  9133. #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
  9134. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  9135. #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
  9136. #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  9137. #define RCC_PLLCFGR_PLLSRC_Pos (22U)
  9138. #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
  9139. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  9140. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
  9141. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
  9142. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
  9143. #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
  9144. #define RCC_PLLCFGR_PLLQ_Pos (24U)
  9145. #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
  9146. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  9147. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
  9148. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  9149. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  9150. #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  9151. /*
  9152. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9153. */
  9154. #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
  9155. #define RCC_PLLCFGR_PLLR_Pos (28U)
  9156. #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
  9157. #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
  9158. #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
  9159. #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
  9160. #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
  9161. /******************** Bit definition for RCC_CFGR register ******************/
  9162. /*!< SW configuration */
  9163. #define RCC_CFGR_SW_Pos (0U)
  9164. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  9165. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  9166. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  9167. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  9168. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  9169. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  9170. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  9171. /*!< SWS configuration */
  9172. #define RCC_CFGR_SWS_Pos (2U)
  9173. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  9174. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  9175. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  9176. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  9177. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  9178. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  9179. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  9180. /*!< HPRE configuration */
  9181. #define RCC_CFGR_HPRE_Pos (4U)
  9182. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  9183. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  9184. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  9185. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  9186. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  9187. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  9188. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  9189. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  9190. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  9191. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  9192. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  9193. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  9194. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  9195. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  9196. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  9197. /*!< PPRE1 configuration */
  9198. #define RCC_CFGR_PPRE1_Pos (10U)
  9199. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
  9200. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  9201. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  9202. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
  9203. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
  9204. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  9205. #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
  9206. #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
  9207. #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
  9208. #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
  9209. /*!< PPRE2 configuration */
  9210. #define RCC_CFGR_PPRE2_Pos (13U)
  9211. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
  9212. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  9213. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  9214. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
  9215. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
  9216. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  9217. #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
  9218. #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
  9219. #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
  9220. #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
  9221. /*!< RTCPRE configuration */
  9222. #define RCC_CFGR_RTCPRE_Pos (16U)
  9223. #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
  9224. #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
  9225. #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
  9226. #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
  9227. #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
  9228. #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
  9229. #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
  9230. /*!< MCO1 configuration */
  9231. #define RCC_CFGR_MCO1_Pos (21U)
  9232. #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
  9233. #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
  9234. #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
  9235. #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
  9236. #define RCC_CFGR_MCO1PRE_Pos (24U)
  9237. #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
  9238. #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
  9239. #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
  9240. #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
  9241. #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
  9242. #define RCC_CFGR_MCO2PRE_Pos (27U)
  9243. #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
  9244. #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
  9245. #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
  9246. #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
  9247. #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
  9248. #define RCC_CFGR_MCO2_Pos (30U)
  9249. #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
  9250. #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
  9251. #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
  9252. #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
  9253. /******************** Bit definition for RCC_CIR register *******************/
  9254. #define RCC_CIR_LSIRDYF_Pos (0U)
  9255. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  9256. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
  9257. #define RCC_CIR_LSERDYF_Pos (1U)
  9258. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  9259. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
  9260. #define RCC_CIR_HSIRDYF_Pos (2U)
  9261. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  9262. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
  9263. #define RCC_CIR_HSERDYF_Pos (3U)
  9264. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  9265. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
  9266. #define RCC_CIR_PLLRDYF_Pos (4U)
  9267. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  9268. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
  9269. #define RCC_CIR_PLLI2SRDYF_Pos (5U)
  9270. #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
  9271. #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
  9272. #define RCC_CIR_CSSF_Pos (7U)
  9273. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  9274. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
  9275. #define RCC_CIR_LSIRDYIE_Pos (8U)
  9276. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  9277. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
  9278. #define RCC_CIR_LSERDYIE_Pos (9U)
  9279. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  9280. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
  9281. #define RCC_CIR_HSIRDYIE_Pos (10U)
  9282. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  9283. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
  9284. #define RCC_CIR_HSERDYIE_Pos (11U)
  9285. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  9286. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
  9287. #define RCC_CIR_PLLRDYIE_Pos (12U)
  9288. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  9289. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
  9290. #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
  9291. #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
  9292. #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
  9293. #define RCC_CIR_LSIRDYC_Pos (16U)
  9294. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  9295. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
  9296. #define RCC_CIR_LSERDYC_Pos (17U)
  9297. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  9298. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
  9299. #define RCC_CIR_HSIRDYC_Pos (18U)
  9300. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  9301. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
  9302. #define RCC_CIR_HSERDYC_Pos (19U)
  9303. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  9304. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
  9305. #define RCC_CIR_PLLRDYC_Pos (20U)
  9306. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  9307. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
  9308. #define RCC_CIR_PLLI2SRDYC_Pos (21U)
  9309. #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
  9310. #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
  9311. #define RCC_CIR_CSSC_Pos (23U)
  9312. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  9313. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
  9314. /******************** Bit definition for RCC_AHB1RSTR register **************/
  9315. #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
  9316. #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  9317. #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
  9318. #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
  9319. #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  9320. #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
  9321. #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
  9322. #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  9323. #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
  9324. #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
  9325. #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
  9326. #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
  9327. #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
  9328. #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
  9329. #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
  9330. #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
  9331. #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
  9332. #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
  9333. #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
  9334. #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
  9335. #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
  9336. #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
  9337. #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  9338. #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
  9339. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  9340. #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  9341. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  9342. #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
  9343. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
  9344. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  9345. #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
  9346. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
  9347. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  9348. /******************** Bit definition for RCC_AHB2RSTR register **************/
  9349. #define RCC_AHB2RSTR_RNGRST_Pos (6U)
  9350. #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
  9351. #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
  9352. #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
  9353. #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
  9354. #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
  9355. /******************** Bit definition for RCC_AHB3RSTR register **************/
  9356. #define RCC_AHB3RSTR_FSMCRST_Pos (0U)
  9357. #define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */
  9358. #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
  9359. #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
  9360. #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
  9361. #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
  9362. /******************** Bit definition for RCC_APB1RSTR register **************/
  9363. #define RCC_APB1RSTR_TIM2RST_Pos (0U)
  9364. #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
  9365. #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
  9366. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  9367. #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  9368. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
  9369. #define RCC_APB1RSTR_TIM4RST_Pos (2U)
  9370. #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
  9371. #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
  9372. #define RCC_APB1RSTR_TIM5RST_Pos (3U)
  9373. #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
  9374. #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
  9375. #define RCC_APB1RSTR_TIM6RST_Pos (4U)
  9376. #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
  9377. #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
  9378. #define RCC_APB1RSTR_TIM7RST_Pos (5U)
  9379. #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
  9380. #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
  9381. #define RCC_APB1RSTR_TIM12RST_Pos (6U)
  9382. #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
  9383. #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
  9384. #define RCC_APB1RSTR_TIM13RST_Pos (7U)
  9385. #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
  9386. #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
  9387. #define RCC_APB1RSTR_TIM14RST_Pos (8U)
  9388. #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
  9389. #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
  9390. #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
  9391. #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
  9392. #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
  9393. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  9394. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  9395. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
  9396. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  9397. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  9398. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
  9399. #define RCC_APB1RSTR_SPI3RST_Pos (15U)
  9400. #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
  9401. #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
  9402. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  9403. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  9404. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
  9405. #define RCC_APB1RSTR_USART3RST_Pos (18U)
  9406. #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
  9407. #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
  9408. #define RCC_APB1RSTR_UART4RST_Pos (19U)
  9409. #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
  9410. #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
  9411. #define RCC_APB1RSTR_UART5RST_Pos (20U)
  9412. #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
  9413. #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
  9414. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  9415. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  9416. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
  9417. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  9418. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  9419. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
  9420. #define RCC_APB1RSTR_I2C3RST_Pos (23U)
  9421. #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
  9422. #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
  9423. #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
  9424. #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
  9425. #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
  9426. #define RCC_APB1RSTR_CAN1RST_Pos (25U)
  9427. #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
  9428. #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
  9429. #define RCC_APB1RSTR_CAN2RST_Pos (26U)
  9430. #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
  9431. #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
  9432. #define RCC_APB1RSTR_CAN3RST_Pos (27U)
  9433. #define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x08000000 */
  9434. #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
  9435. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  9436. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  9437. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
  9438. #define RCC_APB1RSTR_DACRST_Pos (29U)
  9439. #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
  9440. #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
  9441. #define RCC_APB1RSTR_UART7RST_Pos (30U)
  9442. #define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
  9443. #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
  9444. #define RCC_APB1RSTR_UART8RST_Pos (31U)
  9445. #define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
  9446. #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
  9447. /******************** Bit definition for RCC_APB2RSTR register **************/
  9448. #define RCC_APB2RSTR_TIM1RST_Pos (0U)
  9449. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
  9450. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  9451. #define RCC_APB2RSTR_TIM8RST_Pos (1U)
  9452. #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
  9453. #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
  9454. #define RCC_APB2RSTR_USART1RST_Pos (4U)
  9455. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
  9456. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  9457. #define RCC_APB2RSTR_USART6RST_Pos (5U)
  9458. #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
  9459. #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
  9460. #define RCC_APB2RSTR_UART9RST_Pos (6U)
  9461. #define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
  9462. #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
  9463. #define RCC_APB2RSTR_UART10RST_Pos (7U)
  9464. #define RCC_APB2RSTR_UART10RST_Msk (0x1UL << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */
  9465. #define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
  9466. #define RCC_APB2RSTR_ADCRST_Pos (8U)
  9467. #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
  9468. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
  9469. #define RCC_APB2RSTR_SDIORST_Pos (11U)
  9470. #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
  9471. #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
  9472. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  9473. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  9474. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  9475. #define RCC_APB2RSTR_SPI4RST_Pos (13U)
  9476. #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
  9477. #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
  9478. #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
  9479. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
  9480. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  9481. #define RCC_APB2RSTR_TIM9RST_Pos (16U)
  9482. #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
  9483. #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
  9484. #define RCC_APB2RSTR_TIM10RST_Pos (17U)
  9485. #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
  9486. #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
  9487. #define RCC_APB2RSTR_TIM11RST_Pos (18U)
  9488. #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
  9489. #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
  9490. #define RCC_APB2RSTR_SPI5RST_Pos (20U)
  9491. #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
  9492. #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
  9493. #define RCC_APB2RSTR_SAI1RST_Pos (22U)
  9494. #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
  9495. #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
  9496. #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
  9497. #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
  9498. #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
  9499. #define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
  9500. #define RCC_APB2RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */
  9501. #define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
  9502. /******************** Bit definition for RCC_AHB1ENR register ***************/
  9503. #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
  9504. #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  9505. #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
  9506. #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
  9507. #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  9508. #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
  9509. #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
  9510. #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  9511. #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
  9512. #define RCC_AHB1ENR_GPIODEN_Pos (3U)
  9513. #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
  9514. #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
  9515. #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
  9516. #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
  9517. #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
  9518. #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
  9519. #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
  9520. #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
  9521. #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
  9522. #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
  9523. #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
  9524. #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
  9525. #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  9526. #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
  9527. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  9528. #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  9529. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  9530. #define RCC_AHB1ENR_DMA1EN_Pos (21U)
  9531. #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
  9532. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  9533. #define RCC_AHB1ENR_DMA2EN_Pos (22U)
  9534. #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
  9535. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  9536. /******************** Bit definition for RCC_AHB2ENR register ***************/
  9537. /*
  9538. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9539. */
  9540. #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
  9541. #define RCC_AHB2ENR_RNGEN_Pos (6U)
  9542. #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
  9543. #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
  9544. #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
  9545. #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
  9546. #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
  9547. /******************** Bit definition for RCC_AHB3ENR register ***************/
  9548. /*
  9549. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9550. */
  9551. #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
  9552. #define RCC_AHB3ENR_FSMCEN_Pos (0U)
  9553. #define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */
  9554. #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
  9555. #define RCC_AHB3ENR_QSPIEN_Pos (1U)
  9556. #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
  9557. #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
  9558. /******************** Bit definition for RCC_APB1ENR register ***************/
  9559. #define RCC_APB1ENR_TIM2EN_Pos (0U)
  9560. #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
  9561. #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
  9562. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  9563. #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  9564. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
  9565. #define RCC_APB1ENR_TIM4EN_Pos (2U)
  9566. #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
  9567. #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
  9568. #define RCC_APB1ENR_TIM5EN_Pos (3U)
  9569. #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
  9570. #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
  9571. #define RCC_APB1ENR_TIM6EN_Pos (4U)
  9572. #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
  9573. #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
  9574. #define RCC_APB1ENR_TIM7EN_Pos (5U)
  9575. #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
  9576. #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
  9577. #define RCC_APB1ENR_TIM12EN_Pos (6U)
  9578. #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
  9579. #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
  9580. #define RCC_APB1ENR_TIM13EN_Pos (7U)
  9581. #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
  9582. #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
  9583. #define RCC_APB1ENR_TIM14EN_Pos (8U)
  9584. #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
  9585. #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
  9586. #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
  9587. #define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
  9588. #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
  9589. #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
  9590. #define RCC_APB1ENR_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
  9591. #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
  9592. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  9593. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  9594. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
  9595. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  9596. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  9597. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
  9598. #define RCC_APB1ENR_SPI3EN_Pos (15U)
  9599. #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
  9600. #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
  9601. #define RCC_APB1ENR_USART2EN_Pos (17U)
  9602. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  9603. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
  9604. #define RCC_APB1ENR_USART3EN_Pos (18U)
  9605. #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
  9606. #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
  9607. #define RCC_APB1ENR_UART4EN_Pos (19U)
  9608. #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
  9609. #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
  9610. #define RCC_APB1ENR_UART5EN_Pos (20U)
  9611. #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
  9612. #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
  9613. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  9614. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  9615. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
  9616. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  9617. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  9618. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
  9619. #define RCC_APB1ENR_I2C3EN_Pos (23U)
  9620. #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
  9621. #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
  9622. #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
  9623. #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
  9624. #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
  9625. #define RCC_APB1ENR_CAN1EN_Pos (25U)
  9626. #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
  9627. #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
  9628. #define RCC_APB1ENR_CAN2EN_Pos (26U)
  9629. #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
  9630. #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
  9631. #define RCC_APB1ENR_CAN3EN_Pos (27U)
  9632. #define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x08000000 */
  9633. #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
  9634. #define RCC_APB1ENR_PWREN_Pos (28U)
  9635. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  9636. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
  9637. #define RCC_APB1ENR_DACEN_Pos (29U)
  9638. #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
  9639. #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
  9640. #define RCC_APB1ENR_UART7EN_Pos (30U)
  9641. #define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
  9642. #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
  9643. #define RCC_APB1ENR_UART8EN_Pos (31U)
  9644. #define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
  9645. #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
  9646. /******************** Bit definition for RCC_APB2ENR register ***************/
  9647. #define RCC_APB2ENR_TIM1EN_Pos (0U)
  9648. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
  9649. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  9650. #define RCC_APB2ENR_TIM8EN_Pos (1U)
  9651. #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
  9652. #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
  9653. #define RCC_APB2ENR_USART1EN_Pos (4U)
  9654. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
  9655. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  9656. #define RCC_APB2ENR_USART6EN_Pos (5U)
  9657. #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
  9658. #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
  9659. #define RCC_APB2ENR_UART9EN_Pos (6U)
  9660. #define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
  9661. #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
  9662. #define RCC_APB2ENR_UART10EN_Pos (7U)
  9663. #define RCC_APB2ENR_UART10EN_Msk (0x1UL << RCC_APB2ENR_UART10EN_Pos) /*!< 0x00000080 */
  9664. #define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
  9665. #define RCC_APB2ENR_ADC1EN_Pos (8U)
  9666. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
  9667. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
  9668. #define RCC_APB2ENR_SDIOEN_Pos (11U)
  9669. #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
  9670. #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
  9671. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  9672. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  9673. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  9674. #define RCC_APB2ENR_SPI4EN_Pos (13U)
  9675. #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
  9676. #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
  9677. #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
  9678. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
  9679. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  9680. #define RCC_APB2ENR_EXTITEN_Pos (15U)
  9681. #define RCC_APB2ENR_EXTITEN_Msk (0x1UL << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
  9682. #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
  9683. #define RCC_APB2ENR_TIM9EN_Pos (16U)
  9684. #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
  9685. #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
  9686. #define RCC_APB2ENR_TIM10EN_Pos (17U)
  9687. #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
  9688. #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
  9689. #define RCC_APB2ENR_TIM11EN_Pos (18U)
  9690. #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
  9691. #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
  9692. #define RCC_APB2ENR_SPI5EN_Pos (20U)
  9693. #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
  9694. #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
  9695. #define RCC_APB2ENR_SAI1EN_Pos (22U)
  9696. #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
  9697. #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
  9698. #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
  9699. #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
  9700. #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
  9701. #define RCC_APB2ENR_DFSDM2EN_Pos (25U)
  9702. #define RCC_APB2ENR_DFSDM2EN_Msk (0x1UL << RCC_APB2ENR_DFSDM2EN_Pos) /*!< 0x02000000 */
  9703. #define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
  9704. /******************** Bit definition for RCC_AHB1LPENR register *************/
  9705. #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
  9706. #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
  9707. #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
  9708. #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
  9709. #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
  9710. #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
  9711. #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
  9712. #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
  9713. #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
  9714. #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
  9715. #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
  9716. #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
  9717. #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
  9718. #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
  9719. #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
  9720. #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
  9721. #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
  9722. #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
  9723. #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
  9724. #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
  9725. #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
  9726. #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
  9727. #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
  9728. #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
  9729. #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
  9730. #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
  9731. #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
  9732. #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
  9733. #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
  9734. #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
  9735. #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
  9736. #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
  9737. #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
  9738. #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
  9739. #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
  9740. #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
  9741. #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
  9742. #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
  9743. #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
  9744. #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
  9745. #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
  9746. #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
  9747. /******************** Bit definition for RCC_AHB2LPENR register *************/
  9748. #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
  9749. #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
  9750. #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
  9751. #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
  9752. #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
  9753. #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
  9754. /******************** Bit definition for RCC_AHB3LPENR register *************/
  9755. #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
  9756. #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
  9757. #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
  9758. #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
  9759. #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
  9760. #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
  9761. /******************** Bit definition for RCC_APB1LPENR register *************/
  9762. #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
  9763. #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
  9764. #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
  9765. #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
  9766. #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
  9767. #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
  9768. #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
  9769. #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
  9770. #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
  9771. #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
  9772. #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
  9773. #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
  9774. #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
  9775. #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
  9776. #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
  9777. #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
  9778. #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
  9779. #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
  9780. #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
  9781. #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
  9782. #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
  9783. #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
  9784. #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
  9785. #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
  9786. #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
  9787. #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
  9788. #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
  9789. #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
  9790. #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
  9791. #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
  9792. #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
  9793. #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
  9794. #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
  9795. #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
  9796. #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
  9797. #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
  9798. #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
  9799. #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
  9800. #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
  9801. #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
  9802. #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
  9803. #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
  9804. #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
  9805. #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
  9806. #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
  9807. #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
  9808. #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
  9809. #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
  9810. #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
  9811. #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
  9812. #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
  9813. #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
  9814. #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
  9815. #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
  9816. #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
  9817. #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
  9818. #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
  9819. #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
  9820. #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
  9821. #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
  9822. #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
  9823. #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
  9824. #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
  9825. #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
  9826. #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
  9827. #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
  9828. #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
  9829. #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
  9830. #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
  9831. #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
  9832. #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
  9833. #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
  9834. #define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
  9835. #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */
  9836. #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
  9837. #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
  9838. #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
  9839. #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
  9840. #define RCC_APB1LPENR_DACLPEN_Pos (29U)
  9841. #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
  9842. #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
  9843. #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
  9844. #define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
  9845. #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
  9846. #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
  9847. #define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
  9848. #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
  9849. /******************** Bit definition for RCC_APB2LPENR register *************/
  9850. #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
  9851. #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
  9852. #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
  9853. #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
  9854. #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
  9855. #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
  9856. #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
  9857. #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
  9858. #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
  9859. #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
  9860. #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
  9861. #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
  9862. #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
  9863. #define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
  9864. #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
  9865. #define RCC_APB2LPENR_UART10LPEN_Pos (7U)
  9866. #define RCC_APB2LPENR_UART10LPEN_Msk (0x1UL << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */
  9867. #define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
  9868. #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
  9869. #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
  9870. #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
  9871. #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
  9872. #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
  9873. #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
  9874. #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
  9875. #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
  9876. #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
  9877. #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
  9878. #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
  9879. #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
  9880. #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
  9881. #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
  9882. #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
  9883. #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
  9884. #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
  9885. #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
  9886. #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
  9887. #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
  9888. #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
  9889. #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
  9890. #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
  9891. #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
  9892. #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
  9893. #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
  9894. #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
  9895. #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
  9896. #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
  9897. #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
  9898. #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
  9899. #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
  9900. #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
  9901. #define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
  9902. #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
  9903. #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
  9904. #define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
  9905. #define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */
  9906. #define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
  9907. /******************** Bit definition for RCC_BDCR register ******************/
  9908. #define RCC_BDCR_LSEON_Pos (0U)
  9909. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  9910. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  9911. #define RCC_BDCR_LSERDY_Pos (1U)
  9912. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  9913. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  9914. #define RCC_BDCR_LSEBYP_Pos (2U)
  9915. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  9916. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  9917. #define RCC_BDCR_LSEMOD_Pos (3U)
  9918. #define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
  9919. #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
  9920. #define RCC_BDCR_RTCSEL_Pos (8U)
  9921. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  9922. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  9923. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  9924. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  9925. #define RCC_BDCR_RTCEN_Pos (15U)
  9926. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  9927. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  9928. #define RCC_BDCR_BDRST_Pos (16U)
  9929. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  9930. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  9931. /******************** Bit definition for RCC_CSR register *******************/
  9932. #define RCC_CSR_LSION_Pos (0U)
  9933. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  9934. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  9935. #define RCC_CSR_LSIRDY_Pos (1U)
  9936. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  9937. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  9938. #define RCC_CSR_RMVF_Pos (24U)
  9939. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  9940. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  9941. #define RCC_CSR_BORRSTF_Pos (25U)
  9942. #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
  9943. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  9944. #define RCC_CSR_PINRSTF_Pos (26U)
  9945. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  9946. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  9947. #define RCC_CSR_PORRSTF_Pos (27U)
  9948. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  9949. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
  9950. #define RCC_CSR_SFTRSTF_Pos (28U)
  9951. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  9952. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  9953. #define RCC_CSR_IWDGRSTF_Pos (29U)
  9954. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  9955. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  9956. #define RCC_CSR_WWDGRSTF_Pos (30U)
  9957. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  9958. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  9959. #define RCC_CSR_LPWRRSTF_Pos (31U)
  9960. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  9961. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  9962. /* Legacy defines */
  9963. #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
  9964. #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
  9965. /******************** Bit definition for RCC_SSCGR register *****************/
  9966. #define RCC_SSCGR_MODPER_Pos (0U)
  9967. #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
  9968. #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
  9969. #define RCC_SSCGR_INCSTEP_Pos (13U)
  9970. #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
  9971. #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
  9972. #define RCC_SSCGR_SPREADSEL_Pos (30U)
  9973. #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
  9974. #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
  9975. #define RCC_SSCGR_SSCGEN_Pos (31U)
  9976. #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
  9977. #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
  9978. /******************** Bit definition for RCC_PLLI2SCFGR register ************/
  9979. #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
  9980. #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
  9981. #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
  9982. #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
  9983. #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
  9984. #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
  9985. #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
  9986. #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
  9987. #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
  9988. #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
  9989. #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
  9990. #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
  9991. #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
  9992. #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
  9993. #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
  9994. #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
  9995. #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
  9996. #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
  9997. #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
  9998. #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
  9999. #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
  10000. #define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
  10001. #define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
  10002. #define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
  10003. #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
  10004. #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
  10005. #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
  10006. #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
  10007. #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
  10008. #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
  10009. #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
  10010. #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
  10011. #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
  10012. #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
  10013. #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
  10014. #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
  10015. #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
  10016. /******************** Bit definition for RCC_DCKCFGR register ***************/
  10017. #define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
  10018. #define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */
  10019. #define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
  10020. #define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */
  10021. #define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */
  10022. #define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */
  10023. #define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */
  10024. #define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */
  10025. #define RCC_DCKCFGR_PLLDIVR_Pos (8U)
  10026. #define RCC_DCKCFGR_PLLDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */
  10027. #define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
  10028. #define RCC_DCKCFGR_PLLDIVR_0 (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */
  10029. #define RCC_DCKCFGR_PLLDIVR_1 (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */
  10030. #define RCC_DCKCFGR_PLLDIVR_2 (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */
  10031. #define RCC_DCKCFGR_PLLDIVR_3 (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */
  10032. #define RCC_DCKCFGR_PLLDIVR_4 (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
  10033. #define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
  10034. #define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */
  10035. #define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
  10036. #define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
  10037. #define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
  10038. #define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
  10039. /*
  10040. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  10041. */
  10042. #define RCC_SAI1A_PLLSOURCE_SUPPORT /*!< SAI1 block A PLL Main source clock support */
  10043. #define RCC_SAI1B_PLLSOURCE_SUPPORT /*!< SAI1 block B PLL Main source clock support */
  10044. #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
  10045. #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
  10046. #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
  10047. #define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
  10048. #define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
  10049. #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
  10050. #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
  10051. #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
  10052. #define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
  10053. #define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
  10054. #define RCC_DCKCFGR_TIMPRE_Pos (24U)
  10055. #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
  10056. #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
  10057. #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
  10058. #define RCC_DCKCFGR_I2S1SRC_Msk (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
  10059. #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
  10060. #define RCC_DCKCFGR_I2S1SRC_0 (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
  10061. #define RCC_DCKCFGR_I2S1SRC_1 (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
  10062. #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
  10063. #define RCC_DCKCFGR_I2S2SRC_Msk (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
  10064. #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
  10065. #define RCC_DCKCFGR_I2S2SRC_0 (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
  10066. #define RCC_DCKCFGR_I2S2SRC_1 (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
  10067. #define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
  10068. #define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
  10069. #define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
  10070. /******************** Bit definition for RCC_CKGATENR register ***************/
  10071. #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
  10072. #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
  10073. #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
  10074. #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
  10075. #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
  10076. #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
  10077. #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
  10078. #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
  10079. #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
  10080. #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
  10081. #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
  10082. #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
  10083. #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
  10084. #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
  10085. #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
  10086. #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
  10087. #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
  10088. #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
  10089. #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
  10090. #define RCC_CKGATENR_RCC_CKEN_Msk (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
  10091. #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
  10092. #define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
  10093. #define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
  10094. #define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
  10095. /******************** Bit definition for RCC_DCKCFGR2 register ***************/
  10096. #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
  10097. #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
  10098. #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
  10099. #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
  10100. #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
  10101. #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
  10102. #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
  10103. #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
  10104. #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
  10105. #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
  10106. #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
  10107. #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
  10108. #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
  10109. #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
  10110. #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
  10111. #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
  10112. /******************************************************************************/
  10113. /* */
  10114. /* RNG */
  10115. /* */
  10116. /******************************************************************************/
  10117. /******************** Bits definition for RNG_CR register *******************/
  10118. #define RNG_CR_RNGEN_Pos (2U)
  10119. #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
  10120. #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
  10121. #define RNG_CR_IE_Pos (3U)
  10122. #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
  10123. #define RNG_CR_IE RNG_CR_IE_Msk
  10124. /******************** Bits definition for RNG_SR register *******************/
  10125. #define RNG_SR_DRDY_Pos (0U)
  10126. #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
  10127. #define RNG_SR_DRDY RNG_SR_DRDY_Msk
  10128. #define RNG_SR_CECS_Pos (1U)
  10129. #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
  10130. #define RNG_SR_CECS RNG_SR_CECS_Msk
  10131. #define RNG_SR_SECS_Pos (2U)
  10132. #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
  10133. #define RNG_SR_SECS RNG_SR_SECS_Msk
  10134. #define RNG_SR_CEIS_Pos (5U)
  10135. #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
  10136. #define RNG_SR_CEIS RNG_SR_CEIS_Msk
  10137. #define RNG_SR_SEIS_Pos (6U)
  10138. #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
  10139. #define RNG_SR_SEIS RNG_SR_SEIS_Msk
  10140. /******************************************************************************/
  10141. /* */
  10142. /* Real-Time Clock (RTC) */
  10143. /* */
  10144. /******************************************************************************/
  10145. /******************** Bits definition for RTC_TR register *******************/
  10146. #define RTC_TR_PM_Pos (22U)
  10147. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  10148. #define RTC_TR_PM RTC_TR_PM_Msk
  10149. #define RTC_TR_HT_Pos (20U)
  10150. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  10151. #define RTC_TR_HT RTC_TR_HT_Msk
  10152. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  10153. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  10154. #define RTC_TR_HU_Pos (16U)
  10155. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  10156. #define RTC_TR_HU RTC_TR_HU_Msk
  10157. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  10158. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  10159. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  10160. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  10161. #define RTC_TR_MNT_Pos (12U)
  10162. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  10163. #define RTC_TR_MNT RTC_TR_MNT_Msk
  10164. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  10165. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  10166. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  10167. #define RTC_TR_MNU_Pos (8U)
  10168. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  10169. #define RTC_TR_MNU RTC_TR_MNU_Msk
  10170. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  10171. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  10172. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  10173. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  10174. #define RTC_TR_ST_Pos (4U)
  10175. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  10176. #define RTC_TR_ST RTC_TR_ST_Msk
  10177. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  10178. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  10179. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  10180. #define RTC_TR_SU_Pos (0U)
  10181. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  10182. #define RTC_TR_SU RTC_TR_SU_Msk
  10183. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  10184. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  10185. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  10186. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  10187. /******************** Bits definition for RTC_DR register *******************/
  10188. #define RTC_DR_YT_Pos (20U)
  10189. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  10190. #define RTC_DR_YT RTC_DR_YT_Msk
  10191. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  10192. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  10193. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  10194. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  10195. #define RTC_DR_YU_Pos (16U)
  10196. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  10197. #define RTC_DR_YU RTC_DR_YU_Msk
  10198. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  10199. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  10200. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  10201. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  10202. #define RTC_DR_WDU_Pos (13U)
  10203. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  10204. #define RTC_DR_WDU RTC_DR_WDU_Msk
  10205. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  10206. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  10207. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  10208. #define RTC_DR_MT_Pos (12U)
  10209. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  10210. #define RTC_DR_MT RTC_DR_MT_Msk
  10211. #define RTC_DR_MU_Pos (8U)
  10212. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  10213. #define RTC_DR_MU RTC_DR_MU_Msk
  10214. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  10215. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  10216. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  10217. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  10218. #define RTC_DR_DT_Pos (4U)
  10219. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  10220. #define RTC_DR_DT RTC_DR_DT_Msk
  10221. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  10222. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  10223. #define RTC_DR_DU_Pos (0U)
  10224. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  10225. #define RTC_DR_DU RTC_DR_DU_Msk
  10226. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  10227. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  10228. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  10229. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  10230. /******************** Bits definition for RTC_CR register *******************/
  10231. #define RTC_CR_COE_Pos (23U)
  10232. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  10233. #define RTC_CR_COE RTC_CR_COE_Msk
  10234. #define RTC_CR_OSEL_Pos (21U)
  10235. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  10236. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  10237. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  10238. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  10239. #define RTC_CR_POL_Pos (20U)
  10240. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  10241. #define RTC_CR_POL RTC_CR_POL_Msk
  10242. #define RTC_CR_COSEL_Pos (19U)
  10243. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  10244. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  10245. #define RTC_CR_BKP_Pos (18U)
  10246. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  10247. #define RTC_CR_BKP RTC_CR_BKP_Msk
  10248. #define RTC_CR_SUB1H_Pos (17U)
  10249. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  10250. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  10251. #define RTC_CR_ADD1H_Pos (16U)
  10252. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  10253. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  10254. #define RTC_CR_TSIE_Pos (15U)
  10255. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  10256. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  10257. #define RTC_CR_WUTIE_Pos (14U)
  10258. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  10259. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  10260. #define RTC_CR_ALRBIE_Pos (13U)
  10261. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  10262. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  10263. #define RTC_CR_ALRAIE_Pos (12U)
  10264. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  10265. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  10266. #define RTC_CR_TSE_Pos (11U)
  10267. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  10268. #define RTC_CR_TSE RTC_CR_TSE_Msk
  10269. #define RTC_CR_WUTE_Pos (10U)
  10270. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  10271. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  10272. #define RTC_CR_ALRBE_Pos (9U)
  10273. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  10274. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  10275. #define RTC_CR_ALRAE_Pos (8U)
  10276. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  10277. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  10278. #define RTC_CR_DCE_Pos (7U)
  10279. #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */
  10280. #define RTC_CR_DCE RTC_CR_DCE_Msk
  10281. #define RTC_CR_FMT_Pos (6U)
  10282. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  10283. #define RTC_CR_FMT RTC_CR_FMT_Msk
  10284. #define RTC_CR_BYPSHAD_Pos (5U)
  10285. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  10286. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  10287. #define RTC_CR_REFCKON_Pos (4U)
  10288. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  10289. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  10290. #define RTC_CR_TSEDGE_Pos (3U)
  10291. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  10292. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  10293. #define RTC_CR_WUCKSEL_Pos (0U)
  10294. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  10295. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  10296. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  10297. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  10298. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  10299. /* Legacy defines */
  10300. #define RTC_CR_BCK RTC_CR_BKP
  10301. /******************** Bits definition for RTC_ISR register ******************/
  10302. #define RTC_ISR_RECALPF_Pos (16U)
  10303. #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  10304. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  10305. #define RTC_ISR_TAMP1F_Pos (13U)
  10306. #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  10307. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  10308. #define RTC_ISR_TAMP2F_Pos (14U)
  10309. #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  10310. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  10311. #define RTC_ISR_TSOVF_Pos (12U)
  10312. #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  10313. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  10314. #define RTC_ISR_TSF_Pos (11U)
  10315. #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  10316. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  10317. #define RTC_ISR_WUTF_Pos (10U)
  10318. #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  10319. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  10320. #define RTC_ISR_ALRBF_Pos (9U)
  10321. #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  10322. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  10323. #define RTC_ISR_ALRAF_Pos (8U)
  10324. #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  10325. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  10326. #define RTC_ISR_INIT_Pos (7U)
  10327. #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  10328. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  10329. #define RTC_ISR_INITF_Pos (6U)
  10330. #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  10331. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  10332. #define RTC_ISR_RSF_Pos (5U)
  10333. #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  10334. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  10335. #define RTC_ISR_INITS_Pos (4U)
  10336. #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  10337. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  10338. #define RTC_ISR_SHPF_Pos (3U)
  10339. #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  10340. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  10341. #define RTC_ISR_WUTWF_Pos (2U)
  10342. #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  10343. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  10344. #define RTC_ISR_ALRBWF_Pos (1U)
  10345. #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  10346. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  10347. #define RTC_ISR_ALRAWF_Pos (0U)
  10348. #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  10349. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  10350. /******************** Bits definition for RTC_PRER register *****************/
  10351. #define RTC_PRER_PREDIV_A_Pos (16U)
  10352. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  10353. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  10354. #define RTC_PRER_PREDIV_S_Pos (0U)
  10355. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  10356. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  10357. /******************** Bits definition for RTC_WUTR register *****************/
  10358. #define RTC_WUTR_WUT_Pos (0U)
  10359. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  10360. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  10361. /******************** Bits definition for RTC_CALIBR register ***************/
  10362. #define RTC_CALIBR_DCS_Pos (7U)
  10363. #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
  10364. #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
  10365. #define RTC_CALIBR_DC_Pos (0U)
  10366. #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
  10367. #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
  10368. /******************** Bits definition for RTC_ALRMAR register ***************/
  10369. #define RTC_ALRMAR_MSK4_Pos (31U)
  10370. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  10371. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  10372. #define RTC_ALRMAR_WDSEL_Pos (30U)
  10373. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  10374. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  10375. #define RTC_ALRMAR_DT_Pos (28U)
  10376. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  10377. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  10378. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  10379. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  10380. #define RTC_ALRMAR_DU_Pos (24U)
  10381. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  10382. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  10383. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  10384. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  10385. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  10386. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  10387. #define RTC_ALRMAR_MSK3_Pos (23U)
  10388. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  10389. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  10390. #define RTC_ALRMAR_PM_Pos (22U)
  10391. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  10392. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  10393. #define RTC_ALRMAR_HT_Pos (20U)
  10394. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  10395. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  10396. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  10397. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  10398. #define RTC_ALRMAR_HU_Pos (16U)
  10399. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  10400. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  10401. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  10402. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  10403. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  10404. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  10405. #define RTC_ALRMAR_MSK2_Pos (15U)
  10406. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  10407. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  10408. #define RTC_ALRMAR_MNT_Pos (12U)
  10409. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  10410. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  10411. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  10412. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  10413. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  10414. #define RTC_ALRMAR_MNU_Pos (8U)
  10415. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  10416. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  10417. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  10418. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  10419. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  10420. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  10421. #define RTC_ALRMAR_MSK1_Pos (7U)
  10422. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  10423. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  10424. #define RTC_ALRMAR_ST_Pos (4U)
  10425. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  10426. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  10427. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  10428. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  10429. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  10430. #define RTC_ALRMAR_SU_Pos (0U)
  10431. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  10432. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  10433. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  10434. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  10435. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  10436. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  10437. /******************** Bits definition for RTC_ALRMBR register ***************/
  10438. #define RTC_ALRMBR_MSK4_Pos (31U)
  10439. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  10440. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  10441. #define RTC_ALRMBR_WDSEL_Pos (30U)
  10442. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  10443. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  10444. #define RTC_ALRMBR_DT_Pos (28U)
  10445. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  10446. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  10447. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  10448. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  10449. #define RTC_ALRMBR_DU_Pos (24U)
  10450. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  10451. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  10452. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  10453. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  10454. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  10455. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  10456. #define RTC_ALRMBR_MSK3_Pos (23U)
  10457. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  10458. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  10459. #define RTC_ALRMBR_PM_Pos (22U)
  10460. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  10461. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  10462. #define RTC_ALRMBR_HT_Pos (20U)
  10463. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  10464. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  10465. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  10466. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  10467. #define RTC_ALRMBR_HU_Pos (16U)
  10468. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  10469. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  10470. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  10471. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  10472. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  10473. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  10474. #define RTC_ALRMBR_MSK2_Pos (15U)
  10475. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  10476. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  10477. #define RTC_ALRMBR_MNT_Pos (12U)
  10478. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  10479. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  10480. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  10481. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  10482. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  10483. #define RTC_ALRMBR_MNU_Pos (8U)
  10484. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  10485. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  10486. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  10487. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  10488. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  10489. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  10490. #define RTC_ALRMBR_MSK1_Pos (7U)
  10491. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  10492. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  10493. #define RTC_ALRMBR_ST_Pos (4U)
  10494. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  10495. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  10496. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  10497. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  10498. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  10499. #define RTC_ALRMBR_SU_Pos (0U)
  10500. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  10501. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  10502. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  10503. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  10504. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  10505. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  10506. /******************** Bits definition for RTC_WPR register ******************/
  10507. #define RTC_WPR_KEY_Pos (0U)
  10508. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  10509. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  10510. /******************** Bits definition for RTC_SSR register ******************/
  10511. #define RTC_SSR_SS_Pos (0U)
  10512. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  10513. #define RTC_SSR_SS RTC_SSR_SS_Msk
  10514. /******************** Bits definition for RTC_SHIFTR register ***************/
  10515. #define RTC_SHIFTR_SUBFS_Pos (0U)
  10516. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  10517. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  10518. #define RTC_SHIFTR_ADD1S_Pos (31U)
  10519. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  10520. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  10521. /******************** Bits definition for RTC_TSTR register *****************/
  10522. #define RTC_TSTR_PM_Pos (22U)
  10523. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  10524. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  10525. #define RTC_TSTR_HT_Pos (20U)
  10526. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  10527. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  10528. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  10529. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  10530. #define RTC_TSTR_HU_Pos (16U)
  10531. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  10532. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  10533. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  10534. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  10535. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  10536. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  10537. #define RTC_TSTR_MNT_Pos (12U)
  10538. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  10539. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  10540. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  10541. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  10542. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  10543. #define RTC_TSTR_MNU_Pos (8U)
  10544. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  10545. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  10546. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  10547. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  10548. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  10549. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  10550. #define RTC_TSTR_ST_Pos (4U)
  10551. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  10552. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  10553. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  10554. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  10555. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  10556. #define RTC_TSTR_SU_Pos (0U)
  10557. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  10558. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  10559. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  10560. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  10561. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  10562. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  10563. /******************** Bits definition for RTC_TSDR register *****************/
  10564. #define RTC_TSDR_WDU_Pos (13U)
  10565. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  10566. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  10567. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  10568. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  10569. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  10570. #define RTC_TSDR_MT_Pos (12U)
  10571. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  10572. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  10573. #define RTC_TSDR_MU_Pos (8U)
  10574. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  10575. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  10576. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  10577. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  10578. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  10579. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  10580. #define RTC_TSDR_DT_Pos (4U)
  10581. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  10582. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  10583. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  10584. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  10585. #define RTC_TSDR_DU_Pos (0U)
  10586. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  10587. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  10588. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  10589. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  10590. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  10591. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  10592. /******************** Bits definition for RTC_TSSSR register ****************/
  10593. #define RTC_TSSSR_SS_Pos (0U)
  10594. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  10595. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  10596. /******************** Bits definition for RTC_CAL register *****************/
  10597. #define RTC_CALR_CALP_Pos (15U)
  10598. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  10599. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  10600. #define RTC_CALR_CALW8_Pos (14U)
  10601. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  10602. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  10603. #define RTC_CALR_CALW16_Pos (13U)
  10604. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  10605. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  10606. #define RTC_CALR_CALM_Pos (0U)
  10607. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  10608. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  10609. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  10610. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  10611. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  10612. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  10613. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  10614. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  10615. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  10616. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  10617. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  10618. /******************** Bits definition for RTC_TAFCR register ****************/
  10619. #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
  10620. #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
  10621. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
  10622. #define RTC_TAFCR_TSINSEL_Pos (17U)
  10623. #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
  10624. #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
  10625. #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
  10626. #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
  10627. #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
  10628. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  10629. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  10630. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  10631. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  10632. #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  10633. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  10634. #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  10635. #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  10636. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  10637. #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  10638. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  10639. #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  10640. #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  10641. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  10642. #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  10643. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  10644. #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  10645. #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  10646. #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  10647. #define RTC_TAFCR_TAMPTS_Pos (7U)
  10648. #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  10649. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  10650. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  10651. #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  10652. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  10653. #define RTC_TAFCR_TAMP2E_Pos (3U)
  10654. #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  10655. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  10656. #define RTC_TAFCR_TAMPIE_Pos (2U)
  10657. #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  10658. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  10659. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  10660. #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  10661. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  10662. #define RTC_TAFCR_TAMP1E_Pos (0U)
  10663. #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  10664. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  10665. /* Legacy defines */
  10666. #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
  10667. /******************** Bits definition for RTC_ALRMASSR register *************/
  10668. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  10669. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  10670. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  10671. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  10672. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  10673. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  10674. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  10675. #define RTC_ALRMASSR_SS_Pos (0U)
  10676. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  10677. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  10678. /******************** Bits definition for RTC_ALRMBSSR register *************/
  10679. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  10680. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  10681. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  10682. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  10683. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  10684. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  10685. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  10686. #define RTC_ALRMBSSR_SS_Pos (0U)
  10687. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  10688. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  10689. /******************** Bits definition for RTC_BKP0R register ****************/
  10690. #define RTC_BKP0R_Pos (0U)
  10691. #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  10692. #define RTC_BKP0R RTC_BKP0R_Msk
  10693. /******************** Bits definition for RTC_BKP1R register ****************/
  10694. #define RTC_BKP1R_Pos (0U)
  10695. #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  10696. #define RTC_BKP1R RTC_BKP1R_Msk
  10697. /******************** Bits definition for RTC_BKP2R register ****************/
  10698. #define RTC_BKP2R_Pos (0U)
  10699. #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  10700. #define RTC_BKP2R RTC_BKP2R_Msk
  10701. /******************** Bits definition for RTC_BKP3R register ****************/
  10702. #define RTC_BKP3R_Pos (0U)
  10703. #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  10704. #define RTC_BKP3R RTC_BKP3R_Msk
  10705. /******************** Bits definition for RTC_BKP4R register ****************/
  10706. #define RTC_BKP4R_Pos (0U)
  10707. #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  10708. #define RTC_BKP4R RTC_BKP4R_Msk
  10709. /******************** Bits definition for RTC_BKP5R register ****************/
  10710. #define RTC_BKP5R_Pos (0U)
  10711. #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  10712. #define RTC_BKP5R RTC_BKP5R_Msk
  10713. /******************** Bits definition for RTC_BKP6R register ****************/
  10714. #define RTC_BKP6R_Pos (0U)
  10715. #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  10716. #define RTC_BKP6R RTC_BKP6R_Msk
  10717. /******************** Bits definition for RTC_BKP7R register ****************/
  10718. #define RTC_BKP7R_Pos (0U)
  10719. #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  10720. #define RTC_BKP7R RTC_BKP7R_Msk
  10721. /******************** Bits definition for RTC_BKP8R register ****************/
  10722. #define RTC_BKP8R_Pos (0U)
  10723. #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  10724. #define RTC_BKP8R RTC_BKP8R_Msk
  10725. /******************** Bits definition for RTC_BKP9R register ****************/
  10726. #define RTC_BKP9R_Pos (0U)
  10727. #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  10728. #define RTC_BKP9R RTC_BKP9R_Msk
  10729. /******************** Bits definition for RTC_BKP10R register ***************/
  10730. #define RTC_BKP10R_Pos (0U)
  10731. #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  10732. #define RTC_BKP10R RTC_BKP10R_Msk
  10733. /******************** Bits definition for RTC_BKP11R register ***************/
  10734. #define RTC_BKP11R_Pos (0U)
  10735. #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  10736. #define RTC_BKP11R RTC_BKP11R_Msk
  10737. /******************** Bits definition for RTC_BKP12R register ***************/
  10738. #define RTC_BKP12R_Pos (0U)
  10739. #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  10740. #define RTC_BKP12R RTC_BKP12R_Msk
  10741. /******************** Bits definition for RTC_BKP13R register ***************/
  10742. #define RTC_BKP13R_Pos (0U)
  10743. #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  10744. #define RTC_BKP13R RTC_BKP13R_Msk
  10745. /******************** Bits definition for RTC_BKP14R register ***************/
  10746. #define RTC_BKP14R_Pos (0U)
  10747. #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  10748. #define RTC_BKP14R RTC_BKP14R_Msk
  10749. /******************** Bits definition for RTC_BKP15R register ***************/
  10750. #define RTC_BKP15R_Pos (0U)
  10751. #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  10752. #define RTC_BKP15R RTC_BKP15R_Msk
  10753. /******************** Bits definition for RTC_BKP16R register ***************/
  10754. #define RTC_BKP16R_Pos (0U)
  10755. #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  10756. #define RTC_BKP16R RTC_BKP16R_Msk
  10757. /******************** Bits definition for RTC_BKP17R register ***************/
  10758. #define RTC_BKP17R_Pos (0U)
  10759. #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  10760. #define RTC_BKP17R RTC_BKP17R_Msk
  10761. /******************** Bits definition for RTC_BKP18R register ***************/
  10762. #define RTC_BKP18R_Pos (0U)
  10763. #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  10764. #define RTC_BKP18R RTC_BKP18R_Msk
  10765. /******************** Bits definition for RTC_BKP19R register ***************/
  10766. #define RTC_BKP19R_Pos (0U)
  10767. #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  10768. #define RTC_BKP19R RTC_BKP19R_Msk
  10769. /******************** Number of backup registers ******************************/
  10770. #define RTC_BKP_NUMBER 0x000000014U
  10771. /******************************************************************************/
  10772. /* */
  10773. /* Serial Audio Interface */
  10774. /* */
  10775. /******************************************************************************/
  10776. /******************** Bit definition for SAI_GCR register *******************/
  10777. #define SAI_GCR_SYNCIN_Pos (0U)
  10778. #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
  10779. #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
  10780. #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
  10781. #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
  10782. #define SAI_GCR_SYNCOUT_Pos (4U)
  10783. #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
  10784. #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
  10785. #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
  10786. #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
  10787. /******************* Bit definition for SAI_xCR1 register *******************/
  10788. #define SAI_xCR1_MODE_Pos (0U)
  10789. #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
  10790. #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
  10791. #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
  10792. #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
  10793. #define SAI_xCR1_PRTCFG_Pos (2U)
  10794. #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
  10795. #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
  10796. #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
  10797. #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
  10798. #define SAI_xCR1_DS_Pos (5U)
  10799. #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
  10800. #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
  10801. #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
  10802. #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
  10803. #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
  10804. #define SAI_xCR1_LSBFIRST_Pos (8U)
  10805. #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
  10806. #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
  10807. #define SAI_xCR1_CKSTR_Pos (9U)
  10808. #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
  10809. #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
  10810. #define SAI_xCR1_SYNCEN_Pos (10U)
  10811. #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
  10812. #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
  10813. #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
  10814. #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
  10815. #define SAI_xCR1_MONO_Pos (12U)
  10816. #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
  10817. #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
  10818. #define SAI_xCR1_OUTDRIV_Pos (13U)
  10819. #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
  10820. #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
  10821. #define SAI_xCR1_SAIEN_Pos (16U)
  10822. #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
  10823. #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
  10824. #define SAI_xCR1_DMAEN_Pos (17U)
  10825. #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
  10826. #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
  10827. #define SAI_xCR1_NODIV_Pos (19U)
  10828. #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
  10829. #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
  10830. #define SAI_xCR1_MCKDIV_Pos (20U)
  10831. #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
  10832. #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
  10833. #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
  10834. #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
  10835. #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
  10836. #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
  10837. /******************* Bit definition for SAI_xCR2 register *******************/
  10838. #define SAI_xCR2_FTH_Pos (0U)
  10839. #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
  10840. #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
  10841. #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
  10842. #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
  10843. #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
  10844. #define SAI_xCR2_FFLUSH_Pos (3U)
  10845. #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
  10846. #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
  10847. #define SAI_xCR2_TRIS_Pos (4U)
  10848. #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
  10849. #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
  10850. #define SAI_xCR2_MUTE_Pos (5U)
  10851. #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
  10852. #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
  10853. #define SAI_xCR2_MUTEVAL_Pos (6U)
  10854. #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
  10855. #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
  10856. #define SAI_xCR2_MUTECNT_Pos (7U)
  10857. #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
  10858. #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
  10859. #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
  10860. #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
  10861. #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
  10862. #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
  10863. #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
  10864. #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
  10865. #define SAI_xCR2_CPL_Pos (13U)
  10866. #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
  10867. #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
  10868. #define SAI_xCR2_COMP_Pos (14U)
  10869. #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
  10870. #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
  10871. #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
  10872. #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
  10873. /****************** Bit definition for SAI_xFRCR register *******************/
  10874. #define SAI_xFRCR_FRL_Pos (0U)
  10875. #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
  10876. #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
  10877. #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
  10878. #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
  10879. #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
  10880. #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
  10881. #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
  10882. #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
  10883. #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
  10884. #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
  10885. #define SAI_xFRCR_FSALL_Pos (8U)
  10886. #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
  10887. #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
  10888. #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
  10889. #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
  10890. #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
  10891. #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
  10892. #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
  10893. #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
  10894. #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
  10895. #define SAI_xFRCR_FSDEF_Pos (16U)
  10896. #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
  10897. #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
  10898. #define SAI_xFRCR_FSPOL_Pos (17U)
  10899. #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
  10900. #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
  10901. #define SAI_xFRCR_FSOFF_Pos (18U)
  10902. #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
  10903. #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
  10904. /* Legacy defines */
  10905. #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
  10906. /****************** Bit definition for SAI_xSLOTR register *******************/
  10907. #define SAI_xSLOTR_FBOFF_Pos (0U)
  10908. #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
  10909. #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
  10910. #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
  10911. #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
  10912. #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
  10913. #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
  10914. #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
  10915. #define SAI_xSLOTR_SLOTSZ_Pos (6U)
  10916. #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
  10917. #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
  10918. #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
  10919. #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
  10920. #define SAI_xSLOTR_NBSLOT_Pos (8U)
  10921. #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
  10922. #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
  10923. #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
  10924. #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
  10925. #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
  10926. #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
  10927. #define SAI_xSLOTR_SLOTEN_Pos (16U)
  10928. #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
  10929. #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
  10930. /******************* Bit definition for SAI_xIMR register *******************/
  10931. #define SAI_xIMR_OVRUDRIE_Pos (0U)
  10932. #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
  10933. #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
  10934. #define SAI_xIMR_MUTEDETIE_Pos (1U)
  10935. #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
  10936. #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
  10937. #define SAI_xIMR_WCKCFGIE_Pos (2U)
  10938. #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
  10939. #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
  10940. #define SAI_xIMR_FREQIE_Pos (3U)
  10941. #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
  10942. #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
  10943. #define SAI_xIMR_CNRDYIE_Pos (4U)
  10944. #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
  10945. #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
  10946. #define SAI_xIMR_AFSDETIE_Pos (5U)
  10947. #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
  10948. #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
  10949. #define SAI_xIMR_LFSDETIE_Pos (6U)
  10950. #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
  10951. #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
  10952. /******************** Bit definition for SAI_xSR register *******************/
  10953. #define SAI_xSR_OVRUDR_Pos (0U)
  10954. #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
  10955. #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
  10956. #define SAI_xSR_MUTEDET_Pos (1U)
  10957. #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
  10958. #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
  10959. #define SAI_xSR_WCKCFG_Pos (2U)
  10960. #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
  10961. #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
  10962. #define SAI_xSR_FREQ_Pos (3U)
  10963. #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
  10964. #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
  10965. #define SAI_xSR_CNRDY_Pos (4U)
  10966. #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
  10967. #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
  10968. #define SAI_xSR_AFSDET_Pos (5U)
  10969. #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
  10970. #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
  10971. #define SAI_xSR_LFSDET_Pos (6U)
  10972. #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
  10973. #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
  10974. #define SAI_xSR_FLVL_Pos (16U)
  10975. #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
  10976. #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
  10977. #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
  10978. #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
  10979. #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
  10980. /****************** Bit definition for SAI_xCLRFR register ******************/
  10981. #define SAI_xCLRFR_COVRUDR_Pos (0U)
  10982. #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
  10983. #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
  10984. #define SAI_xCLRFR_CMUTEDET_Pos (1U)
  10985. #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
  10986. #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
  10987. #define SAI_xCLRFR_CWCKCFG_Pos (2U)
  10988. #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
  10989. #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
  10990. #define SAI_xCLRFR_CFREQ_Pos (3U)
  10991. #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
  10992. #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
  10993. #define SAI_xCLRFR_CCNRDY_Pos (4U)
  10994. #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
  10995. #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
  10996. #define SAI_xCLRFR_CAFSDET_Pos (5U)
  10997. #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
  10998. #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
  10999. #define SAI_xCLRFR_CLFSDET_Pos (6U)
  11000. #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
  11001. #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
  11002. /****************** Bit definition for SAI_xDR register ******************/
  11003. #define SAI_xDR_DATA_Pos (0U)
  11004. #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
  11005. #define SAI_xDR_DATA SAI_xDR_DATA_Msk
  11006. /******************************************************************************/
  11007. /* */
  11008. /* SD host Interface */
  11009. /* */
  11010. /******************************************************************************/
  11011. /****************** Bit definition for SDIO_POWER register ******************/
  11012. #define SDIO_POWER_PWRCTRL_Pos (0U)
  11013. #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
  11014. #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
  11015. #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
  11016. #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
  11017. /****************** Bit definition for SDIO_CLKCR register ******************/
  11018. #define SDIO_CLKCR_CLKDIV_Pos (0U)
  11019. #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
  11020. #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
  11021. #define SDIO_CLKCR_CLKEN_Pos (8U)
  11022. #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
  11023. #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
  11024. #define SDIO_CLKCR_PWRSAV_Pos (9U)
  11025. #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
  11026. #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
  11027. #define SDIO_CLKCR_BYPASS_Pos (10U)
  11028. #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
  11029. #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
  11030. #define SDIO_CLKCR_WIDBUS_Pos (11U)
  11031. #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
  11032. #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
  11033. #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
  11034. #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
  11035. #define SDIO_CLKCR_NEGEDGE_Pos (13U)
  11036. #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
  11037. #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
  11038. #define SDIO_CLKCR_HWFC_EN_Pos (14U)
  11039. #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
  11040. #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
  11041. /******************* Bit definition for SDIO_ARG register *******************/
  11042. #define SDIO_ARG_CMDARG_Pos (0U)
  11043. #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
  11044. #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
  11045. /******************* Bit definition for SDIO_CMD register *******************/
  11046. #define SDIO_CMD_CMDINDEX_Pos (0U)
  11047. #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
  11048. #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
  11049. #define SDIO_CMD_WAITRESP_Pos (6U)
  11050. #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
  11051. #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
  11052. #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
  11053. #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
  11054. #define SDIO_CMD_WAITINT_Pos (8U)
  11055. #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
  11056. #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
  11057. #define SDIO_CMD_WAITPEND_Pos (9U)
  11058. #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
  11059. #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
  11060. #define SDIO_CMD_CPSMEN_Pos (10U)
  11061. #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
  11062. #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
  11063. #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
  11064. #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
  11065. #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
  11066. /***************** Bit definition for SDIO_RESPCMD register *****************/
  11067. #define SDIO_RESPCMD_RESPCMD_Pos (0U)
  11068. #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
  11069. #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
  11070. /****************** Bit definition for SDIO_RESP0 register ******************/
  11071. #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
  11072. #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
  11073. #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
  11074. /****************** Bit definition for SDIO_RESP1 register ******************/
  11075. #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
  11076. #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
  11077. #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
  11078. /****************** Bit definition for SDIO_RESP2 register ******************/
  11079. #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
  11080. #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
  11081. #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
  11082. /****************** Bit definition for SDIO_RESP3 register ******************/
  11083. #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
  11084. #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
  11085. #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
  11086. /****************** Bit definition for SDIO_RESP4 register ******************/
  11087. #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
  11088. #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
  11089. #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
  11090. /****************** Bit definition for SDIO_DTIMER register *****************/
  11091. #define SDIO_DTIMER_DATATIME_Pos (0U)
  11092. #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
  11093. #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
  11094. /****************** Bit definition for SDIO_DLEN register *******************/
  11095. #define SDIO_DLEN_DATALENGTH_Pos (0U)
  11096. #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
  11097. #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
  11098. /****************** Bit definition for SDIO_DCTRL register ******************/
  11099. #define SDIO_DCTRL_DTEN_Pos (0U)
  11100. #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
  11101. #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
  11102. #define SDIO_DCTRL_DTDIR_Pos (1U)
  11103. #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
  11104. #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
  11105. #define SDIO_DCTRL_DTMODE_Pos (2U)
  11106. #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
  11107. #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
  11108. #define SDIO_DCTRL_DMAEN_Pos (3U)
  11109. #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
  11110. #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
  11111. #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
  11112. #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
  11113. #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
  11114. #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
  11115. #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
  11116. #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
  11117. #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
  11118. #define SDIO_DCTRL_RWSTART_Pos (8U)
  11119. #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
  11120. #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
  11121. #define SDIO_DCTRL_RWSTOP_Pos (9U)
  11122. #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
  11123. #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
  11124. #define SDIO_DCTRL_RWMOD_Pos (10U)
  11125. #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
  11126. #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
  11127. #define SDIO_DCTRL_SDIOEN_Pos (11U)
  11128. #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
  11129. #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
  11130. /****************** Bit definition for SDIO_DCOUNT register *****************/
  11131. #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
  11132. #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
  11133. #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
  11134. /****************** Bit definition for SDIO_STA register ********************/
  11135. #define SDIO_STA_CCRCFAIL_Pos (0U)
  11136. #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
  11137. #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
  11138. #define SDIO_STA_DCRCFAIL_Pos (1U)
  11139. #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
  11140. #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
  11141. #define SDIO_STA_CTIMEOUT_Pos (2U)
  11142. #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
  11143. #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
  11144. #define SDIO_STA_DTIMEOUT_Pos (3U)
  11145. #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
  11146. #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
  11147. #define SDIO_STA_TXUNDERR_Pos (4U)
  11148. #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
  11149. #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
  11150. #define SDIO_STA_RXOVERR_Pos (5U)
  11151. #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
  11152. #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
  11153. #define SDIO_STA_CMDREND_Pos (6U)
  11154. #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
  11155. #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
  11156. #define SDIO_STA_CMDSENT_Pos (7U)
  11157. #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
  11158. #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
  11159. #define SDIO_STA_DATAEND_Pos (8U)
  11160. #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
  11161. #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
  11162. #define SDIO_STA_DBCKEND_Pos (10U)
  11163. #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
  11164. #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
  11165. #define SDIO_STA_CMDACT_Pos (11U)
  11166. #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
  11167. #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
  11168. #define SDIO_STA_TXACT_Pos (12U)
  11169. #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
  11170. #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
  11171. #define SDIO_STA_RXACT_Pos (13U)
  11172. #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
  11173. #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
  11174. #define SDIO_STA_TXFIFOHE_Pos (14U)
  11175. #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
  11176. #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
  11177. #define SDIO_STA_RXFIFOHF_Pos (15U)
  11178. #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
  11179. #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
  11180. #define SDIO_STA_TXFIFOF_Pos (16U)
  11181. #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
  11182. #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
  11183. #define SDIO_STA_RXFIFOF_Pos (17U)
  11184. #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
  11185. #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
  11186. #define SDIO_STA_TXFIFOE_Pos (18U)
  11187. #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
  11188. #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
  11189. #define SDIO_STA_RXFIFOE_Pos (19U)
  11190. #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
  11191. #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
  11192. #define SDIO_STA_TXDAVL_Pos (20U)
  11193. #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
  11194. #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
  11195. #define SDIO_STA_RXDAVL_Pos (21U)
  11196. #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
  11197. #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
  11198. #define SDIO_STA_SDIOIT_Pos (22U)
  11199. #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
  11200. #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
  11201. /******************* Bit definition for SDIO_ICR register *******************/
  11202. #define SDIO_ICR_CCRCFAILC_Pos (0U)
  11203. #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
  11204. #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
  11205. #define SDIO_ICR_DCRCFAILC_Pos (1U)
  11206. #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
  11207. #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
  11208. #define SDIO_ICR_CTIMEOUTC_Pos (2U)
  11209. #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
  11210. #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
  11211. #define SDIO_ICR_DTIMEOUTC_Pos (3U)
  11212. #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
  11213. #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
  11214. #define SDIO_ICR_TXUNDERRC_Pos (4U)
  11215. #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
  11216. #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
  11217. #define SDIO_ICR_RXOVERRC_Pos (5U)
  11218. #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
  11219. #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
  11220. #define SDIO_ICR_CMDRENDC_Pos (6U)
  11221. #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
  11222. #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
  11223. #define SDIO_ICR_CMDSENTC_Pos (7U)
  11224. #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
  11225. #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
  11226. #define SDIO_ICR_DATAENDC_Pos (8U)
  11227. #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
  11228. #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
  11229. #define SDIO_ICR_DBCKENDC_Pos (10U)
  11230. #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
  11231. #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
  11232. #define SDIO_ICR_SDIOITC_Pos (22U)
  11233. #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
  11234. #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
  11235. /****************** Bit definition for SDIO_MASK register *******************/
  11236. #define SDIO_MASK_CCRCFAILIE_Pos (0U)
  11237. #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
  11238. #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
  11239. #define SDIO_MASK_DCRCFAILIE_Pos (1U)
  11240. #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
  11241. #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
  11242. #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
  11243. #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
  11244. #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
  11245. #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
  11246. #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
  11247. #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
  11248. #define SDIO_MASK_TXUNDERRIE_Pos (4U)
  11249. #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
  11250. #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
  11251. #define SDIO_MASK_RXOVERRIE_Pos (5U)
  11252. #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
  11253. #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
  11254. #define SDIO_MASK_CMDRENDIE_Pos (6U)
  11255. #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
  11256. #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
  11257. #define SDIO_MASK_CMDSENTIE_Pos (7U)
  11258. #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
  11259. #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
  11260. #define SDIO_MASK_DATAENDIE_Pos (8U)
  11261. #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
  11262. #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
  11263. #define SDIO_MASK_DBCKENDIE_Pos (10U)
  11264. #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
  11265. #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
  11266. #define SDIO_MASK_CMDACTIE_Pos (11U)
  11267. #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
  11268. #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
  11269. #define SDIO_MASK_TXACTIE_Pos (12U)
  11270. #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
  11271. #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
  11272. #define SDIO_MASK_RXACTIE_Pos (13U)
  11273. #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
  11274. #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
  11275. #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
  11276. #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
  11277. #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
  11278. #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
  11279. #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
  11280. #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
  11281. #define SDIO_MASK_TXFIFOFIE_Pos (16U)
  11282. #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
  11283. #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
  11284. #define SDIO_MASK_RXFIFOFIE_Pos (17U)
  11285. #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
  11286. #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
  11287. #define SDIO_MASK_TXFIFOEIE_Pos (18U)
  11288. #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
  11289. #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
  11290. #define SDIO_MASK_RXFIFOEIE_Pos (19U)
  11291. #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
  11292. #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
  11293. #define SDIO_MASK_TXDAVLIE_Pos (20U)
  11294. #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
  11295. #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
  11296. #define SDIO_MASK_RXDAVLIE_Pos (21U)
  11297. #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
  11298. #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
  11299. #define SDIO_MASK_SDIOITIE_Pos (22U)
  11300. #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
  11301. #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
  11302. /***************** Bit definition for SDIO_FIFOCNT register *****************/
  11303. #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
  11304. #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
  11305. #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
  11306. /****************** Bit definition for SDIO_FIFO register *******************/
  11307. #define SDIO_FIFO_FIFODATA_Pos (0U)
  11308. #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
  11309. #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
  11310. /******************************************************************************/
  11311. /* */
  11312. /* Serial Peripheral Interface */
  11313. /* */
  11314. /******************************************************************************/
  11315. #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
  11316. #define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
  11317. /******************* Bit definition for SPI_CR1 register ********************/
  11318. #define SPI_CR1_CPHA_Pos (0U)
  11319. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  11320. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  11321. #define SPI_CR1_CPOL_Pos (1U)
  11322. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  11323. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  11324. #define SPI_CR1_MSTR_Pos (2U)
  11325. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  11326. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  11327. #define SPI_CR1_BR_Pos (3U)
  11328. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  11329. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  11330. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  11331. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  11332. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  11333. #define SPI_CR1_SPE_Pos (6U)
  11334. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  11335. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  11336. #define SPI_CR1_LSBFIRST_Pos (7U)
  11337. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  11338. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  11339. #define SPI_CR1_SSI_Pos (8U)
  11340. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  11341. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  11342. #define SPI_CR1_SSM_Pos (9U)
  11343. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  11344. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  11345. #define SPI_CR1_RXONLY_Pos (10U)
  11346. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  11347. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  11348. #define SPI_CR1_DFF_Pos (11U)
  11349. #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
  11350. #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
  11351. #define SPI_CR1_CRCNEXT_Pos (12U)
  11352. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  11353. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  11354. #define SPI_CR1_CRCEN_Pos (13U)
  11355. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  11356. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  11357. #define SPI_CR1_BIDIOE_Pos (14U)
  11358. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  11359. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  11360. #define SPI_CR1_BIDIMODE_Pos (15U)
  11361. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  11362. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  11363. /******************* Bit definition for SPI_CR2 register ********************/
  11364. #define SPI_CR2_RXDMAEN_Pos (0U)
  11365. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  11366. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
  11367. #define SPI_CR2_TXDMAEN_Pos (1U)
  11368. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  11369. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
  11370. #define SPI_CR2_SSOE_Pos (2U)
  11371. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  11372. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
  11373. #define SPI_CR2_FRF_Pos (4U)
  11374. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  11375. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
  11376. #define SPI_CR2_ERRIE_Pos (5U)
  11377. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  11378. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
  11379. #define SPI_CR2_RXNEIE_Pos (6U)
  11380. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  11381. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
  11382. #define SPI_CR2_TXEIE_Pos (7U)
  11383. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  11384. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
  11385. /******************** Bit definition for SPI_SR register ********************/
  11386. #define SPI_SR_RXNE_Pos (0U)
  11387. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  11388. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
  11389. #define SPI_SR_TXE_Pos (1U)
  11390. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  11391. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
  11392. #define SPI_SR_CHSIDE_Pos (2U)
  11393. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  11394. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
  11395. #define SPI_SR_UDR_Pos (3U)
  11396. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  11397. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
  11398. #define SPI_SR_CRCERR_Pos (4U)
  11399. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  11400. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
  11401. #define SPI_SR_MODF_Pos (5U)
  11402. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  11403. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
  11404. #define SPI_SR_OVR_Pos (6U)
  11405. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  11406. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
  11407. #define SPI_SR_BSY_Pos (7U)
  11408. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  11409. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
  11410. #define SPI_SR_FRE_Pos (8U)
  11411. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  11412. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
  11413. /******************** Bit definition for SPI_DR register ********************/
  11414. #define SPI_DR_DR_Pos (0U)
  11415. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  11416. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  11417. /******************* Bit definition for SPI_CRCPR register ******************/
  11418. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  11419. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  11420. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  11421. /****************** Bit definition for SPI_RXCRCR register ******************/
  11422. #define SPI_RXCRCR_RXCRC_Pos (0U)
  11423. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  11424. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  11425. /****************** Bit definition for SPI_TXCRCR register ******************/
  11426. #define SPI_TXCRCR_TXCRC_Pos (0U)
  11427. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  11428. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  11429. /****************** Bit definition for SPI_I2SCFGR register *****************/
  11430. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  11431. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  11432. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  11433. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  11434. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  11435. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  11436. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  11437. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  11438. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  11439. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  11440. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  11441. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  11442. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  11443. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  11444. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  11445. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  11446. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  11447. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  11448. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  11449. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  11450. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  11451. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  11452. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  11453. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  11454. #define SPI_I2SCFGR_I2SE_Pos (10U)
  11455. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  11456. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  11457. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  11458. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  11459. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  11460. #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
  11461. #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
  11462. #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
  11463. /****************** Bit definition for SPI_I2SPR register *******************/
  11464. #define SPI_I2SPR_I2SDIV_Pos (0U)
  11465. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  11466. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  11467. #define SPI_I2SPR_ODD_Pos (8U)
  11468. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  11469. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  11470. #define SPI_I2SPR_MCKOE_Pos (9U)
  11471. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  11472. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  11473. /******************************************************************************/
  11474. /* */
  11475. /* SYSCFG */
  11476. /* */
  11477. /******************************************************************************/
  11478. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  11479. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  11480. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
  11481. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  11482. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  11483. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  11484. /****************** Bit definition for SYSCFG_PMC register ******************/
  11485. #define SYSCFG_PMC_ADC1DC2_Pos (16U)
  11486. #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
  11487. #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  11488. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  11489. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  11490. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  11491. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  11492. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  11493. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  11494. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  11495. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  11496. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  11497. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  11498. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  11499. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  11500. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  11501. /**
  11502. * @brief EXTI0 configuration
  11503. */
  11504. #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
  11505. #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
  11506. #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
  11507. #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
  11508. #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
  11509. #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
  11510. #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
  11511. #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
  11512. /**
  11513. * @brief EXTI1 configuration
  11514. */
  11515. #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
  11516. #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
  11517. #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
  11518. #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
  11519. #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
  11520. #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
  11521. #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
  11522. #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
  11523. /**
  11524. * @brief EXTI2 configuration
  11525. */
  11526. #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
  11527. #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
  11528. #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
  11529. #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
  11530. #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
  11531. #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
  11532. #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
  11533. #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
  11534. /**
  11535. * @brief EXTI3 configuration
  11536. */
  11537. #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
  11538. #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
  11539. #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
  11540. #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
  11541. #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
  11542. #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
  11543. #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
  11544. #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
  11545. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  11546. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  11547. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  11548. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  11549. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  11550. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  11551. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  11552. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  11553. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  11554. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  11555. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  11556. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  11557. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  11558. /**
  11559. * @brief EXTI4 configuration
  11560. */
  11561. #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
  11562. #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
  11563. #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
  11564. #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
  11565. #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
  11566. #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
  11567. #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
  11568. #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
  11569. /**
  11570. * @brief EXTI5 configuration
  11571. */
  11572. #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
  11573. #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
  11574. #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
  11575. #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
  11576. #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
  11577. #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
  11578. #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
  11579. #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
  11580. /**
  11581. * @brief EXTI6 configuration
  11582. */
  11583. #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
  11584. #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
  11585. #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
  11586. #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
  11587. #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
  11588. #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
  11589. #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
  11590. #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
  11591. /**
  11592. * @brief EXTI7 configuration
  11593. */
  11594. #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
  11595. #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
  11596. #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
  11597. #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
  11598. #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
  11599. #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
  11600. #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
  11601. #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
  11602. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  11603. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  11604. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  11605. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  11606. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  11607. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  11608. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  11609. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  11610. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  11611. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  11612. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  11613. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  11614. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  11615. /**
  11616. * @brief EXTI8 configuration
  11617. */
  11618. #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
  11619. #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
  11620. #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
  11621. #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
  11622. #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
  11623. #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
  11624. #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
  11625. #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
  11626. /**
  11627. * @brief EXTI9 configuration
  11628. */
  11629. #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
  11630. #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
  11631. #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
  11632. #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
  11633. #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
  11634. #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
  11635. #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
  11636. #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
  11637. /**
  11638. * @brief EXTI10 configuration
  11639. */
  11640. #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
  11641. #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
  11642. #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
  11643. #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
  11644. #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
  11645. #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
  11646. #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
  11647. #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
  11648. /**
  11649. * @brief EXTI11 configuration
  11650. */
  11651. #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
  11652. #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
  11653. #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
  11654. #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
  11655. #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
  11656. #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
  11657. #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
  11658. #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
  11659. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  11660. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  11661. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  11662. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  11663. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  11664. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  11665. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  11666. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  11667. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  11668. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  11669. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  11670. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  11671. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  11672. /**
  11673. * @brief EXTI12 configuration
  11674. */
  11675. #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
  11676. #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
  11677. #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
  11678. #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
  11679. #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
  11680. #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
  11681. #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
  11682. #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
  11683. /**
  11684. * @brief EXTI13 configuration
  11685. */
  11686. #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
  11687. #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
  11688. #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
  11689. #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
  11690. #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
  11691. #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
  11692. #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
  11693. #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
  11694. /**
  11695. * @brief EXTI14 configuration
  11696. */
  11697. #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
  11698. #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
  11699. #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
  11700. #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
  11701. #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
  11702. #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
  11703. #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
  11704. #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
  11705. /**
  11706. * @brief EXTI15 configuration
  11707. */
  11708. #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
  11709. #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
  11710. #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
  11711. #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
  11712. #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
  11713. #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
  11714. #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
  11715. #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
  11716. /****************** Bit definition for SYSCFG_CMPCR register ****************/
  11717. #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
  11718. #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
  11719. #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
  11720. #define SYSCFG_CMPCR_READY_Pos (8U)
  11721. #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
  11722. #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
  11723. /****************** Bit definition for SYSCFG_CFGR register *****************/
  11724. #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
  11725. #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
  11726. #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
  11727. #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
  11728. #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
  11729. #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
  11730. /****************** Bit definition for SYSCFG_CFGR2 register *****************/
  11731. #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
  11732. #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
  11733. #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
  11734. #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
  11735. #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
  11736. #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
  11737. /****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
  11738. #define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
  11739. #define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */
  11740. #define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk /*!<Bitstream clock source selection */
  11741. #define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
  11742. #define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */
  11743. #define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk /*!<MCHDLY clock enable for DFSDM1 */
  11744. #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
  11745. #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */
  11746. #define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM1 */
  11747. #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
  11748. #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */
  11749. #define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM1 */
  11750. #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
  11751. #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */
  11752. #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */
  11753. #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
  11754. #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */
  11755. #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */
  11756. #define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
  11757. #define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */
  11758. #define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk /*!<Source selection for DFSDM1 */
  11759. #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
  11760. #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */
  11761. #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk /*!<Source selection for 1_CKOUT */
  11762. #define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
  11763. #define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */
  11764. #define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk /*!<MCHDLY clock enable for DFSDM2 */
  11765. #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
  11766. #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */
  11767. #define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk /*!<Source selection for DatIn0 for DFSDM2 */
  11768. #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
  11769. #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */
  11770. #define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk /*!<Source selection for DatIn2 for DFSDM2 */
  11771. #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
  11772. #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */
  11773. #define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk /*!<Source selection for DatIn4 for DFSDM2 */
  11774. #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
  11775. #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */
  11776. #define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk /*!<Source selection for DatIn6 for DFSDM2 */
  11777. #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
  11778. #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */
  11779. #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */
  11780. #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
  11781. #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */
  11782. #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */
  11783. #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
  11784. #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */
  11785. #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2 */
  11786. #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
  11787. #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */
  11788. #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */
  11789. #define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
  11790. #define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */
  11791. #define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk /*!<Source selection for DFSDM2 */
  11792. #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
  11793. #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */
  11794. #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk /*!<Source selection for 2_CKOUT */
  11795. /******************************************************************************/
  11796. /* */
  11797. /* TIM */
  11798. /* */
  11799. /******************************************************************************/
  11800. /******************* Bit definition for TIM_CR1 register ********************/
  11801. #define TIM_CR1_CEN_Pos (0U)
  11802. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  11803. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  11804. #define TIM_CR1_UDIS_Pos (1U)
  11805. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  11806. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  11807. #define TIM_CR1_URS_Pos (2U)
  11808. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  11809. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  11810. #define TIM_CR1_OPM_Pos (3U)
  11811. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  11812. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  11813. #define TIM_CR1_DIR_Pos (4U)
  11814. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  11815. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  11816. #define TIM_CR1_CMS_Pos (5U)
  11817. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  11818. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  11819. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
  11820. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
  11821. #define TIM_CR1_ARPE_Pos (7U)
  11822. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  11823. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  11824. #define TIM_CR1_CKD_Pos (8U)
  11825. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  11826. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  11827. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
  11828. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
  11829. /******************* Bit definition for TIM_CR2 register ********************/
  11830. #define TIM_CR2_CCPC_Pos (0U)
  11831. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  11832. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  11833. #define TIM_CR2_CCUS_Pos (2U)
  11834. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  11835. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  11836. #define TIM_CR2_CCDS_Pos (3U)
  11837. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  11838. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  11839. #define TIM_CR2_MMS_Pos (4U)
  11840. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  11841. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  11842. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
  11843. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
  11844. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
  11845. #define TIM_CR2_TI1S_Pos (7U)
  11846. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  11847. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  11848. #define TIM_CR2_OIS1_Pos (8U)
  11849. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  11850. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  11851. #define TIM_CR2_OIS1N_Pos (9U)
  11852. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  11853. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  11854. #define TIM_CR2_OIS2_Pos (10U)
  11855. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  11856. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  11857. #define TIM_CR2_OIS2N_Pos (11U)
  11858. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  11859. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  11860. #define TIM_CR2_OIS3_Pos (12U)
  11861. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  11862. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  11863. #define TIM_CR2_OIS3N_Pos (13U)
  11864. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  11865. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  11866. #define TIM_CR2_OIS4_Pos (14U)
  11867. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  11868. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  11869. /******************* Bit definition for TIM_SMCR register *******************/
  11870. #define TIM_SMCR_SMS_Pos (0U)
  11871. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  11872. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  11873. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
  11874. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
  11875. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
  11876. #define TIM_SMCR_TS_Pos (4U)
  11877. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  11878. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  11879. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
  11880. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
  11881. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
  11882. #define TIM_SMCR_MSM_Pos (7U)
  11883. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  11884. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  11885. #define TIM_SMCR_ETF_Pos (8U)
  11886. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  11887. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  11888. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
  11889. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
  11890. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
  11891. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
  11892. #define TIM_SMCR_ETPS_Pos (12U)
  11893. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  11894. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  11895. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
  11896. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
  11897. #define TIM_SMCR_ECE_Pos (14U)
  11898. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  11899. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  11900. #define TIM_SMCR_ETP_Pos (15U)
  11901. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  11902. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  11903. /******************* Bit definition for TIM_DIER register *******************/
  11904. #define TIM_DIER_UIE_Pos (0U)
  11905. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  11906. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  11907. #define TIM_DIER_CC1IE_Pos (1U)
  11908. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  11909. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  11910. #define TIM_DIER_CC2IE_Pos (2U)
  11911. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  11912. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  11913. #define TIM_DIER_CC3IE_Pos (3U)
  11914. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  11915. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  11916. #define TIM_DIER_CC4IE_Pos (4U)
  11917. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  11918. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  11919. #define TIM_DIER_COMIE_Pos (5U)
  11920. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  11921. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  11922. #define TIM_DIER_TIE_Pos (6U)
  11923. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  11924. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  11925. #define TIM_DIER_BIE_Pos (7U)
  11926. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  11927. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  11928. #define TIM_DIER_UDE_Pos (8U)
  11929. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  11930. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  11931. #define TIM_DIER_CC1DE_Pos (9U)
  11932. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  11933. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  11934. #define TIM_DIER_CC2DE_Pos (10U)
  11935. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  11936. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  11937. #define TIM_DIER_CC3DE_Pos (11U)
  11938. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  11939. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  11940. #define TIM_DIER_CC4DE_Pos (12U)
  11941. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  11942. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  11943. #define TIM_DIER_COMDE_Pos (13U)
  11944. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  11945. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  11946. #define TIM_DIER_TDE_Pos (14U)
  11947. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  11948. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  11949. /******************** Bit definition for TIM_SR register ********************/
  11950. #define TIM_SR_UIF_Pos (0U)
  11951. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  11952. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  11953. #define TIM_SR_CC1IF_Pos (1U)
  11954. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  11955. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  11956. #define TIM_SR_CC2IF_Pos (2U)
  11957. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  11958. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  11959. #define TIM_SR_CC3IF_Pos (3U)
  11960. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  11961. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  11962. #define TIM_SR_CC4IF_Pos (4U)
  11963. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  11964. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  11965. #define TIM_SR_COMIF_Pos (5U)
  11966. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  11967. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  11968. #define TIM_SR_TIF_Pos (6U)
  11969. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  11970. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  11971. #define TIM_SR_BIF_Pos (7U)
  11972. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  11973. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  11974. #define TIM_SR_CC1OF_Pos (9U)
  11975. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  11976. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  11977. #define TIM_SR_CC2OF_Pos (10U)
  11978. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  11979. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  11980. #define TIM_SR_CC3OF_Pos (11U)
  11981. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  11982. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  11983. #define TIM_SR_CC4OF_Pos (12U)
  11984. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  11985. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  11986. /******************* Bit definition for TIM_EGR register ********************/
  11987. #define TIM_EGR_UG_Pos (0U)
  11988. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  11989. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  11990. #define TIM_EGR_CC1G_Pos (1U)
  11991. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  11992. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  11993. #define TIM_EGR_CC2G_Pos (2U)
  11994. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  11995. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  11996. #define TIM_EGR_CC3G_Pos (3U)
  11997. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  11998. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  11999. #define TIM_EGR_CC4G_Pos (4U)
  12000. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  12001. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  12002. #define TIM_EGR_COMG_Pos (5U)
  12003. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  12004. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  12005. #define TIM_EGR_TG_Pos (6U)
  12006. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  12007. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  12008. #define TIM_EGR_BG_Pos (7U)
  12009. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  12010. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  12011. /****************** Bit definition for TIM_CCMR1 register *******************/
  12012. #define TIM_CCMR1_CC1S_Pos (0U)
  12013. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  12014. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  12015. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
  12016. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
  12017. #define TIM_CCMR1_OC1FE_Pos (2U)
  12018. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  12019. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  12020. #define TIM_CCMR1_OC1PE_Pos (3U)
  12021. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  12022. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  12023. #define TIM_CCMR1_OC1M_Pos (4U)
  12024. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  12025. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  12026. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
  12027. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
  12028. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
  12029. #define TIM_CCMR1_OC1CE_Pos (7U)
  12030. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  12031. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  12032. #define TIM_CCMR1_CC2S_Pos (8U)
  12033. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  12034. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  12035. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
  12036. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
  12037. #define TIM_CCMR1_OC2FE_Pos (10U)
  12038. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  12039. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  12040. #define TIM_CCMR1_OC2PE_Pos (11U)
  12041. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  12042. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  12043. #define TIM_CCMR1_OC2M_Pos (12U)
  12044. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  12045. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  12046. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
  12047. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
  12048. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
  12049. #define TIM_CCMR1_OC2CE_Pos (15U)
  12050. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  12051. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  12052. /*----------------------------------------------------------------------------*/
  12053. #define TIM_CCMR1_IC1PSC_Pos (2U)
  12054. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  12055. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  12056. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
  12057. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
  12058. #define TIM_CCMR1_IC1F_Pos (4U)
  12059. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  12060. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  12061. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
  12062. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
  12063. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
  12064. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
  12065. #define TIM_CCMR1_IC2PSC_Pos (10U)
  12066. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  12067. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  12068. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
  12069. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
  12070. #define TIM_CCMR1_IC2F_Pos (12U)
  12071. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  12072. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  12073. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
  12074. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
  12075. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
  12076. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
  12077. /****************** Bit definition for TIM_CCMR2 register *******************/
  12078. #define TIM_CCMR2_CC3S_Pos (0U)
  12079. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  12080. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  12081. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
  12082. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
  12083. #define TIM_CCMR2_OC3FE_Pos (2U)
  12084. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  12085. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  12086. #define TIM_CCMR2_OC3PE_Pos (3U)
  12087. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  12088. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  12089. #define TIM_CCMR2_OC3M_Pos (4U)
  12090. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  12091. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  12092. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
  12093. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
  12094. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
  12095. #define TIM_CCMR2_OC3CE_Pos (7U)
  12096. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  12097. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  12098. #define TIM_CCMR2_CC4S_Pos (8U)
  12099. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  12100. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  12101. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
  12102. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
  12103. #define TIM_CCMR2_OC4FE_Pos (10U)
  12104. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  12105. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  12106. #define TIM_CCMR2_OC4PE_Pos (11U)
  12107. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  12108. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  12109. #define TIM_CCMR2_OC4M_Pos (12U)
  12110. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  12111. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  12112. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
  12113. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
  12114. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
  12115. #define TIM_CCMR2_OC4CE_Pos (15U)
  12116. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  12117. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  12118. /*----------------------------------------------------------------------------*/
  12119. #define TIM_CCMR2_IC3PSC_Pos (2U)
  12120. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  12121. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  12122. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
  12123. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
  12124. #define TIM_CCMR2_IC3F_Pos (4U)
  12125. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  12126. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  12127. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
  12128. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
  12129. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
  12130. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
  12131. #define TIM_CCMR2_IC4PSC_Pos (10U)
  12132. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  12133. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  12134. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
  12135. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
  12136. #define TIM_CCMR2_IC4F_Pos (12U)
  12137. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  12138. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  12139. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
  12140. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
  12141. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
  12142. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
  12143. /******************* Bit definition for TIM_CCER register *******************/
  12144. #define TIM_CCER_CC1E_Pos (0U)
  12145. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  12146. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  12147. #define TIM_CCER_CC1P_Pos (1U)
  12148. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  12149. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  12150. #define TIM_CCER_CC1NE_Pos (2U)
  12151. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  12152. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  12153. #define TIM_CCER_CC1NP_Pos (3U)
  12154. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  12155. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  12156. #define TIM_CCER_CC2E_Pos (4U)
  12157. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  12158. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  12159. #define TIM_CCER_CC2P_Pos (5U)
  12160. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  12161. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  12162. #define TIM_CCER_CC2NE_Pos (6U)
  12163. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  12164. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  12165. #define TIM_CCER_CC2NP_Pos (7U)
  12166. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  12167. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  12168. #define TIM_CCER_CC3E_Pos (8U)
  12169. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  12170. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  12171. #define TIM_CCER_CC3P_Pos (9U)
  12172. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  12173. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  12174. #define TIM_CCER_CC3NE_Pos (10U)
  12175. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  12176. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  12177. #define TIM_CCER_CC3NP_Pos (11U)
  12178. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  12179. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  12180. #define TIM_CCER_CC4E_Pos (12U)
  12181. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  12182. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  12183. #define TIM_CCER_CC4P_Pos (13U)
  12184. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  12185. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  12186. #define TIM_CCER_CC4NP_Pos (15U)
  12187. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  12188. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  12189. /******************* Bit definition for TIM_CNT register ********************/
  12190. #define TIM_CNT_CNT_Pos (0U)
  12191. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  12192. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  12193. /******************* Bit definition for TIM_PSC register ********************/
  12194. #define TIM_PSC_PSC_Pos (0U)
  12195. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  12196. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  12197. /******************* Bit definition for TIM_ARR register ********************/
  12198. #define TIM_ARR_ARR_Pos (0U)
  12199. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  12200. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  12201. /******************* Bit definition for TIM_RCR register ********************/
  12202. #define TIM_RCR_REP_Pos (0U)
  12203. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  12204. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  12205. /******************* Bit definition for TIM_CCR1 register *******************/
  12206. #define TIM_CCR1_CCR1_Pos (0U)
  12207. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  12208. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  12209. /******************* Bit definition for TIM_CCR2 register *******************/
  12210. #define TIM_CCR2_CCR2_Pos (0U)
  12211. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  12212. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  12213. /******************* Bit definition for TIM_CCR3 register *******************/
  12214. #define TIM_CCR3_CCR3_Pos (0U)
  12215. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  12216. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  12217. /******************* Bit definition for TIM_CCR4 register *******************/
  12218. #define TIM_CCR4_CCR4_Pos (0U)
  12219. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  12220. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  12221. /******************* Bit definition for TIM_BDTR register *******************/
  12222. #define TIM_BDTR_DTG_Pos (0U)
  12223. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  12224. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  12225. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
  12226. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
  12227. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
  12228. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
  12229. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
  12230. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
  12231. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
  12232. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
  12233. #define TIM_BDTR_LOCK_Pos (8U)
  12234. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  12235. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  12236. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
  12237. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
  12238. #define TIM_BDTR_OSSI_Pos (10U)
  12239. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  12240. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  12241. #define TIM_BDTR_OSSR_Pos (11U)
  12242. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  12243. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  12244. #define TIM_BDTR_BKE_Pos (12U)
  12245. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  12246. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  12247. #define TIM_BDTR_BKP_Pos (13U)
  12248. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  12249. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  12250. #define TIM_BDTR_AOE_Pos (14U)
  12251. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  12252. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  12253. #define TIM_BDTR_MOE_Pos (15U)
  12254. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  12255. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  12256. /******************* Bit definition for TIM_DCR register ********************/
  12257. #define TIM_DCR_DBA_Pos (0U)
  12258. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  12259. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  12260. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
  12261. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
  12262. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
  12263. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
  12264. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
  12265. #define TIM_DCR_DBL_Pos (8U)
  12266. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  12267. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  12268. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
  12269. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
  12270. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
  12271. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
  12272. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
  12273. /******************* Bit definition for TIM_DMAR register *******************/
  12274. #define TIM_DMAR_DMAB_Pos (0U)
  12275. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  12276. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  12277. /******************* Bit definition for TIM_OR register *********************/
  12278. #define TIM_OR_TI1_RMP_Pos (0U)
  12279. #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  12280. #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
  12281. #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  12282. #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  12283. #define TIM_OR_TI4_RMP_Pos (6U)
  12284. #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
  12285. #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
  12286. #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
  12287. #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
  12288. #define TIM_OR_ITR1_RMP_Pos (10U)
  12289. #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
  12290. #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
  12291. #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
  12292. #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
  12293. /******************************************************************************/
  12294. /* */
  12295. /* Low Power Timer (LPTIM) */
  12296. /* */
  12297. /******************************************************************************/
  12298. /****************** Bit definition for LPTIM_ISR register *******************/
  12299. #define LPTIM_ISR_CMPM_Pos (0U)
  12300. #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
  12301. #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
  12302. #define LPTIM_ISR_ARRM_Pos (1U)
  12303. #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
  12304. #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
  12305. #define LPTIM_ISR_EXTTRIG_Pos (2U)
  12306. #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
  12307. #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
  12308. #define LPTIM_ISR_CMPOK_Pos (3U)
  12309. #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
  12310. #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
  12311. #define LPTIM_ISR_ARROK_Pos (4U)
  12312. #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
  12313. #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
  12314. #define LPTIM_ISR_UP_Pos (5U)
  12315. #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
  12316. #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
  12317. #define LPTIM_ISR_DOWN_Pos (6U)
  12318. #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
  12319. #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
  12320. /****************** Bit definition for LPTIM_ICR register *******************/
  12321. #define LPTIM_ICR_CMPMCF_Pos (0U)
  12322. #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
  12323. #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
  12324. #define LPTIM_ICR_ARRMCF_Pos (1U)
  12325. #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
  12326. #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
  12327. #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
  12328. #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
  12329. #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
  12330. #define LPTIM_ICR_CMPOKCF_Pos (3U)
  12331. #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
  12332. #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
  12333. #define LPTIM_ICR_ARROKCF_Pos (4U)
  12334. #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
  12335. #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
  12336. #define LPTIM_ICR_UPCF_Pos (5U)
  12337. #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
  12338. #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
  12339. #define LPTIM_ICR_DOWNCF_Pos (6U)
  12340. #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
  12341. #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
  12342. /****************** Bit definition for LPTIM_IER register ********************/
  12343. #define LPTIM_IER_CMPMIE_Pos (0U)
  12344. #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
  12345. #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
  12346. #define LPTIM_IER_ARRMIE_Pos (1U)
  12347. #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
  12348. #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
  12349. #define LPTIM_IER_EXTTRIGIE_Pos (2U)
  12350. #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
  12351. #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
  12352. #define LPTIM_IER_CMPOKIE_Pos (3U)
  12353. #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
  12354. #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
  12355. #define LPTIM_IER_ARROKIE_Pos (4U)
  12356. #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
  12357. #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
  12358. #define LPTIM_IER_UPIE_Pos (5U)
  12359. #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
  12360. #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
  12361. #define LPTIM_IER_DOWNIE_Pos (6U)
  12362. #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
  12363. #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
  12364. /****************** Bit definition for LPTIM_CFGR register *******************/
  12365. #define LPTIM_CFGR_CKSEL_Pos (0U)
  12366. #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
  12367. #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
  12368. #define LPTIM_CFGR_CKPOL_Pos (1U)
  12369. #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
  12370. #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
  12371. #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
  12372. #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
  12373. #define LPTIM_CFGR_CKFLT_Pos (3U)
  12374. #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
  12375. #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
  12376. #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
  12377. #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
  12378. #define LPTIM_CFGR_TRGFLT_Pos (6U)
  12379. #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
  12380. #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
  12381. #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
  12382. #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
  12383. #define LPTIM_CFGR_PRESC_Pos (9U)
  12384. #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
  12385. #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
  12386. #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
  12387. #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
  12388. #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
  12389. #define LPTIM_CFGR_TRIGSEL_Pos (13U)
  12390. #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
  12391. #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
  12392. #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
  12393. #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
  12394. #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
  12395. #define LPTIM_CFGR_TRIGEN_Pos (17U)
  12396. #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
  12397. #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
  12398. #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
  12399. #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
  12400. #define LPTIM_CFGR_TIMOUT_Pos (19U)
  12401. #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
  12402. #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
  12403. #define LPTIM_CFGR_WAVE_Pos (20U)
  12404. #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
  12405. #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
  12406. #define LPTIM_CFGR_WAVPOL_Pos (21U)
  12407. #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
  12408. #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
  12409. #define LPTIM_CFGR_PRELOAD_Pos (22U)
  12410. #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
  12411. #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
  12412. #define LPTIM_CFGR_COUNTMODE_Pos (23U)
  12413. #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
  12414. #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
  12415. #define LPTIM_CFGR_ENC_Pos (24U)
  12416. #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
  12417. #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
  12418. /****************** Bit definition for LPTIM_CR register ********************/
  12419. #define LPTIM_CR_ENABLE_Pos (0U)
  12420. #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
  12421. #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
  12422. #define LPTIM_CR_SNGSTRT_Pos (1U)
  12423. #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
  12424. #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
  12425. #define LPTIM_CR_CNTSTRT_Pos (2U)
  12426. #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
  12427. #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
  12428. /****************** Bit definition for LPTIM_CMP register *******************/
  12429. #define LPTIM_CMP_CMP_Pos (0U)
  12430. #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
  12431. #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
  12432. /****************** Bit definition for LPTIM_ARR register *******************/
  12433. #define LPTIM_ARR_ARR_Pos (0U)
  12434. #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
  12435. #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
  12436. /****************** Bit definition for LPTIM_CNT register *******************/
  12437. #define LPTIM_CNT_CNT_Pos (0U)
  12438. #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
  12439. #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
  12440. /****************** Bit definition for LPTIM_OR register *******************/
  12441. #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
  12442. #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
  12443. #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
  12444. #define LPTIM_OR_LPT_IN1_RMP_0 (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
  12445. #define LPTIM_OR_LPT_IN1_RMP_1 (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
  12446. #define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
  12447. #define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1UL << LPTIM_OR_TIM1_ITR2_RMP_Pos) /*!< 0x00000004 */
  12448. #define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk /*!< Bit 2 */
  12449. #define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
  12450. #define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM5_ITR1_RMP_Pos) /*!< 0x00000008 */
  12451. #define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk /*!< Bit 3 */
  12452. #define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
  12453. #define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM9_ITR1_RMP_Pos) /*!< 0x00000010 */
  12454. #define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk /*!< Bit 4 */
  12455. /* Legacy Defines */
  12456. #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
  12457. #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
  12458. #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
  12459. /******************************************************************************/
  12460. /* */
  12461. /* Universal Synchronous Asynchronous Receiver Transmitter */
  12462. /* */
  12463. /******************************************************************************/
  12464. /******************* Bit definition for USART_SR register *******************/
  12465. #define USART_SR_PE_Pos (0U)
  12466. #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
  12467. #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
  12468. #define USART_SR_FE_Pos (1U)
  12469. #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
  12470. #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
  12471. #define USART_SR_NE_Pos (2U)
  12472. #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
  12473. #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
  12474. #define USART_SR_ORE_Pos (3U)
  12475. #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
  12476. #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
  12477. #define USART_SR_IDLE_Pos (4U)
  12478. #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
  12479. #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
  12480. #define USART_SR_RXNE_Pos (5U)
  12481. #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
  12482. #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
  12483. #define USART_SR_TC_Pos (6U)
  12484. #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
  12485. #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
  12486. #define USART_SR_TXE_Pos (7U)
  12487. #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
  12488. #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
  12489. #define USART_SR_LBD_Pos (8U)
  12490. #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
  12491. #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
  12492. #define USART_SR_CTS_Pos (9U)
  12493. #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
  12494. #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
  12495. /******************* Bit definition for USART_DR register *******************/
  12496. #define USART_DR_DR_Pos (0U)
  12497. #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
  12498. #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
  12499. /****************** Bit definition for USART_BRR register *******************/
  12500. #define USART_BRR_DIV_Fraction_Pos (0U)
  12501. #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
  12502. #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
  12503. #define USART_BRR_DIV_Mantissa_Pos (4U)
  12504. #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
  12505. #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
  12506. /****************** Bit definition for USART_CR1 register *******************/
  12507. #define USART_CR1_SBK_Pos (0U)
  12508. #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
  12509. #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
  12510. #define USART_CR1_RWU_Pos (1U)
  12511. #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
  12512. #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
  12513. #define USART_CR1_RE_Pos (2U)
  12514. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  12515. #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
  12516. #define USART_CR1_TE_Pos (3U)
  12517. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  12518. #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
  12519. #define USART_CR1_IDLEIE_Pos (4U)
  12520. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  12521. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
  12522. #define USART_CR1_RXNEIE_Pos (5U)
  12523. #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  12524. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
  12525. #define USART_CR1_TCIE_Pos (6U)
  12526. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  12527. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
  12528. #define USART_CR1_TXEIE_Pos (7U)
  12529. #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  12530. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
  12531. #define USART_CR1_PEIE_Pos (8U)
  12532. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  12533. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
  12534. #define USART_CR1_PS_Pos (9U)
  12535. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  12536. #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
  12537. #define USART_CR1_PCE_Pos (10U)
  12538. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  12539. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
  12540. #define USART_CR1_WAKE_Pos (11U)
  12541. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  12542. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
  12543. #define USART_CR1_M_Pos (12U)
  12544. #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
  12545. #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
  12546. #define USART_CR1_UE_Pos (13U)
  12547. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
  12548. #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
  12549. #define USART_CR1_OVER8_Pos (15U)
  12550. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  12551. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
  12552. /****************** Bit definition for USART_CR2 register *******************/
  12553. #define USART_CR2_ADD_Pos (0U)
  12554. #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
  12555. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
  12556. #define USART_CR2_LBDL_Pos (5U)
  12557. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  12558. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
  12559. #define USART_CR2_LBDIE_Pos (6U)
  12560. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  12561. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
  12562. #define USART_CR2_LBCL_Pos (8U)
  12563. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  12564. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
  12565. #define USART_CR2_CPHA_Pos (9U)
  12566. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  12567. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
  12568. #define USART_CR2_CPOL_Pos (10U)
  12569. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  12570. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
  12571. #define USART_CR2_CLKEN_Pos (11U)
  12572. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  12573. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
  12574. #define USART_CR2_STOP_Pos (12U)
  12575. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  12576. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
  12577. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
  12578. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
  12579. #define USART_CR2_LINEN_Pos (14U)
  12580. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  12581. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
  12582. /****************** Bit definition for USART_CR3 register *******************/
  12583. #define USART_CR3_EIE_Pos (0U)
  12584. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  12585. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
  12586. #define USART_CR3_IREN_Pos (1U)
  12587. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  12588. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
  12589. #define USART_CR3_IRLP_Pos (2U)
  12590. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  12591. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
  12592. #define USART_CR3_HDSEL_Pos (3U)
  12593. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  12594. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
  12595. #define USART_CR3_NACK_Pos (4U)
  12596. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  12597. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
  12598. #define USART_CR3_SCEN_Pos (5U)
  12599. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  12600. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
  12601. #define USART_CR3_DMAR_Pos (6U)
  12602. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  12603. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
  12604. #define USART_CR3_DMAT_Pos (7U)
  12605. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  12606. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
  12607. #define USART_CR3_RTSE_Pos (8U)
  12608. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  12609. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
  12610. #define USART_CR3_CTSE_Pos (9U)
  12611. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  12612. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
  12613. #define USART_CR3_CTSIE_Pos (10U)
  12614. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  12615. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
  12616. #define USART_CR3_ONEBIT_Pos (11U)
  12617. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  12618. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
  12619. /****************** Bit definition for USART_GTPR register ******************/
  12620. #define USART_GTPR_PSC_Pos (0U)
  12621. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  12622. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
  12623. #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
  12624. #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
  12625. #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
  12626. #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
  12627. #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
  12628. #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
  12629. #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
  12630. #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
  12631. #define USART_GTPR_GT_Pos (8U)
  12632. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  12633. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
  12634. /******************************************************************************/
  12635. /* */
  12636. /* Window WATCHDOG */
  12637. /* */
  12638. /******************************************************************************/
  12639. /******************* Bit definition for WWDG_CR register ********************/
  12640. #define WWDG_CR_T_Pos (0U)
  12641. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  12642. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  12643. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
  12644. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
  12645. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
  12646. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
  12647. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
  12648. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
  12649. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
  12650. /* Legacy defines */
  12651. #define WWDG_CR_T0 WWDG_CR_T_0
  12652. #define WWDG_CR_T1 WWDG_CR_T_1
  12653. #define WWDG_CR_T2 WWDG_CR_T_2
  12654. #define WWDG_CR_T3 WWDG_CR_T_3
  12655. #define WWDG_CR_T4 WWDG_CR_T_4
  12656. #define WWDG_CR_T5 WWDG_CR_T_5
  12657. #define WWDG_CR_T6 WWDG_CR_T_6
  12658. #define WWDG_CR_WDGA_Pos (7U)
  12659. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  12660. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  12661. /******************* Bit definition for WWDG_CFR register *******************/
  12662. #define WWDG_CFR_W_Pos (0U)
  12663. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  12664. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  12665. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
  12666. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
  12667. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
  12668. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
  12669. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
  12670. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
  12671. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
  12672. /* Legacy defines */
  12673. #define WWDG_CFR_W0 WWDG_CFR_W_0
  12674. #define WWDG_CFR_W1 WWDG_CFR_W_1
  12675. #define WWDG_CFR_W2 WWDG_CFR_W_2
  12676. #define WWDG_CFR_W3 WWDG_CFR_W_3
  12677. #define WWDG_CFR_W4 WWDG_CFR_W_4
  12678. #define WWDG_CFR_W5 WWDG_CFR_W_5
  12679. #define WWDG_CFR_W6 WWDG_CFR_W_6
  12680. #define WWDG_CFR_WDGTB_Pos (7U)
  12681. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  12682. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  12683. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
  12684. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
  12685. /* Legacy defines */
  12686. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  12687. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  12688. #define WWDG_CFR_EWI_Pos (9U)
  12689. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  12690. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  12691. /******************* Bit definition for WWDG_SR register ********************/
  12692. #define WWDG_SR_EWIF_Pos (0U)
  12693. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  12694. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  12695. /******************************************************************************/
  12696. /* */
  12697. /* DBG */
  12698. /* */
  12699. /******************************************************************************/
  12700. /******************** Bit definition for DBGMCU_IDCODE register *************/
  12701. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  12702. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  12703. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  12704. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  12705. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  12706. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  12707. /******************** Bit definition for DBGMCU_CR register *****************/
  12708. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  12709. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  12710. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  12711. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  12712. #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  12713. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  12714. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  12715. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  12716. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  12717. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  12718. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  12719. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  12720. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  12721. #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  12722. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  12723. #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  12724. #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  12725. /******************** Bit definition for DBGMCU_APB1_FZ register ************/
  12726. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
  12727. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  12728. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
  12729. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
  12730. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  12731. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
  12732. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
  12733. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
  12734. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
  12735. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
  12736. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
  12737. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
  12738. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
  12739. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
  12740. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
  12741. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
  12742. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
  12743. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
  12744. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
  12745. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
  12746. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
  12747. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
  12748. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
  12749. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
  12750. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
  12751. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
  12752. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
  12753. #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
  12754. #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */
  12755. #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
  12756. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  12757. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  12758. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
  12759. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  12760. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  12761. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
  12762. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  12763. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  12764. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
  12765. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  12766. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  12767. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
  12768. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
  12769. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
  12770. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
  12771. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
  12772. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
  12773. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
  12774. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
  12775. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
  12776. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
  12777. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
  12778. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
  12779. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
  12780. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
  12781. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
  12782. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
  12783. #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
  12784. #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */
  12785. #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
  12786. /******************** Bit definition for DBGMCU_APB2_FZ register ************/
  12787. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
  12788. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
  12789. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
  12790. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
  12791. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
  12792. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
  12793. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
  12794. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
  12795. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
  12796. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
  12797. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
  12798. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
  12799. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
  12800. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
  12801. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
  12802. /******************************************************************************/
  12803. /* */
  12804. /* USB_OTG */
  12805. /* */
  12806. /******************************************************************************/
  12807. /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
  12808. #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
  12809. #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
  12810. #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
  12811. #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
  12812. #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
  12813. #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
  12814. #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
  12815. #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
  12816. #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
  12817. #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
  12818. #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
  12819. #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
  12820. #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
  12821. #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
  12822. #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
  12823. #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
  12824. #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
  12825. #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
  12826. #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
  12827. #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
  12828. #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
  12829. #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
  12830. #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
  12831. #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
  12832. #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
  12833. #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
  12834. #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
  12835. #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
  12836. #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
  12837. #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
  12838. #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
  12839. #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
  12840. #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
  12841. #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
  12842. #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
  12843. #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
  12844. #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
  12845. #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
  12846. #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
  12847. #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
  12848. #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
  12849. #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
  12850. #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
  12851. #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
  12852. #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
  12853. #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
  12854. #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
  12855. #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
  12856. #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
  12857. #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
  12858. #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
  12859. #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
  12860. #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
  12861. #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
  12862. /******************** Bit definition forUSB_OTG_HCFG register ********************/
  12863. #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
  12864. #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
  12865. #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
  12866. #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
  12867. #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
  12868. #define USB_OTG_HCFG_FSLSS_Pos (2U)
  12869. #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
  12870. #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
  12871. /******************** Bit definition for USB_OTG_DCFG register ********************/
  12872. #define USB_OTG_DCFG_DSPD_Pos (0U)
  12873. #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
  12874. #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
  12875. #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
  12876. #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
  12877. #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
  12878. #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
  12879. #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
  12880. #define USB_OTG_DCFG_DAD_Pos (4U)
  12881. #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
  12882. #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
  12883. #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
  12884. #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
  12885. #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
  12886. #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
  12887. #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
  12888. #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
  12889. #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
  12890. #define USB_OTG_DCFG_PFIVL_Pos (11U)
  12891. #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
  12892. #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
  12893. #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
  12894. #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
  12895. #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
  12896. #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
  12897. #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
  12898. #define USB_OTG_DCFG_ERRATIM_Pos (15U)
  12899. #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
  12900. #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
  12901. #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
  12902. #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
  12903. #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
  12904. #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
  12905. #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
  12906. /******************** Bit definition for USB_OTG_PCGCR register ********************/
  12907. #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
  12908. #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
  12909. #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
  12910. #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
  12911. #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
  12912. #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
  12913. #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
  12914. #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
  12915. #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
  12916. /******************** Bit definition for USB_OTG_GOTGINT register ********************/
  12917. #define USB_OTG_GOTGINT_SEDET_Pos (2U)
  12918. #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
  12919. #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
  12920. #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
  12921. #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
  12922. #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
  12923. #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
  12924. #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
  12925. #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
  12926. #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
  12927. #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
  12928. #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
  12929. #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
  12930. #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
  12931. #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
  12932. #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
  12933. #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
  12934. #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
  12935. #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
  12936. #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
  12937. #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
  12938. /******************** Bit definition for USB_OTG_DCTL register ********************/
  12939. #define USB_OTG_DCTL_RWUSIG_Pos (0U)
  12940. #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
  12941. #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
  12942. #define USB_OTG_DCTL_SDIS_Pos (1U)
  12943. #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
  12944. #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
  12945. #define USB_OTG_DCTL_GINSTS_Pos (2U)
  12946. #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
  12947. #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
  12948. #define USB_OTG_DCTL_GONSTS_Pos (3U)
  12949. #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
  12950. #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
  12951. #define USB_OTG_DCTL_TCTL_Pos (4U)
  12952. #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
  12953. #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
  12954. #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
  12955. #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
  12956. #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
  12957. #define USB_OTG_DCTL_SGINAK_Pos (7U)
  12958. #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
  12959. #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
  12960. #define USB_OTG_DCTL_CGINAK_Pos (8U)
  12961. #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
  12962. #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
  12963. #define USB_OTG_DCTL_SGONAK_Pos (9U)
  12964. #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
  12965. #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
  12966. #define USB_OTG_DCTL_CGONAK_Pos (10U)
  12967. #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
  12968. #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
  12969. #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
  12970. #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
  12971. #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
  12972. /******************** Bit definition for USB_OTG_HFIR register ********************/
  12973. #define USB_OTG_HFIR_FRIVL_Pos (0U)
  12974. #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
  12975. #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
  12976. /******************** Bit definition for USB_OTG_HFNUM register ********************/
  12977. #define USB_OTG_HFNUM_FRNUM_Pos (0U)
  12978. #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
  12979. #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
  12980. #define USB_OTG_HFNUM_FTREM_Pos (16U)
  12981. #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
  12982. #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
  12983. /******************** Bit definition for USB_OTG_DSTS register ********************/
  12984. #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
  12985. #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
  12986. #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
  12987. #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
  12988. #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
  12989. #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
  12990. #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
  12991. #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
  12992. #define USB_OTG_DSTS_EERR_Pos (3U)
  12993. #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
  12994. #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
  12995. #define USB_OTG_DSTS_FNSOF_Pos (8U)
  12996. #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
  12997. #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
  12998. /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
  12999. #define USB_OTG_GAHBCFG_GINT_Pos (0U)
  13000. #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
  13001. #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
  13002. #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
  13003. #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
  13004. #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
  13005. #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
  13006. #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
  13007. #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
  13008. #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
  13009. #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
  13010. #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
  13011. #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
  13012. #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
  13013. #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
  13014. #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
  13015. #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
  13016. #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
  13017. #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
  13018. #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
  13019. /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
  13020. #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
  13021. #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
  13022. #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
  13023. #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
  13024. #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
  13025. #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
  13026. #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
  13027. #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
  13028. #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
  13029. #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
  13030. #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
  13031. #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
  13032. #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
  13033. #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
  13034. #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
  13035. #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
  13036. #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
  13037. #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
  13038. #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
  13039. #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
  13040. #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
  13041. #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
  13042. #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
  13043. #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
  13044. #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
  13045. #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
  13046. #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
  13047. #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
  13048. #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
  13049. #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
  13050. #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
  13051. #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
  13052. #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
  13053. #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
  13054. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
  13055. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
  13056. #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
  13057. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
  13058. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
  13059. #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
  13060. #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
  13061. #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
  13062. #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
  13063. #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
  13064. #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
  13065. #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
  13066. #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
  13067. #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
  13068. #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
  13069. #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
  13070. #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
  13071. #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
  13072. #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
  13073. #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
  13074. #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
  13075. #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
  13076. #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
  13077. #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
  13078. #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
  13079. #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
  13080. #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
  13081. /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
  13082. #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
  13083. #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
  13084. #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
  13085. #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
  13086. #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
  13087. #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
  13088. #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
  13089. #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
  13090. #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
  13091. #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
  13092. #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
  13093. #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
  13094. #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
  13095. #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
  13096. #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
  13097. #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
  13098. #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
  13099. #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
  13100. #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
  13101. #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
  13102. #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
  13103. #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
  13104. #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
  13105. #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
  13106. #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
  13107. #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
  13108. #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
  13109. #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
  13110. #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
  13111. /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
  13112. #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
  13113. #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  13114. #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  13115. #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
  13116. #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
  13117. #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  13118. #define USB_OTG_DIEPMSK_TOM_Pos (3U)
  13119. #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
  13120. #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  13121. #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
  13122. #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
  13123. #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  13124. #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
  13125. #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
  13126. #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  13127. #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
  13128. #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
  13129. #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  13130. #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
  13131. #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
  13132. #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
  13133. #define USB_OTG_DIEPMSK_BIM_Pos (9U)
  13134. #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
  13135. #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
  13136. /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
  13137. #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
  13138. #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
  13139. #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
  13140. #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
  13141. #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
  13142. #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
  13143. #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
  13144. #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
  13145. #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
  13146. #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
  13147. #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
  13148. #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
  13149. #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
  13150. #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
  13151. #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
  13152. #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
  13153. #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
  13154. #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
  13155. #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
  13156. #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
  13157. #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
  13158. #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
  13159. #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
  13160. #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
  13161. #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
  13162. /******************** Bit definition for USB_OTG_HAINT register ********************/
  13163. #define USB_OTG_HAINT_HAINT_Pos (0U)
  13164. #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
  13165. #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
  13166. /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
  13167. #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
  13168. #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  13169. #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  13170. #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
  13171. #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
  13172. #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  13173. #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
  13174. #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
  13175. #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
  13176. #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
  13177. #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
  13178. #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
  13179. #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
  13180. #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
  13181. #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
  13182. #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
  13183. #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
  13184. #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
  13185. #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
  13186. #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
  13187. #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
  13188. #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
  13189. #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
  13190. #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
  13191. #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
  13192. #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
  13193. #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
  13194. #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
  13195. #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
  13196. #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
  13197. #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
  13198. #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
  13199. #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
  13200. #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
  13201. #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
  13202. #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
  13203. /******************** Bit definition for USB_OTG_GINTSTS register ********************/
  13204. #define USB_OTG_GINTSTS_CMOD_Pos (0U)
  13205. #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
  13206. #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
  13207. #define USB_OTG_GINTSTS_MMIS_Pos (1U)
  13208. #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
  13209. #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
  13210. #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
  13211. #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
  13212. #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
  13213. #define USB_OTG_GINTSTS_SOF_Pos (3U)
  13214. #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
  13215. #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
  13216. #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
  13217. #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
  13218. #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
  13219. #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
  13220. #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
  13221. #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
  13222. #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
  13223. #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
  13224. #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
  13225. #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
  13226. #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
  13227. #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
  13228. #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
  13229. #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
  13230. #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
  13231. #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
  13232. #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
  13233. #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
  13234. #define USB_OTG_GINTSTS_USBRST_Pos (12U)
  13235. #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
  13236. #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
  13237. #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
  13238. #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
  13239. #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
  13240. #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
  13241. #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
  13242. #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
  13243. #define USB_OTG_GINTSTS_EOPF_Pos (15U)
  13244. #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
  13245. #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
  13246. #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
  13247. #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
  13248. #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
  13249. #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
  13250. #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
  13251. #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
  13252. #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
  13253. #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
  13254. #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
  13255. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
  13256. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
  13257. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
  13258. #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
  13259. #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
  13260. #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
  13261. #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
  13262. #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
  13263. #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
  13264. #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
  13265. #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
  13266. #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
  13267. #define USB_OTG_GINTSTS_HCINT_Pos (25U)
  13268. #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
  13269. #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
  13270. #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
  13271. #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
  13272. #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
  13273. #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
  13274. #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
  13275. #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
  13276. #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
  13277. #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
  13278. #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
  13279. #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
  13280. #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
  13281. #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
  13282. #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
  13283. #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
  13284. #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
  13285. #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
  13286. #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
  13287. #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
  13288. /******************** Bit definition for USB_OTG_GINTMSK register ********************/
  13289. #define USB_OTG_GINTMSK_MMISM_Pos (1U)
  13290. #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
  13291. #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
  13292. #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
  13293. #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
  13294. #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
  13295. #define USB_OTG_GINTMSK_SOFM_Pos (3U)
  13296. #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
  13297. #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
  13298. #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
  13299. #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
  13300. #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
  13301. #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
  13302. #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
  13303. #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
  13304. #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
  13305. #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
  13306. #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
  13307. #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
  13308. #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
  13309. #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
  13310. #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
  13311. #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
  13312. #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
  13313. #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
  13314. #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
  13315. #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
  13316. #define USB_OTG_GINTMSK_USBRST_Pos (12U)
  13317. #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
  13318. #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
  13319. #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
  13320. #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
  13321. #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
  13322. #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
  13323. #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
  13324. #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
  13325. #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
  13326. #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
  13327. #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
  13328. #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
  13329. #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
  13330. #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
  13331. #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
  13332. #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
  13333. #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
  13334. #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
  13335. #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
  13336. #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
  13337. #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
  13338. #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
  13339. #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
  13340. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
  13341. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
  13342. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
  13343. #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
  13344. #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
  13345. #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
  13346. #define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
  13347. #define USB_OTG_GINTMSK_RSTDETM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
  13348. #define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */
  13349. #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
  13350. #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
  13351. #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
  13352. #define USB_OTG_GINTMSK_HCIM_Pos (25U)
  13353. #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
  13354. #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
  13355. #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
  13356. #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
  13357. #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
  13358. #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
  13359. #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
  13360. #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
  13361. #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
  13362. #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
  13363. #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
  13364. #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
  13365. #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
  13366. #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
  13367. #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
  13368. #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
  13369. #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
  13370. #define USB_OTG_GINTMSK_WUIM_Pos (31U)
  13371. #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
  13372. #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
  13373. /******************** Bit definition for USB_OTG_DAINT register ********************/
  13374. #define USB_OTG_DAINT_IEPINT_Pos (0U)
  13375. #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
  13376. #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
  13377. #define USB_OTG_DAINT_OEPINT_Pos (16U)
  13378. #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
  13379. #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
  13380. /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
  13381. #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
  13382. #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
  13383. #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
  13384. /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
  13385. #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
  13386. #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
  13387. #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
  13388. #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
  13389. #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
  13390. #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
  13391. #define USB_OTG_GRXSTSP_DPID_Pos (15U)
  13392. #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
  13393. #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
  13394. #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
  13395. #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
  13396. #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
  13397. /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
  13398. #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
  13399. #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
  13400. #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
  13401. #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
  13402. #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
  13403. #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
  13404. /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
  13405. #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
  13406. #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
  13407. #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
  13408. /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
  13409. #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
  13410. #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
  13411. #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
  13412. /******************** Bit definition for OTG register ********************/
  13413. #define USB_OTG_NPTXFSA_Pos (0U)
  13414. #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
  13415. #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
  13416. #define USB_OTG_NPTXFD_Pos (16U)
  13417. #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
  13418. #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
  13419. #define USB_OTG_TX0FSA_Pos (0U)
  13420. #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
  13421. #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
  13422. #define USB_OTG_TX0FD_Pos (16U)
  13423. #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
  13424. #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
  13425. /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
  13426. #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
  13427. #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
  13428. #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
  13429. /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
  13430. #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
  13431. #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
  13432. #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
  13433. #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
  13434. #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
  13435. #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
  13436. #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
  13437. #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
  13438. #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
  13439. #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
  13440. #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
  13441. #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
  13442. #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
  13443. #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
  13444. #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
  13445. #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
  13446. #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
  13447. #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
  13448. #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
  13449. #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
  13450. #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
  13451. #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
  13452. #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
  13453. #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
  13454. /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
  13455. #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
  13456. #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
  13457. #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
  13458. #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
  13459. #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
  13460. #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
  13461. #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
  13462. #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
  13463. #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
  13464. #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
  13465. #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
  13466. #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
  13467. #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
  13468. #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
  13469. #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
  13470. #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
  13471. #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
  13472. #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
  13473. #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
  13474. #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
  13475. #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
  13476. #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
  13477. #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
  13478. #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
  13479. #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
  13480. #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
  13481. #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
  13482. #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
  13483. #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
  13484. #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
  13485. #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
  13486. #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
  13487. #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
  13488. #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
  13489. #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
  13490. #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
  13491. /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
  13492. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
  13493. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
  13494. #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
  13495. /******************** Bit definition for USB_OTG_DEACHINT register ********************/
  13496. #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
  13497. #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
  13498. #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
  13499. #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
  13500. #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
  13501. #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
  13502. /******************** Bit definition for USB_OTG_GCCFG register ********************/
  13503. #define USB_OTG_GCCFG_DCDET_Pos (0U)
  13504. #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
  13505. #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
  13506. #define USB_OTG_GCCFG_PDET_Pos (1U)
  13507. #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
  13508. #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
  13509. #define USB_OTG_GCCFG_SDET_Pos (2U)
  13510. #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
  13511. #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
  13512. #define USB_OTG_GCCFG_PS2DET_Pos (3U)
  13513. #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
  13514. #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
  13515. #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
  13516. #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
  13517. #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
  13518. #define USB_OTG_GCCFG_BCDEN_Pos (17U)
  13519. #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
  13520. #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
  13521. #define USB_OTG_GCCFG_DCDEN_Pos (18U)
  13522. #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
  13523. #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
  13524. #define USB_OTG_GCCFG_PDEN_Pos (19U)
  13525. #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
  13526. #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
  13527. #define USB_OTG_GCCFG_SDEN_Pos (20U)
  13528. #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
  13529. #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
  13530. #define USB_OTG_GCCFG_VBDEN_Pos (21U)
  13531. #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
  13532. #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
  13533. /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
  13534. #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
  13535. #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
  13536. #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
  13537. #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
  13538. #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
  13539. #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
  13540. /******************** Bit definition for USB_OTG_CID register ********************/
  13541. #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
  13542. #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
  13543. #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
  13544. /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
  13545. #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
  13546. #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
  13547. #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
  13548. #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
  13549. #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
  13550. #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
  13551. #define USB_OTG_GLPMCFG_BESL_Pos (2U)
  13552. #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
  13553. #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
  13554. #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
  13555. #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
  13556. #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
  13557. #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
  13558. #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
  13559. #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
  13560. #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
  13561. #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
  13562. #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
  13563. #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
  13564. #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
  13565. #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
  13566. #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
  13567. #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
  13568. #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
  13569. #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
  13570. #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
  13571. #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
  13572. #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
  13573. #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
  13574. #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
  13575. #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
  13576. #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
  13577. #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
  13578. #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
  13579. #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
  13580. #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
  13581. #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
  13582. #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
  13583. #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
  13584. #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
  13585. #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
  13586. #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
  13587. #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
  13588. #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
  13589. #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
  13590. /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
  13591. #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
  13592. #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  13593. #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  13594. #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
  13595. #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  13596. #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  13597. #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
  13598. #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  13599. #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  13600. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
  13601. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  13602. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  13603. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
  13604. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  13605. #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  13606. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
  13607. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  13608. #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  13609. #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
  13610. #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  13611. #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
  13612. #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
  13613. #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  13614. #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  13615. #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
  13616. #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  13617. #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  13618. /******************** Bit definition for USB_OTG_HPRT register ********************/
  13619. #define USB_OTG_HPRT_PCSTS_Pos (0U)
  13620. #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
  13621. #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
  13622. #define USB_OTG_HPRT_PCDET_Pos (1U)
  13623. #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
  13624. #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
  13625. #define USB_OTG_HPRT_PENA_Pos (2U)
  13626. #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
  13627. #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
  13628. #define USB_OTG_HPRT_PENCHNG_Pos (3U)
  13629. #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
  13630. #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
  13631. #define USB_OTG_HPRT_POCA_Pos (4U)
  13632. #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
  13633. #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
  13634. #define USB_OTG_HPRT_POCCHNG_Pos (5U)
  13635. #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
  13636. #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
  13637. #define USB_OTG_HPRT_PRES_Pos (6U)
  13638. #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
  13639. #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
  13640. #define USB_OTG_HPRT_PSUSP_Pos (7U)
  13641. #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
  13642. #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
  13643. #define USB_OTG_HPRT_PRST_Pos (8U)
  13644. #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
  13645. #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
  13646. #define USB_OTG_HPRT_PLSTS_Pos (10U)
  13647. #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
  13648. #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
  13649. #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
  13650. #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
  13651. #define USB_OTG_HPRT_PPWR_Pos (12U)
  13652. #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
  13653. #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
  13654. #define USB_OTG_HPRT_PTCTL_Pos (13U)
  13655. #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
  13656. #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
  13657. #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
  13658. #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
  13659. #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
  13660. #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
  13661. #define USB_OTG_HPRT_PSPD_Pos (17U)
  13662. #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
  13663. #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
  13664. #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
  13665. #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
  13666. /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
  13667. #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
  13668. #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  13669. #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  13670. #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
  13671. #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  13672. #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  13673. #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
  13674. #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  13675. #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
  13676. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
  13677. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  13678. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  13679. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
  13680. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  13681. #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  13682. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
  13683. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  13684. #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  13685. #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
  13686. #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  13687. #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
  13688. #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
  13689. #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  13690. #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  13691. #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
  13692. #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
  13693. #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
  13694. #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
  13695. #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  13696. #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  13697. #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
  13698. #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
  13699. #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
  13700. /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
  13701. #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
  13702. #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
  13703. #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
  13704. #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
  13705. #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
  13706. #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
  13707. /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
  13708. #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
  13709. #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  13710. #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
  13711. #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
  13712. #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  13713. #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
  13714. #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
  13715. #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
  13716. #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
  13717. #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
  13718. #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  13719. #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
  13720. #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
  13721. #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  13722. #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
  13723. #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  13724. #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  13725. #define USB_OTG_DIEPCTL_STALL_Pos (21U)
  13726. #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
  13727. #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
  13728. #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
  13729. #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
  13730. #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
  13731. #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
  13732. #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
  13733. #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
  13734. #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
  13735. #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
  13736. #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
  13737. #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
  13738. #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
  13739. #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
  13740. #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
  13741. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
  13742. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  13743. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  13744. #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
  13745. #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  13746. #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
  13747. #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
  13748. #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  13749. #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
  13750. #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
  13751. #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
  13752. #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
  13753. /******************** Bit definition for USB_OTG_HCCHAR register ********************/
  13754. #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
  13755. #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
  13756. #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
  13757. #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
  13758. #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
  13759. #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
  13760. #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
  13761. #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
  13762. #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
  13763. #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
  13764. #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
  13765. #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
  13766. #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
  13767. #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
  13768. #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
  13769. #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
  13770. #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
  13771. #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
  13772. #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
  13773. #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
  13774. #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
  13775. #define USB_OTG_HCCHAR_MC_Pos (20U)
  13776. #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
  13777. #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
  13778. #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
  13779. #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
  13780. #define USB_OTG_HCCHAR_DAD_Pos (22U)
  13781. #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
  13782. #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
  13783. #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
  13784. #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
  13785. #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
  13786. #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
  13787. #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
  13788. #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
  13789. #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
  13790. #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
  13791. #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
  13792. #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
  13793. #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
  13794. #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
  13795. #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
  13796. #define USB_OTG_HCCHAR_CHENA_Pos (31U)
  13797. #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
  13798. #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
  13799. /******************** Bit definition for USB_OTG_HCSPLT register ********************/
  13800. #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
  13801. #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
  13802. #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
  13803. #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
  13804. #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
  13805. #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
  13806. #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
  13807. #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
  13808. #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
  13809. #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
  13810. #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
  13811. #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
  13812. #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
  13813. #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
  13814. #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
  13815. #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
  13816. #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
  13817. #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
  13818. #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
  13819. #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
  13820. #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
  13821. #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
  13822. #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
  13823. #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
  13824. #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
  13825. #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
  13826. #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
  13827. #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
  13828. #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
  13829. #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
  13830. #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
  13831. /******************** Bit definition for USB_OTG_HCINT register ********************/
  13832. #define USB_OTG_HCINT_XFRC_Pos (0U)
  13833. #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
  13834. #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
  13835. #define USB_OTG_HCINT_CHH_Pos (1U)
  13836. #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
  13837. #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
  13838. #define USB_OTG_HCINT_AHBERR_Pos (2U)
  13839. #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
  13840. #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
  13841. #define USB_OTG_HCINT_STALL_Pos (3U)
  13842. #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
  13843. #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
  13844. #define USB_OTG_HCINT_NAK_Pos (4U)
  13845. #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
  13846. #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
  13847. #define USB_OTG_HCINT_ACK_Pos (5U)
  13848. #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
  13849. #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
  13850. #define USB_OTG_HCINT_NYET_Pos (6U)
  13851. #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
  13852. #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
  13853. #define USB_OTG_HCINT_TXERR_Pos (7U)
  13854. #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
  13855. #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
  13856. #define USB_OTG_HCINT_BBERR_Pos (8U)
  13857. #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
  13858. #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
  13859. #define USB_OTG_HCINT_FRMOR_Pos (9U)
  13860. #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
  13861. #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
  13862. #define USB_OTG_HCINT_DTERR_Pos (10U)
  13863. #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
  13864. #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
  13865. /******************** Bit definition for USB_OTG_DIEPINT register ********************/
  13866. #define USB_OTG_DIEPINT_XFRC_Pos (0U)
  13867. #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
  13868. #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  13869. #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
  13870. #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
  13871. #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  13872. #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
  13873. #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
  13874. #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
  13875. #define USB_OTG_DIEPINT_TOC_Pos (3U)
  13876. #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
  13877. #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
  13878. #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
  13879. #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
  13880. #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
  13881. #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
  13882. #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
  13883. #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
  13884. #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
  13885. #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
  13886. #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
  13887. #define USB_OTG_DIEPINT_TXFE_Pos (7U)
  13888. #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
  13889. #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
  13890. #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
  13891. #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
  13892. #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
  13893. #define USB_OTG_DIEPINT_BNA_Pos (9U)
  13894. #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
  13895. #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
  13896. #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
  13897. #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
  13898. #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
  13899. #define USB_OTG_DIEPINT_BERR_Pos (12U)
  13900. #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
  13901. #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
  13902. #define USB_OTG_DIEPINT_NAK_Pos (13U)
  13903. #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
  13904. #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
  13905. /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
  13906. #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
  13907. #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
  13908. #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
  13909. #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
  13910. #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
  13911. #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
  13912. #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
  13913. #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
  13914. #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
  13915. #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
  13916. #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
  13917. #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
  13918. #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
  13919. #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
  13920. #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
  13921. #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
  13922. #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
  13923. #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
  13924. #define USB_OTG_HCINTMSK_NYET_Pos (6U)
  13925. #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
  13926. #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
  13927. #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
  13928. #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
  13929. #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
  13930. #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
  13931. #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
  13932. #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
  13933. #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
  13934. #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
  13935. #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
  13936. #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
  13937. #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
  13938. #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
  13939. /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
  13940. #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
  13941. #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  13942. #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  13943. #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
  13944. #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  13945. #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
  13946. #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
  13947. #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
  13948. #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
  13949. /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
  13950. #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
  13951. #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  13952. #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
  13953. #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
  13954. #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  13955. #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
  13956. #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
  13957. #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
  13958. #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
  13959. #define USB_OTG_HCTSIZ_DPID_Pos (29U)
  13960. #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
  13961. #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
  13962. #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
  13963. #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
  13964. /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
  13965. #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
  13966. #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  13967. #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
  13968. /******************** Bit definition for USB_OTG_HCDMA register ********************/
  13969. #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
  13970. #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  13971. #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
  13972. /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
  13973. #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
  13974. #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
  13975. #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
  13976. /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
  13977. #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
  13978. #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
  13979. #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
  13980. #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
  13981. #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
  13982. #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
  13983. /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
  13984. #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
  13985. #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  13986. #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
  13987. #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
  13988. #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  13989. #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
  13990. #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
  13991. #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  13992. #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
  13993. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
  13994. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  13995. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  13996. #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
  13997. #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  13998. #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
  13999. #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
  14000. #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  14001. #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
  14002. #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  14003. #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  14004. #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
  14005. #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
  14006. #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
  14007. #define USB_OTG_DOEPCTL_STALL_Pos (21U)
  14008. #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
  14009. #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
  14010. #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
  14011. #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
  14012. #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
  14013. #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
  14014. #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
  14015. #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
  14016. #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
  14017. #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  14018. #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
  14019. #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
  14020. #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
  14021. #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
  14022. /******************** Bit definition for USB_OTG_DOEPINT register ********************/
  14023. #define USB_OTG_DOEPINT_XFRC_Pos (0U)
  14024. #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
  14025. #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  14026. #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
  14027. #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
  14028. #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  14029. #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
  14030. #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
  14031. #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
  14032. #define USB_OTG_DOEPINT_STUP_Pos (3U)
  14033. #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
  14034. #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
  14035. #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
  14036. #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
  14037. #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
  14038. #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
  14039. #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
  14040. #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
  14041. #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
  14042. #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
  14043. #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
  14044. #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
  14045. #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
  14046. #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
  14047. #define USB_OTG_DOEPINT_NAK_Pos (13U)
  14048. #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
  14049. #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
  14050. #define USB_OTG_DOEPINT_NYET_Pos (14U)
  14051. #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
  14052. #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
  14053. #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
  14054. #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
  14055. #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
  14056. /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
  14057. #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
  14058. #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  14059. #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  14060. #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
  14061. #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  14062. #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
  14063. #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
  14064. #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
  14065. #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
  14066. #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
  14067. #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
  14068. /******************** Bit definition for PCGCCTL register ********************/
  14069. #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
  14070. #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
  14071. #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
  14072. #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
  14073. #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
  14074. #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
  14075. #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
  14076. #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
  14077. #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
  14078. /* Legacy define */
  14079. /******************** Bit definition for OTG register ********************/
  14080. #define USB_OTG_CHNUM_Pos (0U)
  14081. #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
  14082. #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
  14083. #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
  14084. #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
  14085. #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
  14086. #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
  14087. #define USB_OTG_BCNT_Pos (4U)
  14088. #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
  14089. #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
  14090. #define USB_OTG_DPID_Pos (15U)
  14091. #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
  14092. #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
  14093. #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
  14094. #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
  14095. #define USB_OTG_PKTSTS_Pos (17U)
  14096. #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
  14097. #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
  14098. #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
  14099. #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
  14100. #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
  14101. #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
  14102. #define USB_OTG_EPNUM_Pos (0U)
  14103. #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
  14104. #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
  14105. #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
  14106. #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
  14107. #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
  14108. #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
  14109. #define USB_OTG_FRMNUM_Pos (21U)
  14110. #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
  14111. #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
  14112. #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
  14113. #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
  14114. #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
  14115. #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
  14116. /**
  14117. * @}
  14118. */
  14119. /**
  14120. * @}
  14121. */
  14122. /** @addtogroup Exported_macros
  14123. * @{
  14124. */
  14125. /******************************* ADC Instances ********************************/
  14126. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  14127. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
  14128. /******************************* CAN Instances ********************************/
  14129. #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
  14130. ((INSTANCE) == CAN2) || \
  14131. ((INSTANCE) == CAN3))
  14132. /****************************** DFSDM Instances *******************************/
  14133. #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
  14134. ((INSTANCE) == DFSDM1_Filter1) || \
  14135. ((INSTANCE) == DFSDM2_Filter0) || \
  14136. ((INSTANCE) == DFSDM2_Filter1) || \
  14137. ((INSTANCE) == DFSDM2_Filter2) || \
  14138. ((INSTANCE) == DFSDM2_Filter3))
  14139. #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
  14140. ((INSTANCE) == DFSDM1_Channel1) || \
  14141. ((INSTANCE) == DFSDM1_Channel2) || \
  14142. ((INSTANCE) == DFSDM1_Channel3) || \
  14143. ((INSTANCE) == DFSDM2_Channel0) || \
  14144. ((INSTANCE) == DFSDM2_Channel1) || \
  14145. ((INSTANCE) == DFSDM2_Channel2) || \
  14146. ((INSTANCE) == DFSDM2_Channel3) || \
  14147. ((INSTANCE) == DFSDM2_Channel4) || \
  14148. ((INSTANCE) == DFSDM2_Channel5) || \
  14149. ((INSTANCE) == DFSDM2_Channel6) || \
  14150. ((INSTANCE) == DFSDM2_Channel7))
  14151. /******************************* CRC Instances ********************************/
  14152. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  14153. /******************************* DAC Instances ********************************/
  14154. #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
  14155. /******************************** DMA Instances *******************************/
  14156. #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
  14157. ((INSTANCE) == DMA1_Stream1) || \
  14158. ((INSTANCE) == DMA1_Stream2) || \
  14159. ((INSTANCE) == DMA1_Stream3) || \
  14160. ((INSTANCE) == DMA1_Stream4) || \
  14161. ((INSTANCE) == DMA1_Stream5) || \
  14162. ((INSTANCE) == DMA1_Stream6) || \
  14163. ((INSTANCE) == DMA1_Stream7) || \
  14164. ((INSTANCE) == DMA2_Stream0) || \
  14165. ((INSTANCE) == DMA2_Stream1) || \
  14166. ((INSTANCE) == DMA2_Stream2) || \
  14167. ((INSTANCE) == DMA2_Stream3) || \
  14168. ((INSTANCE) == DMA2_Stream4) || \
  14169. ((INSTANCE) == DMA2_Stream5) || \
  14170. ((INSTANCE) == DMA2_Stream6) || \
  14171. ((INSTANCE) == DMA2_Stream7))
  14172. /******************************* GPIO Instances *******************************/
  14173. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  14174. ((INSTANCE) == GPIOB) || \
  14175. ((INSTANCE) == GPIOC) || \
  14176. ((INSTANCE) == GPIOD) || \
  14177. ((INSTANCE) == GPIOE) || \
  14178. ((INSTANCE) == GPIOF) || \
  14179. ((INSTANCE) == GPIOG) || \
  14180. ((INSTANCE) == GPIOH))
  14181. /******************************** I2C Instances *******************************/
  14182. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  14183. ((INSTANCE) == I2C2) || \
  14184. ((INSTANCE) == I2C3))
  14185. /******************************* SMBUS Instances ******************************/
  14186. #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
  14187. /******************************** I2S Instances *******************************/
  14188. #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
  14189. ((INSTANCE) == SPI3))
  14190. #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  14191. ((INSTANCE) == SPI2) || \
  14192. ((INSTANCE) == SPI3) || \
  14193. ((INSTANCE) == SPI4) || \
  14194. ((INSTANCE) == SPI5))
  14195. /*************************** I2S Extended Instances ***************************/
  14196. #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
  14197. ((INSTANCE) == I2S3ext))
  14198. /* Legacy Defines */
  14199. #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
  14200. /******************************* LPTIM Instances ******************************/
  14201. #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
  14202. /******************************* RNG Instances ********************************/
  14203. #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
  14204. /****************************** RTC Instances *********************************/
  14205. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  14206. /******************************** SPI Instances *******************************/
  14207. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  14208. ((INSTANCE) == SPI2) || \
  14209. ((INSTANCE) == SPI3) || \
  14210. ((INSTANCE) == SPI4) || \
  14211. ((INSTANCE) == SPI5))
  14212. /*************************** SPI Extended Instances ***************************/
  14213. #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
  14214. ((INSTANCE) == SPI2) || \
  14215. ((INSTANCE) == SPI3) || \
  14216. ((INSTANCE) == SPI4) || \
  14217. ((INSTANCE) == SPI5) || \
  14218. ((INSTANCE) == I2S2ext) || \
  14219. ((INSTANCE) == I2S3ext))
  14220. /******************************* SAI Instances ********************************/
  14221. #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
  14222. ((PERIPH) == SAI1_Block_B))
  14223. /****************** TIM Instances : All supported instances *******************/
  14224. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14225. ((INSTANCE) == TIM2) || \
  14226. ((INSTANCE) == TIM3) || \
  14227. ((INSTANCE) == TIM4) || \
  14228. ((INSTANCE) == TIM5) || \
  14229. ((INSTANCE) == TIM6) || \
  14230. ((INSTANCE) == TIM7) || \
  14231. ((INSTANCE) == TIM8) || \
  14232. ((INSTANCE) == TIM9) || \
  14233. ((INSTANCE) == TIM10)|| \
  14234. ((INSTANCE) == TIM11)|| \
  14235. ((INSTANCE) == TIM12)|| \
  14236. ((INSTANCE) == TIM13)|| \
  14237. ((INSTANCE) == TIM14))
  14238. /****************** TIM Instances : supporting synchronization ****************/
  14239. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  14240. /************* TIM Instances : at least 1 capture/compare channel *************/
  14241. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14242. ((INSTANCE) == TIM2) || \
  14243. ((INSTANCE) == TIM3) || \
  14244. ((INSTANCE) == TIM4) || \
  14245. ((INSTANCE) == TIM5) || \
  14246. ((INSTANCE) == TIM8) || \
  14247. ((INSTANCE) == TIM9) || \
  14248. ((INSTANCE) == TIM10) || \
  14249. ((INSTANCE) == TIM11) || \
  14250. ((INSTANCE) == TIM12) || \
  14251. ((INSTANCE) == TIM13) || \
  14252. ((INSTANCE) == TIM14))
  14253. /************ TIM Instances : at least 2 capture/compare channels *************/
  14254. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14255. ((INSTANCE) == TIM2) || \
  14256. ((INSTANCE) == TIM3) || \
  14257. ((INSTANCE) == TIM4) || \
  14258. ((INSTANCE) == TIM5) || \
  14259. ((INSTANCE) == TIM8) || \
  14260. ((INSTANCE) == TIM9) || \
  14261. ((INSTANCE) == TIM12))
  14262. /************ TIM Instances : at least 3 capture/compare channels *************/
  14263. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14264. ((INSTANCE) == TIM2) || \
  14265. ((INSTANCE) == TIM3) || \
  14266. ((INSTANCE) == TIM4) || \
  14267. ((INSTANCE) == TIM5) || \
  14268. ((INSTANCE) == TIM8))
  14269. /************ TIM Instances : at least 4 capture/compare channels *************/
  14270. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14271. ((INSTANCE) == TIM2) || \
  14272. ((INSTANCE) == TIM3) || \
  14273. ((INSTANCE) == TIM4) || \
  14274. ((INSTANCE) == TIM5) || \
  14275. ((INSTANCE) == TIM8))
  14276. /******************** TIM Instances : Advanced-control timers *****************/
  14277. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14278. ((INSTANCE) == TIM8))
  14279. /******************* TIM Instances : Timer input XOR function *****************/
  14280. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14281. ((INSTANCE) == TIM2) || \
  14282. ((INSTANCE) == TIM3) || \
  14283. ((INSTANCE) == TIM4) || \
  14284. ((INSTANCE) == TIM5) || \
  14285. ((INSTANCE) == TIM8))
  14286. /****************** TIM Instances : DMA requests generation (UDE) *************/
  14287. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14288. ((INSTANCE) == TIM2) || \
  14289. ((INSTANCE) == TIM3) || \
  14290. ((INSTANCE) == TIM4) || \
  14291. ((INSTANCE) == TIM5) || \
  14292. ((INSTANCE) == TIM6) || \
  14293. ((INSTANCE) == TIM7) || \
  14294. ((INSTANCE) == TIM8))
  14295. /************ TIM Instances : DMA requests generation (CCxDE) *****************/
  14296. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14297. ((INSTANCE) == TIM2) || \
  14298. ((INSTANCE) == TIM3) || \
  14299. ((INSTANCE) == TIM4) || \
  14300. ((INSTANCE) == TIM5) || \
  14301. ((INSTANCE) == TIM8))
  14302. /************ TIM Instances : DMA requests generation (COMDE) *****************/
  14303. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14304. ((INSTANCE) == TIM2) || \
  14305. ((INSTANCE) == TIM3) || \
  14306. ((INSTANCE) == TIM4) || \
  14307. ((INSTANCE) == TIM5) || \
  14308. ((INSTANCE) == TIM8))
  14309. /******************** TIM Instances : DMA burst feature ***********************/
  14310. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14311. ((INSTANCE) == TIM2) || \
  14312. ((INSTANCE) == TIM3) || \
  14313. ((INSTANCE) == TIM4) || \
  14314. ((INSTANCE) == TIM5) || \
  14315. ((INSTANCE) == TIM8))
  14316. /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
  14317. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14318. ((INSTANCE) == TIM2) || \
  14319. ((INSTANCE) == TIM3) || \
  14320. ((INSTANCE) == TIM4) || \
  14321. ((INSTANCE) == TIM5) || \
  14322. ((INSTANCE) == TIM6) || \
  14323. ((INSTANCE) == TIM7) || \
  14324. ((INSTANCE) == TIM8))
  14325. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  14326. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14327. ((INSTANCE) == TIM2) || \
  14328. ((INSTANCE) == TIM3) || \
  14329. ((INSTANCE) == TIM4) || \
  14330. ((INSTANCE) == TIM5) || \
  14331. ((INSTANCE) == TIM8) || \
  14332. ((INSTANCE) == TIM9) || \
  14333. ((INSTANCE) == TIM12))
  14334. /********************** TIM Instances : 32 bit Counter ************************/
  14335. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
  14336. ((INSTANCE) == TIM5))
  14337. /***************** TIM Instances : external trigger input availabe ************/
  14338. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14339. ((INSTANCE) == TIM2) || \
  14340. ((INSTANCE) == TIM3) || \
  14341. ((INSTANCE) == TIM4) || \
  14342. ((INSTANCE) == TIM5) || \
  14343. ((INSTANCE) == TIM8))
  14344. /****************** TIM Instances : remapping capability **********************/
  14345. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
  14346. ((INSTANCE) == TIM5) || \
  14347. ((INSTANCE) == TIM11))
  14348. /******************* TIM Instances : output(s) available **********************/
  14349. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  14350. ((((INSTANCE) == TIM1) && \
  14351. (((CHANNEL) == TIM_CHANNEL_1) || \
  14352. ((CHANNEL) == TIM_CHANNEL_2) || \
  14353. ((CHANNEL) == TIM_CHANNEL_3) || \
  14354. ((CHANNEL) == TIM_CHANNEL_4))) \
  14355. || \
  14356. (((INSTANCE) == TIM2) && \
  14357. (((CHANNEL) == TIM_CHANNEL_1) || \
  14358. ((CHANNEL) == TIM_CHANNEL_2) || \
  14359. ((CHANNEL) == TIM_CHANNEL_3) || \
  14360. ((CHANNEL) == TIM_CHANNEL_4))) \
  14361. || \
  14362. (((INSTANCE) == TIM3) && \
  14363. (((CHANNEL) == TIM_CHANNEL_1) || \
  14364. ((CHANNEL) == TIM_CHANNEL_2) || \
  14365. ((CHANNEL) == TIM_CHANNEL_3) || \
  14366. ((CHANNEL) == TIM_CHANNEL_4))) \
  14367. || \
  14368. (((INSTANCE) == TIM4) && \
  14369. (((CHANNEL) == TIM_CHANNEL_1) || \
  14370. ((CHANNEL) == TIM_CHANNEL_2) || \
  14371. ((CHANNEL) == TIM_CHANNEL_3) || \
  14372. ((CHANNEL) == TIM_CHANNEL_4))) \
  14373. || \
  14374. (((INSTANCE) == TIM5) && \
  14375. (((CHANNEL) == TIM_CHANNEL_1) || \
  14376. ((CHANNEL) == TIM_CHANNEL_2) || \
  14377. ((CHANNEL) == TIM_CHANNEL_3) || \
  14378. ((CHANNEL) == TIM_CHANNEL_4))) \
  14379. || \
  14380. (((INSTANCE) == TIM8) && \
  14381. (((CHANNEL) == TIM_CHANNEL_1) || \
  14382. ((CHANNEL) == TIM_CHANNEL_2) || \
  14383. ((CHANNEL) == TIM_CHANNEL_3) || \
  14384. ((CHANNEL) == TIM_CHANNEL_4))) \
  14385. || \
  14386. (((INSTANCE) == TIM9) && \
  14387. (((CHANNEL) == TIM_CHANNEL_1) || \
  14388. ((CHANNEL) == TIM_CHANNEL_2))) \
  14389. || \
  14390. (((INSTANCE) == TIM10) && \
  14391. (((CHANNEL) == TIM_CHANNEL_1))) \
  14392. || \
  14393. (((INSTANCE) == TIM11) && \
  14394. (((CHANNEL) == TIM_CHANNEL_1))) \
  14395. || \
  14396. (((INSTANCE) == TIM12) && \
  14397. (((CHANNEL) == TIM_CHANNEL_1) || \
  14398. ((CHANNEL) == TIM_CHANNEL_2))) \
  14399. || \
  14400. (((INSTANCE) == TIM13) && \
  14401. (((CHANNEL) == TIM_CHANNEL_1))) \
  14402. || \
  14403. (((INSTANCE) == TIM14) && \
  14404. (((CHANNEL) == TIM_CHANNEL_1))))
  14405. /************ TIM Instances : complementary output(s) available ***************/
  14406. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  14407. ((((INSTANCE) == TIM1) && \
  14408. (((CHANNEL) == TIM_CHANNEL_1) || \
  14409. ((CHANNEL) == TIM_CHANNEL_2) || \
  14410. ((CHANNEL) == TIM_CHANNEL_3))) \
  14411. || \
  14412. (((INSTANCE) == TIM8) && \
  14413. (((CHANNEL) == TIM_CHANNEL_1) || \
  14414. ((CHANNEL) == TIM_CHANNEL_2) || \
  14415. ((CHANNEL) == TIM_CHANNEL_3))))
  14416. /****************** TIM Instances : supporting counting mode selection ********/
  14417. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14418. ((INSTANCE) == TIM2) || \
  14419. ((INSTANCE) == TIM3) || \
  14420. ((INSTANCE) == TIM4) || \
  14421. ((INSTANCE) == TIM5) || \
  14422. ((INSTANCE) == TIM8))
  14423. /****************** TIM Instances : supporting clock division *****************/
  14424. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14425. ((INSTANCE) == TIM2) || \
  14426. ((INSTANCE) == TIM3) || \
  14427. ((INSTANCE) == TIM4) || \
  14428. ((INSTANCE) == TIM5) || \
  14429. ((INSTANCE) == TIM8) || \
  14430. ((INSTANCE) == TIM9) || \
  14431. ((INSTANCE) == TIM10)|| \
  14432. ((INSTANCE) == TIM11)|| \
  14433. ((INSTANCE) == TIM12)|| \
  14434. ((INSTANCE) == TIM13)|| \
  14435. ((INSTANCE) == TIM14))
  14436. /****************** TIM Instances : supporting commutation event generation ***/
  14437. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
  14438. ((INSTANCE) == TIM8))
  14439. /****************** TIM Instances : supporting OCxREF clear *******************/
  14440. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14441. ((INSTANCE) == TIM2) || \
  14442. ((INSTANCE) == TIM3) || \
  14443. ((INSTANCE) == TIM4) || \
  14444. ((INSTANCE) == TIM5) || \
  14445. ((INSTANCE) == TIM8))
  14446. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  14447. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14448. ((INSTANCE) == TIM2) || \
  14449. ((INSTANCE) == TIM3) || \
  14450. ((INSTANCE) == TIM4) || \
  14451. ((INSTANCE) == TIM5) || \
  14452. ((INSTANCE) == TIM8) || \
  14453. ((INSTANCE) == TIM9) || \
  14454. ((INSTANCE) == TIM12))
  14455. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  14456. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14457. ((INSTANCE) == TIM2) || \
  14458. ((INSTANCE) == TIM3) || \
  14459. ((INSTANCE) == TIM4) || \
  14460. ((INSTANCE) == TIM5) || \
  14461. ((INSTANCE) == TIM8))
  14462. /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
  14463. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14464. ((INSTANCE) == TIM2) || \
  14465. ((INSTANCE) == TIM3) || \
  14466. ((INSTANCE) == TIM4) || \
  14467. ((INSTANCE) == TIM5) || \
  14468. ((INSTANCE) == TIM8) || \
  14469. ((INSTANCE) == TIM9) || \
  14470. ((INSTANCE) == TIM12))
  14471. /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
  14472. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14473. ((INSTANCE) == TIM2) || \
  14474. ((INSTANCE) == TIM3) || \
  14475. ((INSTANCE) == TIM4) || \
  14476. ((INSTANCE) == TIM5) || \
  14477. ((INSTANCE) == TIM8) || \
  14478. ((INSTANCE) == TIM9) || \
  14479. ((INSTANCE) == TIM12))
  14480. /****************** TIM Instances : supporting repetition counter *************/
  14481. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14482. ((INSTANCE) == TIM8))
  14483. /****************** TIM Instances : supporting encoder interface **************/
  14484. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14485. ((INSTANCE) == TIM2) || \
  14486. ((INSTANCE) == TIM3) || \
  14487. ((INSTANCE) == TIM4) || \
  14488. ((INSTANCE) == TIM5) || \
  14489. ((INSTANCE) == TIM8) || \
  14490. ((INSTANCE) == TIM9))
  14491. /****************** TIM Instances : supporting Hall sensor interface **********/
  14492. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14493. ((INSTANCE) == TIM2) || \
  14494. ((INSTANCE) == TIM3) || \
  14495. ((INSTANCE) == TIM4) || \
  14496. ((INSTANCE) == TIM5) || \
  14497. ((INSTANCE) == TIM8))
  14498. /****************** TIM Instances : supporting the break function *************/
  14499. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  14500. ((INSTANCE) == TIM8))
  14501. /******************** USART Instances : Synchronous mode **********************/
  14502. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  14503. ((INSTANCE) == USART2) || \
  14504. ((INSTANCE) == USART3) || \
  14505. ((INSTANCE) == USART6))
  14506. /******************** UART Instances : Half-Duplex mode **********************/
  14507. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  14508. ((INSTANCE) == USART2) || \
  14509. ((INSTANCE) == USART3) || \
  14510. ((INSTANCE) == UART4) || \
  14511. ((INSTANCE) == UART5) || \
  14512. ((INSTANCE) == USART6) || \
  14513. ((INSTANCE) == UART7) || \
  14514. ((INSTANCE) == UART8) || \
  14515. ((INSTANCE) == UART9) || \
  14516. ((INSTANCE) == UART10))
  14517. /* Legacy defines */
  14518. #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  14519. /****************** UART Instances : Hardware Flow control ********************/
  14520. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  14521. ((INSTANCE) == USART2) || \
  14522. ((INSTANCE) == USART3) || \
  14523. ((INSTANCE) == USART6))
  14524. /******************** UART Instances : LIN mode **********************/
  14525. #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  14526. /********************* UART Instances : Smart card mode ***********************/
  14527. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  14528. ((INSTANCE) == USART2) || \
  14529. ((INSTANCE) == USART3) || \
  14530. ((INSTANCE) == USART6))
  14531. /*********************** UART Instances : IRDA mode ***************************/
  14532. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  14533. ((INSTANCE) == USART2) || \
  14534. ((INSTANCE) == USART3) || \
  14535. ((INSTANCE) == UART4) || \
  14536. ((INSTANCE) == UART5) || \
  14537. ((INSTANCE) == USART6) || \
  14538. ((INSTANCE) == UART7) || \
  14539. ((INSTANCE) == UART8) || \
  14540. ((INSTANCE) == UART9) || \
  14541. ((INSTANCE) == UART10))
  14542. /*********************** PCD Instances ****************************************/
  14543. #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
  14544. /*********************** HCD Instances ****************************************/
  14545. #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
  14546. /****************************** SDIO Instances ********************************/
  14547. #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
  14548. /****************************** IWDG Instances ********************************/
  14549. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  14550. /****************************** WWDG Instances ********************************/
  14551. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  14552. /***************************** FMPI2C Instances *******************************/
  14553. #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
  14554. #define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
  14555. /****************************** QSPI Instances ********************************/
  14556. #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
  14557. /****************************** USB Instances ********************************/
  14558. #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
  14559. /****************************** USB Exported Constants ************************/
  14560. #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
  14561. #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
  14562. #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
  14563. #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
  14564. /*
  14565. * @brief Specific devices reset values definitions
  14566. */
  14567. #define RCC_PLLCFGR_RST_VALUE 0x24003010U
  14568. #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
  14569. #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
  14570. #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
  14571. #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
  14572. #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  14573. #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
  14574. #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  14575. #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  14576. #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  14577. #define RCC_PLLN_MIN_VALUE 50U
  14578. #define RCC_PLLN_MAX_VALUE 432U
  14579. #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  14580. #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  14581. #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  14582. #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  14583. #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  14584. #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  14585. #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  14586. /**
  14587. * @}
  14588. */
  14589. /**
  14590. * @}
  14591. */
  14592. /**
  14593. * @}
  14594. */
  14595. #ifdef __cplusplus
  14596. }
  14597. #endif /* __cplusplus */
  14598. #endif /* __STM32F413xx_H */
  14599. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/