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system_stm32f4xx.c 28 KB

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  1. /**
  2. ******************************************************************************
  3. * @file system_stm32f4xx.c
  4. * @author MCD Application Team
  5. * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
  6. *
  7. * This file provides two functions and one global variable to be called from
  8. * user application:
  9. * - SystemInit(): This function is called at startup just after reset and
  10. * before branch to main program. This call is made inside
  11. * the "startup_stm32f4xx.s" file.
  12. *
  13. * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14. * by the user application to setup the SysTick
  15. * timer or configure other parameters.
  16. *
  17. * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18. * be called whenever the core clock is changed
  19. * during program execution.
  20. *
  21. *
  22. ******************************************************************************
  23. * @attention
  24. *
  25. * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  26. *
  27. * Redistribution and use in source and binary forms, with or without modification,
  28. * are permitted provided that the following conditions are met:
  29. * 1. Redistributions of source code must retain the above copyright notice,
  30. * this list of conditions and the following disclaimer.
  31. * 2. Redistributions in binary form must reproduce the above copyright notice,
  32. * this list of conditions and the following disclaimer in the documentation
  33. * and/or other materials provided with the distribution.
  34. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  35. * may be used to endorse or promote products derived from this software
  36. * without specific prior written permission.
  37. *
  38. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  39. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  40. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  41. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  42. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  43. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  44. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  45. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  46. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48. *
  49. ******************************************************************************
  50. */
  51. /** @addtogroup CMSIS
  52. * @{
  53. */
  54. /** @addtogroup stm32f4xx_system
  55. * @{
  56. */
  57. /** @addtogroup STM32F4xx_System_Private_Includes
  58. * @{
  59. */
  60. #include "stm32f4xx.h"
  61. #if !defined (HSE_VALUE)
  62. #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
  63. #endif /* HSE_VALUE */
  64. #if !defined (HSI_VALUE)
  65. #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  66. #endif /* HSI_VALUE */
  67. /**
  68. * @}
  69. */
  70. /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
  71. * @{
  72. */
  73. /**
  74. * @}
  75. */
  76. /** @addtogroup STM32F4xx_System_Private_Defines
  77. * @{
  78. */
  79. /************************* Miscellaneous Configuration ************************/
  80. /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
  81. #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  82. || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  83. || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
  84. /* #define DATA_IN_ExtSRAM */
  85. #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
  86. STM32F412Zx || STM32F412Vx */
  87. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  88. || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
  89. /* #define DATA_IN_ExtSDRAM */
  90. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
  91. STM32F479xx */
  92. /*!< Uncomment the following line if you need to relocate your vector Table in
  93. Internal SRAM. */
  94. /* #define VECT_TAB_SRAM */
  95. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
  96. This value must be a multiple of 0x200. */
  97. /******************************************************************************/
  98. /**
  99. * @}
  100. */
  101. /** @addtogroup STM32F4xx_System_Private_Macros
  102. * @{
  103. */
  104. /**
  105. * @}
  106. */
  107. /** @addtogroup STM32F4xx_System_Private_Variables
  108. * @{
  109. */
  110. /* This variable is updated in three ways:
  111. 1) by calling CMSIS function SystemCoreClockUpdate()
  112. 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  113. 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  114. Note: If you use this function to configure the system clock; then there
  115. is no need to call the 2 first functions listed above, since SystemCoreClock
  116. variable is updated automatically.
  117. */
  118. uint32_t SystemCoreClock = 16000000;
  119. const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  120. const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
  121. /**
  122. * @}
  123. */
  124. /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
  125. * @{
  126. */
  127. #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
  128. static void SystemInit_ExtMemCtl(void);
  129. #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
  130. /**
  131. * @}
  132. */
  133. /** @addtogroup STM32F4xx_System_Private_Functions
  134. * @{
  135. */
  136. /**
  137. * @brief Setup the microcontroller system
  138. * Initialize the FPU setting, vector table location and External memory
  139. * configuration.
  140. * @param None
  141. * @retval None
  142. */
  143. void SystemInit(void)
  144. {
  145. /* FPU settings ------------------------------------------------------------*/
  146. #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  147. SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
  148. #endif
  149. /* Reset the RCC clock configuration to the default reset state ------------*/
  150. /* Set HSION bit */
  151. RCC->CR |= (uint32_t)0x00000001;
  152. /* Reset CFGR register */
  153. RCC->CFGR = 0x00000000;
  154. /* Reset HSEON, CSSON and PLLON bits */
  155. RCC->CR &= (uint32_t)0xFEF6FFFF;
  156. /* Reset PLLCFGR register */
  157. RCC->PLLCFGR = 0x24003010;
  158. /* Reset HSEBYP bit */
  159. RCC->CR &= (uint32_t)0xFFFBFFFF;
  160. /* Disable all interrupts */
  161. RCC->CIR = 0x00000000;
  162. #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
  163. SystemInit_ExtMemCtl();
  164. #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
  165. /* Configure the Vector Table location add offset address ------------------*/
  166. #ifdef VECT_TAB_SRAM
  167. SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
  168. #else
  169. SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
  170. #endif
  171. }
  172. /**
  173. * @brief Update SystemCoreClock variable according to Clock Register Values.
  174. * The SystemCoreClock variable contains the core clock (HCLK), it can
  175. * be used by the user application to setup the SysTick timer or configure
  176. * other parameters.
  177. *
  178. * @note Each time the core clock (HCLK) changes, this function must be called
  179. * to update SystemCoreClock variable value. Otherwise, any configuration
  180. * based on this variable will be incorrect.
  181. *
  182. * @note - The system frequency computed by this function is not the real
  183. * frequency in the chip. It is calculated based on the predefined
  184. * constant and the selected clock source:
  185. *
  186. * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  187. *
  188. * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  189. *
  190. * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  191. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
  192. *
  193. * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
  194. * 16 MHz) but the real value may vary depending on the variations
  195. * in voltage and temperature.
  196. *
  197. * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
  198. * depends on the application requirements), user has to ensure that HSE_VALUE
  199. * is same as the real frequency of the crystal used. Otherwise, this function
  200. * may have wrong result.
  201. *
  202. * - The result of this function could be not correct when using fractional
  203. * value for HSE crystal.
  204. *
  205. * @param None
  206. * @retval None
  207. */
  208. void SystemCoreClockUpdate(void)
  209. {
  210. uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
  211. /* Get SYSCLK source -------------------------------------------------------*/
  212. tmp = RCC->CFGR & RCC_CFGR_SWS;
  213. switch (tmp)
  214. {
  215. case 0x00: /* HSI used as system clock source */
  216. SystemCoreClock = HSI_VALUE;
  217. break;
  218. case 0x04: /* HSE used as system clock source */
  219. SystemCoreClock = HSE_VALUE;
  220. break;
  221. case 0x08: /* PLL used as system clock source */
  222. /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
  223. SYSCLK = PLL_VCO / PLL_P
  224. */
  225. pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
  226. pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
  227. if (pllsource != 0)
  228. {
  229. /* HSE used as PLL clock source */
  230. pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
  231. }
  232. else
  233. {
  234. /* HSI used as PLL clock source */
  235. pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
  236. }
  237. pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
  238. SystemCoreClock = pllvco/pllp;
  239. break;
  240. default:
  241. SystemCoreClock = HSI_VALUE;
  242. break;
  243. }
  244. /* Compute HCLK frequency --------------------------------------------------*/
  245. /* Get HCLK prescaler */
  246. tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  247. /* HCLK frequency */
  248. SystemCoreClock >>= tmp;
  249. }
  250. #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
  251. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  252. || defined(STM32F469xx) || defined(STM32F479xx)
  253. /**
  254. * @brief Setup the external memory controller.
  255. * Called in startup_stm32f4xx.s before jump to main.
  256. * This function configures the external memories (SRAM/SDRAM)
  257. * This SRAM/SDRAM will be used as program data memory (including heap and stack).
  258. * @param None
  259. * @retval None
  260. */
  261. void SystemInit_ExtMemCtl(void)
  262. {
  263. __IO uint32_t tmp = 0x00;
  264. register uint32_t tmpreg = 0, timeout = 0xFFFF;
  265. register __IO uint32_t index;
  266. /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
  267. RCC->AHB1ENR |= 0x000001F8;
  268. /* Delay after an RCC peripheral clock enabling */
  269. tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
  270. /* Connect PDx pins to FMC Alternate function */
  271. GPIOD->AFR[0] = 0x00CCC0CC;
  272. GPIOD->AFR[1] = 0xCCCCCCCC;
  273. /* Configure PDx pins in Alternate function mode */
  274. GPIOD->MODER = 0xAAAA0A8A;
  275. /* Configure PDx pins speed to 100 MHz */
  276. GPIOD->OSPEEDR = 0xFFFF0FCF;
  277. /* Configure PDx pins Output type to push-pull */
  278. GPIOD->OTYPER = 0x00000000;
  279. /* No pull-up, pull-down for PDx pins */
  280. GPIOD->PUPDR = 0x00000000;
  281. /* Connect PEx pins to FMC Alternate function */
  282. GPIOE->AFR[0] = 0xC00CC0CC;
  283. GPIOE->AFR[1] = 0xCCCCCCCC;
  284. /* Configure PEx pins in Alternate function mode */
  285. GPIOE->MODER = 0xAAAA828A;
  286. /* Configure PEx pins speed to 100 MHz */
  287. GPIOE->OSPEEDR = 0xFFFFC3CF;
  288. /* Configure PEx pins Output type to push-pull */
  289. GPIOE->OTYPER = 0x00000000;
  290. /* No pull-up, pull-down for PEx pins */
  291. GPIOE->PUPDR = 0x00000000;
  292. /* Connect PFx pins to FMC Alternate function */
  293. GPIOF->AFR[0] = 0xCCCCCCCC;
  294. GPIOF->AFR[1] = 0xCCCCCCCC;
  295. /* Configure PFx pins in Alternate function mode */
  296. GPIOF->MODER = 0xAA800AAA;
  297. /* Configure PFx pins speed to 50 MHz */
  298. GPIOF->OSPEEDR = 0xAA800AAA;
  299. /* Configure PFx pins Output type to push-pull */
  300. GPIOF->OTYPER = 0x00000000;
  301. /* No pull-up, pull-down for PFx pins */
  302. GPIOF->PUPDR = 0x00000000;
  303. /* Connect PGx pins to FMC Alternate function */
  304. GPIOG->AFR[0] = 0xCCCCCCCC;
  305. GPIOG->AFR[1] = 0xCCCCCCCC;
  306. /* Configure PGx pins in Alternate function mode */
  307. GPIOG->MODER = 0xAAAAAAAA;
  308. /* Configure PGx pins speed to 50 MHz */
  309. GPIOG->OSPEEDR = 0xAAAAAAAA;
  310. /* Configure PGx pins Output type to push-pull */
  311. GPIOG->OTYPER = 0x00000000;
  312. /* No pull-up, pull-down for PGx pins */
  313. GPIOG->PUPDR = 0x00000000;
  314. /* Connect PHx pins to FMC Alternate function */
  315. GPIOH->AFR[0] = 0x00C0CC00;
  316. GPIOH->AFR[1] = 0xCCCCCCCC;
  317. /* Configure PHx pins in Alternate function mode */
  318. GPIOH->MODER = 0xAAAA08A0;
  319. /* Configure PHx pins speed to 50 MHz */
  320. GPIOH->OSPEEDR = 0xAAAA08A0;
  321. /* Configure PHx pins Output type to push-pull */
  322. GPIOH->OTYPER = 0x00000000;
  323. /* No pull-up, pull-down for PHx pins */
  324. GPIOH->PUPDR = 0x00000000;
  325. /* Connect PIx pins to FMC Alternate function */
  326. GPIOI->AFR[0] = 0xCCCCCCCC;
  327. GPIOI->AFR[1] = 0x00000CC0;
  328. /* Configure PIx pins in Alternate function mode */
  329. GPIOI->MODER = 0x0028AAAA;
  330. /* Configure PIx pins speed to 50 MHz */
  331. GPIOI->OSPEEDR = 0x0028AAAA;
  332. /* Configure PIx pins Output type to push-pull */
  333. GPIOI->OTYPER = 0x00000000;
  334. /* No pull-up, pull-down for PIx pins */
  335. GPIOI->PUPDR = 0x00000000;
  336. /*-- FMC Configuration -------------------------------------------------------*/
  337. /* Enable the FMC interface clock */
  338. RCC->AHB3ENR |= 0x00000001;
  339. /* Delay after an RCC peripheral clock enabling */
  340. tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
  341. FMC_Bank5_6->SDCR[0] = 0x000019E4;
  342. FMC_Bank5_6->SDTR[0] = 0x01115351;
  343. /* SDRAM initialization sequence */
  344. /* Clock enable command */
  345. FMC_Bank5_6->SDCMR = 0x00000011;
  346. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  347. while((tmpreg != 0) && (timeout-- > 0))
  348. {
  349. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  350. }
  351. /* Delay */
  352. for (index = 0; index<1000; index++);
  353. /* PALL command */
  354. FMC_Bank5_6->SDCMR = 0x00000012;
  355. timeout = 0xFFFF;
  356. while((tmpreg != 0) && (timeout-- > 0))
  357. {
  358. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  359. }
  360. /* Auto refresh command */
  361. FMC_Bank5_6->SDCMR = 0x00000073;
  362. timeout = 0xFFFF;
  363. while((tmpreg != 0) && (timeout-- > 0))
  364. {
  365. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  366. }
  367. /* MRD register program */
  368. FMC_Bank5_6->SDCMR = 0x00046014;
  369. timeout = 0xFFFF;
  370. while((tmpreg != 0) && (timeout-- > 0))
  371. {
  372. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  373. }
  374. /* Set refresh count */
  375. tmpreg = FMC_Bank5_6->SDRTR;
  376. FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
  377. /* Disable write protection */
  378. tmpreg = FMC_Bank5_6->SDCR[0];
  379. FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
  380. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
  381. /* Configure and enable Bank1_SRAM2 */
  382. FMC_Bank1->BTCR[2] = 0x00001011;
  383. FMC_Bank1->BTCR[3] = 0x00000201;
  384. FMC_Bank1E->BWTR[2] = 0x0fffffff;
  385. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
  386. #if defined(STM32F469xx) || defined(STM32F479xx)
  387. /* Configure and enable Bank1_SRAM2 */
  388. FMC_Bank1->BTCR[2] = 0x00001091;
  389. FMC_Bank1->BTCR[3] = 0x00110212;
  390. FMC_Bank1E->BWTR[2] = 0x0fffffff;
  391. #endif /* STM32F469xx || STM32F479xx */
  392. (void)(tmp);
  393. }
  394. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
  395. #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
  396. /**
  397. * @brief Setup the external memory controller.
  398. * Called in startup_stm32f4xx.s before jump to main.
  399. * This function configures the external memories (SRAM/SDRAM)
  400. * This SRAM/SDRAM will be used as program data memory (including heap and stack).
  401. * @param None
  402. * @retval None
  403. */
  404. void SystemInit_ExtMemCtl(void)
  405. {
  406. __IO uint32_t tmp = 0x00;
  407. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  408. || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
  409. #if defined (DATA_IN_ExtSDRAM)
  410. register uint32_t tmpreg = 0, timeout = 0xFFFF;
  411. register __IO uint32_t index;
  412. #if defined(STM32F446xx)
  413. /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
  414. clock */
  415. RCC->AHB1ENR |= 0x0000007D;
  416. #else
  417. /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
  418. clock */
  419. RCC->AHB1ENR |= 0x000001F8;
  420. #endif /* STM32F446xx */
  421. /* Delay after an RCC peripheral clock enabling */
  422. tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
  423. #if defined(STM32F446xx)
  424. /* Connect PAx pins to FMC Alternate function */
  425. GPIOA->AFR[0] |= 0xC0000000;
  426. GPIOA->AFR[1] |= 0x00000000;
  427. /* Configure PDx pins in Alternate function mode */
  428. GPIOA->MODER |= 0x00008000;
  429. /* Configure PDx pins speed to 50 MHz */
  430. GPIOA->OSPEEDR |= 0x00008000;
  431. /* Configure PDx pins Output type to push-pull */
  432. GPIOA->OTYPER |= 0x00000000;
  433. /* No pull-up, pull-down for PDx pins */
  434. GPIOA->PUPDR |= 0x00000000;
  435. /* Connect PCx pins to FMC Alternate function */
  436. GPIOC->AFR[0] |= 0x00CC0000;
  437. GPIOC->AFR[1] |= 0x00000000;
  438. /* Configure PDx pins in Alternate function mode */
  439. GPIOC->MODER |= 0x00000A00;
  440. /* Configure PDx pins speed to 50 MHz */
  441. GPIOC->OSPEEDR |= 0x00000A00;
  442. /* Configure PDx pins Output type to push-pull */
  443. GPIOC->OTYPER |= 0x00000000;
  444. /* No pull-up, pull-down for PDx pins */
  445. GPIOC->PUPDR |= 0x00000000;
  446. #endif /* STM32F446xx */
  447. /* Connect PDx pins to FMC Alternate function */
  448. GPIOD->AFR[0] = 0x000000CC;
  449. GPIOD->AFR[1] = 0xCC000CCC;
  450. /* Configure PDx pins in Alternate function mode */
  451. GPIOD->MODER = 0xA02A000A;
  452. /* Configure PDx pins speed to 50 MHz */
  453. GPIOD->OSPEEDR = 0xA02A000A;
  454. /* Configure PDx pins Output type to push-pull */
  455. GPIOD->OTYPER = 0x00000000;
  456. /* No pull-up, pull-down for PDx pins */
  457. GPIOD->PUPDR = 0x00000000;
  458. /* Connect PEx pins to FMC Alternate function */
  459. GPIOE->AFR[0] = 0xC00000CC;
  460. GPIOE->AFR[1] = 0xCCCCCCCC;
  461. /* Configure PEx pins in Alternate function mode */
  462. GPIOE->MODER = 0xAAAA800A;
  463. /* Configure PEx pins speed to 50 MHz */
  464. GPIOE->OSPEEDR = 0xAAAA800A;
  465. /* Configure PEx pins Output type to push-pull */
  466. GPIOE->OTYPER = 0x00000000;
  467. /* No pull-up, pull-down for PEx pins */
  468. GPIOE->PUPDR = 0x00000000;
  469. /* Connect PFx pins to FMC Alternate function */
  470. GPIOF->AFR[0] = 0xCCCCCCCC;
  471. GPIOF->AFR[1] = 0xCCCCCCCC;
  472. /* Configure PFx pins in Alternate function mode */
  473. GPIOF->MODER = 0xAA800AAA;
  474. /* Configure PFx pins speed to 50 MHz */
  475. GPIOF->OSPEEDR = 0xAA800AAA;
  476. /* Configure PFx pins Output type to push-pull */
  477. GPIOF->OTYPER = 0x00000000;
  478. /* No pull-up, pull-down for PFx pins */
  479. GPIOF->PUPDR = 0x00000000;
  480. /* Connect PGx pins to FMC Alternate function */
  481. GPIOG->AFR[0] = 0xCCCCCCCC;
  482. GPIOG->AFR[1] = 0xCCCCCCCC;
  483. /* Configure PGx pins in Alternate function mode */
  484. GPIOG->MODER = 0xAAAAAAAA;
  485. /* Configure PGx pins speed to 50 MHz */
  486. GPIOG->OSPEEDR = 0xAAAAAAAA;
  487. /* Configure PGx pins Output type to push-pull */
  488. GPIOG->OTYPER = 0x00000000;
  489. /* No pull-up, pull-down for PGx pins */
  490. GPIOG->PUPDR = 0x00000000;
  491. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  492. || defined(STM32F469xx) || defined(STM32F479xx)
  493. /* Connect PHx pins to FMC Alternate function */
  494. GPIOH->AFR[0] = 0x00C0CC00;
  495. GPIOH->AFR[1] = 0xCCCCCCCC;
  496. /* Configure PHx pins in Alternate function mode */
  497. GPIOH->MODER = 0xAAAA08A0;
  498. /* Configure PHx pins speed to 50 MHz */
  499. GPIOH->OSPEEDR = 0xAAAA08A0;
  500. /* Configure PHx pins Output type to push-pull */
  501. GPIOH->OTYPER = 0x00000000;
  502. /* No pull-up, pull-down for PHx pins */
  503. GPIOH->PUPDR = 0x00000000;
  504. /* Connect PIx pins to FMC Alternate function */
  505. GPIOI->AFR[0] = 0xCCCCCCCC;
  506. GPIOI->AFR[1] = 0x00000CC0;
  507. /* Configure PIx pins in Alternate function mode */
  508. GPIOI->MODER = 0x0028AAAA;
  509. /* Configure PIx pins speed to 50 MHz */
  510. GPIOI->OSPEEDR = 0x0028AAAA;
  511. /* Configure PIx pins Output type to push-pull */
  512. GPIOI->OTYPER = 0x00000000;
  513. /* No pull-up, pull-down for PIx pins */
  514. GPIOI->PUPDR = 0x00000000;
  515. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
  516. /*-- FMC Configuration -------------------------------------------------------*/
  517. /* Enable the FMC interface clock */
  518. RCC->AHB3ENR |= 0x00000001;
  519. /* Delay after an RCC peripheral clock enabling */
  520. tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
  521. /* Configure and enable SDRAM bank1 */
  522. #if defined(STM32F446xx)
  523. FMC_Bank5_6->SDCR[0] = 0x00001954;
  524. #else
  525. FMC_Bank5_6->SDCR[0] = 0x000019E4;
  526. #endif /* STM32F446xx */
  527. FMC_Bank5_6->SDTR[0] = 0x01115351;
  528. /* SDRAM initialization sequence */
  529. /* Clock enable command */
  530. FMC_Bank5_6->SDCMR = 0x00000011;
  531. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  532. while((tmpreg != 0) && (timeout-- > 0))
  533. {
  534. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  535. }
  536. /* Delay */
  537. for (index = 0; index<1000; index++);
  538. /* PALL command */
  539. FMC_Bank5_6->SDCMR = 0x00000012;
  540. timeout = 0xFFFF;
  541. while((tmpreg != 0) && (timeout-- > 0))
  542. {
  543. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  544. }
  545. /* Auto refresh command */
  546. #if defined(STM32F446xx)
  547. FMC_Bank5_6->SDCMR = 0x000000F3;
  548. #else
  549. FMC_Bank5_6->SDCMR = 0x00000073;
  550. #endif /* STM32F446xx */
  551. timeout = 0xFFFF;
  552. while((tmpreg != 0) && (timeout-- > 0))
  553. {
  554. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  555. }
  556. /* MRD register program */
  557. #if defined(STM32F446xx)
  558. FMC_Bank5_6->SDCMR = 0x00044014;
  559. #else
  560. FMC_Bank5_6->SDCMR = 0x00046014;
  561. #endif /* STM32F446xx */
  562. timeout = 0xFFFF;
  563. while((tmpreg != 0) && (timeout-- > 0))
  564. {
  565. tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
  566. }
  567. /* Set refresh count */
  568. tmpreg = FMC_Bank5_6->SDRTR;
  569. #if defined(STM32F446xx)
  570. FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
  571. #else
  572. FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
  573. #endif /* STM32F446xx */
  574. /* Disable write protection */
  575. tmpreg = FMC_Bank5_6->SDCR[0];
  576. FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
  577. #endif /* DATA_IN_ExtSDRAM */
  578. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
  579. #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  580. || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  581. || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
  582. #if defined(DATA_IN_ExtSRAM)
  583. /*-- GPIOs Configuration -----------------------------------------------------*/
  584. /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
  585. RCC->AHB1ENR |= 0x00000078;
  586. /* Delay after an RCC peripheral clock enabling */
  587. tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
  588. /* Connect PDx pins to FMC Alternate function */
  589. GPIOD->AFR[0] = 0x00CCC0CC;
  590. GPIOD->AFR[1] = 0xCCCCCCCC;
  591. /* Configure PDx pins in Alternate function mode */
  592. GPIOD->MODER = 0xAAAA0A8A;
  593. /* Configure PDx pins speed to 100 MHz */
  594. GPIOD->OSPEEDR = 0xFFFF0FCF;
  595. /* Configure PDx pins Output type to push-pull */
  596. GPIOD->OTYPER = 0x00000000;
  597. /* No pull-up, pull-down for PDx pins */
  598. GPIOD->PUPDR = 0x00000000;
  599. /* Connect PEx pins to FMC Alternate function */
  600. GPIOE->AFR[0] = 0xC00CC0CC;
  601. GPIOE->AFR[1] = 0xCCCCCCCC;
  602. /* Configure PEx pins in Alternate function mode */
  603. GPIOE->MODER = 0xAAAA828A;
  604. /* Configure PEx pins speed to 100 MHz */
  605. GPIOE->OSPEEDR = 0xFFFFC3CF;
  606. /* Configure PEx pins Output type to push-pull */
  607. GPIOE->OTYPER = 0x00000000;
  608. /* No pull-up, pull-down for PEx pins */
  609. GPIOE->PUPDR = 0x00000000;
  610. /* Connect PFx pins to FMC Alternate function */
  611. GPIOF->AFR[0] = 0x00CCCCCC;
  612. GPIOF->AFR[1] = 0xCCCC0000;
  613. /* Configure PFx pins in Alternate function mode */
  614. GPIOF->MODER = 0xAA000AAA;
  615. /* Configure PFx pins speed to 100 MHz */
  616. GPIOF->OSPEEDR = 0xFF000FFF;
  617. /* Configure PFx pins Output type to push-pull */
  618. GPIOF->OTYPER = 0x00000000;
  619. /* No pull-up, pull-down for PFx pins */
  620. GPIOF->PUPDR = 0x00000000;
  621. /* Connect PGx pins to FMC Alternate function */
  622. GPIOG->AFR[0] = 0x00CCCCCC;
  623. GPIOG->AFR[1] = 0x000000C0;
  624. /* Configure PGx pins in Alternate function mode */
  625. GPIOG->MODER = 0x00085AAA;
  626. /* Configure PGx pins speed to 100 MHz */
  627. GPIOG->OSPEEDR = 0x000CAFFF;
  628. /* Configure PGx pins Output type to push-pull */
  629. GPIOG->OTYPER = 0x00000000;
  630. /* No pull-up, pull-down for PGx pins */
  631. GPIOG->PUPDR = 0x00000000;
  632. /*-- FMC/FSMC Configuration --------------------------------------------------*/
  633. /* Enable the FMC/FSMC interface clock */
  634. RCC->AHB3ENR |= 0x00000001;
  635. #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
  636. /* Delay after an RCC peripheral clock enabling */
  637. tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
  638. /* Configure and enable Bank1_SRAM2 */
  639. FMC_Bank1->BTCR[2] = 0x00001011;
  640. FMC_Bank1->BTCR[3] = 0x00000201;
  641. FMC_Bank1E->BWTR[2] = 0x0fffffff;
  642. #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
  643. #if defined(STM32F469xx) || defined(STM32F479xx)
  644. /* Delay after an RCC peripheral clock enabling */
  645. tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
  646. /* Configure and enable Bank1_SRAM2 */
  647. FMC_Bank1->BTCR[2] = 0x00001091;
  648. FMC_Bank1->BTCR[3] = 0x00110212;
  649. FMC_Bank1E->BWTR[2] = 0x0fffffff;
  650. #endif /* STM32F469xx || STM32F479xx */
  651. #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
  652. || defined(STM32F412Zx) || defined(STM32F412Vx)
  653. /* Delay after an RCC peripheral clock enabling */
  654. tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
  655. /* Configure and enable Bank1_SRAM2 */
  656. FSMC_Bank1->BTCR[2] = 0x00001011;
  657. FSMC_Bank1->BTCR[3] = 0x00000201;
  658. FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
  659. #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
  660. #endif /* DATA_IN_ExtSRAM */
  661. #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
  662. STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
  663. (void)(tmp);
  664. }
  665. #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
  666. /**
  667. * @}
  668. */
  669. /**
  670. * @}
  671. */
  672. /**
  673. * @}
  674. */
  675. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/