stm32f427xx.h 1.4 MB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f427xx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32F427xx Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - peripherals registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32f427xx
  45. * @{
  46. */
  47. #ifndef __STM32F427xx_H
  48. #define __STM32F427xx_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
  59. #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 1U /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32F4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  77. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  78. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  79. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  80. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  81. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  82. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  83. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  84. /****** STM32 specific Interrupt Numbers **********************************************************************/
  85. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  86. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  87. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  88. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  89. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  90. RCC_IRQn = 5, /*!< RCC global Interrupt */
  91. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  92. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  93. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  94. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  95. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  96. DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
  97. DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
  98. DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
  99. DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
  100. DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
  101. DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
  102. DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
  103. ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
  104. CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
  105. CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
  106. CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
  107. CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
  108. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  109. TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
  110. TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
  111. TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
  112. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  113. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  114. TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
  115. TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
  116. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  117. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  118. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  119. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  120. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  121. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  122. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  123. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  124. USART3_IRQn = 39, /*!< USART3 global Interrupt */
  125. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  126. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  127. OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
  128. TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
  129. TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
  130. TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
  131. TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
  132. DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
  133. FMC_IRQn = 48, /*!< FMC global Interrupt */
  134. SDIO_IRQn = 49, /*!< SDIO global Interrupt */
  135. TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
  136. SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
  137. UART4_IRQn = 52, /*!< UART4 global Interrupt */
  138. UART5_IRQn = 53, /*!< UART5 global Interrupt */
  139. TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
  140. TIM7_IRQn = 55, /*!< TIM7 global interrupt */
  141. DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
  142. DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
  143. DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
  144. DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
  145. DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
  146. ETH_IRQn = 61, /*!< Ethernet global Interrupt */
  147. ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
  148. CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
  149. CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
  150. CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
  151. CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
  152. OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
  153. DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
  154. DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
  155. DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
  156. USART6_IRQn = 71, /*!< USART6 global interrupt */
  157. I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
  158. I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
  159. OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
  160. OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
  161. OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
  162. OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
  163. DCMI_IRQn = 78, /*!< DCMI global interrupt */
  164. HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
  165. FPU_IRQn = 81, /*!< FPU global interrupt */
  166. UART7_IRQn = 82, /*!< UART7 global interrupt */
  167. UART8_IRQn = 83, /*!< UART8 global interrupt */
  168. SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
  169. SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
  170. SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
  171. SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
  172. DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
  173. } IRQn_Type;
  174. /**
  175. * @}
  176. */
  177. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  178. #include "system_stm32f4xx.h"
  179. #include <stdint.h>
  180. /** @addtogroup Peripheral_registers_structures
  181. * @{
  182. */
  183. /**
  184. * @brief Analog to Digital Converter
  185. */
  186. typedef struct
  187. {
  188. __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
  189. __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
  190. __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
  191. __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
  192. __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
  193. __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  194. __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  195. __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  196. __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  197. __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
  198. __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
  199. __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
  200. __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
  201. __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
  202. __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
  203. __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
  204. __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
  205. __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
  206. __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
  207. __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
  208. } ADC_TypeDef;
  209. typedef struct
  210. {
  211. __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
  212. __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
  213. __IO uint32_t CDR; /*!< ADC common regular data register for dual
  214. AND triple modes, Address offset: ADC1 base address + 0x308 */
  215. } ADC_Common_TypeDef;
  216. /**
  217. * @brief Controller Area Network TxMailBox
  218. */
  219. typedef struct
  220. {
  221. __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
  222. __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
  223. __IO uint32_t TDLR; /*!< CAN mailbox data low register */
  224. __IO uint32_t TDHR; /*!< CAN mailbox data high register */
  225. } CAN_TxMailBox_TypeDef;
  226. /**
  227. * @brief Controller Area Network FIFOMailBox
  228. */
  229. typedef struct
  230. {
  231. __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
  232. __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
  233. __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
  234. __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
  235. } CAN_FIFOMailBox_TypeDef;
  236. /**
  237. * @brief Controller Area Network FilterRegister
  238. */
  239. typedef struct
  240. {
  241. __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
  242. __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
  243. } CAN_FilterRegister_TypeDef;
  244. /**
  245. * @brief Controller Area Network
  246. */
  247. typedef struct
  248. {
  249. __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
  250. __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
  251. __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
  252. __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
  253. __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
  254. __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
  255. __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
  256. __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
  257. uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
  258. CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
  259. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
  260. uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
  261. __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
  262. __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
  263. uint32_t RESERVED2; /*!< Reserved, 0x208 */
  264. __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
  265. uint32_t RESERVED3; /*!< Reserved, 0x210 */
  266. __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
  267. uint32_t RESERVED4; /*!< Reserved, 0x218 */
  268. __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
  269. uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
  270. CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
  271. } CAN_TypeDef;
  272. /**
  273. * @brief CRC calculation unit
  274. */
  275. typedef struct
  276. {
  277. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  278. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  279. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  280. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  281. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  282. } CRC_TypeDef;
  283. /**
  284. * @brief Digital to Analog Converter
  285. */
  286. typedef struct
  287. {
  288. __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
  289. __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
  290. __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  291. __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
  292. __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
  293. __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  294. __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
  295. __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
  296. __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
  297. __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
  298. __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
  299. __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
  300. __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
  301. __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
  302. } DAC_TypeDef;
  303. /**
  304. * @brief Debug MCU
  305. */
  306. typedef struct
  307. {
  308. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  309. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  310. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  311. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  312. }DBGMCU_TypeDef;
  313. /**
  314. * @brief DCMI
  315. */
  316. typedef struct
  317. {
  318. __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
  319. __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
  320. __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
  321. __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
  322. __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
  323. __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
  324. __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
  325. __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
  326. __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
  327. __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
  328. __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
  329. } DCMI_TypeDef;
  330. /**
  331. * @brief DMA Controller
  332. */
  333. typedef struct
  334. {
  335. __IO uint32_t CR; /*!< DMA stream x configuration register */
  336. __IO uint32_t NDTR; /*!< DMA stream x number of data register */
  337. __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
  338. __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
  339. __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
  340. __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
  341. } DMA_Stream_TypeDef;
  342. typedef struct
  343. {
  344. __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
  345. __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
  346. __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
  347. __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
  348. } DMA_TypeDef;
  349. /**
  350. * @brief DMA2D Controller
  351. */
  352. typedef struct
  353. {
  354. __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
  355. __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
  356. __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
  357. __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
  358. __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
  359. __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
  360. __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
  361. __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
  362. __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
  363. __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
  364. __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
  365. __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
  366. __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
  367. __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
  368. __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
  369. __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
  370. __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
  371. __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
  372. __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
  373. __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
  374. uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
  375. __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
  376. __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
  377. } DMA2D_TypeDef;
  378. /**
  379. * @brief Ethernet MAC
  380. */
  381. typedef struct
  382. {
  383. __IO uint32_t MACCR;
  384. __IO uint32_t MACFFR;
  385. __IO uint32_t MACHTHR;
  386. __IO uint32_t MACHTLR;
  387. __IO uint32_t MACMIIAR;
  388. __IO uint32_t MACMIIDR;
  389. __IO uint32_t MACFCR;
  390. __IO uint32_t MACVLANTR; /* 8 */
  391. uint32_t RESERVED0[2];
  392. __IO uint32_t MACRWUFFR; /* 11 */
  393. __IO uint32_t MACPMTCSR;
  394. uint32_t RESERVED1;
  395. __IO uint32_t MACDBGR;
  396. __IO uint32_t MACSR; /* 15 */
  397. __IO uint32_t MACIMR;
  398. __IO uint32_t MACA0HR;
  399. __IO uint32_t MACA0LR;
  400. __IO uint32_t MACA1HR;
  401. __IO uint32_t MACA1LR;
  402. __IO uint32_t MACA2HR;
  403. __IO uint32_t MACA2LR;
  404. __IO uint32_t MACA3HR;
  405. __IO uint32_t MACA3LR; /* 24 */
  406. uint32_t RESERVED2[40];
  407. __IO uint32_t MMCCR; /* 65 */
  408. __IO uint32_t MMCRIR;
  409. __IO uint32_t MMCTIR;
  410. __IO uint32_t MMCRIMR;
  411. __IO uint32_t MMCTIMR; /* 69 */
  412. uint32_t RESERVED3[14];
  413. __IO uint32_t MMCTGFSCCR; /* 84 */
  414. __IO uint32_t MMCTGFMSCCR;
  415. uint32_t RESERVED4[5];
  416. __IO uint32_t MMCTGFCR;
  417. uint32_t RESERVED5[10];
  418. __IO uint32_t MMCRFCECR;
  419. __IO uint32_t MMCRFAECR;
  420. uint32_t RESERVED6[10];
  421. __IO uint32_t MMCRGUFCR;
  422. uint32_t RESERVED7[334];
  423. __IO uint32_t PTPTSCR;
  424. __IO uint32_t PTPSSIR;
  425. __IO uint32_t PTPTSHR;
  426. __IO uint32_t PTPTSLR;
  427. __IO uint32_t PTPTSHUR;
  428. __IO uint32_t PTPTSLUR;
  429. __IO uint32_t PTPTSAR;
  430. __IO uint32_t PTPTTHR;
  431. __IO uint32_t PTPTTLR;
  432. __IO uint32_t RESERVED8;
  433. __IO uint32_t PTPTSSR;
  434. uint32_t RESERVED9[565];
  435. __IO uint32_t DMABMR;
  436. __IO uint32_t DMATPDR;
  437. __IO uint32_t DMARPDR;
  438. __IO uint32_t DMARDLAR;
  439. __IO uint32_t DMATDLAR;
  440. __IO uint32_t DMASR;
  441. __IO uint32_t DMAOMR;
  442. __IO uint32_t DMAIER;
  443. __IO uint32_t DMAMFBOCR;
  444. __IO uint32_t DMARSWTR;
  445. uint32_t RESERVED10[8];
  446. __IO uint32_t DMACHTDR;
  447. __IO uint32_t DMACHRDR;
  448. __IO uint32_t DMACHTBAR;
  449. __IO uint32_t DMACHRBAR;
  450. } ETH_TypeDef;
  451. /**
  452. * @brief External Interrupt/Event Controller
  453. */
  454. typedef struct
  455. {
  456. __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
  457. __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
  458. __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
  459. __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
  460. __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
  461. __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
  462. } EXTI_TypeDef;
  463. /**
  464. * @brief FLASH Registers
  465. */
  466. typedef struct
  467. {
  468. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  469. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
  470. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
  471. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
  472. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
  473. __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
  474. __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
  475. } FLASH_TypeDef;
  476. /**
  477. * @brief Flexible Memory Controller
  478. */
  479. typedef struct
  480. {
  481. __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
  482. } FMC_Bank1_TypeDef;
  483. /**
  484. * @brief Flexible Memory Controller Bank1E
  485. */
  486. typedef struct
  487. {
  488. __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
  489. } FMC_Bank1E_TypeDef;
  490. /**
  491. * @brief Flexible Memory Controller Bank2
  492. */
  493. typedef struct
  494. {
  495. __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
  496. __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
  497. __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
  498. __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
  499. uint32_t RESERVED0; /*!< Reserved, 0x70 */
  500. __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
  501. uint32_t RESERVED1; /*!< Reserved, 0x78 */
  502. uint32_t RESERVED2; /*!< Reserved, 0x7C */
  503. __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
  504. __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
  505. __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
  506. __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
  507. uint32_t RESERVED3; /*!< Reserved, 0x90 */
  508. __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
  509. } FMC_Bank2_3_TypeDef;
  510. /**
  511. * @brief Flexible Memory Controller Bank4
  512. */
  513. typedef struct
  514. {
  515. __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
  516. __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
  517. __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
  518. __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
  519. __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
  520. } FMC_Bank4_TypeDef;
  521. /**
  522. * @brief Flexible Memory Controller Bank5_6
  523. */
  524. typedef struct
  525. {
  526. __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
  527. __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
  528. __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
  529. __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
  530. __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
  531. } FMC_Bank5_6_TypeDef;
  532. /**
  533. * @brief General Purpose I/O
  534. */
  535. typedef struct
  536. {
  537. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  538. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  539. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  540. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  541. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  542. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  543. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  544. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  545. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  546. } GPIO_TypeDef;
  547. /**
  548. * @brief System configuration controller
  549. */
  550. typedef struct
  551. {
  552. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  553. __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
  554. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  555. uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
  556. __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
  557. } SYSCFG_TypeDef;
  558. /**
  559. * @brief Inter-integrated Circuit Interface
  560. */
  561. typedef struct
  562. {
  563. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  564. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  565. __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
  566. __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
  567. __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
  568. __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
  569. __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
  570. __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
  571. __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
  572. __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
  573. } I2C_TypeDef;
  574. /**
  575. * @brief Independent WATCHDOG
  576. */
  577. typedef struct
  578. {
  579. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  580. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  581. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  582. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  583. } IWDG_TypeDef;
  584. /**
  585. * @brief Power Control
  586. */
  587. typedef struct
  588. {
  589. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  590. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  591. } PWR_TypeDef;
  592. /**
  593. * @brief Reset and Clock Control
  594. */
  595. typedef struct
  596. {
  597. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  598. __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
  599. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  600. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
  601. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
  602. __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
  603. __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
  604. uint32_t RESERVED0; /*!< Reserved, 0x1C */
  605. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
  606. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
  607. uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
  608. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
  609. __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
  610. __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
  611. uint32_t RESERVED2; /*!< Reserved, 0x3C */
  612. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
  613. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
  614. uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
  615. __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  616. __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
  617. __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
  618. uint32_t RESERVED4; /*!< Reserved, 0x5C */
  619. __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  620. __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  621. uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
  622. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
  623. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
  624. uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
  625. __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
  626. __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
  627. __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
  628. __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
  629. } RCC_TypeDef;
  630. /**
  631. * @brief Real-Time Clock
  632. */
  633. typedef struct
  634. {
  635. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  636. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  637. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  638. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  639. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  640. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  641. __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
  642. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  643. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  644. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  645. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  646. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  647. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  648. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  649. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  650. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  651. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  652. __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
  653. __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
  654. uint32_t RESERVED7; /*!< Reserved, 0x4C */
  655. __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
  656. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  657. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  658. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  659. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  660. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  661. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  662. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  663. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  664. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  665. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  666. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  667. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  668. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  669. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  670. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  671. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  672. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  673. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  674. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  675. } RTC_TypeDef;
  676. /**
  677. * @brief Serial Audio Interface
  678. */
  679. typedef struct
  680. {
  681. __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
  682. } SAI_TypeDef;
  683. typedef struct
  684. {
  685. __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
  686. __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
  687. __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
  688. __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
  689. __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
  690. __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
  691. __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
  692. __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
  693. } SAI_Block_TypeDef;
  694. /**
  695. * @brief SD host Interface
  696. */
  697. typedef struct
  698. {
  699. __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
  700. __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
  701. __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
  702. __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
  703. __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
  704. __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
  705. __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
  706. __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
  707. __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
  708. __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
  709. __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
  710. __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
  711. __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
  712. __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
  713. __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
  714. __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
  715. uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
  716. __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
  717. uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
  718. __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
  719. } SDIO_TypeDef;
  720. /**
  721. * @brief Serial Peripheral Interface
  722. */
  723. typedef struct
  724. {
  725. __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
  726. __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
  727. __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
  728. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  729. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  730. __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
  731. __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
  732. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  733. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  734. } SPI_TypeDef;
  735. /**
  736. * @brief TIM
  737. */
  738. typedef struct
  739. {
  740. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  741. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  742. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  743. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  744. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  745. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  746. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  747. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  748. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  749. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  750. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  751. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  752. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  753. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  754. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  755. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  756. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  757. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  758. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  759. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  760. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  761. } TIM_TypeDef;
  762. /**
  763. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  764. */
  765. typedef struct
  766. {
  767. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  768. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  769. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  770. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  771. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  772. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  773. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  774. } USART_TypeDef;
  775. /**
  776. * @brief Window WATCHDOG
  777. */
  778. typedef struct
  779. {
  780. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  781. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  782. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  783. } WWDG_TypeDef;
  784. /**
  785. * @brief RNG
  786. */
  787. typedef struct
  788. {
  789. __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
  790. __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
  791. __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
  792. } RNG_TypeDef;
  793. /**
  794. * @brief USB_OTG_Core_Registers
  795. */
  796. typedef struct
  797. {
  798. __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
  799. __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
  800. __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
  801. __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
  802. __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
  803. __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
  804. __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
  805. __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
  806. __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
  807. __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
  808. __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
  809. __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
  810. uint32_t Reserved30[2]; /*!< Reserved 030h */
  811. __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
  812. __IO uint32_t CID; /*!< User ID Register 03Ch */
  813. uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
  814. __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
  815. __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
  816. } USB_OTG_GlobalTypeDef;
  817. /**
  818. * @brief USB_OTG_device_Registers
  819. */
  820. typedef struct
  821. {
  822. __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
  823. __IO uint32_t DCTL; /*!< dev Control Register 804h */
  824. __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
  825. uint32_t Reserved0C; /*!< Reserved 80Ch */
  826. __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
  827. __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
  828. __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
  829. __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
  830. uint32_t Reserved20; /*!< Reserved 820h */
  831. uint32_t Reserved9; /*!< Reserved 824h */
  832. __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
  833. __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
  834. __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
  835. __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
  836. __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
  837. __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
  838. uint32_t Reserved40; /*!< dedicated EP mask 840h */
  839. __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
  840. uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
  841. __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
  842. } USB_OTG_DeviceTypeDef;
  843. /**
  844. * @brief USB_OTG_IN_Endpoint-Specific_Register
  845. */
  846. typedef struct
  847. {
  848. __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
  849. uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
  850. __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
  851. uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
  852. __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
  853. __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
  854. __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
  855. uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
  856. } USB_OTG_INEndpointTypeDef;
  857. /**
  858. * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  859. */
  860. typedef struct
  861. {
  862. __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
  863. uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
  864. __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
  865. uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
  866. __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
  867. __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
  868. uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
  869. } USB_OTG_OUTEndpointTypeDef;
  870. /**
  871. * @brief USB_OTG_Host_Mode_Register_Structures
  872. */
  873. typedef struct
  874. {
  875. __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
  876. __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
  877. __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
  878. uint32_t Reserved40C; /*!< Reserved 40Ch */
  879. __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
  880. __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
  881. __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
  882. } USB_OTG_HostTypeDef;
  883. /**
  884. * @brief USB_OTG_Host_Channel_Specific_Registers
  885. */
  886. typedef struct
  887. {
  888. __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
  889. __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
  890. __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
  891. __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
  892. __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
  893. __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
  894. uint32_t Reserved[2]; /*!< Reserved */
  895. } USB_OTG_HostChannelTypeDef;
  896. /**
  897. * @}
  898. */
  899. /** @addtogroup Peripheral_memory_map
  900. * @{
  901. */
  902. #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 2 MB) base address in the alias region */
  903. #define CCMDATARAM_BASE 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
  904. #define SRAM1_BASE 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
  905. #define SRAM2_BASE 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
  906. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  907. #define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
  908. #define FMC_R_BASE 0xA0000000UL /*!< FMC registers base address */
  909. #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
  910. #define SRAM2_BB_BASE 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
  911. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  912. #define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
  913. #define FLASH_END 0x081FFFFFUL /*!< FLASH end address */
  914. #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
  915. #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
  916. #define CCMDATARAM_END 0x1000FFFFUL /*!< CCM data RAM end address */
  917. /* Legacy defines */
  918. #define SRAM_BASE SRAM1_BASE
  919. #define SRAM_BB_BASE SRAM1_BB_BASE
  920. /*!< Peripheral memory map */
  921. #define APB1PERIPH_BASE PERIPH_BASE
  922. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  923. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  924. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
  925. /*!< APB1 peripherals */
  926. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
  927. #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
  928. #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
  929. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
  930. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
  931. #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
  932. #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
  933. #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
  934. #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
  935. #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
  936. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
  937. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
  938. #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
  939. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
  940. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
  941. #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
  942. #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
  943. #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
  944. #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
  945. #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
  946. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
  947. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
  948. #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
  949. #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
  950. #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
  951. #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
  952. #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
  953. #define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
  954. #define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
  955. /*!< APB2 peripherals */
  956. #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
  957. #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
  958. #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
  959. #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
  960. #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
  961. #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
  962. #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
  963. #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
  964. /* Legacy define */
  965. #define ADC_BASE ADC123_COMMON_BASE
  966. #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
  967. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
  968. #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
  969. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
  970. #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
  971. #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
  972. #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
  973. #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
  974. #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
  975. #define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
  976. #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
  977. #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
  978. #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
  979. /*!< AHB1 peripherals */
  980. #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
  981. #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
  982. #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
  983. #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
  984. #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
  985. #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
  986. #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
  987. #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
  988. #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
  989. #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
  990. #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
  991. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
  992. #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
  993. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
  994. #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
  995. #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
  996. #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
  997. #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
  998. #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
  999. #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
  1000. #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
  1001. #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
  1002. #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
  1003. #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
  1004. #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
  1005. #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
  1006. #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
  1007. #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
  1008. #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
  1009. #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
  1010. #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
  1011. #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
  1012. #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
  1013. #define ETH_MAC_BASE (ETH_BASE)
  1014. #define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
  1015. #define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
  1016. #define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
  1017. #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
  1018. /*!< AHB2 peripherals */
  1019. #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
  1020. #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
  1021. /*!< FMC Bankx registers base address */
  1022. #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
  1023. #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
  1024. #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)
  1025. #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)
  1026. #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
  1027. /*!< Debug MCU registers base address */
  1028. #define DBGMCU_BASE 0xE0042000UL
  1029. /*!< USB registers base address */
  1030. #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
  1031. #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
  1032. #define USB_OTG_GLOBAL_BASE 0x000UL
  1033. #define USB_OTG_DEVICE_BASE 0x800UL
  1034. #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
  1035. #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
  1036. #define USB_OTG_EP_REG_SIZE 0x20UL
  1037. #define USB_OTG_HOST_BASE 0x400UL
  1038. #define USB_OTG_HOST_PORT_BASE 0x440UL
  1039. #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
  1040. #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
  1041. #define USB_OTG_PCGCCTL_BASE 0xE00UL
  1042. #define USB_OTG_FIFO_BASE 0x1000UL
  1043. #define USB_OTG_FIFO_SIZE 0x1000UL
  1044. #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
  1045. #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
  1046. #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
  1047. /**
  1048. * @}
  1049. */
  1050. /** @addtogroup Peripheral_declaration
  1051. * @{
  1052. */
  1053. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  1054. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  1055. #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
  1056. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  1057. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  1058. #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
  1059. #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
  1060. #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
  1061. #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
  1062. #define RTC ((RTC_TypeDef *) RTC_BASE)
  1063. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  1064. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  1065. #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
  1066. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  1067. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  1068. #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
  1069. #define USART2 ((USART_TypeDef *) USART2_BASE)
  1070. #define USART3 ((USART_TypeDef *) USART3_BASE)
  1071. #define UART4 ((USART_TypeDef *) UART4_BASE)
  1072. #define UART5 ((USART_TypeDef *) UART5_BASE)
  1073. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  1074. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  1075. #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
  1076. #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
  1077. #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
  1078. #define PWR ((PWR_TypeDef *) PWR_BASE)
  1079. #define DAC1 ((DAC_TypeDef *) DAC_BASE)
  1080. #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
  1081. #define UART7 ((USART_TypeDef *) UART7_BASE)
  1082. #define UART8 ((USART_TypeDef *) UART8_BASE)
  1083. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  1084. #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
  1085. #define USART1 ((USART_TypeDef *) USART1_BASE)
  1086. #define USART6 ((USART_TypeDef *) USART6_BASE)
  1087. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  1088. #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
  1089. #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
  1090. #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
  1091. /* Legacy define */
  1092. #define ADC ADC123_COMMON
  1093. #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
  1094. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  1095. #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
  1096. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  1097. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  1098. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  1099. #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
  1100. #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
  1101. #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
  1102. #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
  1103. #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
  1104. #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
  1105. #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
  1106. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  1107. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  1108. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  1109. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  1110. #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
  1111. #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
  1112. #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
  1113. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  1114. #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
  1115. #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
  1116. #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
  1117. #define CRC ((CRC_TypeDef *) CRC_BASE)
  1118. #define RCC ((RCC_TypeDef *) RCC_BASE)
  1119. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  1120. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  1121. #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  1122. #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
  1123. #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
  1124. #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
  1125. #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
  1126. #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
  1127. #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
  1128. #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
  1129. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  1130. #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
  1131. #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
  1132. #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
  1133. #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
  1134. #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
  1135. #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
  1136. #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
  1137. #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
  1138. #define ETH ((ETH_TypeDef *) ETH_BASE)
  1139. #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
  1140. #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
  1141. #define RNG ((RNG_TypeDef *) RNG_BASE)
  1142. #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
  1143. #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
  1144. #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
  1145. #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
  1146. #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
  1147. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  1148. #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
  1149. #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
  1150. /**
  1151. * @}
  1152. */
  1153. /** @addtogroup Exported_constants
  1154. * @{
  1155. */
  1156. /** @addtogroup Peripheral_Registers_Bits_Definition
  1157. * @{
  1158. */
  1159. /******************************************************************************/
  1160. /* Peripheral Registers_Bits_Definition */
  1161. /******************************************************************************/
  1162. /******************************************************************************/
  1163. /* */
  1164. /* Analog to Digital Converter */
  1165. /* */
  1166. /******************************************************************************/
  1167. /*
  1168. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  1169. */
  1170. #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
  1171. /******************** Bit definition for ADC_SR register ********************/
  1172. #define ADC_SR_AWD_Pos (0U)
  1173. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  1174. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
  1175. #define ADC_SR_EOC_Pos (1U)
  1176. #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
  1177. #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
  1178. #define ADC_SR_JEOC_Pos (2U)
  1179. #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
  1180. #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
  1181. #define ADC_SR_JSTRT_Pos (3U)
  1182. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  1183. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
  1184. #define ADC_SR_STRT_Pos (4U)
  1185. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  1186. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
  1187. #define ADC_SR_OVR_Pos (5U)
  1188. #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
  1189. #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
  1190. /******************* Bit definition for ADC_CR1 register ********************/
  1191. #define ADC_CR1_AWDCH_Pos (0U)
  1192. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  1193. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
  1194. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  1195. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  1196. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  1197. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  1198. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  1199. #define ADC_CR1_EOCIE_Pos (5U)
  1200. #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
  1201. #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
  1202. #define ADC_CR1_AWDIE_Pos (6U)
  1203. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  1204. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
  1205. #define ADC_CR1_JEOCIE_Pos (7U)
  1206. #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
  1207. #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
  1208. #define ADC_CR1_SCAN_Pos (8U)
  1209. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  1210. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
  1211. #define ADC_CR1_AWDSGL_Pos (9U)
  1212. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  1213. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
  1214. #define ADC_CR1_JAUTO_Pos (10U)
  1215. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  1216. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
  1217. #define ADC_CR1_DISCEN_Pos (11U)
  1218. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  1219. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
  1220. #define ADC_CR1_JDISCEN_Pos (12U)
  1221. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  1222. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
  1223. #define ADC_CR1_DISCNUM_Pos (13U)
  1224. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  1225. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
  1226. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  1227. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  1228. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  1229. #define ADC_CR1_JAWDEN_Pos (22U)
  1230. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  1231. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
  1232. #define ADC_CR1_AWDEN_Pos (23U)
  1233. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  1234. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
  1235. #define ADC_CR1_RES_Pos (24U)
  1236. #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
  1237. #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
  1238. #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
  1239. #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
  1240. #define ADC_CR1_OVRIE_Pos (26U)
  1241. #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
  1242. #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
  1243. /******************* Bit definition for ADC_CR2 register ********************/
  1244. #define ADC_CR2_ADON_Pos (0U)
  1245. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  1246. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
  1247. #define ADC_CR2_CONT_Pos (1U)
  1248. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  1249. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
  1250. #define ADC_CR2_DMA_Pos (8U)
  1251. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  1252. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
  1253. #define ADC_CR2_DDS_Pos (9U)
  1254. #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
  1255. #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
  1256. #define ADC_CR2_EOCS_Pos (10U)
  1257. #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
  1258. #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
  1259. #define ADC_CR2_ALIGN_Pos (11U)
  1260. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  1261. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
  1262. #define ADC_CR2_JEXTSEL_Pos (16U)
  1263. #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
  1264. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
  1265. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
  1266. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
  1267. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
  1268. #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
  1269. #define ADC_CR2_JEXTEN_Pos (20U)
  1270. #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
  1271. #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
  1272. #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
  1273. #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
  1274. #define ADC_CR2_JSWSTART_Pos (22U)
  1275. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
  1276. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
  1277. #define ADC_CR2_EXTSEL_Pos (24U)
  1278. #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
  1279. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
  1280. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
  1281. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
  1282. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
  1283. #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
  1284. #define ADC_CR2_EXTEN_Pos (28U)
  1285. #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
  1286. #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
  1287. #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
  1288. #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
  1289. #define ADC_CR2_SWSTART_Pos (30U)
  1290. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
  1291. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
  1292. /****************** Bit definition for ADC_SMPR1 register *******************/
  1293. #define ADC_SMPR1_SMP10_Pos (0U)
  1294. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  1295. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
  1296. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  1297. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  1298. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  1299. #define ADC_SMPR1_SMP11_Pos (3U)
  1300. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  1301. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
  1302. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  1303. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  1304. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  1305. #define ADC_SMPR1_SMP12_Pos (6U)
  1306. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  1307. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
  1308. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  1309. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  1310. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  1311. #define ADC_SMPR1_SMP13_Pos (9U)
  1312. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  1313. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
  1314. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  1315. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  1316. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  1317. #define ADC_SMPR1_SMP14_Pos (12U)
  1318. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  1319. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
  1320. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  1321. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  1322. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  1323. #define ADC_SMPR1_SMP15_Pos (15U)
  1324. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  1325. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
  1326. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  1327. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  1328. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  1329. #define ADC_SMPR1_SMP16_Pos (18U)
  1330. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  1331. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
  1332. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  1333. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  1334. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  1335. #define ADC_SMPR1_SMP17_Pos (21U)
  1336. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  1337. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
  1338. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  1339. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  1340. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  1341. #define ADC_SMPR1_SMP18_Pos (24U)
  1342. #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
  1343. #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
  1344. #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
  1345. #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
  1346. #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
  1347. /****************** Bit definition for ADC_SMPR2 register *******************/
  1348. #define ADC_SMPR2_SMP0_Pos (0U)
  1349. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  1350. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
  1351. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  1352. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  1353. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  1354. #define ADC_SMPR2_SMP1_Pos (3U)
  1355. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  1356. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
  1357. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  1358. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  1359. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  1360. #define ADC_SMPR2_SMP2_Pos (6U)
  1361. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  1362. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
  1363. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  1364. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  1365. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  1366. #define ADC_SMPR2_SMP3_Pos (9U)
  1367. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  1368. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
  1369. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  1370. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  1371. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  1372. #define ADC_SMPR2_SMP4_Pos (12U)
  1373. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  1374. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
  1375. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  1376. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  1377. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  1378. #define ADC_SMPR2_SMP5_Pos (15U)
  1379. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  1380. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
  1381. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  1382. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  1383. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  1384. #define ADC_SMPR2_SMP6_Pos (18U)
  1385. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  1386. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
  1387. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  1388. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  1389. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  1390. #define ADC_SMPR2_SMP7_Pos (21U)
  1391. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  1392. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
  1393. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  1394. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  1395. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  1396. #define ADC_SMPR2_SMP8_Pos (24U)
  1397. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  1398. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
  1399. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  1400. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  1401. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  1402. #define ADC_SMPR2_SMP9_Pos (27U)
  1403. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  1404. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
  1405. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  1406. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  1407. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  1408. /****************** Bit definition for ADC_JOFR1 register *******************/
  1409. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  1410. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  1411. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
  1412. /****************** Bit definition for ADC_JOFR2 register *******************/
  1413. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  1414. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  1415. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
  1416. /****************** Bit definition for ADC_JOFR3 register *******************/
  1417. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  1418. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  1419. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
  1420. /****************** Bit definition for ADC_JOFR4 register *******************/
  1421. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  1422. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  1423. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
  1424. /******************* Bit definition for ADC_HTR register ********************/
  1425. #define ADC_HTR_HT_Pos (0U)
  1426. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  1427. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
  1428. /******************* Bit definition for ADC_LTR register ********************/
  1429. #define ADC_LTR_LT_Pos (0U)
  1430. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  1431. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
  1432. /******************* Bit definition for ADC_SQR1 register *******************/
  1433. #define ADC_SQR1_SQ13_Pos (0U)
  1434. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  1435. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
  1436. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  1437. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  1438. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  1439. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  1440. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  1441. #define ADC_SQR1_SQ14_Pos (5U)
  1442. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  1443. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
  1444. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  1445. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  1446. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  1447. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  1448. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  1449. #define ADC_SQR1_SQ15_Pos (10U)
  1450. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  1451. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
  1452. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  1453. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  1454. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  1455. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  1456. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  1457. #define ADC_SQR1_SQ16_Pos (15U)
  1458. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  1459. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
  1460. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  1461. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  1462. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  1463. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  1464. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  1465. #define ADC_SQR1_L_Pos (20U)
  1466. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  1467. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
  1468. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  1469. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  1470. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  1471. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  1472. /******************* Bit definition for ADC_SQR2 register *******************/
  1473. #define ADC_SQR2_SQ7_Pos (0U)
  1474. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  1475. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
  1476. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  1477. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  1478. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  1479. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  1480. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  1481. #define ADC_SQR2_SQ8_Pos (5U)
  1482. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  1483. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
  1484. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  1485. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  1486. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  1487. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  1488. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  1489. #define ADC_SQR2_SQ9_Pos (10U)
  1490. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  1491. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
  1492. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  1493. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  1494. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  1495. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  1496. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  1497. #define ADC_SQR2_SQ10_Pos (15U)
  1498. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  1499. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
  1500. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  1501. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  1502. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  1503. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  1504. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  1505. #define ADC_SQR2_SQ11_Pos (20U)
  1506. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  1507. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
  1508. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  1509. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  1510. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  1511. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  1512. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  1513. #define ADC_SQR2_SQ12_Pos (25U)
  1514. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  1515. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
  1516. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  1517. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  1518. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  1519. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  1520. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  1521. /******************* Bit definition for ADC_SQR3 register *******************/
  1522. #define ADC_SQR3_SQ1_Pos (0U)
  1523. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  1524. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
  1525. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  1526. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  1527. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  1528. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  1529. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  1530. #define ADC_SQR3_SQ2_Pos (5U)
  1531. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  1532. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
  1533. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  1534. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  1535. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  1536. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  1537. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  1538. #define ADC_SQR3_SQ3_Pos (10U)
  1539. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  1540. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
  1541. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  1542. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  1543. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  1544. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  1545. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  1546. #define ADC_SQR3_SQ4_Pos (15U)
  1547. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  1548. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
  1549. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  1550. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  1551. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  1552. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  1553. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  1554. #define ADC_SQR3_SQ5_Pos (20U)
  1555. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  1556. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
  1557. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  1558. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  1559. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  1560. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  1561. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  1562. #define ADC_SQR3_SQ6_Pos (25U)
  1563. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  1564. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
  1565. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  1566. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  1567. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  1568. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  1569. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  1570. /******************* Bit definition for ADC_JSQR register *******************/
  1571. #define ADC_JSQR_JSQ1_Pos (0U)
  1572. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  1573. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
  1574. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  1575. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  1576. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  1577. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  1578. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  1579. #define ADC_JSQR_JSQ2_Pos (5U)
  1580. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  1581. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1582. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  1583. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  1584. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  1585. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  1586. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  1587. #define ADC_JSQR_JSQ3_Pos (10U)
  1588. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  1589. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1590. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  1591. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  1592. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  1593. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  1594. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  1595. #define ADC_JSQR_JSQ4_Pos (15U)
  1596. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  1597. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
  1598. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  1599. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  1600. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  1601. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  1602. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  1603. #define ADC_JSQR_JL_Pos (20U)
  1604. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  1605. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
  1606. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  1607. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  1608. /******************* Bit definition for ADC_JDR1 register *******************/
  1609. #define ADC_JDR1_JDATA_Pos (0U)
  1610. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1611. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
  1612. /******************* Bit definition for ADC_JDR2 register *******************/
  1613. #define ADC_JDR2_JDATA_Pos (0U)
  1614. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1615. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
  1616. /******************* Bit definition for ADC_JDR3 register *******************/
  1617. #define ADC_JDR3_JDATA_Pos (0U)
  1618. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1619. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
  1620. /******************* Bit definition for ADC_JDR4 register *******************/
  1621. #define ADC_JDR4_JDATA_Pos (0U)
  1622. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1623. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
  1624. /******************** Bit definition for ADC_DR register ********************/
  1625. #define ADC_DR_DATA_Pos (0U)
  1626. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1627. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
  1628. #define ADC_DR_ADC2DATA_Pos (16U)
  1629. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  1630. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
  1631. /******************* Bit definition for ADC_CSR register ********************/
  1632. #define ADC_CSR_AWD1_Pos (0U)
  1633. #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
  1634. #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
  1635. #define ADC_CSR_EOC1_Pos (1U)
  1636. #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
  1637. #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
  1638. #define ADC_CSR_JEOC1_Pos (2U)
  1639. #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
  1640. #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
  1641. #define ADC_CSR_JSTRT1_Pos (3U)
  1642. #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
  1643. #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
  1644. #define ADC_CSR_STRT1_Pos (4U)
  1645. #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
  1646. #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
  1647. #define ADC_CSR_OVR1_Pos (5U)
  1648. #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
  1649. #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
  1650. #define ADC_CSR_AWD2_Pos (8U)
  1651. #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
  1652. #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
  1653. #define ADC_CSR_EOC2_Pos (9U)
  1654. #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
  1655. #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
  1656. #define ADC_CSR_JEOC2_Pos (10U)
  1657. #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
  1658. #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
  1659. #define ADC_CSR_JSTRT2_Pos (11U)
  1660. #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
  1661. #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
  1662. #define ADC_CSR_STRT2_Pos (12U)
  1663. #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
  1664. #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
  1665. #define ADC_CSR_OVR2_Pos (13U)
  1666. #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
  1667. #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
  1668. #define ADC_CSR_AWD3_Pos (16U)
  1669. #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
  1670. #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
  1671. #define ADC_CSR_EOC3_Pos (17U)
  1672. #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
  1673. #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
  1674. #define ADC_CSR_JEOC3_Pos (18U)
  1675. #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
  1676. #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
  1677. #define ADC_CSR_JSTRT3_Pos (19U)
  1678. #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
  1679. #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
  1680. #define ADC_CSR_STRT3_Pos (20U)
  1681. #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
  1682. #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
  1683. #define ADC_CSR_OVR3_Pos (21U)
  1684. #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
  1685. #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
  1686. /* Legacy defines */
  1687. #define ADC_CSR_DOVR1 ADC_CSR_OVR1
  1688. #define ADC_CSR_DOVR2 ADC_CSR_OVR2
  1689. #define ADC_CSR_DOVR3 ADC_CSR_OVR3
  1690. /******************* Bit definition for ADC_CCR register ********************/
  1691. #define ADC_CCR_MULTI_Pos (0U)
  1692. #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
  1693. #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
  1694. #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
  1695. #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
  1696. #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
  1697. #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
  1698. #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
  1699. #define ADC_CCR_DELAY_Pos (8U)
  1700. #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
  1701. #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
  1702. #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
  1703. #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
  1704. #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
  1705. #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
  1706. #define ADC_CCR_DDS_Pos (13U)
  1707. #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
  1708. #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
  1709. #define ADC_CCR_DMA_Pos (14U)
  1710. #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
  1711. #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
  1712. #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
  1713. #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
  1714. #define ADC_CCR_ADCPRE_Pos (16U)
  1715. #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
  1716. #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
  1717. #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
  1718. #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
  1719. #define ADC_CCR_VBATE_Pos (22U)
  1720. #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
  1721. #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
  1722. #define ADC_CCR_TSVREFE_Pos (23U)
  1723. #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
  1724. #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
  1725. /******************* Bit definition for ADC_CDR register ********************/
  1726. #define ADC_CDR_DATA1_Pos (0U)
  1727. #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
  1728. #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
  1729. #define ADC_CDR_DATA2_Pos (16U)
  1730. #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
  1731. #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
  1732. /* Legacy defines */
  1733. #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
  1734. #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
  1735. /******************************************************************************/
  1736. /* */
  1737. /* Controller Area Network */
  1738. /* */
  1739. /******************************************************************************/
  1740. /*!<CAN control and status registers */
  1741. /******************* Bit definition for CAN_MCR register ********************/
  1742. #define CAN_MCR_INRQ_Pos (0U)
  1743. #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
  1744. #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
  1745. #define CAN_MCR_SLEEP_Pos (1U)
  1746. #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
  1747. #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
  1748. #define CAN_MCR_TXFP_Pos (2U)
  1749. #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
  1750. #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
  1751. #define CAN_MCR_RFLM_Pos (3U)
  1752. #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
  1753. #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
  1754. #define CAN_MCR_NART_Pos (4U)
  1755. #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
  1756. #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
  1757. #define CAN_MCR_AWUM_Pos (5U)
  1758. #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
  1759. #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
  1760. #define CAN_MCR_ABOM_Pos (6U)
  1761. #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
  1762. #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
  1763. #define CAN_MCR_TTCM_Pos (7U)
  1764. #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
  1765. #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
  1766. #define CAN_MCR_RESET_Pos (15U)
  1767. #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
  1768. #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
  1769. #define CAN_MCR_DBF_Pos (16U)
  1770. #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
  1771. #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
  1772. /******************* Bit definition for CAN_MSR register ********************/
  1773. #define CAN_MSR_INAK_Pos (0U)
  1774. #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
  1775. #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
  1776. #define CAN_MSR_SLAK_Pos (1U)
  1777. #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
  1778. #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
  1779. #define CAN_MSR_ERRI_Pos (2U)
  1780. #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
  1781. #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
  1782. #define CAN_MSR_WKUI_Pos (3U)
  1783. #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
  1784. #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
  1785. #define CAN_MSR_SLAKI_Pos (4U)
  1786. #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
  1787. #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
  1788. #define CAN_MSR_TXM_Pos (8U)
  1789. #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
  1790. #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
  1791. #define CAN_MSR_RXM_Pos (9U)
  1792. #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
  1793. #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
  1794. #define CAN_MSR_SAMP_Pos (10U)
  1795. #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
  1796. #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
  1797. #define CAN_MSR_RX_Pos (11U)
  1798. #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
  1799. #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
  1800. /******************* Bit definition for CAN_TSR register ********************/
  1801. #define CAN_TSR_RQCP0_Pos (0U)
  1802. #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
  1803. #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
  1804. #define CAN_TSR_TXOK0_Pos (1U)
  1805. #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
  1806. #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
  1807. #define CAN_TSR_ALST0_Pos (2U)
  1808. #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
  1809. #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
  1810. #define CAN_TSR_TERR0_Pos (3U)
  1811. #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
  1812. #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
  1813. #define CAN_TSR_ABRQ0_Pos (7U)
  1814. #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
  1815. #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
  1816. #define CAN_TSR_RQCP1_Pos (8U)
  1817. #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
  1818. #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
  1819. #define CAN_TSR_TXOK1_Pos (9U)
  1820. #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
  1821. #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
  1822. #define CAN_TSR_ALST1_Pos (10U)
  1823. #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
  1824. #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
  1825. #define CAN_TSR_TERR1_Pos (11U)
  1826. #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
  1827. #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
  1828. #define CAN_TSR_ABRQ1_Pos (15U)
  1829. #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
  1830. #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
  1831. #define CAN_TSR_RQCP2_Pos (16U)
  1832. #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
  1833. #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
  1834. #define CAN_TSR_TXOK2_Pos (17U)
  1835. #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
  1836. #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
  1837. #define CAN_TSR_ALST2_Pos (18U)
  1838. #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
  1839. #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
  1840. #define CAN_TSR_TERR2_Pos (19U)
  1841. #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
  1842. #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
  1843. #define CAN_TSR_ABRQ2_Pos (23U)
  1844. #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
  1845. #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
  1846. #define CAN_TSR_CODE_Pos (24U)
  1847. #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
  1848. #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
  1849. #define CAN_TSR_TME_Pos (26U)
  1850. #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
  1851. #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
  1852. #define CAN_TSR_TME0_Pos (26U)
  1853. #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
  1854. #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
  1855. #define CAN_TSR_TME1_Pos (27U)
  1856. #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
  1857. #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
  1858. #define CAN_TSR_TME2_Pos (28U)
  1859. #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
  1860. #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
  1861. #define CAN_TSR_LOW_Pos (29U)
  1862. #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
  1863. #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
  1864. #define CAN_TSR_LOW0_Pos (29U)
  1865. #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
  1866. #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
  1867. #define CAN_TSR_LOW1_Pos (30U)
  1868. #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
  1869. #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
  1870. #define CAN_TSR_LOW2_Pos (31U)
  1871. #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
  1872. #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
  1873. /******************* Bit definition for CAN_RF0R register *******************/
  1874. #define CAN_RF0R_FMP0_Pos (0U)
  1875. #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
  1876. #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
  1877. #define CAN_RF0R_FULL0_Pos (3U)
  1878. #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
  1879. #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
  1880. #define CAN_RF0R_FOVR0_Pos (4U)
  1881. #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
  1882. #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
  1883. #define CAN_RF0R_RFOM0_Pos (5U)
  1884. #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
  1885. #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
  1886. /******************* Bit definition for CAN_RF1R register *******************/
  1887. #define CAN_RF1R_FMP1_Pos (0U)
  1888. #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
  1889. #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
  1890. #define CAN_RF1R_FULL1_Pos (3U)
  1891. #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
  1892. #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
  1893. #define CAN_RF1R_FOVR1_Pos (4U)
  1894. #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
  1895. #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
  1896. #define CAN_RF1R_RFOM1_Pos (5U)
  1897. #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
  1898. #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
  1899. /******************** Bit definition for CAN_IER register *******************/
  1900. #define CAN_IER_TMEIE_Pos (0U)
  1901. #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
  1902. #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
  1903. #define CAN_IER_FMPIE0_Pos (1U)
  1904. #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
  1905. #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
  1906. #define CAN_IER_FFIE0_Pos (2U)
  1907. #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
  1908. #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
  1909. #define CAN_IER_FOVIE0_Pos (3U)
  1910. #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
  1911. #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
  1912. #define CAN_IER_FMPIE1_Pos (4U)
  1913. #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
  1914. #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
  1915. #define CAN_IER_FFIE1_Pos (5U)
  1916. #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
  1917. #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
  1918. #define CAN_IER_FOVIE1_Pos (6U)
  1919. #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
  1920. #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
  1921. #define CAN_IER_EWGIE_Pos (8U)
  1922. #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
  1923. #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
  1924. #define CAN_IER_EPVIE_Pos (9U)
  1925. #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
  1926. #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
  1927. #define CAN_IER_BOFIE_Pos (10U)
  1928. #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
  1929. #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
  1930. #define CAN_IER_LECIE_Pos (11U)
  1931. #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
  1932. #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
  1933. #define CAN_IER_ERRIE_Pos (15U)
  1934. #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
  1935. #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
  1936. #define CAN_IER_WKUIE_Pos (16U)
  1937. #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
  1938. #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
  1939. #define CAN_IER_SLKIE_Pos (17U)
  1940. #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
  1941. #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
  1942. #define CAN_IER_EWGIE_Pos (8U)
  1943. /******************** Bit definition for CAN_ESR register *******************/
  1944. #define CAN_ESR_EWGF_Pos (0U)
  1945. #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
  1946. #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
  1947. #define CAN_ESR_EPVF_Pos (1U)
  1948. #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
  1949. #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
  1950. #define CAN_ESR_BOFF_Pos (2U)
  1951. #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
  1952. #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
  1953. #define CAN_ESR_LEC_Pos (4U)
  1954. #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
  1955. #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
  1956. #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
  1957. #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
  1958. #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
  1959. #define CAN_ESR_TEC_Pos (16U)
  1960. #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
  1961. #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
  1962. #define CAN_ESR_REC_Pos (24U)
  1963. #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
  1964. #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
  1965. /******************* Bit definition for CAN_BTR register ********************/
  1966. #define CAN_BTR_BRP_Pos (0U)
  1967. #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
  1968. #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
  1969. #define CAN_BTR_TS1_Pos (16U)
  1970. #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
  1971. #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
  1972. #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
  1973. #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
  1974. #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
  1975. #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
  1976. #define CAN_BTR_TS2_Pos (20U)
  1977. #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
  1978. #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
  1979. #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
  1980. #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
  1981. #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
  1982. #define CAN_BTR_SJW_Pos (24U)
  1983. #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
  1984. #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
  1985. #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
  1986. #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
  1987. #define CAN_BTR_LBKM_Pos (30U)
  1988. #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
  1989. #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
  1990. #define CAN_BTR_SILM_Pos (31U)
  1991. #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
  1992. #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
  1993. /*!<Mailbox registers */
  1994. /****************** Bit definition for CAN_TI0R register ********************/
  1995. #define CAN_TI0R_TXRQ_Pos (0U)
  1996. #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
  1997. #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
  1998. #define CAN_TI0R_RTR_Pos (1U)
  1999. #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
  2000. #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
  2001. #define CAN_TI0R_IDE_Pos (2U)
  2002. #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
  2003. #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
  2004. #define CAN_TI0R_EXID_Pos (3U)
  2005. #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2006. #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
  2007. #define CAN_TI0R_STID_Pos (21U)
  2008. #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
  2009. #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2010. /****************** Bit definition for CAN_TDT0R register *******************/
  2011. #define CAN_TDT0R_DLC_Pos (0U)
  2012. #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
  2013. #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
  2014. #define CAN_TDT0R_TGT_Pos (8U)
  2015. #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
  2016. #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
  2017. #define CAN_TDT0R_TIME_Pos (16U)
  2018. #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2019. #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
  2020. /****************** Bit definition for CAN_TDL0R register *******************/
  2021. #define CAN_TDL0R_DATA0_Pos (0U)
  2022. #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
  2023. #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
  2024. #define CAN_TDL0R_DATA1_Pos (8U)
  2025. #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2026. #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
  2027. #define CAN_TDL0R_DATA2_Pos (16U)
  2028. #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2029. #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
  2030. #define CAN_TDL0R_DATA3_Pos (24U)
  2031. #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2032. #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
  2033. /****************** Bit definition for CAN_TDH0R register *******************/
  2034. #define CAN_TDH0R_DATA4_Pos (0U)
  2035. #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
  2036. #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
  2037. #define CAN_TDH0R_DATA5_Pos (8U)
  2038. #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2039. #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
  2040. #define CAN_TDH0R_DATA6_Pos (16U)
  2041. #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2042. #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
  2043. #define CAN_TDH0R_DATA7_Pos (24U)
  2044. #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2045. #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
  2046. /******************* Bit definition for CAN_TI1R register *******************/
  2047. #define CAN_TI1R_TXRQ_Pos (0U)
  2048. #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
  2049. #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2050. #define CAN_TI1R_RTR_Pos (1U)
  2051. #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
  2052. #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
  2053. #define CAN_TI1R_IDE_Pos (2U)
  2054. #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
  2055. #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
  2056. #define CAN_TI1R_EXID_Pos (3U)
  2057. #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2058. #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
  2059. #define CAN_TI1R_STID_Pos (21U)
  2060. #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
  2061. #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2062. /******************* Bit definition for CAN_TDT1R register ******************/
  2063. #define CAN_TDT1R_DLC_Pos (0U)
  2064. #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
  2065. #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
  2066. #define CAN_TDT1R_TGT_Pos (8U)
  2067. #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
  2068. #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
  2069. #define CAN_TDT1R_TIME_Pos (16U)
  2070. #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2071. #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
  2072. /******************* Bit definition for CAN_TDL1R register ******************/
  2073. #define CAN_TDL1R_DATA0_Pos (0U)
  2074. #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
  2075. #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
  2076. #define CAN_TDL1R_DATA1_Pos (8U)
  2077. #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2078. #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
  2079. #define CAN_TDL1R_DATA2_Pos (16U)
  2080. #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2081. #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
  2082. #define CAN_TDL1R_DATA3_Pos (24U)
  2083. #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2084. #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
  2085. /******************* Bit definition for CAN_TDH1R register ******************/
  2086. #define CAN_TDH1R_DATA4_Pos (0U)
  2087. #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
  2088. #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
  2089. #define CAN_TDH1R_DATA5_Pos (8U)
  2090. #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2091. #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
  2092. #define CAN_TDH1R_DATA6_Pos (16U)
  2093. #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2094. #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
  2095. #define CAN_TDH1R_DATA7_Pos (24U)
  2096. #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2097. #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
  2098. /******************* Bit definition for CAN_TI2R register *******************/
  2099. #define CAN_TI2R_TXRQ_Pos (0U)
  2100. #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
  2101. #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
  2102. #define CAN_TI2R_RTR_Pos (1U)
  2103. #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
  2104. #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
  2105. #define CAN_TI2R_IDE_Pos (2U)
  2106. #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
  2107. #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
  2108. #define CAN_TI2R_EXID_Pos (3U)
  2109. #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
  2110. #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
  2111. #define CAN_TI2R_STID_Pos (21U)
  2112. #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
  2113. #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2114. /******************* Bit definition for CAN_TDT2R register ******************/
  2115. #define CAN_TDT2R_DLC_Pos (0U)
  2116. #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
  2117. #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
  2118. #define CAN_TDT2R_TGT_Pos (8U)
  2119. #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
  2120. #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
  2121. #define CAN_TDT2R_TIME_Pos (16U)
  2122. #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
  2123. #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
  2124. /******************* Bit definition for CAN_TDL2R register ******************/
  2125. #define CAN_TDL2R_DATA0_Pos (0U)
  2126. #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
  2127. #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
  2128. #define CAN_TDL2R_DATA1_Pos (8U)
  2129. #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
  2130. #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
  2131. #define CAN_TDL2R_DATA2_Pos (16U)
  2132. #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
  2133. #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
  2134. #define CAN_TDL2R_DATA3_Pos (24U)
  2135. #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
  2136. #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
  2137. /******************* Bit definition for CAN_TDH2R register ******************/
  2138. #define CAN_TDH2R_DATA4_Pos (0U)
  2139. #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
  2140. #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
  2141. #define CAN_TDH2R_DATA5_Pos (8U)
  2142. #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
  2143. #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
  2144. #define CAN_TDH2R_DATA6_Pos (16U)
  2145. #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
  2146. #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
  2147. #define CAN_TDH2R_DATA7_Pos (24U)
  2148. #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
  2149. #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
  2150. /******************* Bit definition for CAN_RI0R register *******************/
  2151. #define CAN_RI0R_RTR_Pos (1U)
  2152. #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
  2153. #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
  2154. #define CAN_RI0R_IDE_Pos (2U)
  2155. #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
  2156. #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
  2157. #define CAN_RI0R_EXID_Pos (3U)
  2158. #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
  2159. #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
  2160. #define CAN_RI0R_STID_Pos (21U)
  2161. #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
  2162. #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2163. /******************* Bit definition for CAN_RDT0R register ******************/
  2164. #define CAN_RDT0R_DLC_Pos (0U)
  2165. #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
  2166. #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
  2167. #define CAN_RDT0R_FMI_Pos (8U)
  2168. #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
  2169. #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
  2170. #define CAN_RDT0R_TIME_Pos (16U)
  2171. #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  2172. #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
  2173. /******************* Bit definition for CAN_RDL0R register ******************/
  2174. #define CAN_RDL0R_DATA0_Pos (0U)
  2175. #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
  2176. #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
  2177. #define CAN_RDL0R_DATA1_Pos (8U)
  2178. #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  2179. #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
  2180. #define CAN_RDL0R_DATA2_Pos (16U)
  2181. #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  2182. #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
  2183. #define CAN_RDL0R_DATA3_Pos (24U)
  2184. #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
  2185. #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
  2186. /******************* Bit definition for CAN_RDH0R register ******************/
  2187. #define CAN_RDH0R_DATA4_Pos (0U)
  2188. #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
  2189. #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
  2190. #define CAN_RDH0R_DATA5_Pos (8U)
  2191. #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  2192. #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
  2193. #define CAN_RDH0R_DATA6_Pos (16U)
  2194. #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  2195. #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
  2196. #define CAN_RDH0R_DATA7_Pos (24U)
  2197. #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
  2198. #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
  2199. /******************* Bit definition for CAN_RI1R register *******************/
  2200. #define CAN_RI1R_RTR_Pos (1U)
  2201. #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
  2202. #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
  2203. #define CAN_RI1R_IDE_Pos (2U)
  2204. #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
  2205. #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
  2206. #define CAN_RI1R_EXID_Pos (3U)
  2207. #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
  2208. #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
  2209. #define CAN_RI1R_STID_Pos (21U)
  2210. #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
  2211. #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
  2212. /******************* Bit definition for CAN_RDT1R register ******************/
  2213. #define CAN_RDT1R_DLC_Pos (0U)
  2214. #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
  2215. #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
  2216. #define CAN_RDT1R_FMI_Pos (8U)
  2217. #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
  2218. #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
  2219. #define CAN_RDT1R_TIME_Pos (16U)
  2220. #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  2221. #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
  2222. /******************* Bit definition for CAN_RDL1R register ******************/
  2223. #define CAN_RDL1R_DATA0_Pos (0U)
  2224. #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
  2225. #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
  2226. #define CAN_RDL1R_DATA1_Pos (8U)
  2227. #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  2228. #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
  2229. #define CAN_RDL1R_DATA2_Pos (16U)
  2230. #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  2231. #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
  2232. #define CAN_RDL1R_DATA3_Pos (24U)
  2233. #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
  2234. #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
  2235. /******************* Bit definition for CAN_RDH1R register ******************/
  2236. #define CAN_RDH1R_DATA4_Pos (0U)
  2237. #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
  2238. #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
  2239. #define CAN_RDH1R_DATA5_Pos (8U)
  2240. #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  2241. #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
  2242. #define CAN_RDH1R_DATA6_Pos (16U)
  2243. #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  2244. #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
  2245. #define CAN_RDH1R_DATA7_Pos (24U)
  2246. #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
  2247. #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
  2248. /*!<CAN filter registers */
  2249. /******************* Bit definition for CAN_FMR register ********************/
  2250. #define CAN_FMR_FINIT_Pos (0U)
  2251. #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
  2252. #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
  2253. #define CAN_FMR_CAN2SB_Pos (8U)
  2254. #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
  2255. #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
  2256. /******************* Bit definition for CAN_FM1R register *******************/
  2257. #define CAN_FM1R_FBM_Pos (0U)
  2258. #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
  2259. #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
  2260. #define CAN_FM1R_FBM0_Pos (0U)
  2261. #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
  2262. #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
  2263. #define CAN_FM1R_FBM1_Pos (1U)
  2264. #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
  2265. #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
  2266. #define CAN_FM1R_FBM2_Pos (2U)
  2267. #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
  2268. #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
  2269. #define CAN_FM1R_FBM3_Pos (3U)
  2270. #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
  2271. #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
  2272. #define CAN_FM1R_FBM4_Pos (4U)
  2273. #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
  2274. #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
  2275. #define CAN_FM1R_FBM5_Pos (5U)
  2276. #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
  2277. #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
  2278. #define CAN_FM1R_FBM6_Pos (6U)
  2279. #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
  2280. #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
  2281. #define CAN_FM1R_FBM7_Pos (7U)
  2282. #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
  2283. #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
  2284. #define CAN_FM1R_FBM8_Pos (8U)
  2285. #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
  2286. #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
  2287. #define CAN_FM1R_FBM9_Pos (9U)
  2288. #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
  2289. #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
  2290. #define CAN_FM1R_FBM10_Pos (10U)
  2291. #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
  2292. #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
  2293. #define CAN_FM1R_FBM11_Pos (11U)
  2294. #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
  2295. #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
  2296. #define CAN_FM1R_FBM12_Pos (12U)
  2297. #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
  2298. #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
  2299. #define CAN_FM1R_FBM13_Pos (13U)
  2300. #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
  2301. #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
  2302. #define CAN_FM1R_FBM14_Pos (14U)
  2303. #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
  2304. #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
  2305. #define CAN_FM1R_FBM15_Pos (15U)
  2306. #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
  2307. #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
  2308. #define CAN_FM1R_FBM16_Pos (16U)
  2309. #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
  2310. #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
  2311. #define CAN_FM1R_FBM17_Pos (17U)
  2312. #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
  2313. #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
  2314. #define CAN_FM1R_FBM18_Pos (18U)
  2315. #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
  2316. #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
  2317. #define CAN_FM1R_FBM19_Pos (19U)
  2318. #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
  2319. #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
  2320. #define CAN_FM1R_FBM20_Pos (20U)
  2321. #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
  2322. #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
  2323. #define CAN_FM1R_FBM21_Pos (21U)
  2324. #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
  2325. #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
  2326. #define CAN_FM1R_FBM22_Pos (22U)
  2327. #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
  2328. #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
  2329. #define CAN_FM1R_FBM23_Pos (23U)
  2330. #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
  2331. #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
  2332. #define CAN_FM1R_FBM24_Pos (24U)
  2333. #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
  2334. #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
  2335. #define CAN_FM1R_FBM25_Pos (25U)
  2336. #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
  2337. #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
  2338. #define CAN_FM1R_FBM26_Pos (26U)
  2339. #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
  2340. #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
  2341. #define CAN_FM1R_FBM27_Pos (27U)
  2342. #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
  2343. #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
  2344. /******************* Bit definition for CAN_FS1R register *******************/
  2345. #define CAN_FS1R_FSC_Pos (0U)
  2346. #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
  2347. #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
  2348. #define CAN_FS1R_FSC0_Pos (0U)
  2349. #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
  2350. #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
  2351. #define CAN_FS1R_FSC1_Pos (1U)
  2352. #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
  2353. #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
  2354. #define CAN_FS1R_FSC2_Pos (2U)
  2355. #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
  2356. #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
  2357. #define CAN_FS1R_FSC3_Pos (3U)
  2358. #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
  2359. #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
  2360. #define CAN_FS1R_FSC4_Pos (4U)
  2361. #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
  2362. #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
  2363. #define CAN_FS1R_FSC5_Pos (5U)
  2364. #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
  2365. #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
  2366. #define CAN_FS1R_FSC6_Pos (6U)
  2367. #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
  2368. #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
  2369. #define CAN_FS1R_FSC7_Pos (7U)
  2370. #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
  2371. #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
  2372. #define CAN_FS1R_FSC8_Pos (8U)
  2373. #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
  2374. #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
  2375. #define CAN_FS1R_FSC9_Pos (9U)
  2376. #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
  2377. #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
  2378. #define CAN_FS1R_FSC10_Pos (10U)
  2379. #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
  2380. #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
  2381. #define CAN_FS1R_FSC11_Pos (11U)
  2382. #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
  2383. #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
  2384. #define CAN_FS1R_FSC12_Pos (12U)
  2385. #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
  2386. #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
  2387. #define CAN_FS1R_FSC13_Pos (13U)
  2388. #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
  2389. #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
  2390. #define CAN_FS1R_FSC14_Pos (14U)
  2391. #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
  2392. #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
  2393. #define CAN_FS1R_FSC15_Pos (15U)
  2394. #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
  2395. #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
  2396. #define CAN_FS1R_FSC16_Pos (16U)
  2397. #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
  2398. #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
  2399. #define CAN_FS1R_FSC17_Pos (17U)
  2400. #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
  2401. #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
  2402. #define CAN_FS1R_FSC18_Pos (18U)
  2403. #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
  2404. #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
  2405. #define CAN_FS1R_FSC19_Pos (19U)
  2406. #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
  2407. #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
  2408. #define CAN_FS1R_FSC20_Pos (20U)
  2409. #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
  2410. #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
  2411. #define CAN_FS1R_FSC21_Pos (21U)
  2412. #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
  2413. #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
  2414. #define CAN_FS1R_FSC22_Pos (22U)
  2415. #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
  2416. #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
  2417. #define CAN_FS1R_FSC23_Pos (23U)
  2418. #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
  2419. #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
  2420. #define CAN_FS1R_FSC24_Pos (24U)
  2421. #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
  2422. #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
  2423. #define CAN_FS1R_FSC25_Pos (25U)
  2424. #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
  2425. #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
  2426. #define CAN_FS1R_FSC26_Pos (26U)
  2427. #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
  2428. #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
  2429. #define CAN_FS1R_FSC27_Pos (27U)
  2430. #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
  2431. #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
  2432. /****************** Bit definition for CAN_FFA1R register *******************/
  2433. #define CAN_FFA1R_FFA_Pos (0U)
  2434. #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
  2435. #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
  2436. #define CAN_FFA1R_FFA0_Pos (0U)
  2437. #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
  2438. #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
  2439. #define CAN_FFA1R_FFA1_Pos (1U)
  2440. #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
  2441. #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
  2442. #define CAN_FFA1R_FFA2_Pos (2U)
  2443. #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
  2444. #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
  2445. #define CAN_FFA1R_FFA3_Pos (3U)
  2446. #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
  2447. #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
  2448. #define CAN_FFA1R_FFA4_Pos (4U)
  2449. #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
  2450. #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
  2451. #define CAN_FFA1R_FFA5_Pos (5U)
  2452. #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
  2453. #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
  2454. #define CAN_FFA1R_FFA6_Pos (6U)
  2455. #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
  2456. #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
  2457. #define CAN_FFA1R_FFA7_Pos (7U)
  2458. #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
  2459. #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
  2460. #define CAN_FFA1R_FFA8_Pos (8U)
  2461. #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
  2462. #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
  2463. #define CAN_FFA1R_FFA9_Pos (9U)
  2464. #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
  2465. #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
  2466. #define CAN_FFA1R_FFA10_Pos (10U)
  2467. #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
  2468. #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
  2469. #define CAN_FFA1R_FFA11_Pos (11U)
  2470. #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
  2471. #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
  2472. #define CAN_FFA1R_FFA12_Pos (12U)
  2473. #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
  2474. #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
  2475. #define CAN_FFA1R_FFA13_Pos (13U)
  2476. #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
  2477. #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
  2478. #define CAN_FFA1R_FFA14_Pos (14U)
  2479. #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
  2480. #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
  2481. #define CAN_FFA1R_FFA15_Pos (15U)
  2482. #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
  2483. #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
  2484. #define CAN_FFA1R_FFA16_Pos (16U)
  2485. #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
  2486. #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
  2487. #define CAN_FFA1R_FFA17_Pos (17U)
  2488. #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
  2489. #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
  2490. #define CAN_FFA1R_FFA18_Pos (18U)
  2491. #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
  2492. #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
  2493. #define CAN_FFA1R_FFA19_Pos (19U)
  2494. #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
  2495. #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
  2496. #define CAN_FFA1R_FFA20_Pos (20U)
  2497. #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
  2498. #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
  2499. #define CAN_FFA1R_FFA21_Pos (21U)
  2500. #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
  2501. #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
  2502. #define CAN_FFA1R_FFA22_Pos (22U)
  2503. #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
  2504. #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
  2505. #define CAN_FFA1R_FFA23_Pos (23U)
  2506. #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
  2507. #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
  2508. #define CAN_FFA1R_FFA24_Pos (24U)
  2509. #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
  2510. #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
  2511. #define CAN_FFA1R_FFA25_Pos (25U)
  2512. #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
  2513. #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
  2514. #define CAN_FFA1R_FFA26_Pos (26U)
  2515. #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
  2516. #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
  2517. #define CAN_FFA1R_FFA27_Pos (27U)
  2518. #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
  2519. #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
  2520. /******************* Bit definition for CAN_FA1R register *******************/
  2521. #define CAN_FA1R_FACT_Pos (0U)
  2522. #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
  2523. #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
  2524. #define CAN_FA1R_FACT0_Pos (0U)
  2525. #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
  2526. #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
  2527. #define CAN_FA1R_FACT1_Pos (1U)
  2528. #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
  2529. #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
  2530. #define CAN_FA1R_FACT2_Pos (2U)
  2531. #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
  2532. #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
  2533. #define CAN_FA1R_FACT3_Pos (3U)
  2534. #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
  2535. #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
  2536. #define CAN_FA1R_FACT4_Pos (4U)
  2537. #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
  2538. #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
  2539. #define CAN_FA1R_FACT5_Pos (5U)
  2540. #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
  2541. #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
  2542. #define CAN_FA1R_FACT6_Pos (6U)
  2543. #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
  2544. #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
  2545. #define CAN_FA1R_FACT7_Pos (7U)
  2546. #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
  2547. #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
  2548. #define CAN_FA1R_FACT8_Pos (8U)
  2549. #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
  2550. #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
  2551. #define CAN_FA1R_FACT9_Pos (9U)
  2552. #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
  2553. #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
  2554. #define CAN_FA1R_FACT10_Pos (10U)
  2555. #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
  2556. #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
  2557. #define CAN_FA1R_FACT11_Pos (11U)
  2558. #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
  2559. #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
  2560. #define CAN_FA1R_FACT12_Pos (12U)
  2561. #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
  2562. #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
  2563. #define CAN_FA1R_FACT13_Pos (13U)
  2564. #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
  2565. #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
  2566. #define CAN_FA1R_FACT14_Pos (14U)
  2567. #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
  2568. #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
  2569. #define CAN_FA1R_FACT15_Pos (15U)
  2570. #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
  2571. #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
  2572. #define CAN_FA1R_FACT16_Pos (16U)
  2573. #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
  2574. #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
  2575. #define CAN_FA1R_FACT17_Pos (17U)
  2576. #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
  2577. #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
  2578. #define CAN_FA1R_FACT18_Pos (18U)
  2579. #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
  2580. #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
  2581. #define CAN_FA1R_FACT19_Pos (19U)
  2582. #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
  2583. #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
  2584. #define CAN_FA1R_FACT20_Pos (20U)
  2585. #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
  2586. #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
  2587. #define CAN_FA1R_FACT21_Pos (21U)
  2588. #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
  2589. #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
  2590. #define CAN_FA1R_FACT22_Pos (22U)
  2591. #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
  2592. #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
  2593. #define CAN_FA1R_FACT23_Pos (23U)
  2594. #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
  2595. #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
  2596. #define CAN_FA1R_FACT24_Pos (24U)
  2597. #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
  2598. #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
  2599. #define CAN_FA1R_FACT25_Pos (25U)
  2600. #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
  2601. #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
  2602. #define CAN_FA1R_FACT26_Pos (26U)
  2603. #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
  2604. #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
  2605. #define CAN_FA1R_FACT27_Pos (27U)
  2606. #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
  2607. #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
  2608. /******************* Bit definition for CAN_F0R1 register *******************/
  2609. #define CAN_F0R1_FB0_Pos (0U)
  2610. #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
  2611. #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
  2612. #define CAN_F0R1_FB1_Pos (1U)
  2613. #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
  2614. #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
  2615. #define CAN_F0R1_FB2_Pos (2U)
  2616. #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
  2617. #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
  2618. #define CAN_F0R1_FB3_Pos (3U)
  2619. #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
  2620. #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
  2621. #define CAN_F0R1_FB4_Pos (4U)
  2622. #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
  2623. #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
  2624. #define CAN_F0R1_FB5_Pos (5U)
  2625. #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
  2626. #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
  2627. #define CAN_F0R1_FB6_Pos (6U)
  2628. #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
  2629. #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
  2630. #define CAN_F0R1_FB7_Pos (7U)
  2631. #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
  2632. #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
  2633. #define CAN_F0R1_FB8_Pos (8U)
  2634. #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
  2635. #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
  2636. #define CAN_F0R1_FB9_Pos (9U)
  2637. #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
  2638. #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
  2639. #define CAN_F0R1_FB10_Pos (10U)
  2640. #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
  2641. #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
  2642. #define CAN_F0R1_FB11_Pos (11U)
  2643. #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
  2644. #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
  2645. #define CAN_F0R1_FB12_Pos (12U)
  2646. #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
  2647. #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
  2648. #define CAN_F0R1_FB13_Pos (13U)
  2649. #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
  2650. #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
  2651. #define CAN_F0R1_FB14_Pos (14U)
  2652. #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
  2653. #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
  2654. #define CAN_F0R1_FB15_Pos (15U)
  2655. #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
  2656. #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
  2657. #define CAN_F0R1_FB16_Pos (16U)
  2658. #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
  2659. #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
  2660. #define CAN_F0R1_FB17_Pos (17U)
  2661. #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
  2662. #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
  2663. #define CAN_F0R1_FB18_Pos (18U)
  2664. #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
  2665. #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
  2666. #define CAN_F0R1_FB19_Pos (19U)
  2667. #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
  2668. #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
  2669. #define CAN_F0R1_FB20_Pos (20U)
  2670. #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
  2671. #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
  2672. #define CAN_F0R1_FB21_Pos (21U)
  2673. #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
  2674. #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
  2675. #define CAN_F0R1_FB22_Pos (22U)
  2676. #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
  2677. #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
  2678. #define CAN_F0R1_FB23_Pos (23U)
  2679. #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
  2680. #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
  2681. #define CAN_F0R1_FB24_Pos (24U)
  2682. #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
  2683. #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
  2684. #define CAN_F0R1_FB25_Pos (25U)
  2685. #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
  2686. #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
  2687. #define CAN_F0R1_FB26_Pos (26U)
  2688. #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
  2689. #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
  2690. #define CAN_F0R1_FB27_Pos (27U)
  2691. #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
  2692. #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
  2693. #define CAN_F0R1_FB28_Pos (28U)
  2694. #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
  2695. #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
  2696. #define CAN_F0R1_FB29_Pos (29U)
  2697. #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
  2698. #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
  2699. #define CAN_F0R1_FB30_Pos (30U)
  2700. #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
  2701. #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
  2702. #define CAN_F0R1_FB31_Pos (31U)
  2703. #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
  2704. #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
  2705. /******************* Bit definition for CAN_F1R1 register *******************/
  2706. #define CAN_F1R1_FB0_Pos (0U)
  2707. #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
  2708. #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
  2709. #define CAN_F1R1_FB1_Pos (1U)
  2710. #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
  2711. #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
  2712. #define CAN_F1R1_FB2_Pos (2U)
  2713. #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
  2714. #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
  2715. #define CAN_F1R1_FB3_Pos (3U)
  2716. #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
  2717. #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
  2718. #define CAN_F1R1_FB4_Pos (4U)
  2719. #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
  2720. #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
  2721. #define CAN_F1R1_FB5_Pos (5U)
  2722. #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
  2723. #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
  2724. #define CAN_F1R1_FB6_Pos (6U)
  2725. #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
  2726. #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
  2727. #define CAN_F1R1_FB7_Pos (7U)
  2728. #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
  2729. #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
  2730. #define CAN_F1R1_FB8_Pos (8U)
  2731. #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
  2732. #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
  2733. #define CAN_F1R1_FB9_Pos (9U)
  2734. #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
  2735. #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
  2736. #define CAN_F1R1_FB10_Pos (10U)
  2737. #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
  2738. #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
  2739. #define CAN_F1R1_FB11_Pos (11U)
  2740. #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
  2741. #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
  2742. #define CAN_F1R1_FB12_Pos (12U)
  2743. #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
  2744. #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
  2745. #define CAN_F1R1_FB13_Pos (13U)
  2746. #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
  2747. #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
  2748. #define CAN_F1R1_FB14_Pos (14U)
  2749. #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
  2750. #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
  2751. #define CAN_F1R1_FB15_Pos (15U)
  2752. #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
  2753. #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
  2754. #define CAN_F1R1_FB16_Pos (16U)
  2755. #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
  2756. #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
  2757. #define CAN_F1R1_FB17_Pos (17U)
  2758. #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
  2759. #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
  2760. #define CAN_F1R1_FB18_Pos (18U)
  2761. #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
  2762. #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
  2763. #define CAN_F1R1_FB19_Pos (19U)
  2764. #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
  2765. #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
  2766. #define CAN_F1R1_FB20_Pos (20U)
  2767. #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
  2768. #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
  2769. #define CAN_F1R1_FB21_Pos (21U)
  2770. #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
  2771. #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
  2772. #define CAN_F1R1_FB22_Pos (22U)
  2773. #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
  2774. #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
  2775. #define CAN_F1R1_FB23_Pos (23U)
  2776. #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
  2777. #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
  2778. #define CAN_F1R1_FB24_Pos (24U)
  2779. #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
  2780. #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
  2781. #define CAN_F1R1_FB25_Pos (25U)
  2782. #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
  2783. #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
  2784. #define CAN_F1R1_FB26_Pos (26U)
  2785. #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
  2786. #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
  2787. #define CAN_F1R1_FB27_Pos (27U)
  2788. #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
  2789. #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
  2790. #define CAN_F1R1_FB28_Pos (28U)
  2791. #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
  2792. #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
  2793. #define CAN_F1R1_FB29_Pos (29U)
  2794. #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
  2795. #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
  2796. #define CAN_F1R1_FB30_Pos (30U)
  2797. #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
  2798. #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
  2799. #define CAN_F1R1_FB31_Pos (31U)
  2800. #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
  2801. #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
  2802. /******************* Bit definition for CAN_F2R1 register *******************/
  2803. #define CAN_F2R1_FB0_Pos (0U)
  2804. #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
  2805. #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
  2806. #define CAN_F2R1_FB1_Pos (1U)
  2807. #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
  2808. #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
  2809. #define CAN_F2R1_FB2_Pos (2U)
  2810. #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
  2811. #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
  2812. #define CAN_F2R1_FB3_Pos (3U)
  2813. #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
  2814. #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
  2815. #define CAN_F2R1_FB4_Pos (4U)
  2816. #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
  2817. #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
  2818. #define CAN_F2R1_FB5_Pos (5U)
  2819. #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
  2820. #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
  2821. #define CAN_F2R1_FB6_Pos (6U)
  2822. #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
  2823. #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
  2824. #define CAN_F2R1_FB7_Pos (7U)
  2825. #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
  2826. #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
  2827. #define CAN_F2R1_FB8_Pos (8U)
  2828. #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
  2829. #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
  2830. #define CAN_F2R1_FB9_Pos (9U)
  2831. #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
  2832. #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
  2833. #define CAN_F2R1_FB10_Pos (10U)
  2834. #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
  2835. #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
  2836. #define CAN_F2R1_FB11_Pos (11U)
  2837. #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
  2838. #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
  2839. #define CAN_F2R1_FB12_Pos (12U)
  2840. #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
  2841. #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
  2842. #define CAN_F2R1_FB13_Pos (13U)
  2843. #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
  2844. #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
  2845. #define CAN_F2R1_FB14_Pos (14U)
  2846. #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
  2847. #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
  2848. #define CAN_F2R1_FB15_Pos (15U)
  2849. #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
  2850. #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
  2851. #define CAN_F2R1_FB16_Pos (16U)
  2852. #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
  2853. #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
  2854. #define CAN_F2R1_FB17_Pos (17U)
  2855. #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
  2856. #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
  2857. #define CAN_F2R1_FB18_Pos (18U)
  2858. #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
  2859. #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
  2860. #define CAN_F2R1_FB19_Pos (19U)
  2861. #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
  2862. #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
  2863. #define CAN_F2R1_FB20_Pos (20U)
  2864. #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
  2865. #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
  2866. #define CAN_F2R1_FB21_Pos (21U)
  2867. #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
  2868. #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
  2869. #define CAN_F2R1_FB22_Pos (22U)
  2870. #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
  2871. #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
  2872. #define CAN_F2R1_FB23_Pos (23U)
  2873. #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
  2874. #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
  2875. #define CAN_F2R1_FB24_Pos (24U)
  2876. #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
  2877. #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
  2878. #define CAN_F2R1_FB25_Pos (25U)
  2879. #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
  2880. #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
  2881. #define CAN_F2R1_FB26_Pos (26U)
  2882. #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
  2883. #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
  2884. #define CAN_F2R1_FB27_Pos (27U)
  2885. #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
  2886. #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
  2887. #define CAN_F2R1_FB28_Pos (28U)
  2888. #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
  2889. #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
  2890. #define CAN_F2R1_FB29_Pos (29U)
  2891. #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
  2892. #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
  2893. #define CAN_F2R1_FB30_Pos (30U)
  2894. #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
  2895. #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
  2896. #define CAN_F2R1_FB31_Pos (31U)
  2897. #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
  2898. #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
  2899. /******************* Bit definition for CAN_F3R1 register *******************/
  2900. #define CAN_F3R1_FB0_Pos (0U)
  2901. #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
  2902. #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
  2903. #define CAN_F3R1_FB1_Pos (1U)
  2904. #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
  2905. #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
  2906. #define CAN_F3R1_FB2_Pos (2U)
  2907. #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
  2908. #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
  2909. #define CAN_F3R1_FB3_Pos (3U)
  2910. #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
  2911. #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
  2912. #define CAN_F3R1_FB4_Pos (4U)
  2913. #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
  2914. #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
  2915. #define CAN_F3R1_FB5_Pos (5U)
  2916. #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
  2917. #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
  2918. #define CAN_F3R1_FB6_Pos (6U)
  2919. #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
  2920. #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
  2921. #define CAN_F3R1_FB7_Pos (7U)
  2922. #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
  2923. #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
  2924. #define CAN_F3R1_FB8_Pos (8U)
  2925. #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
  2926. #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
  2927. #define CAN_F3R1_FB9_Pos (9U)
  2928. #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
  2929. #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
  2930. #define CAN_F3R1_FB10_Pos (10U)
  2931. #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
  2932. #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
  2933. #define CAN_F3R1_FB11_Pos (11U)
  2934. #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
  2935. #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
  2936. #define CAN_F3R1_FB12_Pos (12U)
  2937. #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
  2938. #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
  2939. #define CAN_F3R1_FB13_Pos (13U)
  2940. #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
  2941. #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
  2942. #define CAN_F3R1_FB14_Pos (14U)
  2943. #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
  2944. #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
  2945. #define CAN_F3R1_FB15_Pos (15U)
  2946. #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
  2947. #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
  2948. #define CAN_F3R1_FB16_Pos (16U)
  2949. #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
  2950. #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
  2951. #define CAN_F3R1_FB17_Pos (17U)
  2952. #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
  2953. #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
  2954. #define CAN_F3R1_FB18_Pos (18U)
  2955. #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
  2956. #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
  2957. #define CAN_F3R1_FB19_Pos (19U)
  2958. #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
  2959. #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
  2960. #define CAN_F3R1_FB20_Pos (20U)
  2961. #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
  2962. #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
  2963. #define CAN_F3R1_FB21_Pos (21U)
  2964. #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
  2965. #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
  2966. #define CAN_F3R1_FB22_Pos (22U)
  2967. #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
  2968. #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
  2969. #define CAN_F3R1_FB23_Pos (23U)
  2970. #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
  2971. #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
  2972. #define CAN_F3R1_FB24_Pos (24U)
  2973. #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
  2974. #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
  2975. #define CAN_F3R1_FB25_Pos (25U)
  2976. #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
  2977. #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
  2978. #define CAN_F3R1_FB26_Pos (26U)
  2979. #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
  2980. #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
  2981. #define CAN_F3R1_FB27_Pos (27U)
  2982. #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
  2983. #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
  2984. #define CAN_F3R1_FB28_Pos (28U)
  2985. #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
  2986. #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
  2987. #define CAN_F3R1_FB29_Pos (29U)
  2988. #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
  2989. #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
  2990. #define CAN_F3R1_FB30_Pos (30U)
  2991. #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
  2992. #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
  2993. #define CAN_F3R1_FB31_Pos (31U)
  2994. #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
  2995. #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
  2996. /******************* Bit definition for CAN_F4R1 register *******************/
  2997. #define CAN_F4R1_FB0_Pos (0U)
  2998. #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
  2999. #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
  3000. #define CAN_F4R1_FB1_Pos (1U)
  3001. #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
  3002. #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
  3003. #define CAN_F4R1_FB2_Pos (2U)
  3004. #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
  3005. #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
  3006. #define CAN_F4R1_FB3_Pos (3U)
  3007. #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
  3008. #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
  3009. #define CAN_F4R1_FB4_Pos (4U)
  3010. #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
  3011. #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
  3012. #define CAN_F4R1_FB5_Pos (5U)
  3013. #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
  3014. #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
  3015. #define CAN_F4R1_FB6_Pos (6U)
  3016. #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
  3017. #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
  3018. #define CAN_F4R1_FB7_Pos (7U)
  3019. #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
  3020. #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
  3021. #define CAN_F4R1_FB8_Pos (8U)
  3022. #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
  3023. #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
  3024. #define CAN_F4R1_FB9_Pos (9U)
  3025. #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
  3026. #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
  3027. #define CAN_F4R1_FB10_Pos (10U)
  3028. #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
  3029. #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
  3030. #define CAN_F4R1_FB11_Pos (11U)
  3031. #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
  3032. #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
  3033. #define CAN_F4R1_FB12_Pos (12U)
  3034. #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
  3035. #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
  3036. #define CAN_F4R1_FB13_Pos (13U)
  3037. #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
  3038. #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
  3039. #define CAN_F4R1_FB14_Pos (14U)
  3040. #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
  3041. #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
  3042. #define CAN_F4R1_FB15_Pos (15U)
  3043. #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
  3044. #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
  3045. #define CAN_F4R1_FB16_Pos (16U)
  3046. #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
  3047. #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
  3048. #define CAN_F4R1_FB17_Pos (17U)
  3049. #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
  3050. #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
  3051. #define CAN_F4R1_FB18_Pos (18U)
  3052. #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
  3053. #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
  3054. #define CAN_F4R1_FB19_Pos (19U)
  3055. #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
  3056. #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
  3057. #define CAN_F4R1_FB20_Pos (20U)
  3058. #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
  3059. #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
  3060. #define CAN_F4R1_FB21_Pos (21U)
  3061. #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
  3062. #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
  3063. #define CAN_F4R1_FB22_Pos (22U)
  3064. #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
  3065. #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
  3066. #define CAN_F4R1_FB23_Pos (23U)
  3067. #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
  3068. #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
  3069. #define CAN_F4R1_FB24_Pos (24U)
  3070. #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
  3071. #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
  3072. #define CAN_F4R1_FB25_Pos (25U)
  3073. #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
  3074. #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
  3075. #define CAN_F4R1_FB26_Pos (26U)
  3076. #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
  3077. #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
  3078. #define CAN_F4R1_FB27_Pos (27U)
  3079. #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
  3080. #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
  3081. #define CAN_F4R1_FB28_Pos (28U)
  3082. #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
  3083. #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
  3084. #define CAN_F4R1_FB29_Pos (29U)
  3085. #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
  3086. #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
  3087. #define CAN_F4R1_FB30_Pos (30U)
  3088. #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
  3089. #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
  3090. #define CAN_F4R1_FB31_Pos (31U)
  3091. #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
  3092. #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
  3093. /******************* Bit definition for CAN_F5R1 register *******************/
  3094. #define CAN_F5R1_FB0_Pos (0U)
  3095. #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
  3096. #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
  3097. #define CAN_F5R1_FB1_Pos (1U)
  3098. #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
  3099. #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
  3100. #define CAN_F5R1_FB2_Pos (2U)
  3101. #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
  3102. #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
  3103. #define CAN_F5R1_FB3_Pos (3U)
  3104. #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
  3105. #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
  3106. #define CAN_F5R1_FB4_Pos (4U)
  3107. #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
  3108. #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
  3109. #define CAN_F5R1_FB5_Pos (5U)
  3110. #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
  3111. #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
  3112. #define CAN_F5R1_FB6_Pos (6U)
  3113. #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
  3114. #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
  3115. #define CAN_F5R1_FB7_Pos (7U)
  3116. #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
  3117. #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
  3118. #define CAN_F5R1_FB8_Pos (8U)
  3119. #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
  3120. #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
  3121. #define CAN_F5R1_FB9_Pos (9U)
  3122. #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
  3123. #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
  3124. #define CAN_F5R1_FB10_Pos (10U)
  3125. #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
  3126. #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
  3127. #define CAN_F5R1_FB11_Pos (11U)
  3128. #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
  3129. #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
  3130. #define CAN_F5R1_FB12_Pos (12U)
  3131. #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
  3132. #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
  3133. #define CAN_F5R1_FB13_Pos (13U)
  3134. #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
  3135. #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
  3136. #define CAN_F5R1_FB14_Pos (14U)
  3137. #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
  3138. #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
  3139. #define CAN_F5R1_FB15_Pos (15U)
  3140. #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
  3141. #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
  3142. #define CAN_F5R1_FB16_Pos (16U)
  3143. #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
  3144. #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
  3145. #define CAN_F5R1_FB17_Pos (17U)
  3146. #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
  3147. #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
  3148. #define CAN_F5R1_FB18_Pos (18U)
  3149. #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
  3150. #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
  3151. #define CAN_F5R1_FB19_Pos (19U)
  3152. #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
  3153. #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
  3154. #define CAN_F5R1_FB20_Pos (20U)
  3155. #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
  3156. #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
  3157. #define CAN_F5R1_FB21_Pos (21U)
  3158. #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
  3159. #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
  3160. #define CAN_F5R1_FB22_Pos (22U)
  3161. #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
  3162. #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
  3163. #define CAN_F5R1_FB23_Pos (23U)
  3164. #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
  3165. #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
  3166. #define CAN_F5R1_FB24_Pos (24U)
  3167. #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
  3168. #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
  3169. #define CAN_F5R1_FB25_Pos (25U)
  3170. #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
  3171. #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
  3172. #define CAN_F5R1_FB26_Pos (26U)
  3173. #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
  3174. #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
  3175. #define CAN_F5R1_FB27_Pos (27U)
  3176. #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
  3177. #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
  3178. #define CAN_F5R1_FB28_Pos (28U)
  3179. #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
  3180. #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
  3181. #define CAN_F5R1_FB29_Pos (29U)
  3182. #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
  3183. #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
  3184. #define CAN_F5R1_FB30_Pos (30U)
  3185. #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
  3186. #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
  3187. #define CAN_F5R1_FB31_Pos (31U)
  3188. #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
  3189. #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
  3190. /******************* Bit definition for CAN_F6R1 register *******************/
  3191. #define CAN_F6R1_FB0_Pos (0U)
  3192. #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
  3193. #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
  3194. #define CAN_F6R1_FB1_Pos (1U)
  3195. #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
  3196. #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
  3197. #define CAN_F6R1_FB2_Pos (2U)
  3198. #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
  3199. #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
  3200. #define CAN_F6R1_FB3_Pos (3U)
  3201. #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
  3202. #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
  3203. #define CAN_F6R1_FB4_Pos (4U)
  3204. #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
  3205. #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
  3206. #define CAN_F6R1_FB5_Pos (5U)
  3207. #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
  3208. #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
  3209. #define CAN_F6R1_FB6_Pos (6U)
  3210. #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
  3211. #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
  3212. #define CAN_F6R1_FB7_Pos (7U)
  3213. #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
  3214. #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
  3215. #define CAN_F6R1_FB8_Pos (8U)
  3216. #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
  3217. #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
  3218. #define CAN_F6R1_FB9_Pos (9U)
  3219. #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
  3220. #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
  3221. #define CAN_F6R1_FB10_Pos (10U)
  3222. #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
  3223. #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
  3224. #define CAN_F6R1_FB11_Pos (11U)
  3225. #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
  3226. #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
  3227. #define CAN_F6R1_FB12_Pos (12U)
  3228. #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
  3229. #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
  3230. #define CAN_F6R1_FB13_Pos (13U)
  3231. #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
  3232. #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
  3233. #define CAN_F6R1_FB14_Pos (14U)
  3234. #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
  3235. #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
  3236. #define CAN_F6R1_FB15_Pos (15U)
  3237. #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
  3238. #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
  3239. #define CAN_F6R1_FB16_Pos (16U)
  3240. #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
  3241. #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
  3242. #define CAN_F6R1_FB17_Pos (17U)
  3243. #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
  3244. #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
  3245. #define CAN_F6R1_FB18_Pos (18U)
  3246. #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
  3247. #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
  3248. #define CAN_F6R1_FB19_Pos (19U)
  3249. #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
  3250. #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
  3251. #define CAN_F6R1_FB20_Pos (20U)
  3252. #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
  3253. #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
  3254. #define CAN_F6R1_FB21_Pos (21U)
  3255. #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
  3256. #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
  3257. #define CAN_F6R1_FB22_Pos (22U)
  3258. #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
  3259. #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
  3260. #define CAN_F6R1_FB23_Pos (23U)
  3261. #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
  3262. #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
  3263. #define CAN_F6R1_FB24_Pos (24U)
  3264. #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
  3265. #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
  3266. #define CAN_F6R1_FB25_Pos (25U)
  3267. #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
  3268. #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
  3269. #define CAN_F6R1_FB26_Pos (26U)
  3270. #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
  3271. #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
  3272. #define CAN_F6R1_FB27_Pos (27U)
  3273. #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
  3274. #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
  3275. #define CAN_F6R1_FB28_Pos (28U)
  3276. #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
  3277. #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
  3278. #define CAN_F6R1_FB29_Pos (29U)
  3279. #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
  3280. #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
  3281. #define CAN_F6R1_FB30_Pos (30U)
  3282. #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
  3283. #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
  3284. #define CAN_F6R1_FB31_Pos (31U)
  3285. #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
  3286. #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
  3287. /******************* Bit definition for CAN_F7R1 register *******************/
  3288. #define CAN_F7R1_FB0_Pos (0U)
  3289. #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
  3290. #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
  3291. #define CAN_F7R1_FB1_Pos (1U)
  3292. #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
  3293. #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
  3294. #define CAN_F7R1_FB2_Pos (2U)
  3295. #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
  3296. #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
  3297. #define CAN_F7R1_FB3_Pos (3U)
  3298. #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
  3299. #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
  3300. #define CAN_F7R1_FB4_Pos (4U)
  3301. #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
  3302. #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
  3303. #define CAN_F7R1_FB5_Pos (5U)
  3304. #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
  3305. #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
  3306. #define CAN_F7R1_FB6_Pos (6U)
  3307. #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
  3308. #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
  3309. #define CAN_F7R1_FB7_Pos (7U)
  3310. #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
  3311. #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
  3312. #define CAN_F7R1_FB8_Pos (8U)
  3313. #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
  3314. #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
  3315. #define CAN_F7R1_FB9_Pos (9U)
  3316. #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
  3317. #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
  3318. #define CAN_F7R1_FB10_Pos (10U)
  3319. #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
  3320. #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
  3321. #define CAN_F7R1_FB11_Pos (11U)
  3322. #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
  3323. #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
  3324. #define CAN_F7R1_FB12_Pos (12U)
  3325. #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
  3326. #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
  3327. #define CAN_F7R1_FB13_Pos (13U)
  3328. #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
  3329. #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
  3330. #define CAN_F7R1_FB14_Pos (14U)
  3331. #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
  3332. #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
  3333. #define CAN_F7R1_FB15_Pos (15U)
  3334. #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
  3335. #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
  3336. #define CAN_F7R1_FB16_Pos (16U)
  3337. #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
  3338. #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
  3339. #define CAN_F7R1_FB17_Pos (17U)
  3340. #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
  3341. #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
  3342. #define CAN_F7R1_FB18_Pos (18U)
  3343. #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
  3344. #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
  3345. #define CAN_F7R1_FB19_Pos (19U)
  3346. #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
  3347. #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
  3348. #define CAN_F7R1_FB20_Pos (20U)
  3349. #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
  3350. #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
  3351. #define CAN_F7R1_FB21_Pos (21U)
  3352. #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
  3353. #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
  3354. #define CAN_F7R1_FB22_Pos (22U)
  3355. #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
  3356. #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
  3357. #define CAN_F7R1_FB23_Pos (23U)
  3358. #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
  3359. #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
  3360. #define CAN_F7R1_FB24_Pos (24U)
  3361. #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
  3362. #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
  3363. #define CAN_F7R1_FB25_Pos (25U)
  3364. #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
  3365. #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
  3366. #define CAN_F7R1_FB26_Pos (26U)
  3367. #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
  3368. #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
  3369. #define CAN_F7R1_FB27_Pos (27U)
  3370. #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
  3371. #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
  3372. #define CAN_F7R1_FB28_Pos (28U)
  3373. #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
  3374. #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
  3375. #define CAN_F7R1_FB29_Pos (29U)
  3376. #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
  3377. #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
  3378. #define CAN_F7R1_FB30_Pos (30U)
  3379. #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
  3380. #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
  3381. #define CAN_F7R1_FB31_Pos (31U)
  3382. #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
  3383. #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
  3384. /******************* Bit definition for CAN_F8R1 register *******************/
  3385. #define CAN_F8R1_FB0_Pos (0U)
  3386. #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
  3387. #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
  3388. #define CAN_F8R1_FB1_Pos (1U)
  3389. #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
  3390. #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
  3391. #define CAN_F8R1_FB2_Pos (2U)
  3392. #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
  3393. #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
  3394. #define CAN_F8R1_FB3_Pos (3U)
  3395. #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
  3396. #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
  3397. #define CAN_F8R1_FB4_Pos (4U)
  3398. #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
  3399. #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
  3400. #define CAN_F8R1_FB5_Pos (5U)
  3401. #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
  3402. #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
  3403. #define CAN_F8R1_FB6_Pos (6U)
  3404. #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
  3405. #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
  3406. #define CAN_F8R1_FB7_Pos (7U)
  3407. #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
  3408. #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
  3409. #define CAN_F8R1_FB8_Pos (8U)
  3410. #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
  3411. #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
  3412. #define CAN_F8R1_FB9_Pos (9U)
  3413. #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
  3414. #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
  3415. #define CAN_F8R1_FB10_Pos (10U)
  3416. #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
  3417. #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
  3418. #define CAN_F8R1_FB11_Pos (11U)
  3419. #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
  3420. #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
  3421. #define CAN_F8R1_FB12_Pos (12U)
  3422. #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
  3423. #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
  3424. #define CAN_F8R1_FB13_Pos (13U)
  3425. #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
  3426. #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
  3427. #define CAN_F8R1_FB14_Pos (14U)
  3428. #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
  3429. #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
  3430. #define CAN_F8R1_FB15_Pos (15U)
  3431. #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
  3432. #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
  3433. #define CAN_F8R1_FB16_Pos (16U)
  3434. #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
  3435. #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
  3436. #define CAN_F8R1_FB17_Pos (17U)
  3437. #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
  3438. #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
  3439. #define CAN_F8R1_FB18_Pos (18U)
  3440. #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
  3441. #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
  3442. #define CAN_F8R1_FB19_Pos (19U)
  3443. #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
  3444. #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
  3445. #define CAN_F8R1_FB20_Pos (20U)
  3446. #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
  3447. #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
  3448. #define CAN_F8R1_FB21_Pos (21U)
  3449. #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
  3450. #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
  3451. #define CAN_F8R1_FB22_Pos (22U)
  3452. #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
  3453. #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
  3454. #define CAN_F8R1_FB23_Pos (23U)
  3455. #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
  3456. #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
  3457. #define CAN_F8R1_FB24_Pos (24U)
  3458. #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
  3459. #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
  3460. #define CAN_F8R1_FB25_Pos (25U)
  3461. #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
  3462. #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
  3463. #define CAN_F8R1_FB26_Pos (26U)
  3464. #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
  3465. #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
  3466. #define CAN_F8R1_FB27_Pos (27U)
  3467. #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
  3468. #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
  3469. #define CAN_F8R1_FB28_Pos (28U)
  3470. #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
  3471. #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
  3472. #define CAN_F8R1_FB29_Pos (29U)
  3473. #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
  3474. #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
  3475. #define CAN_F8R1_FB30_Pos (30U)
  3476. #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
  3477. #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
  3478. #define CAN_F8R1_FB31_Pos (31U)
  3479. #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
  3480. #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
  3481. /******************* Bit definition for CAN_F9R1 register *******************/
  3482. #define CAN_F9R1_FB0_Pos (0U)
  3483. #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
  3484. #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
  3485. #define CAN_F9R1_FB1_Pos (1U)
  3486. #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
  3487. #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
  3488. #define CAN_F9R1_FB2_Pos (2U)
  3489. #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
  3490. #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
  3491. #define CAN_F9R1_FB3_Pos (3U)
  3492. #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
  3493. #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
  3494. #define CAN_F9R1_FB4_Pos (4U)
  3495. #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
  3496. #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
  3497. #define CAN_F9R1_FB5_Pos (5U)
  3498. #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
  3499. #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
  3500. #define CAN_F9R1_FB6_Pos (6U)
  3501. #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
  3502. #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
  3503. #define CAN_F9R1_FB7_Pos (7U)
  3504. #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
  3505. #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
  3506. #define CAN_F9R1_FB8_Pos (8U)
  3507. #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
  3508. #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
  3509. #define CAN_F9R1_FB9_Pos (9U)
  3510. #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
  3511. #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
  3512. #define CAN_F9R1_FB10_Pos (10U)
  3513. #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
  3514. #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
  3515. #define CAN_F9R1_FB11_Pos (11U)
  3516. #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
  3517. #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
  3518. #define CAN_F9R1_FB12_Pos (12U)
  3519. #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
  3520. #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
  3521. #define CAN_F9R1_FB13_Pos (13U)
  3522. #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
  3523. #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
  3524. #define CAN_F9R1_FB14_Pos (14U)
  3525. #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
  3526. #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
  3527. #define CAN_F9R1_FB15_Pos (15U)
  3528. #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
  3529. #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
  3530. #define CAN_F9R1_FB16_Pos (16U)
  3531. #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
  3532. #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
  3533. #define CAN_F9R1_FB17_Pos (17U)
  3534. #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
  3535. #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
  3536. #define CAN_F9R1_FB18_Pos (18U)
  3537. #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
  3538. #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
  3539. #define CAN_F9R1_FB19_Pos (19U)
  3540. #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
  3541. #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
  3542. #define CAN_F9R1_FB20_Pos (20U)
  3543. #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
  3544. #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
  3545. #define CAN_F9R1_FB21_Pos (21U)
  3546. #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
  3547. #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
  3548. #define CAN_F9R1_FB22_Pos (22U)
  3549. #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
  3550. #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
  3551. #define CAN_F9R1_FB23_Pos (23U)
  3552. #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
  3553. #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
  3554. #define CAN_F9R1_FB24_Pos (24U)
  3555. #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
  3556. #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
  3557. #define CAN_F9R1_FB25_Pos (25U)
  3558. #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
  3559. #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
  3560. #define CAN_F9R1_FB26_Pos (26U)
  3561. #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
  3562. #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
  3563. #define CAN_F9R1_FB27_Pos (27U)
  3564. #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
  3565. #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
  3566. #define CAN_F9R1_FB28_Pos (28U)
  3567. #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
  3568. #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
  3569. #define CAN_F9R1_FB29_Pos (29U)
  3570. #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
  3571. #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
  3572. #define CAN_F9R1_FB30_Pos (30U)
  3573. #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
  3574. #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
  3575. #define CAN_F9R1_FB31_Pos (31U)
  3576. #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
  3577. #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
  3578. /******************* Bit definition for CAN_F10R1 register ******************/
  3579. #define CAN_F10R1_FB0_Pos (0U)
  3580. #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
  3581. #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
  3582. #define CAN_F10R1_FB1_Pos (1U)
  3583. #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
  3584. #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
  3585. #define CAN_F10R1_FB2_Pos (2U)
  3586. #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
  3587. #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
  3588. #define CAN_F10R1_FB3_Pos (3U)
  3589. #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
  3590. #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
  3591. #define CAN_F10R1_FB4_Pos (4U)
  3592. #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
  3593. #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
  3594. #define CAN_F10R1_FB5_Pos (5U)
  3595. #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
  3596. #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
  3597. #define CAN_F10R1_FB6_Pos (6U)
  3598. #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
  3599. #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
  3600. #define CAN_F10R1_FB7_Pos (7U)
  3601. #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
  3602. #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
  3603. #define CAN_F10R1_FB8_Pos (8U)
  3604. #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
  3605. #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
  3606. #define CAN_F10R1_FB9_Pos (9U)
  3607. #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
  3608. #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
  3609. #define CAN_F10R1_FB10_Pos (10U)
  3610. #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
  3611. #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
  3612. #define CAN_F10R1_FB11_Pos (11U)
  3613. #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
  3614. #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
  3615. #define CAN_F10R1_FB12_Pos (12U)
  3616. #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
  3617. #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
  3618. #define CAN_F10R1_FB13_Pos (13U)
  3619. #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
  3620. #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
  3621. #define CAN_F10R1_FB14_Pos (14U)
  3622. #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
  3623. #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
  3624. #define CAN_F10R1_FB15_Pos (15U)
  3625. #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
  3626. #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
  3627. #define CAN_F10R1_FB16_Pos (16U)
  3628. #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
  3629. #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
  3630. #define CAN_F10R1_FB17_Pos (17U)
  3631. #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
  3632. #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
  3633. #define CAN_F10R1_FB18_Pos (18U)
  3634. #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
  3635. #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
  3636. #define CAN_F10R1_FB19_Pos (19U)
  3637. #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
  3638. #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
  3639. #define CAN_F10R1_FB20_Pos (20U)
  3640. #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
  3641. #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
  3642. #define CAN_F10R1_FB21_Pos (21U)
  3643. #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
  3644. #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
  3645. #define CAN_F10R1_FB22_Pos (22U)
  3646. #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
  3647. #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
  3648. #define CAN_F10R1_FB23_Pos (23U)
  3649. #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
  3650. #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
  3651. #define CAN_F10R1_FB24_Pos (24U)
  3652. #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
  3653. #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
  3654. #define CAN_F10R1_FB25_Pos (25U)
  3655. #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
  3656. #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
  3657. #define CAN_F10R1_FB26_Pos (26U)
  3658. #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
  3659. #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
  3660. #define CAN_F10R1_FB27_Pos (27U)
  3661. #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
  3662. #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
  3663. #define CAN_F10R1_FB28_Pos (28U)
  3664. #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
  3665. #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
  3666. #define CAN_F10R1_FB29_Pos (29U)
  3667. #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
  3668. #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
  3669. #define CAN_F10R1_FB30_Pos (30U)
  3670. #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
  3671. #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
  3672. #define CAN_F10R1_FB31_Pos (31U)
  3673. #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
  3674. #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
  3675. /******************* Bit definition for CAN_F11R1 register ******************/
  3676. #define CAN_F11R1_FB0_Pos (0U)
  3677. #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
  3678. #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
  3679. #define CAN_F11R1_FB1_Pos (1U)
  3680. #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
  3681. #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
  3682. #define CAN_F11R1_FB2_Pos (2U)
  3683. #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
  3684. #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
  3685. #define CAN_F11R1_FB3_Pos (3U)
  3686. #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
  3687. #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
  3688. #define CAN_F11R1_FB4_Pos (4U)
  3689. #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
  3690. #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
  3691. #define CAN_F11R1_FB5_Pos (5U)
  3692. #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
  3693. #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
  3694. #define CAN_F11R1_FB6_Pos (6U)
  3695. #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
  3696. #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
  3697. #define CAN_F11R1_FB7_Pos (7U)
  3698. #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
  3699. #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
  3700. #define CAN_F11R1_FB8_Pos (8U)
  3701. #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
  3702. #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
  3703. #define CAN_F11R1_FB9_Pos (9U)
  3704. #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
  3705. #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
  3706. #define CAN_F11R1_FB10_Pos (10U)
  3707. #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
  3708. #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
  3709. #define CAN_F11R1_FB11_Pos (11U)
  3710. #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
  3711. #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
  3712. #define CAN_F11R1_FB12_Pos (12U)
  3713. #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
  3714. #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
  3715. #define CAN_F11R1_FB13_Pos (13U)
  3716. #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
  3717. #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
  3718. #define CAN_F11R1_FB14_Pos (14U)
  3719. #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
  3720. #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
  3721. #define CAN_F11R1_FB15_Pos (15U)
  3722. #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
  3723. #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
  3724. #define CAN_F11R1_FB16_Pos (16U)
  3725. #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
  3726. #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
  3727. #define CAN_F11R1_FB17_Pos (17U)
  3728. #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
  3729. #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
  3730. #define CAN_F11R1_FB18_Pos (18U)
  3731. #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
  3732. #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
  3733. #define CAN_F11R1_FB19_Pos (19U)
  3734. #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
  3735. #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
  3736. #define CAN_F11R1_FB20_Pos (20U)
  3737. #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
  3738. #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
  3739. #define CAN_F11R1_FB21_Pos (21U)
  3740. #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
  3741. #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
  3742. #define CAN_F11R1_FB22_Pos (22U)
  3743. #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
  3744. #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
  3745. #define CAN_F11R1_FB23_Pos (23U)
  3746. #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
  3747. #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
  3748. #define CAN_F11R1_FB24_Pos (24U)
  3749. #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
  3750. #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
  3751. #define CAN_F11R1_FB25_Pos (25U)
  3752. #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
  3753. #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
  3754. #define CAN_F11R1_FB26_Pos (26U)
  3755. #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
  3756. #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
  3757. #define CAN_F11R1_FB27_Pos (27U)
  3758. #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
  3759. #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
  3760. #define CAN_F11R1_FB28_Pos (28U)
  3761. #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
  3762. #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
  3763. #define CAN_F11R1_FB29_Pos (29U)
  3764. #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
  3765. #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
  3766. #define CAN_F11R1_FB30_Pos (30U)
  3767. #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
  3768. #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
  3769. #define CAN_F11R1_FB31_Pos (31U)
  3770. #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
  3771. #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
  3772. /******************* Bit definition for CAN_F12R1 register ******************/
  3773. #define CAN_F12R1_FB0_Pos (0U)
  3774. #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
  3775. #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
  3776. #define CAN_F12R1_FB1_Pos (1U)
  3777. #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
  3778. #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
  3779. #define CAN_F12R1_FB2_Pos (2U)
  3780. #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
  3781. #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
  3782. #define CAN_F12R1_FB3_Pos (3U)
  3783. #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
  3784. #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
  3785. #define CAN_F12R1_FB4_Pos (4U)
  3786. #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
  3787. #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
  3788. #define CAN_F12R1_FB5_Pos (5U)
  3789. #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
  3790. #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
  3791. #define CAN_F12R1_FB6_Pos (6U)
  3792. #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
  3793. #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
  3794. #define CAN_F12R1_FB7_Pos (7U)
  3795. #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
  3796. #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
  3797. #define CAN_F12R1_FB8_Pos (8U)
  3798. #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
  3799. #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
  3800. #define CAN_F12R1_FB9_Pos (9U)
  3801. #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
  3802. #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
  3803. #define CAN_F12R1_FB10_Pos (10U)
  3804. #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
  3805. #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
  3806. #define CAN_F12R1_FB11_Pos (11U)
  3807. #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
  3808. #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
  3809. #define CAN_F12R1_FB12_Pos (12U)
  3810. #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
  3811. #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
  3812. #define CAN_F12R1_FB13_Pos (13U)
  3813. #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
  3814. #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
  3815. #define CAN_F12R1_FB14_Pos (14U)
  3816. #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
  3817. #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
  3818. #define CAN_F12R1_FB15_Pos (15U)
  3819. #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
  3820. #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
  3821. #define CAN_F12R1_FB16_Pos (16U)
  3822. #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
  3823. #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
  3824. #define CAN_F12R1_FB17_Pos (17U)
  3825. #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
  3826. #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
  3827. #define CAN_F12R1_FB18_Pos (18U)
  3828. #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
  3829. #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
  3830. #define CAN_F12R1_FB19_Pos (19U)
  3831. #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
  3832. #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
  3833. #define CAN_F12R1_FB20_Pos (20U)
  3834. #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
  3835. #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
  3836. #define CAN_F12R1_FB21_Pos (21U)
  3837. #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
  3838. #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
  3839. #define CAN_F12R1_FB22_Pos (22U)
  3840. #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
  3841. #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
  3842. #define CAN_F12R1_FB23_Pos (23U)
  3843. #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
  3844. #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
  3845. #define CAN_F12R1_FB24_Pos (24U)
  3846. #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
  3847. #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
  3848. #define CAN_F12R1_FB25_Pos (25U)
  3849. #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
  3850. #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
  3851. #define CAN_F12R1_FB26_Pos (26U)
  3852. #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
  3853. #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
  3854. #define CAN_F12R1_FB27_Pos (27U)
  3855. #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
  3856. #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
  3857. #define CAN_F12R1_FB28_Pos (28U)
  3858. #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
  3859. #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
  3860. #define CAN_F12R1_FB29_Pos (29U)
  3861. #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
  3862. #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
  3863. #define CAN_F12R1_FB30_Pos (30U)
  3864. #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
  3865. #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
  3866. #define CAN_F12R1_FB31_Pos (31U)
  3867. #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
  3868. #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
  3869. /******************* Bit definition for CAN_F13R1 register ******************/
  3870. #define CAN_F13R1_FB0_Pos (0U)
  3871. #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
  3872. #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
  3873. #define CAN_F13R1_FB1_Pos (1U)
  3874. #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
  3875. #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
  3876. #define CAN_F13R1_FB2_Pos (2U)
  3877. #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
  3878. #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
  3879. #define CAN_F13R1_FB3_Pos (3U)
  3880. #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
  3881. #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
  3882. #define CAN_F13R1_FB4_Pos (4U)
  3883. #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
  3884. #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
  3885. #define CAN_F13R1_FB5_Pos (5U)
  3886. #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
  3887. #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
  3888. #define CAN_F13R1_FB6_Pos (6U)
  3889. #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
  3890. #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
  3891. #define CAN_F13R1_FB7_Pos (7U)
  3892. #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
  3893. #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
  3894. #define CAN_F13R1_FB8_Pos (8U)
  3895. #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
  3896. #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
  3897. #define CAN_F13R1_FB9_Pos (9U)
  3898. #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
  3899. #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
  3900. #define CAN_F13R1_FB10_Pos (10U)
  3901. #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
  3902. #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
  3903. #define CAN_F13R1_FB11_Pos (11U)
  3904. #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
  3905. #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
  3906. #define CAN_F13R1_FB12_Pos (12U)
  3907. #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
  3908. #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
  3909. #define CAN_F13R1_FB13_Pos (13U)
  3910. #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
  3911. #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
  3912. #define CAN_F13R1_FB14_Pos (14U)
  3913. #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
  3914. #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
  3915. #define CAN_F13R1_FB15_Pos (15U)
  3916. #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
  3917. #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
  3918. #define CAN_F13R1_FB16_Pos (16U)
  3919. #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
  3920. #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
  3921. #define CAN_F13R1_FB17_Pos (17U)
  3922. #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
  3923. #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
  3924. #define CAN_F13R1_FB18_Pos (18U)
  3925. #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
  3926. #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
  3927. #define CAN_F13R1_FB19_Pos (19U)
  3928. #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
  3929. #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
  3930. #define CAN_F13R1_FB20_Pos (20U)
  3931. #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
  3932. #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
  3933. #define CAN_F13R1_FB21_Pos (21U)
  3934. #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
  3935. #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
  3936. #define CAN_F13R1_FB22_Pos (22U)
  3937. #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
  3938. #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
  3939. #define CAN_F13R1_FB23_Pos (23U)
  3940. #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
  3941. #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
  3942. #define CAN_F13R1_FB24_Pos (24U)
  3943. #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
  3944. #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
  3945. #define CAN_F13R1_FB25_Pos (25U)
  3946. #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
  3947. #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
  3948. #define CAN_F13R1_FB26_Pos (26U)
  3949. #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
  3950. #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
  3951. #define CAN_F13R1_FB27_Pos (27U)
  3952. #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
  3953. #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
  3954. #define CAN_F13R1_FB28_Pos (28U)
  3955. #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
  3956. #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
  3957. #define CAN_F13R1_FB29_Pos (29U)
  3958. #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
  3959. #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
  3960. #define CAN_F13R1_FB30_Pos (30U)
  3961. #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
  3962. #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
  3963. #define CAN_F13R1_FB31_Pos (31U)
  3964. #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
  3965. #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
  3966. /******************* Bit definition for CAN_F0R2 register *******************/
  3967. #define CAN_F0R2_FB0_Pos (0U)
  3968. #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
  3969. #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
  3970. #define CAN_F0R2_FB1_Pos (1U)
  3971. #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
  3972. #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
  3973. #define CAN_F0R2_FB2_Pos (2U)
  3974. #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
  3975. #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
  3976. #define CAN_F0R2_FB3_Pos (3U)
  3977. #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
  3978. #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
  3979. #define CAN_F0R2_FB4_Pos (4U)
  3980. #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
  3981. #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
  3982. #define CAN_F0R2_FB5_Pos (5U)
  3983. #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
  3984. #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
  3985. #define CAN_F0R2_FB6_Pos (6U)
  3986. #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
  3987. #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
  3988. #define CAN_F0R2_FB7_Pos (7U)
  3989. #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
  3990. #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
  3991. #define CAN_F0R2_FB8_Pos (8U)
  3992. #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
  3993. #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
  3994. #define CAN_F0R2_FB9_Pos (9U)
  3995. #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
  3996. #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
  3997. #define CAN_F0R2_FB10_Pos (10U)
  3998. #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
  3999. #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
  4000. #define CAN_F0R2_FB11_Pos (11U)
  4001. #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
  4002. #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
  4003. #define CAN_F0R2_FB12_Pos (12U)
  4004. #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
  4005. #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
  4006. #define CAN_F0R2_FB13_Pos (13U)
  4007. #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
  4008. #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
  4009. #define CAN_F0R2_FB14_Pos (14U)
  4010. #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
  4011. #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
  4012. #define CAN_F0R2_FB15_Pos (15U)
  4013. #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
  4014. #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
  4015. #define CAN_F0R2_FB16_Pos (16U)
  4016. #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
  4017. #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
  4018. #define CAN_F0R2_FB17_Pos (17U)
  4019. #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
  4020. #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
  4021. #define CAN_F0R2_FB18_Pos (18U)
  4022. #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
  4023. #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
  4024. #define CAN_F0R2_FB19_Pos (19U)
  4025. #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
  4026. #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
  4027. #define CAN_F0R2_FB20_Pos (20U)
  4028. #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
  4029. #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
  4030. #define CAN_F0R2_FB21_Pos (21U)
  4031. #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
  4032. #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
  4033. #define CAN_F0R2_FB22_Pos (22U)
  4034. #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
  4035. #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
  4036. #define CAN_F0R2_FB23_Pos (23U)
  4037. #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
  4038. #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
  4039. #define CAN_F0R2_FB24_Pos (24U)
  4040. #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
  4041. #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
  4042. #define CAN_F0R2_FB25_Pos (25U)
  4043. #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
  4044. #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
  4045. #define CAN_F0R2_FB26_Pos (26U)
  4046. #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
  4047. #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
  4048. #define CAN_F0R2_FB27_Pos (27U)
  4049. #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
  4050. #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
  4051. #define CAN_F0R2_FB28_Pos (28U)
  4052. #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
  4053. #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
  4054. #define CAN_F0R2_FB29_Pos (29U)
  4055. #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
  4056. #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
  4057. #define CAN_F0R2_FB30_Pos (30U)
  4058. #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
  4059. #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
  4060. #define CAN_F0R2_FB31_Pos (31U)
  4061. #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
  4062. #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
  4063. /******************* Bit definition for CAN_F1R2 register *******************/
  4064. #define CAN_F1R2_FB0_Pos (0U)
  4065. #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
  4066. #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
  4067. #define CAN_F1R2_FB1_Pos (1U)
  4068. #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
  4069. #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
  4070. #define CAN_F1R2_FB2_Pos (2U)
  4071. #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
  4072. #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
  4073. #define CAN_F1R2_FB3_Pos (3U)
  4074. #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
  4075. #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
  4076. #define CAN_F1R2_FB4_Pos (4U)
  4077. #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
  4078. #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
  4079. #define CAN_F1R2_FB5_Pos (5U)
  4080. #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
  4081. #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
  4082. #define CAN_F1R2_FB6_Pos (6U)
  4083. #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
  4084. #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
  4085. #define CAN_F1R2_FB7_Pos (7U)
  4086. #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
  4087. #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
  4088. #define CAN_F1R2_FB8_Pos (8U)
  4089. #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
  4090. #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
  4091. #define CAN_F1R2_FB9_Pos (9U)
  4092. #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
  4093. #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
  4094. #define CAN_F1R2_FB10_Pos (10U)
  4095. #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
  4096. #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
  4097. #define CAN_F1R2_FB11_Pos (11U)
  4098. #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
  4099. #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
  4100. #define CAN_F1R2_FB12_Pos (12U)
  4101. #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
  4102. #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
  4103. #define CAN_F1R2_FB13_Pos (13U)
  4104. #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
  4105. #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
  4106. #define CAN_F1R2_FB14_Pos (14U)
  4107. #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
  4108. #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
  4109. #define CAN_F1R2_FB15_Pos (15U)
  4110. #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
  4111. #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
  4112. #define CAN_F1R2_FB16_Pos (16U)
  4113. #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
  4114. #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
  4115. #define CAN_F1R2_FB17_Pos (17U)
  4116. #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
  4117. #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
  4118. #define CAN_F1R2_FB18_Pos (18U)
  4119. #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
  4120. #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
  4121. #define CAN_F1R2_FB19_Pos (19U)
  4122. #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
  4123. #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
  4124. #define CAN_F1R2_FB20_Pos (20U)
  4125. #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
  4126. #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
  4127. #define CAN_F1R2_FB21_Pos (21U)
  4128. #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
  4129. #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
  4130. #define CAN_F1R2_FB22_Pos (22U)
  4131. #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
  4132. #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
  4133. #define CAN_F1R2_FB23_Pos (23U)
  4134. #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
  4135. #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
  4136. #define CAN_F1R2_FB24_Pos (24U)
  4137. #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
  4138. #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
  4139. #define CAN_F1R2_FB25_Pos (25U)
  4140. #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
  4141. #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
  4142. #define CAN_F1R2_FB26_Pos (26U)
  4143. #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
  4144. #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
  4145. #define CAN_F1R2_FB27_Pos (27U)
  4146. #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
  4147. #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
  4148. #define CAN_F1R2_FB28_Pos (28U)
  4149. #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
  4150. #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
  4151. #define CAN_F1R2_FB29_Pos (29U)
  4152. #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
  4153. #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
  4154. #define CAN_F1R2_FB30_Pos (30U)
  4155. #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
  4156. #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
  4157. #define CAN_F1R2_FB31_Pos (31U)
  4158. #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
  4159. #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
  4160. /******************* Bit definition for CAN_F2R2 register *******************/
  4161. #define CAN_F2R2_FB0_Pos (0U)
  4162. #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
  4163. #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
  4164. #define CAN_F2R2_FB1_Pos (1U)
  4165. #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
  4166. #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
  4167. #define CAN_F2R2_FB2_Pos (2U)
  4168. #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
  4169. #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
  4170. #define CAN_F2R2_FB3_Pos (3U)
  4171. #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
  4172. #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
  4173. #define CAN_F2R2_FB4_Pos (4U)
  4174. #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
  4175. #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
  4176. #define CAN_F2R2_FB5_Pos (5U)
  4177. #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
  4178. #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
  4179. #define CAN_F2R2_FB6_Pos (6U)
  4180. #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
  4181. #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
  4182. #define CAN_F2R2_FB7_Pos (7U)
  4183. #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
  4184. #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
  4185. #define CAN_F2R2_FB8_Pos (8U)
  4186. #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
  4187. #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
  4188. #define CAN_F2R2_FB9_Pos (9U)
  4189. #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
  4190. #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
  4191. #define CAN_F2R2_FB10_Pos (10U)
  4192. #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
  4193. #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
  4194. #define CAN_F2R2_FB11_Pos (11U)
  4195. #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
  4196. #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
  4197. #define CAN_F2R2_FB12_Pos (12U)
  4198. #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
  4199. #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
  4200. #define CAN_F2R2_FB13_Pos (13U)
  4201. #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
  4202. #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
  4203. #define CAN_F2R2_FB14_Pos (14U)
  4204. #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
  4205. #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
  4206. #define CAN_F2R2_FB15_Pos (15U)
  4207. #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
  4208. #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
  4209. #define CAN_F2R2_FB16_Pos (16U)
  4210. #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
  4211. #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
  4212. #define CAN_F2R2_FB17_Pos (17U)
  4213. #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
  4214. #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
  4215. #define CAN_F2R2_FB18_Pos (18U)
  4216. #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
  4217. #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
  4218. #define CAN_F2R2_FB19_Pos (19U)
  4219. #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
  4220. #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
  4221. #define CAN_F2R2_FB20_Pos (20U)
  4222. #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
  4223. #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
  4224. #define CAN_F2R2_FB21_Pos (21U)
  4225. #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
  4226. #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
  4227. #define CAN_F2R2_FB22_Pos (22U)
  4228. #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
  4229. #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
  4230. #define CAN_F2R2_FB23_Pos (23U)
  4231. #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
  4232. #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
  4233. #define CAN_F2R2_FB24_Pos (24U)
  4234. #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
  4235. #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
  4236. #define CAN_F2R2_FB25_Pos (25U)
  4237. #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
  4238. #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
  4239. #define CAN_F2R2_FB26_Pos (26U)
  4240. #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
  4241. #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
  4242. #define CAN_F2R2_FB27_Pos (27U)
  4243. #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
  4244. #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
  4245. #define CAN_F2R2_FB28_Pos (28U)
  4246. #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
  4247. #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
  4248. #define CAN_F2R2_FB29_Pos (29U)
  4249. #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
  4250. #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
  4251. #define CAN_F2R2_FB30_Pos (30U)
  4252. #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
  4253. #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
  4254. #define CAN_F2R2_FB31_Pos (31U)
  4255. #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
  4256. #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
  4257. /******************* Bit definition for CAN_F3R2 register *******************/
  4258. #define CAN_F3R2_FB0_Pos (0U)
  4259. #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
  4260. #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
  4261. #define CAN_F3R2_FB1_Pos (1U)
  4262. #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
  4263. #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
  4264. #define CAN_F3R2_FB2_Pos (2U)
  4265. #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
  4266. #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
  4267. #define CAN_F3R2_FB3_Pos (3U)
  4268. #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
  4269. #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
  4270. #define CAN_F3R2_FB4_Pos (4U)
  4271. #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
  4272. #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
  4273. #define CAN_F3R2_FB5_Pos (5U)
  4274. #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
  4275. #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
  4276. #define CAN_F3R2_FB6_Pos (6U)
  4277. #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
  4278. #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
  4279. #define CAN_F3R2_FB7_Pos (7U)
  4280. #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
  4281. #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
  4282. #define CAN_F3R2_FB8_Pos (8U)
  4283. #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
  4284. #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
  4285. #define CAN_F3R2_FB9_Pos (9U)
  4286. #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
  4287. #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
  4288. #define CAN_F3R2_FB10_Pos (10U)
  4289. #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
  4290. #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
  4291. #define CAN_F3R2_FB11_Pos (11U)
  4292. #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
  4293. #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
  4294. #define CAN_F3R2_FB12_Pos (12U)
  4295. #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
  4296. #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
  4297. #define CAN_F3R2_FB13_Pos (13U)
  4298. #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
  4299. #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
  4300. #define CAN_F3R2_FB14_Pos (14U)
  4301. #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
  4302. #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
  4303. #define CAN_F3R2_FB15_Pos (15U)
  4304. #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
  4305. #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
  4306. #define CAN_F3R2_FB16_Pos (16U)
  4307. #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
  4308. #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
  4309. #define CAN_F3R2_FB17_Pos (17U)
  4310. #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
  4311. #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
  4312. #define CAN_F3R2_FB18_Pos (18U)
  4313. #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
  4314. #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
  4315. #define CAN_F3R2_FB19_Pos (19U)
  4316. #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
  4317. #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
  4318. #define CAN_F3R2_FB20_Pos (20U)
  4319. #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
  4320. #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
  4321. #define CAN_F3R2_FB21_Pos (21U)
  4322. #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
  4323. #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
  4324. #define CAN_F3R2_FB22_Pos (22U)
  4325. #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
  4326. #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
  4327. #define CAN_F3R2_FB23_Pos (23U)
  4328. #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
  4329. #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
  4330. #define CAN_F3R2_FB24_Pos (24U)
  4331. #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
  4332. #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
  4333. #define CAN_F3R2_FB25_Pos (25U)
  4334. #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
  4335. #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
  4336. #define CAN_F3R2_FB26_Pos (26U)
  4337. #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
  4338. #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
  4339. #define CAN_F3R2_FB27_Pos (27U)
  4340. #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
  4341. #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
  4342. #define CAN_F3R2_FB28_Pos (28U)
  4343. #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
  4344. #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
  4345. #define CAN_F3R2_FB29_Pos (29U)
  4346. #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
  4347. #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
  4348. #define CAN_F3R2_FB30_Pos (30U)
  4349. #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
  4350. #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
  4351. #define CAN_F3R2_FB31_Pos (31U)
  4352. #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
  4353. #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
  4354. /******************* Bit definition for CAN_F4R2 register *******************/
  4355. #define CAN_F4R2_FB0_Pos (0U)
  4356. #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
  4357. #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
  4358. #define CAN_F4R2_FB1_Pos (1U)
  4359. #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
  4360. #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
  4361. #define CAN_F4R2_FB2_Pos (2U)
  4362. #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
  4363. #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
  4364. #define CAN_F4R2_FB3_Pos (3U)
  4365. #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
  4366. #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
  4367. #define CAN_F4R2_FB4_Pos (4U)
  4368. #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
  4369. #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
  4370. #define CAN_F4R2_FB5_Pos (5U)
  4371. #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
  4372. #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
  4373. #define CAN_F4R2_FB6_Pos (6U)
  4374. #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
  4375. #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
  4376. #define CAN_F4R2_FB7_Pos (7U)
  4377. #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
  4378. #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
  4379. #define CAN_F4R2_FB8_Pos (8U)
  4380. #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
  4381. #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
  4382. #define CAN_F4R2_FB9_Pos (9U)
  4383. #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
  4384. #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
  4385. #define CAN_F4R2_FB10_Pos (10U)
  4386. #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
  4387. #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
  4388. #define CAN_F4R2_FB11_Pos (11U)
  4389. #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
  4390. #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
  4391. #define CAN_F4R2_FB12_Pos (12U)
  4392. #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
  4393. #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
  4394. #define CAN_F4R2_FB13_Pos (13U)
  4395. #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
  4396. #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
  4397. #define CAN_F4R2_FB14_Pos (14U)
  4398. #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
  4399. #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
  4400. #define CAN_F4R2_FB15_Pos (15U)
  4401. #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
  4402. #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
  4403. #define CAN_F4R2_FB16_Pos (16U)
  4404. #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
  4405. #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
  4406. #define CAN_F4R2_FB17_Pos (17U)
  4407. #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
  4408. #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
  4409. #define CAN_F4R2_FB18_Pos (18U)
  4410. #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
  4411. #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
  4412. #define CAN_F4R2_FB19_Pos (19U)
  4413. #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
  4414. #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
  4415. #define CAN_F4R2_FB20_Pos (20U)
  4416. #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
  4417. #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
  4418. #define CAN_F4R2_FB21_Pos (21U)
  4419. #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
  4420. #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
  4421. #define CAN_F4R2_FB22_Pos (22U)
  4422. #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
  4423. #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
  4424. #define CAN_F4R2_FB23_Pos (23U)
  4425. #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
  4426. #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
  4427. #define CAN_F4R2_FB24_Pos (24U)
  4428. #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
  4429. #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
  4430. #define CAN_F4R2_FB25_Pos (25U)
  4431. #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
  4432. #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
  4433. #define CAN_F4R2_FB26_Pos (26U)
  4434. #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
  4435. #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
  4436. #define CAN_F4R2_FB27_Pos (27U)
  4437. #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
  4438. #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
  4439. #define CAN_F4R2_FB28_Pos (28U)
  4440. #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
  4441. #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
  4442. #define CAN_F4R2_FB29_Pos (29U)
  4443. #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
  4444. #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
  4445. #define CAN_F4R2_FB30_Pos (30U)
  4446. #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
  4447. #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
  4448. #define CAN_F4R2_FB31_Pos (31U)
  4449. #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
  4450. #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
  4451. /******************* Bit definition for CAN_F5R2 register *******************/
  4452. #define CAN_F5R2_FB0_Pos (0U)
  4453. #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
  4454. #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
  4455. #define CAN_F5R2_FB1_Pos (1U)
  4456. #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
  4457. #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
  4458. #define CAN_F5R2_FB2_Pos (2U)
  4459. #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
  4460. #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
  4461. #define CAN_F5R2_FB3_Pos (3U)
  4462. #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
  4463. #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
  4464. #define CAN_F5R2_FB4_Pos (4U)
  4465. #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
  4466. #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
  4467. #define CAN_F5R2_FB5_Pos (5U)
  4468. #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
  4469. #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
  4470. #define CAN_F5R2_FB6_Pos (6U)
  4471. #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
  4472. #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
  4473. #define CAN_F5R2_FB7_Pos (7U)
  4474. #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
  4475. #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
  4476. #define CAN_F5R2_FB8_Pos (8U)
  4477. #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
  4478. #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
  4479. #define CAN_F5R2_FB9_Pos (9U)
  4480. #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
  4481. #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
  4482. #define CAN_F5R2_FB10_Pos (10U)
  4483. #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
  4484. #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
  4485. #define CAN_F5R2_FB11_Pos (11U)
  4486. #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
  4487. #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
  4488. #define CAN_F5R2_FB12_Pos (12U)
  4489. #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
  4490. #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
  4491. #define CAN_F5R2_FB13_Pos (13U)
  4492. #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
  4493. #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
  4494. #define CAN_F5R2_FB14_Pos (14U)
  4495. #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
  4496. #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
  4497. #define CAN_F5R2_FB15_Pos (15U)
  4498. #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
  4499. #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
  4500. #define CAN_F5R2_FB16_Pos (16U)
  4501. #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
  4502. #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
  4503. #define CAN_F5R2_FB17_Pos (17U)
  4504. #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
  4505. #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
  4506. #define CAN_F5R2_FB18_Pos (18U)
  4507. #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
  4508. #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
  4509. #define CAN_F5R2_FB19_Pos (19U)
  4510. #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
  4511. #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
  4512. #define CAN_F5R2_FB20_Pos (20U)
  4513. #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
  4514. #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
  4515. #define CAN_F5R2_FB21_Pos (21U)
  4516. #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
  4517. #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
  4518. #define CAN_F5R2_FB22_Pos (22U)
  4519. #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
  4520. #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
  4521. #define CAN_F5R2_FB23_Pos (23U)
  4522. #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
  4523. #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
  4524. #define CAN_F5R2_FB24_Pos (24U)
  4525. #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
  4526. #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
  4527. #define CAN_F5R2_FB25_Pos (25U)
  4528. #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
  4529. #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
  4530. #define CAN_F5R2_FB26_Pos (26U)
  4531. #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
  4532. #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
  4533. #define CAN_F5R2_FB27_Pos (27U)
  4534. #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
  4535. #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
  4536. #define CAN_F5R2_FB28_Pos (28U)
  4537. #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
  4538. #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
  4539. #define CAN_F5R2_FB29_Pos (29U)
  4540. #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
  4541. #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
  4542. #define CAN_F5R2_FB30_Pos (30U)
  4543. #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
  4544. #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
  4545. #define CAN_F5R2_FB31_Pos (31U)
  4546. #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
  4547. #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
  4548. /******************* Bit definition for CAN_F6R2 register *******************/
  4549. #define CAN_F6R2_FB0_Pos (0U)
  4550. #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
  4551. #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
  4552. #define CAN_F6R2_FB1_Pos (1U)
  4553. #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
  4554. #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
  4555. #define CAN_F6R2_FB2_Pos (2U)
  4556. #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
  4557. #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
  4558. #define CAN_F6R2_FB3_Pos (3U)
  4559. #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
  4560. #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
  4561. #define CAN_F6R2_FB4_Pos (4U)
  4562. #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
  4563. #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
  4564. #define CAN_F6R2_FB5_Pos (5U)
  4565. #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
  4566. #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
  4567. #define CAN_F6R2_FB6_Pos (6U)
  4568. #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
  4569. #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
  4570. #define CAN_F6R2_FB7_Pos (7U)
  4571. #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
  4572. #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
  4573. #define CAN_F6R2_FB8_Pos (8U)
  4574. #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
  4575. #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
  4576. #define CAN_F6R2_FB9_Pos (9U)
  4577. #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
  4578. #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
  4579. #define CAN_F6R2_FB10_Pos (10U)
  4580. #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
  4581. #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
  4582. #define CAN_F6R2_FB11_Pos (11U)
  4583. #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
  4584. #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
  4585. #define CAN_F6R2_FB12_Pos (12U)
  4586. #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
  4587. #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
  4588. #define CAN_F6R2_FB13_Pos (13U)
  4589. #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
  4590. #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
  4591. #define CAN_F6R2_FB14_Pos (14U)
  4592. #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
  4593. #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
  4594. #define CAN_F6R2_FB15_Pos (15U)
  4595. #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
  4596. #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
  4597. #define CAN_F6R2_FB16_Pos (16U)
  4598. #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
  4599. #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
  4600. #define CAN_F6R2_FB17_Pos (17U)
  4601. #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
  4602. #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
  4603. #define CAN_F6R2_FB18_Pos (18U)
  4604. #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
  4605. #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
  4606. #define CAN_F6R2_FB19_Pos (19U)
  4607. #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
  4608. #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
  4609. #define CAN_F6R2_FB20_Pos (20U)
  4610. #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
  4611. #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
  4612. #define CAN_F6R2_FB21_Pos (21U)
  4613. #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
  4614. #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
  4615. #define CAN_F6R2_FB22_Pos (22U)
  4616. #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
  4617. #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
  4618. #define CAN_F6R2_FB23_Pos (23U)
  4619. #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
  4620. #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
  4621. #define CAN_F6R2_FB24_Pos (24U)
  4622. #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
  4623. #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
  4624. #define CAN_F6R2_FB25_Pos (25U)
  4625. #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
  4626. #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
  4627. #define CAN_F6R2_FB26_Pos (26U)
  4628. #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
  4629. #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
  4630. #define CAN_F6R2_FB27_Pos (27U)
  4631. #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
  4632. #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
  4633. #define CAN_F6R2_FB28_Pos (28U)
  4634. #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
  4635. #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
  4636. #define CAN_F6R2_FB29_Pos (29U)
  4637. #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
  4638. #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
  4639. #define CAN_F6R2_FB30_Pos (30U)
  4640. #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
  4641. #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
  4642. #define CAN_F6R2_FB31_Pos (31U)
  4643. #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
  4644. #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
  4645. /******************* Bit definition for CAN_F7R2 register *******************/
  4646. #define CAN_F7R2_FB0_Pos (0U)
  4647. #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
  4648. #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
  4649. #define CAN_F7R2_FB1_Pos (1U)
  4650. #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
  4651. #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
  4652. #define CAN_F7R2_FB2_Pos (2U)
  4653. #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
  4654. #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
  4655. #define CAN_F7R2_FB3_Pos (3U)
  4656. #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
  4657. #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
  4658. #define CAN_F7R2_FB4_Pos (4U)
  4659. #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
  4660. #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
  4661. #define CAN_F7R2_FB5_Pos (5U)
  4662. #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
  4663. #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
  4664. #define CAN_F7R2_FB6_Pos (6U)
  4665. #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
  4666. #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
  4667. #define CAN_F7R2_FB7_Pos (7U)
  4668. #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
  4669. #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
  4670. #define CAN_F7R2_FB8_Pos (8U)
  4671. #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
  4672. #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
  4673. #define CAN_F7R2_FB9_Pos (9U)
  4674. #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
  4675. #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
  4676. #define CAN_F7R2_FB10_Pos (10U)
  4677. #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
  4678. #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
  4679. #define CAN_F7R2_FB11_Pos (11U)
  4680. #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
  4681. #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
  4682. #define CAN_F7R2_FB12_Pos (12U)
  4683. #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
  4684. #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
  4685. #define CAN_F7R2_FB13_Pos (13U)
  4686. #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
  4687. #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
  4688. #define CAN_F7R2_FB14_Pos (14U)
  4689. #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
  4690. #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
  4691. #define CAN_F7R2_FB15_Pos (15U)
  4692. #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
  4693. #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
  4694. #define CAN_F7R2_FB16_Pos (16U)
  4695. #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
  4696. #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
  4697. #define CAN_F7R2_FB17_Pos (17U)
  4698. #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
  4699. #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
  4700. #define CAN_F7R2_FB18_Pos (18U)
  4701. #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
  4702. #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
  4703. #define CAN_F7R2_FB19_Pos (19U)
  4704. #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
  4705. #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
  4706. #define CAN_F7R2_FB20_Pos (20U)
  4707. #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
  4708. #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
  4709. #define CAN_F7R2_FB21_Pos (21U)
  4710. #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
  4711. #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
  4712. #define CAN_F7R2_FB22_Pos (22U)
  4713. #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
  4714. #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
  4715. #define CAN_F7R2_FB23_Pos (23U)
  4716. #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
  4717. #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
  4718. #define CAN_F7R2_FB24_Pos (24U)
  4719. #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
  4720. #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
  4721. #define CAN_F7R2_FB25_Pos (25U)
  4722. #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
  4723. #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
  4724. #define CAN_F7R2_FB26_Pos (26U)
  4725. #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
  4726. #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
  4727. #define CAN_F7R2_FB27_Pos (27U)
  4728. #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
  4729. #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
  4730. #define CAN_F7R2_FB28_Pos (28U)
  4731. #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
  4732. #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
  4733. #define CAN_F7R2_FB29_Pos (29U)
  4734. #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
  4735. #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
  4736. #define CAN_F7R2_FB30_Pos (30U)
  4737. #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
  4738. #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
  4739. #define CAN_F7R2_FB31_Pos (31U)
  4740. #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
  4741. #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
  4742. /******************* Bit definition for CAN_F8R2 register *******************/
  4743. #define CAN_F8R2_FB0_Pos (0U)
  4744. #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
  4745. #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
  4746. #define CAN_F8R2_FB1_Pos (1U)
  4747. #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
  4748. #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
  4749. #define CAN_F8R2_FB2_Pos (2U)
  4750. #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
  4751. #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
  4752. #define CAN_F8R2_FB3_Pos (3U)
  4753. #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
  4754. #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
  4755. #define CAN_F8R2_FB4_Pos (4U)
  4756. #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
  4757. #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
  4758. #define CAN_F8R2_FB5_Pos (5U)
  4759. #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
  4760. #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
  4761. #define CAN_F8R2_FB6_Pos (6U)
  4762. #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
  4763. #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
  4764. #define CAN_F8R2_FB7_Pos (7U)
  4765. #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
  4766. #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
  4767. #define CAN_F8R2_FB8_Pos (8U)
  4768. #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
  4769. #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
  4770. #define CAN_F8R2_FB9_Pos (9U)
  4771. #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
  4772. #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
  4773. #define CAN_F8R2_FB10_Pos (10U)
  4774. #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
  4775. #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
  4776. #define CAN_F8R2_FB11_Pos (11U)
  4777. #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
  4778. #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
  4779. #define CAN_F8R2_FB12_Pos (12U)
  4780. #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
  4781. #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
  4782. #define CAN_F8R2_FB13_Pos (13U)
  4783. #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
  4784. #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
  4785. #define CAN_F8R2_FB14_Pos (14U)
  4786. #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
  4787. #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
  4788. #define CAN_F8R2_FB15_Pos (15U)
  4789. #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
  4790. #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
  4791. #define CAN_F8R2_FB16_Pos (16U)
  4792. #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
  4793. #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
  4794. #define CAN_F8R2_FB17_Pos (17U)
  4795. #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
  4796. #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
  4797. #define CAN_F8R2_FB18_Pos (18U)
  4798. #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
  4799. #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
  4800. #define CAN_F8R2_FB19_Pos (19U)
  4801. #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
  4802. #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
  4803. #define CAN_F8R2_FB20_Pos (20U)
  4804. #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
  4805. #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
  4806. #define CAN_F8R2_FB21_Pos (21U)
  4807. #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
  4808. #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
  4809. #define CAN_F8R2_FB22_Pos (22U)
  4810. #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
  4811. #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
  4812. #define CAN_F8R2_FB23_Pos (23U)
  4813. #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
  4814. #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
  4815. #define CAN_F8R2_FB24_Pos (24U)
  4816. #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
  4817. #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
  4818. #define CAN_F8R2_FB25_Pos (25U)
  4819. #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
  4820. #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
  4821. #define CAN_F8R2_FB26_Pos (26U)
  4822. #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
  4823. #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
  4824. #define CAN_F8R2_FB27_Pos (27U)
  4825. #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
  4826. #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
  4827. #define CAN_F8R2_FB28_Pos (28U)
  4828. #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
  4829. #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
  4830. #define CAN_F8R2_FB29_Pos (29U)
  4831. #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
  4832. #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
  4833. #define CAN_F8R2_FB30_Pos (30U)
  4834. #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
  4835. #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
  4836. #define CAN_F8R2_FB31_Pos (31U)
  4837. #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
  4838. #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
  4839. /******************* Bit definition for CAN_F9R2 register *******************/
  4840. #define CAN_F9R2_FB0_Pos (0U)
  4841. #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
  4842. #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
  4843. #define CAN_F9R2_FB1_Pos (1U)
  4844. #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
  4845. #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
  4846. #define CAN_F9R2_FB2_Pos (2U)
  4847. #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
  4848. #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
  4849. #define CAN_F9R2_FB3_Pos (3U)
  4850. #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
  4851. #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
  4852. #define CAN_F9R2_FB4_Pos (4U)
  4853. #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
  4854. #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
  4855. #define CAN_F9R2_FB5_Pos (5U)
  4856. #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
  4857. #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
  4858. #define CAN_F9R2_FB6_Pos (6U)
  4859. #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
  4860. #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
  4861. #define CAN_F9R2_FB7_Pos (7U)
  4862. #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
  4863. #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
  4864. #define CAN_F9R2_FB8_Pos (8U)
  4865. #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
  4866. #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
  4867. #define CAN_F9R2_FB9_Pos (9U)
  4868. #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
  4869. #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
  4870. #define CAN_F9R2_FB10_Pos (10U)
  4871. #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
  4872. #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
  4873. #define CAN_F9R2_FB11_Pos (11U)
  4874. #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
  4875. #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
  4876. #define CAN_F9R2_FB12_Pos (12U)
  4877. #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
  4878. #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
  4879. #define CAN_F9R2_FB13_Pos (13U)
  4880. #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
  4881. #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
  4882. #define CAN_F9R2_FB14_Pos (14U)
  4883. #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
  4884. #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
  4885. #define CAN_F9R2_FB15_Pos (15U)
  4886. #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
  4887. #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
  4888. #define CAN_F9R2_FB16_Pos (16U)
  4889. #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
  4890. #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
  4891. #define CAN_F9R2_FB17_Pos (17U)
  4892. #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
  4893. #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
  4894. #define CAN_F9R2_FB18_Pos (18U)
  4895. #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
  4896. #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
  4897. #define CAN_F9R2_FB19_Pos (19U)
  4898. #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
  4899. #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
  4900. #define CAN_F9R2_FB20_Pos (20U)
  4901. #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
  4902. #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
  4903. #define CAN_F9R2_FB21_Pos (21U)
  4904. #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
  4905. #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
  4906. #define CAN_F9R2_FB22_Pos (22U)
  4907. #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
  4908. #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
  4909. #define CAN_F9R2_FB23_Pos (23U)
  4910. #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
  4911. #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
  4912. #define CAN_F9R2_FB24_Pos (24U)
  4913. #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
  4914. #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
  4915. #define CAN_F9R2_FB25_Pos (25U)
  4916. #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
  4917. #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
  4918. #define CAN_F9R2_FB26_Pos (26U)
  4919. #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
  4920. #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
  4921. #define CAN_F9R2_FB27_Pos (27U)
  4922. #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
  4923. #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
  4924. #define CAN_F9R2_FB28_Pos (28U)
  4925. #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
  4926. #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
  4927. #define CAN_F9R2_FB29_Pos (29U)
  4928. #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
  4929. #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
  4930. #define CAN_F9R2_FB30_Pos (30U)
  4931. #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
  4932. #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
  4933. #define CAN_F9R2_FB31_Pos (31U)
  4934. #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
  4935. #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
  4936. /******************* Bit definition for CAN_F10R2 register ******************/
  4937. #define CAN_F10R2_FB0_Pos (0U)
  4938. #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
  4939. #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
  4940. #define CAN_F10R2_FB1_Pos (1U)
  4941. #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
  4942. #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
  4943. #define CAN_F10R2_FB2_Pos (2U)
  4944. #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
  4945. #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
  4946. #define CAN_F10R2_FB3_Pos (3U)
  4947. #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
  4948. #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
  4949. #define CAN_F10R2_FB4_Pos (4U)
  4950. #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
  4951. #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
  4952. #define CAN_F10R2_FB5_Pos (5U)
  4953. #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
  4954. #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
  4955. #define CAN_F10R2_FB6_Pos (6U)
  4956. #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
  4957. #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
  4958. #define CAN_F10R2_FB7_Pos (7U)
  4959. #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
  4960. #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
  4961. #define CAN_F10R2_FB8_Pos (8U)
  4962. #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
  4963. #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
  4964. #define CAN_F10R2_FB9_Pos (9U)
  4965. #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
  4966. #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
  4967. #define CAN_F10R2_FB10_Pos (10U)
  4968. #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
  4969. #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
  4970. #define CAN_F10R2_FB11_Pos (11U)
  4971. #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
  4972. #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
  4973. #define CAN_F10R2_FB12_Pos (12U)
  4974. #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
  4975. #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
  4976. #define CAN_F10R2_FB13_Pos (13U)
  4977. #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
  4978. #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
  4979. #define CAN_F10R2_FB14_Pos (14U)
  4980. #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
  4981. #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
  4982. #define CAN_F10R2_FB15_Pos (15U)
  4983. #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
  4984. #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
  4985. #define CAN_F10R2_FB16_Pos (16U)
  4986. #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
  4987. #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
  4988. #define CAN_F10R2_FB17_Pos (17U)
  4989. #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
  4990. #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
  4991. #define CAN_F10R2_FB18_Pos (18U)
  4992. #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
  4993. #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
  4994. #define CAN_F10R2_FB19_Pos (19U)
  4995. #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
  4996. #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
  4997. #define CAN_F10R2_FB20_Pos (20U)
  4998. #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
  4999. #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
  5000. #define CAN_F10R2_FB21_Pos (21U)
  5001. #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
  5002. #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
  5003. #define CAN_F10R2_FB22_Pos (22U)
  5004. #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
  5005. #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
  5006. #define CAN_F10R2_FB23_Pos (23U)
  5007. #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
  5008. #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
  5009. #define CAN_F10R2_FB24_Pos (24U)
  5010. #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
  5011. #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
  5012. #define CAN_F10R2_FB25_Pos (25U)
  5013. #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
  5014. #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
  5015. #define CAN_F10R2_FB26_Pos (26U)
  5016. #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
  5017. #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
  5018. #define CAN_F10R2_FB27_Pos (27U)
  5019. #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
  5020. #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
  5021. #define CAN_F10R2_FB28_Pos (28U)
  5022. #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
  5023. #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
  5024. #define CAN_F10R2_FB29_Pos (29U)
  5025. #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
  5026. #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
  5027. #define CAN_F10R2_FB30_Pos (30U)
  5028. #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
  5029. #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
  5030. #define CAN_F10R2_FB31_Pos (31U)
  5031. #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
  5032. #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
  5033. /******************* Bit definition for CAN_F11R2 register ******************/
  5034. #define CAN_F11R2_FB0_Pos (0U)
  5035. #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
  5036. #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
  5037. #define CAN_F11R2_FB1_Pos (1U)
  5038. #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
  5039. #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
  5040. #define CAN_F11R2_FB2_Pos (2U)
  5041. #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
  5042. #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
  5043. #define CAN_F11R2_FB3_Pos (3U)
  5044. #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
  5045. #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
  5046. #define CAN_F11R2_FB4_Pos (4U)
  5047. #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
  5048. #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
  5049. #define CAN_F11R2_FB5_Pos (5U)
  5050. #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
  5051. #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
  5052. #define CAN_F11R2_FB6_Pos (6U)
  5053. #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
  5054. #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
  5055. #define CAN_F11R2_FB7_Pos (7U)
  5056. #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
  5057. #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
  5058. #define CAN_F11R2_FB8_Pos (8U)
  5059. #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
  5060. #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
  5061. #define CAN_F11R2_FB9_Pos (9U)
  5062. #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
  5063. #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
  5064. #define CAN_F11R2_FB10_Pos (10U)
  5065. #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
  5066. #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
  5067. #define CAN_F11R2_FB11_Pos (11U)
  5068. #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
  5069. #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
  5070. #define CAN_F11R2_FB12_Pos (12U)
  5071. #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
  5072. #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
  5073. #define CAN_F11R2_FB13_Pos (13U)
  5074. #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
  5075. #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
  5076. #define CAN_F11R2_FB14_Pos (14U)
  5077. #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
  5078. #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
  5079. #define CAN_F11R2_FB15_Pos (15U)
  5080. #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
  5081. #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
  5082. #define CAN_F11R2_FB16_Pos (16U)
  5083. #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
  5084. #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
  5085. #define CAN_F11R2_FB17_Pos (17U)
  5086. #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
  5087. #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
  5088. #define CAN_F11R2_FB18_Pos (18U)
  5089. #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
  5090. #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
  5091. #define CAN_F11R2_FB19_Pos (19U)
  5092. #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
  5093. #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
  5094. #define CAN_F11R2_FB20_Pos (20U)
  5095. #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
  5096. #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
  5097. #define CAN_F11R2_FB21_Pos (21U)
  5098. #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
  5099. #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
  5100. #define CAN_F11R2_FB22_Pos (22U)
  5101. #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
  5102. #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
  5103. #define CAN_F11R2_FB23_Pos (23U)
  5104. #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
  5105. #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
  5106. #define CAN_F11R2_FB24_Pos (24U)
  5107. #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
  5108. #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
  5109. #define CAN_F11R2_FB25_Pos (25U)
  5110. #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
  5111. #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
  5112. #define CAN_F11R2_FB26_Pos (26U)
  5113. #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
  5114. #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
  5115. #define CAN_F11R2_FB27_Pos (27U)
  5116. #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
  5117. #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
  5118. #define CAN_F11R2_FB28_Pos (28U)
  5119. #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
  5120. #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
  5121. #define CAN_F11R2_FB29_Pos (29U)
  5122. #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
  5123. #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
  5124. #define CAN_F11R2_FB30_Pos (30U)
  5125. #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
  5126. #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
  5127. #define CAN_F11R2_FB31_Pos (31U)
  5128. #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
  5129. #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
  5130. /******************* Bit definition for CAN_F12R2 register ******************/
  5131. #define CAN_F12R2_FB0_Pos (0U)
  5132. #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
  5133. #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
  5134. #define CAN_F12R2_FB1_Pos (1U)
  5135. #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
  5136. #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
  5137. #define CAN_F12R2_FB2_Pos (2U)
  5138. #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
  5139. #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
  5140. #define CAN_F12R2_FB3_Pos (3U)
  5141. #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
  5142. #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
  5143. #define CAN_F12R2_FB4_Pos (4U)
  5144. #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
  5145. #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
  5146. #define CAN_F12R2_FB5_Pos (5U)
  5147. #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
  5148. #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
  5149. #define CAN_F12R2_FB6_Pos (6U)
  5150. #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
  5151. #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
  5152. #define CAN_F12R2_FB7_Pos (7U)
  5153. #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
  5154. #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
  5155. #define CAN_F12R2_FB8_Pos (8U)
  5156. #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
  5157. #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
  5158. #define CAN_F12R2_FB9_Pos (9U)
  5159. #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
  5160. #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
  5161. #define CAN_F12R2_FB10_Pos (10U)
  5162. #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
  5163. #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
  5164. #define CAN_F12R2_FB11_Pos (11U)
  5165. #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
  5166. #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
  5167. #define CAN_F12R2_FB12_Pos (12U)
  5168. #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
  5169. #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
  5170. #define CAN_F12R2_FB13_Pos (13U)
  5171. #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
  5172. #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
  5173. #define CAN_F12R2_FB14_Pos (14U)
  5174. #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
  5175. #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
  5176. #define CAN_F12R2_FB15_Pos (15U)
  5177. #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
  5178. #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
  5179. #define CAN_F12R2_FB16_Pos (16U)
  5180. #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
  5181. #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
  5182. #define CAN_F12R2_FB17_Pos (17U)
  5183. #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
  5184. #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
  5185. #define CAN_F12R2_FB18_Pos (18U)
  5186. #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
  5187. #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
  5188. #define CAN_F12R2_FB19_Pos (19U)
  5189. #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
  5190. #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
  5191. #define CAN_F12R2_FB20_Pos (20U)
  5192. #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
  5193. #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
  5194. #define CAN_F12R2_FB21_Pos (21U)
  5195. #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
  5196. #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
  5197. #define CAN_F12R2_FB22_Pos (22U)
  5198. #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
  5199. #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
  5200. #define CAN_F12R2_FB23_Pos (23U)
  5201. #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
  5202. #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
  5203. #define CAN_F12R2_FB24_Pos (24U)
  5204. #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
  5205. #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
  5206. #define CAN_F12R2_FB25_Pos (25U)
  5207. #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
  5208. #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
  5209. #define CAN_F12R2_FB26_Pos (26U)
  5210. #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
  5211. #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
  5212. #define CAN_F12R2_FB27_Pos (27U)
  5213. #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
  5214. #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
  5215. #define CAN_F12R2_FB28_Pos (28U)
  5216. #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
  5217. #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
  5218. #define CAN_F12R2_FB29_Pos (29U)
  5219. #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
  5220. #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
  5221. #define CAN_F12R2_FB30_Pos (30U)
  5222. #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
  5223. #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
  5224. #define CAN_F12R2_FB31_Pos (31U)
  5225. #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
  5226. #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
  5227. /******************* Bit definition for CAN_F13R2 register ******************/
  5228. #define CAN_F13R2_FB0_Pos (0U)
  5229. #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
  5230. #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
  5231. #define CAN_F13R2_FB1_Pos (1U)
  5232. #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
  5233. #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
  5234. #define CAN_F13R2_FB2_Pos (2U)
  5235. #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
  5236. #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
  5237. #define CAN_F13R2_FB3_Pos (3U)
  5238. #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
  5239. #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
  5240. #define CAN_F13R2_FB4_Pos (4U)
  5241. #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
  5242. #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
  5243. #define CAN_F13R2_FB5_Pos (5U)
  5244. #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
  5245. #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
  5246. #define CAN_F13R2_FB6_Pos (6U)
  5247. #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
  5248. #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
  5249. #define CAN_F13R2_FB7_Pos (7U)
  5250. #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
  5251. #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
  5252. #define CAN_F13R2_FB8_Pos (8U)
  5253. #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
  5254. #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
  5255. #define CAN_F13R2_FB9_Pos (9U)
  5256. #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
  5257. #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
  5258. #define CAN_F13R2_FB10_Pos (10U)
  5259. #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
  5260. #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
  5261. #define CAN_F13R2_FB11_Pos (11U)
  5262. #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
  5263. #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
  5264. #define CAN_F13R2_FB12_Pos (12U)
  5265. #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
  5266. #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
  5267. #define CAN_F13R2_FB13_Pos (13U)
  5268. #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
  5269. #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
  5270. #define CAN_F13R2_FB14_Pos (14U)
  5271. #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
  5272. #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
  5273. #define CAN_F13R2_FB15_Pos (15U)
  5274. #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
  5275. #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
  5276. #define CAN_F13R2_FB16_Pos (16U)
  5277. #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
  5278. #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
  5279. #define CAN_F13R2_FB17_Pos (17U)
  5280. #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
  5281. #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
  5282. #define CAN_F13R2_FB18_Pos (18U)
  5283. #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
  5284. #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
  5285. #define CAN_F13R2_FB19_Pos (19U)
  5286. #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
  5287. #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
  5288. #define CAN_F13R2_FB20_Pos (20U)
  5289. #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
  5290. #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
  5291. #define CAN_F13R2_FB21_Pos (21U)
  5292. #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
  5293. #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
  5294. #define CAN_F13R2_FB22_Pos (22U)
  5295. #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
  5296. #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
  5297. #define CAN_F13R2_FB23_Pos (23U)
  5298. #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
  5299. #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
  5300. #define CAN_F13R2_FB24_Pos (24U)
  5301. #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
  5302. #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
  5303. #define CAN_F13R2_FB25_Pos (25U)
  5304. #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
  5305. #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
  5306. #define CAN_F13R2_FB26_Pos (26U)
  5307. #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
  5308. #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
  5309. #define CAN_F13R2_FB27_Pos (27U)
  5310. #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
  5311. #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
  5312. #define CAN_F13R2_FB28_Pos (28U)
  5313. #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
  5314. #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
  5315. #define CAN_F13R2_FB29_Pos (29U)
  5316. #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
  5317. #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
  5318. #define CAN_F13R2_FB30_Pos (30U)
  5319. #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
  5320. #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
  5321. #define CAN_F13R2_FB31_Pos (31U)
  5322. #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
  5323. #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
  5324. /******************************************************************************/
  5325. /* */
  5326. /* CRC calculation unit */
  5327. /* */
  5328. /******************************************************************************/
  5329. /******************* Bit definition for CRC_DR register *********************/
  5330. #define CRC_DR_DR_Pos (0U)
  5331. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  5332. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  5333. /******************* Bit definition for CRC_IDR register ********************/
  5334. #define CRC_IDR_IDR_Pos (0U)
  5335. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  5336. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  5337. /******************** Bit definition for CRC_CR register ********************/
  5338. #define CRC_CR_RESET_Pos (0U)
  5339. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  5340. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  5341. /******************************************************************************/
  5342. /* */
  5343. /* Digital to Analog Converter */
  5344. /* */
  5345. /******************************************************************************/
  5346. /*
  5347. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  5348. */
  5349. #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
  5350. /******************** Bit definition for DAC_CR register ********************/
  5351. #define DAC_CR_EN1_Pos (0U)
  5352. #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
  5353. #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
  5354. #define DAC_CR_BOFF1_Pos (1U)
  5355. #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
  5356. #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
  5357. #define DAC_CR_TEN1_Pos (2U)
  5358. #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
  5359. #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
  5360. #define DAC_CR_TSEL1_Pos (3U)
  5361. #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
  5362. #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
  5363. #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
  5364. #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
  5365. #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
  5366. #define DAC_CR_WAVE1_Pos (6U)
  5367. #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
  5368. #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  5369. #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
  5370. #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
  5371. #define DAC_CR_MAMP1_Pos (8U)
  5372. #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
  5373. #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  5374. #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
  5375. #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
  5376. #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
  5377. #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
  5378. #define DAC_CR_DMAEN1_Pos (12U)
  5379. #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
  5380. #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
  5381. #define DAC_CR_DMAUDRIE1_Pos (13U)
  5382. #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
  5383. #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
  5384. #define DAC_CR_EN2_Pos (16U)
  5385. #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
  5386. #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
  5387. #define DAC_CR_BOFF2_Pos (17U)
  5388. #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
  5389. #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
  5390. #define DAC_CR_TEN2_Pos (18U)
  5391. #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
  5392. #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
  5393. #define DAC_CR_TSEL2_Pos (19U)
  5394. #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
  5395. #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
  5396. #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
  5397. #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
  5398. #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
  5399. #define DAC_CR_WAVE2_Pos (22U)
  5400. #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
  5401. #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  5402. #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
  5403. #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
  5404. #define DAC_CR_MAMP2_Pos (24U)
  5405. #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
  5406. #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  5407. #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
  5408. #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
  5409. #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
  5410. #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
  5411. #define DAC_CR_DMAEN2_Pos (28U)
  5412. #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
  5413. #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
  5414. #define DAC_CR_DMAUDRIE2_Pos (29U)
  5415. #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
  5416. #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
  5417. /***************** Bit definition for DAC_SWTRIGR register ******************/
  5418. #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
  5419. #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
  5420. #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
  5421. #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
  5422. #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
  5423. #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
  5424. /***************** Bit definition for DAC_DHR12R1 register ******************/
  5425. #define DAC_DHR12R1_DACC1DHR_Pos (0U)
  5426. #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
  5427. #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5428. /***************** Bit definition for DAC_DHR12L1 register ******************/
  5429. #define DAC_DHR12L1_DACC1DHR_Pos (4U)
  5430. #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5431. #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5432. /****************** Bit definition for DAC_DHR8R1 register ******************/
  5433. #define DAC_DHR8R1_DACC1DHR_Pos (0U)
  5434. #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
  5435. #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5436. /***************** Bit definition for DAC_DHR12R2 register ******************/
  5437. #define DAC_DHR12R2_DACC2DHR_Pos (0U)
  5438. #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
  5439. #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5440. /***************** Bit definition for DAC_DHR12L2 register ******************/
  5441. #define DAC_DHR12L2_DACC2DHR_Pos (4U)
  5442. #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
  5443. #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5444. /****************** Bit definition for DAC_DHR8R2 register ******************/
  5445. #define DAC_DHR8R2_DACC2DHR_Pos (0U)
  5446. #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
  5447. #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5448. /***************** Bit definition for DAC_DHR12RD register ******************/
  5449. #define DAC_DHR12RD_DACC1DHR_Pos (0U)
  5450. #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
  5451. #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  5452. #define DAC_DHR12RD_DACC2DHR_Pos (16U)
  5453. #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
  5454. #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  5455. /***************** Bit definition for DAC_DHR12LD register ******************/
  5456. #define DAC_DHR12LD_DACC1DHR_Pos (4U)
  5457. #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  5458. #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  5459. #define DAC_DHR12LD_DACC2DHR_Pos (20U)
  5460. #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
  5461. #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  5462. /****************** Bit definition for DAC_DHR8RD register ******************/
  5463. #define DAC_DHR8RD_DACC1DHR_Pos (0U)
  5464. #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
  5465. #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  5466. #define DAC_DHR8RD_DACC2DHR_Pos (8U)
  5467. #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
  5468. #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  5469. /******************* Bit definition for DAC_DOR1 register *******************/
  5470. #define DAC_DOR1_DACC1DOR_Pos (0U)
  5471. #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
  5472. #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
  5473. /******************* Bit definition for DAC_DOR2 register *******************/
  5474. #define DAC_DOR2_DACC2DOR_Pos (0U)
  5475. #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
  5476. #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
  5477. /******************** Bit definition for DAC_SR register ********************/
  5478. #define DAC_SR_DMAUDR1_Pos (13U)
  5479. #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
  5480. #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
  5481. #define DAC_SR_DMAUDR2_Pos (29U)
  5482. #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
  5483. #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
  5484. /******************************************************************************/
  5485. /* */
  5486. /* DCMI */
  5487. /* */
  5488. /******************************************************************************/
  5489. /******************** Bits definition for DCMI_CR register ******************/
  5490. #define DCMI_CR_CAPTURE_Pos (0U)
  5491. #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
  5492. #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
  5493. #define DCMI_CR_CM_Pos (1U)
  5494. #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
  5495. #define DCMI_CR_CM DCMI_CR_CM_Msk
  5496. #define DCMI_CR_CROP_Pos (2U)
  5497. #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
  5498. #define DCMI_CR_CROP DCMI_CR_CROP_Msk
  5499. #define DCMI_CR_JPEG_Pos (3U)
  5500. #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
  5501. #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
  5502. #define DCMI_CR_ESS_Pos (4U)
  5503. #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
  5504. #define DCMI_CR_ESS DCMI_CR_ESS_Msk
  5505. #define DCMI_CR_PCKPOL_Pos (5U)
  5506. #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
  5507. #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
  5508. #define DCMI_CR_HSPOL_Pos (6U)
  5509. #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
  5510. #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
  5511. #define DCMI_CR_VSPOL_Pos (7U)
  5512. #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
  5513. #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
  5514. #define DCMI_CR_FCRC_0 0x00000100U
  5515. #define DCMI_CR_FCRC_1 0x00000200U
  5516. #define DCMI_CR_EDM_0 0x00000400U
  5517. #define DCMI_CR_EDM_1 0x00000800U
  5518. #define DCMI_CR_ENABLE_Pos (14U)
  5519. #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
  5520. #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
  5521. /******************** Bits definition for DCMI_SR register ******************/
  5522. #define DCMI_SR_HSYNC_Pos (0U)
  5523. #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
  5524. #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
  5525. #define DCMI_SR_VSYNC_Pos (1U)
  5526. #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
  5527. #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
  5528. #define DCMI_SR_FNE_Pos (2U)
  5529. #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
  5530. #define DCMI_SR_FNE DCMI_SR_FNE_Msk
  5531. /******************** Bits definition for DCMI_RIS register *****************/
  5532. #define DCMI_RIS_FRAME_RIS_Pos (0U)
  5533. #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
  5534. #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
  5535. #define DCMI_RIS_OVR_RIS_Pos (1U)
  5536. #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
  5537. #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
  5538. #define DCMI_RIS_ERR_RIS_Pos (2U)
  5539. #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
  5540. #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
  5541. #define DCMI_RIS_VSYNC_RIS_Pos (3U)
  5542. #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
  5543. #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
  5544. #define DCMI_RIS_LINE_RIS_Pos (4U)
  5545. #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
  5546. #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
  5547. /* Legacy defines */
  5548. #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
  5549. #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
  5550. #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
  5551. #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
  5552. #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
  5553. #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
  5554. /******************** Bits definition for DCMI_IER register *****************/
  5555. #define DCMI_IER_FRAME_IE_Pos (0U)
  5556. #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
  5557. #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
  5558. #define DCMI_IER_OVR_IE_Pos (1U)
  5559. #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
  5560. #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
  5561. #define DCMI_IER_ERR_IE_Pos (2U)
  5562. #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
  5563. #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
  5564. #define DCMI_IER_VSYNC_IE_Pos (3U)
  5565. #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
  5566. #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
  5567. #define DCMI_IER_LINE_IE_Pos (4U)
  5568. #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
  5569. #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
  5570. /* Legacy defines */
  5571. #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
  5572. /******************** Bits definition for DCMI_MIS register *****************/
  5573. #define DCMI_MIS_FRAME_MIS_Pos (0U)
  5574. #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
  5575. #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
  5576. #define DCMI_MIS_OVR_MIS_Pos (1U)
  5577. #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
  5578. #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
  5579. #define DCMI_MIS_ERR_MIS_Pos (2U)
  5580. #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
  5581. #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
  5582. #define DCMI_MIS_VSYNC_MIS_Pos (3U)
  5583. #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
  5584. #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
  5585. #define DCMI_MIS_LINE_MIS_Pos (4U)
  5586. #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
  5587. #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
  5588. /* Legacy defines */
  5589. #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
  5590. #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
  5591. #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
  5592. #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
  5593. #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
  5594. /******************** Bits definition for DCMI_ICR register *****************/
  5595. #define DCMI_ICR_FRAME_ISC_Pos (0U)
  5596. #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
  5597. #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
  5598. #define DCMI_ICR_OVR_ISC_Pos (1U)
  5599. #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
  5600. #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
  5601. #define DCMI_ICR_ERR_ISC_Pos (2U)
  5602. #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
  5603. #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
  5604. #define DCMI_ICR_VSYNC_ISC_Pos (3U)
  5605. #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
  5606. #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
  5607. #define DCMI_ICR_LINE_ISC_Pos (4U)
  5608. #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
  5609. #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
  5610. /* Legacy defines */
  5611. #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
  5612. /******************** Bits definition for DCMI_ESCR register ******************/
  5613. #define DCMI_ESCR_FSC_Pos (0U)
  5614. #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
  5615. #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
  5616. #define DCMI_ESCR_LSC_Pos (8U)
  5617. #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
  5618. #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
  5619. #define DCMI_ESCR_LEC_Pos (16U)
  5620. #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
  5621. #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
  5622. #define DCMI_ESCR_FEC_Pos (24U)
  5623. #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
  5624. #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
  5625. /******************** Bits definition for DCMI_ESUR register ******************/
  5626. #define DCMI_ESUR_FSU_Pos (0U)
  5627. #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
  5628. #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
  5629. #define DCMI_ESUR_LSU_Pos (8U)
  5630. #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
  5631. #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
  5632. #define DCMI_ESUR_LEU_Pos (16U)
  5633. #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
  5634. #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
  5635. #define DCMI_ESUR_FEU_Pos (24U)
  5636. #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
  5637. #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
  5638. /******************** Bits definition for DCMI_CWSTRT register ******************/
  5639. #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
  5640. #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
  5641. #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
  5642. #define DCMI_CWSTRT_VST_Pos (16U)
  5643. #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
  5644. #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
  5645. /******************** Bits definition for DCMI_CWSIZE register ******************/
  5646. #define DCMI_CWSIZE_CAPCNT_Pos (0U)
  5647. #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
  5648. #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
  5649. #define DCMI_CWSIZE_VLINE_Pos (16U)
  5650. #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
  5651. #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
  5652. /******************** Bits definition for DCMI_DR register *********************/
  5653. #define DCMI_DR_BYTE0_Pos (0U)
  5654. #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
  5655. #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
  5656. #define DCMI_DR_BYTE1_Pos (8U)
  5657. #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
  5658. #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
  5659. #define DCMI_DR_BYTE2_Pos (16U)
  5660. #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
  5661. #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
  5662. #define DCMI_DR_BYTE3_Pos (24U)
  5663. #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
  5664. #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
  5665. /******************************************************************************/
  5666. /* */
  5667. /* DMA Controller */
  5668. /* */
  5669. /******************************************************************************/
  5670. /******************** Bits definition for DMA_SxCR register *****************/
  5671. #define DMA_SxCR_CHSEL_Pos (25U)
  5672. #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
  5673. #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
  5674. #define DMA_SxCR_CHSEL_0 0x02000000U
  5675. #define DMA_SxCR_CHSEL_1 0x04000000U
  5676. #define DMA_SxCR_CHSEL_2 0x08000000U
  5677. #define DMA_SxCR_MBURST_Pos (23U)
  5678. #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
  5679. #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
  5680. #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
  5681. #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
  5682. #define DMA_SxCR_PBURST_Pos (21U)
  5683. #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
  5684. #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
  5685. #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
  5686. #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
  5687. #define DMA_SxCR_CT_Pos (19U)
  5688. #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
  5689. #define DMA_SxCR_CT DMA_SxCR_CT_Msk
  5690. #define DMA_SxCR_DBM_Pos (18U)
  5691. #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
  5692. #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
  5693. #define DMA_SxCR_PL_Pos (16U)
  5694. #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
  5695. #define DMA_SxCR_PL DMA_SxCR_PL_Msk
  5696. #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
  5697. #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
  5698. #define DMA_SxCR_PINCOS_Pos (15U)
  5699. #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
  5700. #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
  5701. #define DMA_SxCR_MSIZE_Pos (13U)
  5702. #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
  5703. #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
  5704. #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
  5705. #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
  5706. #define DMA_SxCR_PSIZE_Pos (11U)
  5707. #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
  5708. #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
  5709. #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
  5710. #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
  5711. #define DMA_SxCR_MINC_Pos (10U)
  5712. #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
  5713. #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
  5714. #define DMA_SxCR_PINC_Pos (9U)
  5715. #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
  5716. #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
  5717. #define DMA_SxCR_CIRC_Pos (8U)
  5718. #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
  5719. #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
  5720. #define DMA_SxCR_DIR_Pos (6U)
  5721. #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
  5722. #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
  5723. #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
  5724. #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
  5725. #define DMA_SxCR_PFCTRL_Pos (5U)
  5726. #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
  5727. #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
  5728. #define DMA_SxCR_TCIE_Pos (4U)
  5729. #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
  5730. #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
  5731. #define DMA_SxCR_HTIE_Pos (3U)
  5732. #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
  5733. #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
  5734. #define DMA_SxCR_TEIE_Pos (2U)
  5735. #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
  5736. #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
  5737. #define DMA_SxCR_DMEIE_Pos (1U)
  5738. #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
  5739. #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
  5740. #define DMA_SxCR_EN_Pos (0U)
  5741. #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
  5742. #define DMA_SxCR_EN DMA_SxCR_EN_Msk
  5743. /* Legacy defines */
  5744. #define DMA_SxCR_ACK_Pos (20U)
  5745. #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
  5746. #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
  5747. /******************** Bits definition for DMA_SxCNDTR register **************/
  5748. #define DMA_SxNDT_Pos (0U)
  5749. #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
  5750. #define DMA_SxNDT DMA_SxNDT_Msk
  5751. #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
  5752. #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
  5753. #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
  5754. #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
  5755. #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
  5756. #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
  5757. #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
  5758. #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
  5759. #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
  5760. #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
  5761. #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
  5762. #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
  5763. #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
  5764. #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
  5765. #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
  5766. #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
  5767. /******************** Bits definition for DMA_SxFCR register ****************/
  5768. #define DMA_SxFCR_FEIE_Pos (7U)
  5769. #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
  5770. #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
  5771. #define DMA_SxFCR_FS_Pos (3U)
  5772. #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
  5773. #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
  5774. #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
  5775. #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
  5776. #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
  5777. #define DMA_SxFCR_DMDIS_Pos (2U)
  5778. #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
  5779. #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
  5780. #define DMA_SxFCR_FTH_Pos (0U)
  5781. #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
  5782. #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
  5783. #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
  5784. #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
  5785. /******************** Bits definition for DMA_LISR register *****************/
  5786. #define DMA_LISR_TCIF3_Pos (27U)
  5787. #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
  5788. #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
  5789. #define DMA_LISR_HTIF3_Pos (26U)
  5790. #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
  5791. #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
  5792. #define DMA_LISR_TEIF3_Pos (25U)
  5793. #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
  5794. #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
  5795. #define DMA_LISR_DMEIF3_Pos (24U)
  5796. #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
  5797. #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
  5798. #define DMA_LISR_FEIF3_Pos (22U)
  5799. #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
  5800. #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
  5801. #define DMA_LISR_TCIF2_Pos (21U)
  5802. #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
  5803. #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
  5804. #define DMA_LISR_HTIF2_Pos (20U)
  5805. #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
  5806. #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
  5807. #define DMA_LISR_TEIF2_Pos (19U)
  5808. #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
  5809. #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
  5810. #define DMA_LISR_DMEIF2_Pos (18U)
  5811. #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
  5812. #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
  5813. #define DMA_LISR_FEIF2_Pos (16U)
  5814. #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
  5815. #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
  5816. #define DMA_LISR_TCIF1_Pos (11U)
  5817. #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
  5818. #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
  5819. #define DMA_LISR_HTIF1_Pos (10U)
  5820. #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
  5821. #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
  5822. #define DMA_LISR_TEIF1_Pos (9U)
  5823. #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
  5824. #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
  5825. #define DMA_LISR_DMEIF1_Pos (8U)
  5826. #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
  5827. #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
  5828. #define DMA_LISR_FEIF1_Pos (6U)
  5829. #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
  5830. #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
  5831. #define DMA_LISR_TCIF0_Pos (5U)
  5832. #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
  5833. #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
  5834. #define DMA_LISR_HTIF0_Pos (4U)
  5835. #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
  5836. #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
  5837. #define DMA_LISR_TEIF0_Pos (3U)
  5838. #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
  5839. #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
  5840. #define DMA_LISR_DMEIF0_Pos (2U)
  5841. #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
  5842. #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
  5843. #define DMA_LISR_FEIF0_Pos (0U)
  5844. #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
  5845. #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
  5846. /******************** Bits definition for DMA_HISR register *****************/
  5847. #define DMA_HISR_TCIF7_Pos (27U)
  5848. #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
  5849. #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
  5850. #define DMA_HISR_HTIF7_Pos (26U)
  5851. #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
  5852. #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
  5853. #define DMA_HISR_TEIF7_Pos (25U)
  5854. #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
  5855. #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
  5856. #define DMA_HISR_DMEIF7_Pos (24U)
  5857. #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
  5858. #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
  5859. #define DMA_HISR_FEIF7_Pos (22U)
  5860. #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
  5861. #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
  5862. #define DMA_HISR_TCIF6_Pos (21U)
  5863. #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
  5864. #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
  5865. #define DMA_HISR_HTIF6_Pos (20U)
  5866. #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
  5867. #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
  5868. #define DMA_HISR_TEIF6_Pos (19U)
  5869. #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
  5870. #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
  5871. #define DMA_HISR_DMEIF6_Pos (18U)
  5872. #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
  5873. #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
  5874. #define DMA_HISR_FEIF6_Pos (16U)
  5875. #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
  5876. #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
  5877. #define DMA_HISR_TCIF5_Pos (11U)
  5878. #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
  5879. #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
  5880. #define DMA_HISR_HTIF5_Pos (10U)
  5881. #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
  5882. #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
  5883. #define DMA_HISR_TEIF5_Pos (9U)
  5884. #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
  5885. #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
  5886. #define DMA_HISR_DMEIF5_Pos (8U)
  5887. #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
  5888. #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
  5889. #define DMA_HISR_FEIF5_Pos (6U)
  5890. #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
  5891. #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
  5892. #define DMA_HISR_TCIF4_Pos (5U)
  5893. #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
  5894. #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
  5895. #define DMA_HISR_HTIF4_Pos (4U)
  5896. #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
  5897. #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
  5898. #define DMA_HISR_TEIF4_Pos (3U)
  5899. #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
  5900. #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
  5901. #define DMA_HISR_DMEIF4_Pos (2U)
  5902. #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
  5903. #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
  5904. #define DMA_HISR_FEIF4_Pos (0U)
  5905. #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
  5906. #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
  5907. /******************** Bits definition for DMA_LIFCR register ****************/
  5908. #define DMA_LIFCR_CTCIF3_Pos (27U)
  5909. #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
  5910. #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
  5911. #define DMA_LIFCR_CHTIF3_Pos (26U)
  5912. #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
  5913. #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
  5914. #define DMA_LIFCR_CTEIF3_Pos (25U)
  5915. #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
  5916. #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
  5917. #define DMA_LIFCR_CDMEIF3_Pos (24U)
  5918. #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
  5919. #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
  5920. #define DMA_LIFCR_CFEIF3_Pos (22U)
  5921. #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
  5922. #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
  5923. #define DMA_LIFCR_CTCIF2_Pos (21U)
  5924. #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
  5925. #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
  5926. #define DMA_LIFCR_CHTIF2_Pos (20U)
  5927. #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
  5928. #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
  5929. #define DMA_LIFCR_CTEIF2_Pos (19U)
  5930. #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
  5931. #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
  5932. #define DMA_LIFCR_CDMEIF2_Pos (18U)
  5933. #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
  5934. #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
  5935. #define DMA_LIFCR_CFEIF2_Pos (16U)
  5936. #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
  5937. #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
  5938. #define DMA_LIFCR_CTCIF1_Pos (11U)
  5939. #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
  5940. #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
  5941. #define DMA_LIFCR_CHTIF1_Pos (10U)
  5942. #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
  5943. #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
  5944. #define DMA_LIFCR_CTEIF1_Pos (9U)
  5945. #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
  5946. #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
  5947. #define DMA_LIFCR_CDMEIF1_Pos (8U)
  5948. #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
  5949. #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
  5950. #define DMA_LIFCR_CFEIF1_Pos (6U)
  5951. #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
  5952. #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
  5953. #define DMA_LIFCR_CTCIF0_Pos (5U)
  5954. #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
  5955. #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
  5956. #define DMA_LIFCR_CHTIF0_Pos (4U)
  5957. #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
  5958. #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
  5959. #define DMA_LIFCR_CTEIF0_Pos (3U)
  5960. #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
  5961. #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
  5962. #define DMA_LIFCR_CDMEIF0_Pos (2U)
  5963. #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
  5964. #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
  5965. #define DMA_LIFCR_CFEIF0_Pos (0U)
  5966. #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
  5967. #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
  5968. /******************** Bits definition for DMA_HIFCR register ****************/
  5969. #define DMA_HIFCR_CTCIF7_Pos (27U)
  5970. #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
  5971. #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
  5972. #define DMA_HIFCR_CHTIF7_Pos (26U)
  5973. #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
  5974. #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
  5975. #define DMA_HIFCR_CTEIF7_Pos (25U)
  5976. #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
  5977. #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
  5978. #define DMA_HIFCR_CDMEIF7_Pos (24U)
  5979. #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
  5980. #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
  5981. #define DMA_HIFCR_CFEIF7_Pos (22U)
  5982. #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
  5983. #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
  5984. #define DMA_HIFCR_CTCIF6_Pos (21U)
  5985. #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
  5986. #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
  5987. #define DMA_HIFCR_CHTIF6_Pos (20U)
  5988. #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
  5989. #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
  5990. #define DMA_HIFCR_CTEIF6_Pos (19U)
  5991. #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
  5992. #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
  5993. #define DMA_HIFCR_CDMEIF6_Pos (18U)
  5994. #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
  5995. #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
  5996. #define DMA_HIFCR_CFEIF6_Pos (16U)
  5997. #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
  5998. #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
  5999. #define DMA_HIFCR_CTCIF5_Pos (11U)
  6000. #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
  6001. #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
  6002. #define DMA_HIFCR_CHTIF5_Pos (10U)
  6003. #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
  6004. #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
  6005. #define DMA_HIFCR_CTEIF5_Pos (9U)
  6006. #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
  6007. #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
  6008. #define DMA_HIFCR_CDMEIF5_Pos (8U)
  6009. #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
  6010. #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
  6011. #define DMA_HIFCR_CFEIF5_Pos (6U)
  6012. #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
  6013. #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
  6014. #define DMA_HIFCR_CTCIF4_Pos (5U)
  6015. #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
  6016. #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
  6017. #define DMA_HIFCR_CHTIF4_Pos (4U)
  6018. #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
  6019. #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
  6020. #define DMA_HIFCR_CTEIF4_Pos (3U)
  6021. #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
  6022. #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
  6023. #define DMA_HIFCR_CDMEIF4_Pos (2U)
  6024. #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
  6025. #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
  6026. #define DMA_HIFCR_CFEIF4_Pos (0U)
  6027. #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
  6028. #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
  6029. /****************** Bit definition for DMA_SxPAR register ********************/
  6030. #define DMA_SxPAR_PA_Pos (0U)
  6031. #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
  6032. #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
  6033. /****************** Bit definition for DMA_SxM0AR register ********************/
  6034. #define DMA_SxM0AR_M0A_Pos (0U)
  6035. #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
  6036. #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
  6037. /****************** Bit definition for DMA_SxM1AR register ********************/
  6038. #define DMA_SxM1AR_M1A_Pos (0U)
  6039. #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
  6040. #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
  6041. /******************************************************************************/
  6042. /* */
  6043. /* AHB Master DMA2D Controller (DMA2D) */
  6044. /* */
  6045. /******************************************************************************/
  6046. /******************** Bit definition for DMA2D_CR register ******************/
  6047. #define DMA2D_CR_START_Pos (0U)
  6048. #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
  6049. #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
  6050. #define DMA2D_CR_SUSP_Pos (1U)
  6051. #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
  6052. #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
  6053. #define DMA2D_CR_ABORT_Pos (2U)
  6054. #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
  6055. #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
  6056. #define DMA2D_CR_TEIE_Pos (8U)
  6057. #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
  6058. #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
  6059. #define DMA2D_CR_TCIE_Pos (9U)
  6060. #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
  6061. #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
  6062. #define DMA2D_CR_TWIE_Pos (10U)
  6063. #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
  6064. #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
  6065. #define DMA2D_CR_CAEIE_Pos (11U)
  6066. #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
  6067. #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
  6068. #define DMA2D_CR_CTCIE_Pos (12U)
  6069. #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
  6070. #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
  6071. #define DMA2D_CR_CEIE_Pos (13U)
  6072. #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
  6073. #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
  6074. #define DMA2D_CR_MODE_Pos (16U)
  6075. #define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
  6076. #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
  6077. #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
  6078. #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
  6079. /******************** Bit definition for DMA2D_ISR register *****************/
  6080. #define DMA2D_ISR_TEIF_Pos (0U)
  6081. #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
  6082. #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
  6083. #define DMA2D_ISR_TCIF_Pos (1U)
  6084. #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
  6085. #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
  6086. #define DMA2D_ISR_TWIF_Pos (2U)
  6087. #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
  6088. #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
  6089. #define DMA2D_ISR_CAEIF_Pos (3U)
  6090. #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
  6091. #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
  6092. #define DMA2D_ISR_CTCIF_Pos (4U)
  6093. #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
  6094. #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
  6095. #define DMA2D_ISR_CEIF_Pos (5U)
  6096. #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
  6097. #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
  6098. /******************** Bit definition for DMA2D_IFCR register ****************/
  6099. #define DMA2D_IFCR_CTEIF_Pos (0U)
  6100. #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
  6101. #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
  6102. #define DMA2D_IFCR_CTCIF_Pos (1U)
  6103. #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
  6104. #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
  6105. #define DMA2D_IFCR_CTWIF_Pos (2U)
  6106. #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
  6107. #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
  6108. #define DMA2D_IFCR_CAECIF_Pos (3U)
  6109. #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
  6110. #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
  6111. #define DMA2D_IFCR_CCTCIF_Pos (4U)
  6112. #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
  6113. #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
  6114. #define DMA2D_IFCR_CCEIF_Pos (5U)
  6115. #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
  6116. #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
  6117. /* Legacy defines */
  6118. #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
  6119. #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
  6120. #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
  6121. #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
  6122. #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
  6123. #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
  6124. /******************** Bit definition for DMA2D_FGMAR register ***************/
  6125. #define DMA2D_FGMAR_MA_Pos (0U)
  6126. #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6127. #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
  6128. /******************** Bit definition for DMA2D_FGOR register ****************/
  6129. #define DMA2D_FGOR_LO_Pos (0U)
  6130. #define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
  6131. #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
  6132. /******************** Bit definition for DMA2D_BGMAR register ***************/
  6133. #define DMA2D_BGMAR_MA_Pos (0U)
  6134. #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6135. #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
  6136. /******************** Bit definition for DMA2D_BGOR register ****************/
  6137. #define DMA2D_BGOR_LO_Pos (0U)
  6138. #define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
  6139. #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
  6140. /******************** Bit definition for DMA2D_FGPFCCR register *************/
  6141. #define DMA2D_FGPFCCR_CM_Pos (0U)
  6142. #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
  6143. #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
  6144. #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
  6145. #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
  6146. #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
  6147. #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
  6148. #define DMA2D_FGPFCCR_CCM_Pos (4U)
  6149. #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
  6150. #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
  6151. #define DMA2D_FGPFCCR_START_Pos (5U)
  6152. #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
  6153. #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
  6154. #define DMA2D_FGPFCCR_CS_Pos (8U)
  6155. #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
  6156. #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
  6157. #define DMA2D_FGPFCCR_AM_Pos (16U)
  6158. #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
  6159. #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
  6160. #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
  6161. #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
  6162. #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
  6163. #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
  6164. #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
  6165. /******************** Bit definition for DMA2D_FGCOLR register **************/
  6166. #define DMA2D_FGCOLR_BLUE_Pos (0U)
  6167. #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
  6168. #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
  6169. #define DMA2D_FGCOLR_GREEN_Pos (8U)
  6170. #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
  6171. #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
  6172. #define DMA2D_FGCOLR_RED_Pos (16U)
  6173. #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
  6174. #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
  6175. /******************** Bit definition for DMA2D_BGPFCCR register *************/
  6176. #define DMA2D_BGPFCCR_CM_Pos (0U)
  6177. #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
  6178. #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
  6179. #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
  6180. #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
  6181. #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
  6182. #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
  6183. #define DMA2D_BGPFCCR_CCM_Pos (4U)
  6184. #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
  6185. #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
  6186. #define DMA2D_BGPFCCR_START_Pos (5U)
  6187. #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
  6188. #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
  6189. #define DMA2D_BGPFCCR_CS_Pos (8U)
  6190. #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
  6191. #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
  6192. #define DMA2D_BGPFCCR_AM_Pos (16U)
  6193. #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
  6194. #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
  6195. #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
  6196. #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
  6197. #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
  6198. #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
  6199. #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
  6200. /******************** Bit definition for DMA2D_BGCOLR register **************/
  6201. #define DMA2D_BGCOLR_BLUE_Pos (0U)
  6202. #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
  6203. #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
  6204. #define DMA2D_BGCOLR_GREEN_Pos (8U)
  6205. #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
  6206. #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
  6207. #define DMA2D_BGCOLR_RED_Pos (16U)
  6208. #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
  6209. #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
  6210. /******************** Bit definition for DMA2D_FGCMAR register **************/
  6211. #define DMA2D_FGCMAR_MA_Pos (0U)
  6212. #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6213. #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
  6214. /******************** Bit definition for DMA2D_BGCMAR register **************/
  6215. #define DMA2D_BGCMAR_MA_Pos (0U)
  6216. #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6217. #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
  6218. /******************** Bit definition for DMA2D_OPFCCR register **************/
  6219. #define DMA2D_OPFCCR_CM_Pos (0U)
  6220. #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
  6221. #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
  6222. #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
  6223. #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
  6224. #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
  6225. /******************** Bit definition for DMA2D_OCOLR register ***************/
  6226. /*!<Mode_ARGB8888/RGB888 */
  6227. #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
  6228. #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
  6229. #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
  6230. #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
  6231. /*!<Mode_RGB565 */
  6232. #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
  6233. #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
  6234. #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
  6235. /*!<Mode_ARGB1555 */
  6236. #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
  6237. #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
  6238. #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
  6239. #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
  6240. /*!<Mode_ARGB4444 */
  6241. #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
  6242. #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
  6243. #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
  6244. #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
  6245. /******************** Bit definition for DMA2D_OMAR register ****************/
  6246. #define DMA2D_OMAR_MA_Pos (0U)
  6247. #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
  6248. #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
  6249. /******************** Bit definition for DMA2D_OOR register *****************/
  6250. #define DMA2D_OOR_LO_Pos (0U)
  6251. #define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
  6252. #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
  6253. /******************** Bit definition for DMA2D_NLR register *****************/
  6254. #define DMA2D_NLR_NL_Pos (0U)
  6255. #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
  6256. #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
  6257. #define DMA2D_NLR_PL_Pos (16U)
  6258. #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
  6259. #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
  6260. /******************** Bit definition for DMA2D_LWR register *****************/
  6261. #define DMA2D_LWR_LW_Pos (0U)
  6262. #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
  6263. #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
  6264. /******************** Bit definition for DMA2D_AMTCR register ***************/
  6265. #define DMA2D_AMTCR_EN_Pos (0U)
  6266. #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
  6267. #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
  6268. #define DMA2D_AMTCR_DT_Pos (8U)
  6269. #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
  6270. #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
  6271. /******************** Bit definition for DMA2D_FGCLUT register **************/
  6272. /******************** Bit definition for DMA2D_BGCLUT register **************/
  6273. /******************************************************************************/
  6274. /* */
  6275. /* External Interrupt/Event Controller */
  6276. /* */
  6277. /******************************************************************************/
  6278. /******************* Bit definition for EXTI_IMR register *******************/
  6279. #define EXTI_IMR_MR0_Pos (0U)
  6280. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  6281. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  6282. #define EXTI_IMR_MR1_Pos (1U)
  6283. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  6284. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  6285. #define EXTI_IMR_MR2_Pos (2U)
  6286. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  6287. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  6288. #define EXTI_IMR_MR3_Pos (3U)
  6289. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  6290. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  6291. #define EXTI_IMR_MR4_Pos (4U)
  6292. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  6293. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  6294. #define EXTI_IMR_MR5_Pos (5U)
  6295. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  6296. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  6297. #define EXTI_IMR_MR6_Pos (6U)
  6298. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  6299. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  6300. #define EXTI_IMR_MR7_Pos (7U)
  6301. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  6302. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  6303. #define EXTI_IMR_MR8_Pos (8U)
  6304. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  6305. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  6306. #define EXTI_IMR_MR9_Pos (9U)
  6307. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  6308. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  6309. #define EXTI_IMR_MR10_Pos (10U)
  6310. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  6311. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  6312. #define EXTI_IMR_MR11_Pos (11U)
  6313. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  6314. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  6315. #define EXTI_IMR_MR12_Pos (12U)
  6316. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  6317. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  6318. #define EXTI_IMR_MR13_Pos (13U)
  6319. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  6320. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  6321. #define EXTI_IMR_MR14_Pos (14U)
  6322. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  6323. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  6324. #define EXTI_IMR_MR15_Pos (15U)
  6325. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  6326. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  6327. #define EXTI_IMR_MR16_Pos (16U)
  6328. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  6329. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  6330. #define EXTI_IMR_MR17_Pos (17U)
  6331. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  6332. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  6333. #define EXTI_IMR_MR18_Pos (18U)
  6334. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  6335. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  6336. #define EXTI_IMR_MR19_Pos (19U)
  6337. #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  6338. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  6339. #define EXTI_IMR_MR20_Pos (20U)
  6340. #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
  6341. #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
  6342. #define EXTI_IMR_MR21_Pos (21U)
  6343. #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
  6344. #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
  6345. #define EXTI_IMR_MR22_Pos (22U)
  6346. #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
  6347. #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
  6348. /* Reference Defines */
  6349. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  6350. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  6351. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  6352. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  6353. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  6354. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  6355. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  6356. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  6357. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  6358. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  6359. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  6360. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  6361. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  6362. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  6363. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  6364. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  6365. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  6366. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  6367. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  6368. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  6369. #define EXTI_IMR_IM20 EXTI_IMR_MR20
  6370. #define EXTI_IMR_IM21 EXTI_IMR_MR21
  6371. #define EXTI_IMR_IM22 EXTI_IMR_MR22
  6372. #define EXTI_IMR_IM_Pos (0U)
  6373. #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
  6374. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  6375. /******************* Bit definition for EXTI_EMR register *******************/
  6376. #define EXTI_EMR_MR0_Pos (0U)
  6377. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  6378. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  6379. #define EXTI_EMR_MR1_Pos (1U)
  6380. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  6381. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  6382. #define EXTI_EMR_MR2_Pos (2U)
  6383. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  6384. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  6385. #define EXTI_EMR_MR3_Pos (3U)
  6386. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  6387. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  6388. #define EXTI_EMR_MR4_Pos (4U)
  6389. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  6390. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  6391. #define EXTI_EMR_MR5_Pos (5U)
  6392. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  6393. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  6394. #define EXTI_EMR_MR6_Pos (6U)
  6395. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  6396. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  6397. #define EXTI_EMR_MR7_Pos (7U)
  6398. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  6399. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  6400. #define EXTI_EMR_MR8_Pos (8U)
  6401. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  6402. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  6403. #define EXTI_EMR_MR9_Pos (9U)
  6404. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  6405. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  6406. #define EXTI_EMR_MR10_Pos (10U)
  6407. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  6408. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  6409. #define EXTI_EMR_MR11_Pos (11U)
  6410. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  6411. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  6412. #define EXTI_EMR_MR12_Pos (12U)
  6413. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  6414. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  6415. #define EXTI_EMR_MR13_Pos (13U)
  6416. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  6417. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  6418. #define EXTI_EMR_MR14_Pos (14U)
  6419. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  6420. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  6421. #define EXTI_EMR_MR15_Pos (15U)
  6422. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  6423. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  6424. #define EXTI_EMR_MR16_Pos (16U)
  6425. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  6426. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  6427. #define EXTI_EMR_MR17_Pos (17U)
  6428. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  6429. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  6430. #define EXTI_EMR_MR18_Pos (18U)
  6431. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  6432. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  6433. #define EXTI_EMR_MR19_Pos (19U)
  6434. #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  6435. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  6436. #define EXTI_EMR_MR20_Pos (20U)
  6437. #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
  6438. #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
  6439. #define EXTI_EMR_MR21_Pos (21U)
  6440. #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
  6441. #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
  6442. #define EXTI_EMR_MR22_Pos (22U)
  6443. #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
  6444. #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
  6445. /* Reference Defines */
  6446. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  6447. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  6448. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  6449. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  6450. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  6451. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  6452. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  6453. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  6454. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  6455. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  6456. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  6457. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  6458. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  6459. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  6460. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  6461. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  6462. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  6463. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  6464. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  6465. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  6466. #define EXTI_EMR_EM20 EXTI_EMR_MR20
  6467. #define EXTI_EMR_EM21 EXTI_EMR_MR21
  6468. #define EXTI_EMR_EM22 EXTI_EMR_MR22
  6469. /****************** Bit definition for EXTI_RTSR register *******************/
  6470. #define EXTI_RTSR_TR0_Pos (0U)
  6471. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  6472. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  6473. #define EXTI_RTSR_TR1_Pos (1U)
  6474. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  6475. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  6476. #define EXTI_RTSR_TR2_Pos (2U)
  6477. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  6478. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  6479. #define EXTI_RTSR_TR3_Pos (3U)
  6480. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  6481. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  6482. #define EXTI_RTSR_TR4_Pos (4U)
  6483. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  6484. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  6485. #define EXTI_RTSR_TR5_Pos (5U)
  6486. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  6487. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  6488. #define EXTI_RTSR_TR6_Pos (6U)
  6489. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  6490. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  6491. #define EXTI_RTSR_TR7_Pos (7U)
  6492. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  6493. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  6494. #define EXTI_RTSR_TR8_Pos (8U)
  6495. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  6496. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  6497. #define EXTI_RTSR_TR9_Pos (9U)
  6498. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  6499. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  6500. #define EXTI_RTSR_TR10_Pos (10U)
  6501. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  6502. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  6503. #define EXTI_RTSR_TR11_Pos (11U)
  6504. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  6505. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  6506. #define EXTI_RTSR_TR12_Pos (12U)
  6507. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  6508. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  6509. #define EXTI_RTSR_TR13_Pos (13U)
  6510. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  6511. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  6512. #define EXTI_RTSR_TR14_Pos (14U)
  6513. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  6514. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  6515. #define EXTI_RTSR_TR15_Pos (15U)
  6516. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  6517. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  6518. #define EXTI_RTSR_TR16_Pos (16U)
  6519. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  6520. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  6521. #define EXTI_RTSR_TR17_Pos (17U)
  6522. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  6523. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  6524. #define EXTI_RTSR_TR18_Pos (18U)
  6525. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  6526. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  6527. #define EXTI_RTSR_TR19_Pos (19U)
  6528. #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  6529. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  6530. #define EXTI_RTSR_TR20_Pos (20U)
  6531. #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
  6532. #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
  6533. #define EXTI_RTSR_TR21_Pos (21U)
  6534. #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
  6535. #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
  6536. #define EXTI_RTSR_TR22_Pos (22U)
  6537. #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
  6538. #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
  6539. /****************** Bit definition for EXTI_FTSR register *******************/
  6540. #define EXTI_FTSR_TR0_Pos (0U)
  6541. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  6542. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  6543. #define EXTI_FTSR_TR1_Pos (1U)
  6544. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  6545. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  6546. #define EXTI_FTSR_TR2_Pos (2U)
  6547. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  6548. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  6549. #define EXTI_FTSR_TR3_Pos (3U)
  6550. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  6551. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  6552. #define EXTI_FTSR_TR4_Pos (4U)
  6553. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  6554. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  6555. #define EXTI_FTSR_TR5_Pos (5U)
  6556. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  6557. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  6558. #define EXTI_FTSR_TR6_Pos (6U)
  6559. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  6560. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  6561. #define EXTI_FTSR_TR7_Pos (7U)
  6562. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  6563. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  6564. #define EXTI_FTSR_TR8_Pos (8U)
  6565. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  6566. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  6567. #define EXTI_FTSR_TR9_Pos (9U)
  6568. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  6569. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  6570. #define EXTI_FTSR_TR10_Pos (10U)
  6571. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  6572. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  6573. #define EXTI_FTSR_TR11_Pos (11U)
  6574. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  6575. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  6576. #define EXTI_FTSR_TR12_Pos (12U)
  6577. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  6578. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  6579. #define EXTI_FTSR_TR13_Pos (13U)
  6580. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  6581. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  6582. #define EXTI_FTSR_TR14_Pos (14U)
  6583. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  6584. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  6585. #define EXTI_FTSR_TR15_Pos (15U)
  6586. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  6587. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  6588. #define EXTI_FTSR_TR16_Pos (16U)
  6589. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  6590. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  6591. #define EXTI_FTSR_TR17_Pos (17U)
  6592. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  6593. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  6594. #define EXTI_FTSR_TR18_Pos (18U)
  6595. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  6596. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  6597. #define EXTI_FTSR_TR19_Pos (19U)
  6598. #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  6599. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  6600. #define EXTI_FTSR_TR20_Pos (20U)
  6601. #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
  6602. #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
  6603. #define EXTI_FTSR_TR21_Pos (21U)
  6604. #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
  6605. #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
  6606. #define EXTI_FTSR_TR22_Pos (22U)
  6607. #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
  6608. #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
  6609. /****************** Bit definition for EXTI_SWIER register ******************/
  6610. #define EXTI_SWIER_SWIER0_Pos (0U)
  6611. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  6612. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  6613. #define EXTI_SWIER_SWIER1_Pos (1U)
  6614. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  6615. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  6616. #define EXTI_SWIER_SWIER2_Pos (2U)
  6617. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  6618. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  6619. #define EXTI_SWIER_SWIER3_Pos (3U)
  6620. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  6621. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  6622. #define EXTI_SWIER_SWIER4_Pos (4U)
  6623. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  6624. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  6625. #define EXTI_SWIER_SWIER5_Pos (5U)
  6626. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  6627. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  6628. #define EXTI_SWIER_SWIER6_Pos (6U)
  6629. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  6630. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  6631. #define EXTI_SWIER_SWIER7_Pos (7U)
  6632. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  6633. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  6634. #define EXTI_SWIER_SWIER8_Pos (8U)
  6635. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  6636. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  6637. #define EXTI_SWIER_SWIER9_Pos (9U)
  6638. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  6639. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  6640. #define EXTI_SWIER_SWIER10_Pos (10U)
  6641. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  6642. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  6643. #define EXTI_SWIER_SWIER11_Pos (11U)
  6644. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  6645. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  6646. #define EXTI_SWIER_SWIER12_Pos (12U)
  6647. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  6648. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  6649. #define EXTI_SWIER_SWIER13_Pos (13U)
  6650. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  6651. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  6652. #define EXTI_SWIER_SWIER14_Pos (14U)
  6653. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  6654. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  6655. #define EXTI_SWIER_SWIER15_Pos (15U)
  6656. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  6657. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  6658. #define EXTI_SWIER_SWIER16_Pos (16U)
  6659. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  6660. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  6661. #define EXTI_SWIER_SWIER17_Pos (17U)
  6662. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  6663. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  6664. #define EXTI_SWIER_SWIER18_Pos (18U)
  6665. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  6666. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  6667. #define EXTI_SWIER_SWIER19_Pos (19U)
  6668. #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  6669. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  6670. #define EXTI_SWIER_SWIER20_Pos (20U)
  6671. #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
  6672. #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
  6673. #define EXTI_SWIER_SWIER21_Pos (21U)
  6674. #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
  6675. #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
  6676. #define EXTI_SWIER_SWIER22_Pos (22U)
  6677. #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
  6678. #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
  6679. /******************* Bit definition for EXTI_PR register ********************/
  6680. #define EXTI_PR_PR0_Pos (0U)
  6681. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  6682. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  6683. #define EXTI_PR_PR1_Pos (1U)
  6684. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  6685. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  6686. #define EXTI_PR_PR2_Pos (2U)
  6687. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  6688. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  6689. #define EXTI_PR_PR3_Pos (3U)
  6690. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  6691. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  6692. #define EXTI_PR_PR4_Pos (4U)
  6693. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  6694. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  6695. #define EXTI_PR_PR5_Pos (5U)
  6696. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  6697. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  6698. #define EXTI_PR_PR6_Pos (6U)
  6699. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  6700. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  6701. #define EXTI_PR_PR7_Pos (7U)
  6702. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  6703. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  6704. #define EXTI_PR_PR8_Pos (8U)
  6705. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  6706. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  6707. #define EXTI_PR_PR9_Pos (9U)
  6708. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  6709. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  6710. #define EXTI_PR_PR10_Pos (10U)
  6711. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  6712. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  6713. #define EXTI_PR_PR11_Pos (11U)
  6714. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  6715. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  6716. #define EXTI_PR_PR12_Pos (12U)
  6717. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  6718. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  6719. #define EXTI_PR_PR13_Pos (13U)
  6720. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  6721. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  6722. #define EXTI_PR_PR14_Pos (14U)
  6723. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  6724. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  6725. #define EXTI_PR_PR15_Pos (15U)
  6726. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  6727. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  6728. #define EXTI_PR_PR16_Pos (16U)
  6729. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  6730. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  6731. #define EXTI_PR_PR17_Pos (17U)
  6732. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  6733. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  6734. #define EXTI_PR_PR18_Pos (18U)
  6735. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  6736. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  6737. #define EXTI_PR_PR19_Pos (19U)
  6738. #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  6739. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
  6740. #define EXTI_PR_PR20_Pos (20U)
  6741. #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
  6742. #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
  6743. #define EXTI_PR_PR21_Pos (21U)
  6744. #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
  6745. #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
  6746. #define EXTI_PR_PR22_Pos (22U)
  6747. #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
  6748. #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
  6749. /******************************************************************************/
  6750. /* */
  6751. /* FLASH */
  6752. /* */
  6753. /******************************************************************************/
  6754. /******************* Bits definition for FLASH_ACR register *****************/
  6755. #define FLASH_ACR_LATENCY_Pos (0U)
  6756. #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
  6757. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  6758. #define FLASH_ACR_LATENCY_0WS 0x00000000U
  6759. #define FLASH_ACR_LATENCY_1WS 0x00000001U
  6760. #define FLASH_ACR_LATENCY_2WS 0x00000002U
  6761. #define FLASH_ACR_LATENCY_3WS 0x00000003U
  6762. #define FLASH_ACR_LATENCY_4WS 0x00000004U
  6763. #define FLASH_ACR_LATENCY_5WS 0x00000005U
  6764. #define FLASH_ACR_LATENCY_6WS 0x00000006U
  6765. #define FLASH_ACR_LATENCY_7WS 0x00000007U
  6766. #define FLASH_ACR_LATENCY_8WS 0x00000008U
  6767. #define FLASH_ACR_LATENCY_9WS 0x00000009U
  6768. #define FLASH_ACR_LATENCY_10WS 0x0000000AU
  6769. #define FLASH_ACR_LATENCY_11WS 0x0000000BU
  6770. #define FLASH_ACR_LATENCY_12WS 0x0000000CU
  6771. #define FLASH_ACR_LATENCY_13WS 0x0000000DU
  6772. #define FLASH_ACR_LATENCY_14WS 0x0000000EU
  6773. #define FLASH_ACR_LATENCY_15WS 0x0000000FU
  6774. #define FLASH_ACR_PRFTEN_Pos (8U)
  6775. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  6776. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  6777. #define FLASH_ACR_ICEN_Pos (9U)
  6778. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  6779. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  6780. #define FLASH_ACR_DCEN_Pos (10U)
  6781. #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  6782. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  6783. #define FLASH_ACR_ICRST_Pos (11U)
  6784. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  6785. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  6786. #define FLASH_ACR_DCRST_Pos (12U)
  6787. #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  6788. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  6789. #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
  6790. #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
  6791. #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
  6792. #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
  6793. #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
  6794. #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
  6795. /******************* Bits definition for FLASH_SR register ******************/
  6796. #define FLASH_SR_EOP_Pos (0U)
  6797. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  6798. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  6799. #define FLASH_SR_SOP_Pos (1U)
  6800. #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
  6801. #define FLASH_SR_SOP FLASH_SR_SOP_Msk
  6802. #define FLASH_SR_WRPERR_Pos (4U)
  6803. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  6804. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  6805. #define FLASH_SR_PGAERR_Pos (5U)
  6806. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  6807. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  6808. #define FLASH_SR_PGPERR_Pos (6U)
  6809. #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
  6810. #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
  6811. #define FLASH_SR_PGSERR_Pos (7U)
  6812. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  6813. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  6814. #define FLASH_SR_RDERR_Pos (8U)
  6815. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
  6816. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  6817. #define FLASH_SR_BSY_Pos (16U)
  6818. #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  6819. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  6820. /******************* Bits definition for FLASH_CR register ******************/
  6821. #define FLASH_CR_PG_Pos (0U)
  6822. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  6823. #define FLASH_CR_PG FLASH_CR_PG_Msk
  6824. #define FLASH_CR_SER_Pos (1U)
  6825. #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
  6826. #define FLASH_CR_SER FLASH_CR_SER_Msk
  6827. #define FLASH_CR_MER_Pos (2U)
  6828. #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  6829. #define FLASH_CR_MER FLASH_CR_MER_Msk
  6830. #define FLASH_CR_MER1 FLASH_CR_MER
  6831. #define FLASH_CR_SNB_Pos (3U)
  6832. #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
  6833. #define FLASH_CR_SNB FLASH_CR_SNB_Msk
  6834. #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
  6835. #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
  6836. #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
  6837. #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
  6838. #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
  6839. #define FLASH_CR_PSIZE_Pos (8U)
  6840. #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
  6841. #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
  6842. #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
  6843. #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
  6844. #define FLASH_CR_MER2_Pos (15U)
  6845. #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
  6846. #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
  6847. #define FLASH_CR_STRT_Pos (16U)
  6848. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  6849. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  6850. #define FLASH_CR_EOPIE_Pos (24U)
  6851. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  6852. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  6853. #define FLASH_CR_LOCK_Pos (31U)
  6854. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  6855. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  6856. /******************* Bits definition for FLASH_OPTCR register ***************/
  6857. #define FLASH_OPTCR_OPTLOCK_Pos (0U)
  6858. #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
  6859. #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
  6860. #define FLASH_OPTCR_OPTSTRT_Pos (1U)
  6861. #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
  6862. #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
  6863. #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
  6864. #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
  6865. #define FLASH_OPTCR_BOR_LEV_Pos (2U)
  6866. #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
  6867. #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
  6868. #define FLASH_OPTCR_BFB2_Pos (4U)
  6869. #define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
  6870. #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
  6871. #define FLASH_OPTCR_WDG_SW_Pos (5U)
  6872. #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
  6873. #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
  6874. #define FLASH_OPTCR_nRST_STOP_Pos (6U)
  6875. #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
  6876. #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
  6877. #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
  6878. #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
  6879. #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
  6880. #define FLASH_OPTCR_RDP_Pos (8U)
  6881. #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
  6882. #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
  6883. #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
  6884. #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
  6885. #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
  6886. #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
  6887. #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
  6888. #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
  6889. #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
  6890. #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
  6891. #define FLASH_OPTCR_nWRP_Pos (16U)
  6892. #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
  6893. #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
  6894. #define FLASH_OPTCR_nWRP_0 0x00010000U
  6895. #define FLASH_OPTCR_nWRP_1 0x00020000U
  6896. #define FLASH_OPTCR_nWRP_2 0x00040000U
  6897. #define FLASH_OPTCR_nWRP_3 0x00080000U
  6898. #define FLASH_OPTCR_nWRP_4 0x00100000U
  6899. #define FLASH_OPTCR_nWRP_5 0x00200000U
  6900. #define FLASH_OPTCR_nWRP_6 0x00400000U
  6901. #define FLASH_OPTCR_nWRP_7 0x00800000U
  6902. #define FLASH_OPTCR_nWRP_8 0x01000000U
  6903. #define FLASH_OPTCR_nWRP_9 0x02000000U
  6904. #define FLASH_OPTCR_nWRP_10 0x04000000U
  6905. #define FLASH_OPTCR_nWRP_11 0x08000000U
  6906. #define FLASH_OPTCR_DB1M_Pos (30U)
  6907. #define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
  6908. #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
  6909. #define FLASH_OPTCR_SPRMOD_Pos (31U)
  6910. #define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
  6911. #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
  6912. /****************** Bits definition for FLASH_OPTCR1 register ***************/
  6913. #define FLASH_OPTCR1_nWRP_Pos (16U)
  6914. #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
  6915. #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
  6916. #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
  6917. #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
  6918. #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
  6919. #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
  6920. #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
  6921. #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
  6922. #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
  6923. #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
  6924. #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
  6925. #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
  6926. #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
  6927. #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
  6928. /******************************************************************************/
  6929. /* */
  6930. /* Flexible Memory Controller */
  6931. /* */
  6932. /******************************************************************************/
  6933. /****************** Bit definition for FMC_BCR1 register *******************/
  6934. #define FMC_BCR1_MBKEN_Pos (0U)
  6935. #define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
  6936. #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
  6937. #define FMC_BCR1_MUXEN_Pos (1U)
  6938. #define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
  6939. #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6940. #define FMC_BCR1_MTYP_Pos (2U)
  6941. #define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
  6942. #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6943. #define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
  6944. #define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
  6945. #define FMC_BCR1_MWID_Pos (4U)
  6946. #define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
  6947. #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  6948. #define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
  6949. #define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
  6950. #define FMC_BCR1_FACCEN_Pos (6U)
  6951. #define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
  6952. #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
  6953. #define FMC_BCR1_BURSTEN_Pos (8U)
  6954. #define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
  6955. #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
  6956. #define FMC_BCR1_WAITPOL_Pos (9U)
  6957. #define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
  6958. #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
  6959. #define FMC_BCR1_WRAPMOD_Pos (10U)
  6960. #define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
  6961. #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
  6962. #define FMC_BCR1_WAITCFG_Pos (11U)
  6963. #define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
  6964. #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
  6965. #define FMC_BCR1_WREN_Pos (12U)
  6966. #define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
  6967. #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
  6968. #define FMC_BCR1_WAITEN_Pos (13U)
  6969. #define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
  6970. #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
  6971. #define FMC_BCR1_EXTMOD_Pos (14U)
  6972. #define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
  6973. #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
  6974. #define FMC_BCR1_ASYNCWAIT_Pos (15U)
  6975. #define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
  6976. #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
  6977. #define FMC_BCR1_CPSIZE_Pos (16U)
  6978. #define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
  6979. #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
  6980. #define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
  6981. #define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
  6982. #define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
  6983. #define FMC_BCR1_CBURSTRW_Pos (19U)
  6984. #define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
  6985. #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
  6986. #define FMC_BCR1_CCLKEN_Pos (20U)
  6987. #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
  6988. #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
  6989. /****************** Bit definition for FMC_BCR2 register *******************/
  6990. #define FMC_BCR2_MBKEN_Pos (0U)
  6991. #define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
  6992. #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
  6993. #define FMC_BCR2_MUXEN_Pos (1U)
  6994. #define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
  6995. #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  6996. #define FMC_BCR2_MTYP_Pos (2U)
  6997. #define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
  6998. #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  6999. #define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
  7000. #define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
  7001. #define FMC_BCR2_MWID_Pos (4U)
  7002. #define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
  7003. #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  7004. #define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
  7005. #define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
  7006. #define FMC_BCR2_FACCEN_Pos (6U)
  7007. #define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
  7008. #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
  7009. #define FMC_BCR2_BURSTEN_Pos (8U)
  7010. #define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
  7011. #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
  7012. #define FMC_BCR2_WAITPOL_Pos (9U)
  7013. #define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
  7014. #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
  7015. #define FMC_BCR2_WRAPMOD_Pos (10U)
  7016. #define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
  7017. #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
  7018. #define FMC_BCR2_WAITCFG_Pos (11U)
  7019. #define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
  7020. #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
  7021. #define FMC_BCR2_WREN_Pos (12U)
  7022. #define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
  7023. #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
  7024. #define FMC_BCR2_WAITEN_Pos (13U)
  7025. #define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
  7026. #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
  7027. #define FMC_BCR2_EXTMOD_Pos (14U)
  7028. #define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
  7029. #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
  7030. #define FMC_BCR2_ASYNCWAIT_Pos (15U)
  7031. #define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
  7032. #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
  7033. #define FMC_BCR2_CPSIZE_Pos (16U)
  7034. #define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
  7035. #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
  7036. #define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
  7037. #define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
  7038. #define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
  7039. #define FMC_BCR2_CBURSTRW_Pos (19U)
  7040. #define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
  7041. #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
  7042. /****************** Bit definition for FMC_BCR3 register *******************/
  7043. #define FMC_BCR3_MBKEN_Pos (0U)
  7044. #define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
  7045. #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
  7046. #define FMC_BCR3_MUXEN_Pos (1U)
  7047. #define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
  7048. #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  7049. #define FMC_BCR3_MTYP_Pos (2U)
  7050. #define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
  7051. #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  7052. #define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
  7053. #define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
  7054. #define FMC_BCR3_MWID_Pos (4U)
  7055. #define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
  7056. #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  7057. #define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
  7058. #define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
  7059. #define FMC_BCR3_FACCEN_Pos (6U)
  7060. #define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
  7061. #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
  7062. #define FMC_BCR3_BURSTEN_Pos (8U)
  7063. #define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
  7064. #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
  7065. #define FMC_BCR3_WAITPOL_Pos (9U)
  7066. #define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
  7067. #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
  7068. #define FMC_BCR3_WRAPMOD_Pos (10U)
  7069. #define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
  7070. #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
  7071. #define FMC_BCR3_WAITCFG_Pos (11U)
  7072. #define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
  7073. #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
  7074. #define FMC_BCR3_WREN_Pos (12U)
  7075. #define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
  7076. #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
  7077. #define FMC_BCR3_WAITEN_Pos (13U)
  7078. #define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
  7079. #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
  7080. #define FMC_BCR3_EXTMOD_Pos (14U)
  7081. #define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
  7082. #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
  7083. #define FMC_BCR3_ASYNCWAIT_Pos (15U)
  7084. #define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
  7085. #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
  7086. #define FMC_BCR3_CPSIZE_Pos (16U)
  7087. #define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
  7088. #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
  7089. #define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
  7090. #define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
  7091. #define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
  7092. #define FMC_BCR3_CBURSTRW_Pos (19U)
  7093. #define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
  7094. #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
  7095. /****************** Bit definition for FMC_BCR4 register *******************/
  7096. #define FMC_BCR4_MBKEN_Pos (0U)
  7097. #define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
  7098. #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
  7099. #define FMC_BCR4_MUXEN_Pos (1U)
  7100. #define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
  7101. #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
  7102. #define FMC_BCR4_MTYP_Pos (2U)
  7103. #define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
  7104. #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
  7105. #define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
  7106. #define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
  7107. #define FMC_BCR4_MWID_Pos (4U)
  7108. #define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
  7109. #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
  7110. #define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
  7111. #define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
  7112. #define FMC_BCR4_FACCEN_Pos (6U)
  7113. #define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
  7114. #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
  7115. #define FMC_BCR4_BURSTEN_Pos (8U)
  7116. #define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
  7117. #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
  7118. #define FMC_BCR4_WAITPOL_Pos (9U)
  7119. #define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
  7120. #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
  7121. #define FMC_BCR4_WRAPMOD_Pos (10U)
  7122. #define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
  7123. #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
  7124. #define FMC_BCR4_WAITCFG_Pos (11U)
  7125. #define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
  7126. #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
  7127. #define FMC_BCR4_WREN_Pos (12U)
  7128. #define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
  7129. #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
  7130. #define FMC_BCR4_WAITEN_Pos (13U)
  7131. #define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
  7132. #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
  7133. #define FMC_BCR4_EXTMOD_Pos (14U)
  7134. #define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
  7135. #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
  7136. #define FMC_BCR4_ASYNCWAIT_Pos (15U)
  7137. #define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
  7138. #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
  7139. #define FMC_BCR4_CPSIZE_Pos (16U)
  7140. #define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
  7141. #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
  7142. #define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
  7143. #define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
  7144. #define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
  7145. #define FMC_BCR4_CBURSTRW_Pos (19U)
  7146. #define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
  7147. #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
  7148. /****************** Bit definition for FMC_BTR1 register ******************/
  7149. #define FMC_BTR1_ADDSET_Pos (0U)
  7150. #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
  7151. #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7152. #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
  7153. #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
  7154. #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
  7155. #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
  7156. #define FMC_BTR1_ADDHLD_Pos (4U)
  7157. #define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  7158. #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7159. #define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
  7160. #define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
  7161. #define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
  7162. #define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
  7163. #define FMC_BTR1_DATAST_Pos (8U)
  7164. #define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
  7165. #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7166. #define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
  7167. #define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
  7168. #define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
  7169. #define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
  7170. #define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
  7171. #define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
  7172. #define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
  7173. #define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
  7174. #define FMC_BTR1_BUSTURN_Pos (16U)
  7175. #define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  7176. #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7177. #define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
  7178. #define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
  7179. #define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
  7180. #define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
  7181. #define FMC_BTR1_CLKDIV_Pos (20U)
  7182. #define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
  7183. #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7184. #define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
  7185. #define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
  7186. #define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
  7187. #define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
  7188. #define FMC_BTR1_DATLAT_Pos (24U)
  7189. #define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
  7190. #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7191. #define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
  7192. #define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
  7193. #define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
  7194. #define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
  7195. #define FMC_BTR1_ACCMOD_Pos (28U)
  7196. #define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
  7197. #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7198. #define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
  7199. #define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
  7200. /****************** Bit definition for FMC_BTR2 register *******************/
  7201. #define FMC_BTR2_ADDSET_Pos (0U)
  7202. #define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
  7203. #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7204. #define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
  7205. #define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
  7206. #define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
  7207. #define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
  7208. #define FMC_BTR2_ADDHLD_Pos (4U)
  7209. #define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  7210. #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7211. #define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
  7212. #define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
  7213. #define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
  7214. #define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
  7215. #define FMC_BTR2_DATAST_Pos (8U)
  7216. #define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
  7217. #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7218. #define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
  7219. #define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
  7220. #define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
  7221. #define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
  7222. #define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
  7223. #define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
  7224. #define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
  7225. #define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
  7226. #define FMC_BTR2_BUSTURN_Pos (16U)
  7227. #define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  7228. #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7229. #define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
  7230. #define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
  7231. #define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
  7232. #define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
  7233. #define FMC_BTR2_CLKDIV_Pos (20U)
  7234. #define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
  7235. #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7236. #define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
  7237. #define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
  7238. #define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
  7239. #define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
  7240. #define FMC_BTR2_DATLAT_Pos (24U)
  7241. #define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
  7242. #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7243. #define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
  7244. #define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
  7245. #define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
  7246. #define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
  7247. #define FMC_BTR2_ACCMOD_Pos (28U)
  7248. #define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
  7249. #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7250. #define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
  7251. #define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
  7252. /******************* Bit definition for FMC_BTR3 register *******************/
  7253. #define FMC_BTR3_ADDSET_Pos (0U)
  7254. #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
  7255. #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7256. #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
  7257. #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
  7258. #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
  7259. #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
  7260. #define FMC_BTR3_ADDHLD_Pos (4U)
  7261. #define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  7262. #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7263. #define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
  7264. #define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
  7265. #define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
  7266. #define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
  7267. #define FMC_BTR3_DATAST_Pos (8U)
  7268. #define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
  7269. #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7270. #define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
  7271. #define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
  7272. #define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
  7273. #define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
  7274. #define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
  7275. #define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
  7276. #define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
  7277. #define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
  7278. #define FMC_BTR3_BUSTURN_Pos (16U)
  7279. #define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  7280. #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7281. #define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
  7282. #define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
  7283. #define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
  7284. #define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
  7285. #define FMC_BTR3_CLKDIV_Pos (20U)
  7286. #define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
  7287. #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7288. #define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
  7289. #define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
  7290. #define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
  7291. #define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
  7292. #define FMC_BTR3_DATLAT_Pos (24U)
  7293. #define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
  7294. #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7295. #define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
  7296. #define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
  7297. #define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
  7298. #define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
  7299. #define FMC_BTR3_ACCMOD_Pos (28U)
  7300. #define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
  7301. #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7302. #define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
  7303. #define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
  7304. /****************** Bit definition for FMC_BTR4 register *******************/
  7305. #define FMC_BTR4_ADDSET_Pos (0U)
  7306. #define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
  7307. #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7308. #define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
  7309. #define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
  7310. #define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
  7311. #define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
  7312. #define FMC_BTR4_ADDHLD_Pos (4U)
  7313. #define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  7314. #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7315. #define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
  7316. #define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
  7317. #define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
  7318. #define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
  7319. #define FMC_BTR4_DATAST_Pos (8U)
  7320. #define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
  7321. #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7322. #define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
  7323. #define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
  7324. #define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
  7325. #define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
  7326. #define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
  7327. #define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
  7328. #define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
  7329. #define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
  7330. #define FMC_BTR4_BUSTURN_Pos (16U)
  7331. #define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  7332. #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
  7333. #define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
  7334. #define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
  7335. #define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
  7336. #define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
  7337. #define FMC_BTR4_CLKDIV_Pos (20U)
  7338. #define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
  7339. #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
  7340. #define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
  7341. #define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
  7342. #define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
  7343. #define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
  7344. #define FMC_BTR4_DATLAT_Pos (24U)
  7345. #define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
  7346. #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
  7347. #define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
  7348. #define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
  7349. #define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
  7350. #define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
  7351. #define FMC_BTR4_ACCMOD_Pos (28U)
  7352. #define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
  7353. #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7354. #define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
  7355. #define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
  7356. /****************** Bit definition for FMC_BWTR1 register ******************/
  7357. #define FMC_BWTR1_ADDSET_Pos (0U)
  7358. #define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
  7359. #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7360. #define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
  7361. #define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
  7362. #define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
  7363. #define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
  7364. #define FMC_BWTR1_ADDHLD_Pos (4U)
  7365. #define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
  7366. #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7367. #define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
  7368. #define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
  7369. #define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
  7370. #define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
  7371. #define FMC_BWTR1_DATAST_Pos (8U)
  7372. #define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
  7373. #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7374. #define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
  7375. #define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
  7376. #define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
  7377. #define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
  7378. #define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
  7379. #define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
  7380. #define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
  7381. #define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
  7382. #define FMC_BWTR1_BUSTURN_Pos (16U)
  7383. #define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
  7384. #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7385. #define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
  7386. #define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
  7387. #define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
  7388. #define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
  7389. #define FMC_BWTR1_ACCMOD_Pos (28U)
  7390. #define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
  7391. #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7392. #define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
  7393. #define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
  7394. /****************** Bit definition for FMC_BWTR2 register ******************/
  7395. #define FMC_BWTR2_ADDSET_Pos (0U)
  7396. #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
  7397. #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7398. #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
  7399. #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
  7400. #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
  7401. #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
  7402. #define FMC_BWTR2_ADDHLD_Pos (4U)
  7403. #define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
  7404. #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7405. #define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
  7406. #define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
  7407. #define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
  7408. #define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
  7409. #define FMC_BWTR2_DATAST_Pos (8U)
  7410. #define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
  7411. #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7412. #define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
  7413. #define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
  7414. #define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
  7415. #define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
  7416. #define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
  7417. #define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
  7418. #define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
  7419. #define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
  7420. #define FMC_BWTR2_BUSTURN_Pos (16U)
  7421. #define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
  7422. #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7423. #define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
  7424. #define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
  7425. #define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
  7426. #define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
  7427. #define FMC_BWTR2_ACCMOD_Pos (28U)
  7428. #define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
  7429. #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7430. #define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
  7431. #define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
  7432. /****************** Bit definition for FMC_BWTR3 register ******************/
  7433. #define FMC_BWTR3_ADDSET_Pos (0U)
  7434. #define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
  7435. #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7436. #define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
  7437. #define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
  7438. #define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
  7439. #define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
  7440. #define FMC_BWTR3_ADDHLD_Pos (4U)
  7441. #define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
  7442. #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7443. #define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
  7444. #define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
  7445. #define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
  7446. #define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
  7447. #define FMC_BWTR3_DATAST_Pos (8U)
  7448. #define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
  7449. #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7450. #define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
  7451. #define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
  7452. #define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
  7453. #define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
  7454. #define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
  7455. #define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
  7456. #define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
  7457. #define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
  7458. #define FMC_BWTR3_BUSTURN_Pos (16U)
  7459. #define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
  7460. #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7461. #define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
  7462. #define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
  7463. #define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
  7464. #define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
  7465. #define FMC_BWTR3_ACCMOD_Pos (28U)
  7466. #define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
  7467. #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7468. #define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
  7469. #define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
  7470. /****************** Bit definition for FMC_BWTR4 register ******************/
  7471. #define FMC_BWTR4_ADDSET_Pos (0U)
  7472. #define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
  7473. #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
  7474. #define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
  7475. #define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
  7476. #define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
  7477. #define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
  7478. #define FMC_BWTR4_ADDHLD_Pos (4U)
  7479. #define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
  7480. #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
  7481. #define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
  7482. #define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
  7483. #define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
  7484. #define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
  7485. #define FMC_BWTR4_DATAST_Pos (8U)
  7486. #define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
  7487. #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
  7488. #define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
  7489. #define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
  7490. #define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
  7491. #define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
  7492. #define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
  7493. #define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
  7494. #define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
  7495. #define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
  7496. #define FMC_BWTR4_BUSTURN_Pos (16U)
  7497. #define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
  7498. #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
  7499. #define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
  7500. #define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
  7501. #define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
  7502. #define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
  7503. #define FMC_BWTR4_ACCMOD_Pos (28U)
  7504. #define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
  7505. #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
  7506. #define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
  7507. #define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
  7508. /****************** Bit definition for FMC_PCR2 register *******************/
  7509. #define FMC_PCR2_PWAITEN_Pos (1U)
  7510. #define FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
  7511. #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
  7512. #define FMC_PCR2_PBKEN_Pos (2U)
  7513. #define FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
  7514. #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
  7515. #define FMC_PCR2_PTYP_Pos (3U)
  7516. #define FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
  7517. #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
  7518. #define FMC_PCR2_PWID_Pos (4U)
  7519. #define FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
  7520. #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
  7521. #define FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
  7522. #define FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
  7523. #define FMC_PCR2_ECCEN_Pos (6U)
  7524. #define FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
  7525. #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
  7526. #define FMC_PCR2_TCLR_Pos (9U)
  7527. #define FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
  7528. #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
  7529. #define FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
  7530. #define FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
  7531. #define FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
  7532. #define FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
  7533. #define FMC_PCR2_TAR_Pos (13U)
  7534. #define FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
  7535. #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
  7536. #define FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
  7537. #define FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
  7538. #define FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
  7539. #define FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
  7540. #define FMC_PCR2_ECCPS_Pos (17U)
  7541. #define FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
  7542. #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
  7543. #define FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
  7544. #define FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
  7545. #define FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
  7546. /****************** Bit definition for FMC_PCR3 register *******************/
  7547. #define FMC_PCR3_PWAITEN_Pos (1U)
  7548. #define FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
  7549. #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
  7550. #define FMC_PCR3_PBKEN_Pos (2U)
  7551. #define FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
  7552. #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
  7553. #define FMC_PCR3_PTYP_Pos (3U)
  7554. #define FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
  7555. #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
  7556. #define FMC_PCR3_PWID_Pos (4U)
  7557. #define FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
  7558. #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
  7559. #define FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
  7560. #define FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
  7561. #define FMC_PCR3_ECCEN_Pos (6U)
  7562. #define FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
  7563. #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
  7564. #define FMC_PCR3_TCLR_Pos (9U)
  7565. #define FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
  7566. #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
  7567. #define FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
  7568. #define FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
  7569. #define FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
  7570. #define FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
  7571. #define FMC_PCR3_TAR_Pos (13U)
  7572. #define FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
  7573. #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
  7574. #define FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
  7575. #define FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
  7576. #define FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
  7577. #define FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
  7578. #define FMC_PCR3_ECCPS_Pos (17U)
  7579. #define FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
  7580. #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
  7581. #define FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
  7582. #define FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
  7583. #define FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
  7584. /****************** Bit definition for FMC_PCR4 register *******************/
  7585. #define FMC_PCR4_PWAITEN_Pos (1U)
  7586. #define FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
  7587. #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
  7588. #define FMC_PCR4_PBKEN_Pos (2U)
  7589. #define FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
  7590. #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
  7591. #define FMC_PCR4_PTYP_Pos (3U)
  7592. #define FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
  7593. #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
  7594. #define FMC_PCR4_PWID_Pos (4U)
  7595. #define FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
  7596. #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
  7597. #define FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
  7598. #define FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
  7599. #define FMC_PCR4_ECCEN_Pos (6U)
  7600. #define FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
  7601. #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
  7602. #define FMC_PCR4_TCLR_Pos (9U)
  7603. #define FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
  7604. #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
  7605. #define FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
  7606. #define FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
  7607. #define FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
  7608. #define FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
  7609. #define FMC_PCR4_TAR_Pos (13U)
  7610. #define FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
  7611. #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
  7612. #define FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
  7613. #define FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
  7614. #define FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
  7615. #define FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
  7616. #define FMC_PCR4_ECCPS_Pos (17U)
  7617. #define FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
  7618. #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
  7619. #define FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
  7620. #define FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
  7621. #define FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
  7622. /******************* Bit definition for FMC_SR2 register *******************/
  7623. #define FMC_SR2_IRS_Pos (0U)
  7624. #define FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
  7625. #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
  7626. #define FMC_SR2_ILS_Pos (1U)
  7627. #define FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
  7628. #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
  7629. #define FMC_SR2_IFS_Pos (2U)
  7630. #define FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
  7631. #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
  7632. #define FMC_SR2_IREN_Pos (3U)
  7633. #define FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
  7634. #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
  7635. #define FMC_SR2_ILEN_Pos (4U)
  7636. #define FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
  7637. #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
  7638. #define FMC_SR2_IFEN_Pos (5U)
  7639. #define FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
  7640. #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
  7641. #define FMC_SR2_FEMPT_Pos (6U)
  7642. #define FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
  7643. #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
  7644. /******************* Bit definition for FMC_SR3 register *******************/
  7645. #define FMC_SR3_IRS_Pos (0U)
  7646. #define FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
  7647. #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
  7648. #define FMC_SR3_ILS_Pos (1U)
  7649. #define FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
  7650. #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
  7651. #define FMC_SR3_IFS_Pos (2U)
  7652. #define FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
  7653. #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
  7654. #define FMC_SR3_IREN_Pos (3U)
  7655. #define FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
  7656. #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
  7657. #define FMC_SR3_ILEN_Pos (4U)
  7658. #define FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
  7659. #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
  7660. #define FMC_SR3_IFEN_Pos (5U)
  7661. #define FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
  7662. #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
  7663. #define FMC_SR3_FEMPT_Pos (6U)
  7664. #define FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
  7665. #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
  7666. /******************* Bit definition for FMC_SR4 register *******************/
  7667. #define FMC_SR4_IRS_Pos (0U)
  7668. #define FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
  7669. #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
  7670. #define FMC_SR4_ILS_Pos (1U)
  7671. #define FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
  7672. #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
  7673. #define FMC_SR4_IFS_Pos (2U)
  7674. #define FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
  7675. #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
  7676. #define FMC_SR4_IREN_Pos (3U)
  7677. #define FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
  7678. #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
  7679. #define FMC_SR4_ILEN_Pos (4U)
  7680. #define FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
  7681. #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
  7682. #define FMC_SR4_IFEN_Pos (5U)
  7683. #define FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
  7684. #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
  7685. #define FMC_SR4_FEMPT_Pos (6U)
  7686. #define FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
  7687. #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
  7688. /****************** Bit definition for FMC_PMEM2 register ******************/
  7689. #define FMC_PMEM2_MEMSET2_Pos (0U)
  7690. #define FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
  7691. #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
  7692. #define FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
  7693. #define FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
  7694. #define FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
  7695. #define FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
  7696. #define FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
  7697. #define FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
  7698. #define FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
  7699. #define FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
  7700. #define FMC_PMEM2_MEMWAIT2_Pos (8U)
  7701. #define FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
  7702. #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
  7703. #define FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
  7704. #define FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
  7705. #define FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
  7706. #define FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
  7707. #define FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
  7708. #define FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
  7709. #define FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
  7710. #define FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
  7711. #define FMC_PMEM2_MEMHOLD2_Pos (16U)
  7712. #define FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
  7713. #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
  7714. #define FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
  7715. #define FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
  7716. #define FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
  7717. #define FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
  7718. #define FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
  7719. #define FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
  7720. #define FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
  7721. #define FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
  7722. #define FMC_PMEM2_MEMHIZ2_Pos (24U)
  7723. #define FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
  7724. #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
  7725. #define FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
  7726. #define FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
  7727. #define FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
  7728. #define FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
  7729. #define FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
  7730. #define FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
  7731. #define FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
  7732. #define FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
  7733. /****************** Bit definition for FMC_PMEM3 register ******************/
  7734. #define FMC_PMEM3_MEMSET3_Pos (0U)
  7735. #define FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
  7736. #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
  7737. #define FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
  7738. #define FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
  7739. #define FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
  7740. #define FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
  7741. #define FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
  7742. #define FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
  7743. #define FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
  7744. #define FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
  7745. #define FMC_PMEM3_MEMWAIT3_Pos (8U)
  7746. #define FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
  7747. #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
  7748. #define FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
  7749. #define FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
  7750. #define FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
  7751. #define FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
  7752. #define FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
  7753. #define FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
  7754. #define FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
  7755. #define FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
  7756. #define FMC_PMEM3_MEMHOLD3_Pos (16U)
  7757. #define FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
  7758. #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
  7759. #define FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
  7760. #define FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
  7761. #define FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
  7762. #define FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
  7763. #define FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
  7764. #define FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
  7765. #define FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
  7766. #define FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
  7767. #define FMC_PMEM3_MEMHIZ3_Pos (24U)
  7768. #define FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
  7769. #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
  7770. #define FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
  7771. #define FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
  7772. #define FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
  7773. #define FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
  7774. #define FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
  7775. #define FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
  7776. #define FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
  7777. #define FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
  7778. /****************** Bit definition for FMC_PMEM4 register ******************/
  7779. #define FMC_PMEM4_MEMSET4_Pos (0U)
  7780. #define FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
  7781. #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
  7782. #define FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
  7783. #define FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
  7784. #define FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
  7785. #define FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
  7786. #define FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
  7787. #define FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
  7788. #define FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
  7789. #define FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
  7790. #define FMC_PMEM4_MEMWAIT4_Pos (8U)
  7791. #define FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
  7792. #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
  7793. #define FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
  7794. #define FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
  7795. #define FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
  7796. #define FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
  7797. #define FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
  7798. #define FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
  7799. #define FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
  7800. #define FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
  7801. #define FMC_PMEM4_MEMHOLD4_Pos (16U)
  7802. #define FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
  7803. #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
  7804. #define FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
  7805. #define FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
  7806. #define FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
  7807. #define FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
  7808. #define FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
  7809. #define FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
  7810. #define FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
  7811. #define FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
  7812. #define FMC_PMEM4_MEMHIZ4_Pos (24U)
  7813. #define FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
  7814. #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
  7815. #define FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
  7816. #define FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
  7817. #define FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
  7818. #define FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
  7819. #define FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
  7820. #define FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
  7821. #define FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
  7822. #define FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
  7823. /****************** Bit definition for FMC_PATT2 register ******************/
  7824. #define FMC_PATT2_ATTSET2_Pos (0U)
  7825. #define FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
  7826. #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
  7827. #define FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
  7828. #define FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
  7829. #define FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
  7830. #define FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
  7831. #define FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
  7832. #define FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
  7833. #define FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
  7834. #define FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
  7835. #define FMC_PATT2_ATTWAIT2_Pos (8U)
  7836. #define FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
  7837. #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
  7838. #define FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
  7839. #define FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
  7840. #define FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
  7841. #define FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
  7842. #define FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
  7843. #define FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
  7844. #define FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
  7845. #define FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
  7846. #define FMC_PATT2_ATTHOLD2_Pos (16U)
  7847. #define FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
  7848. #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
  7849. #define FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
  7850. #define FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
  7851. #define FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
  7852. #define FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
  7853. #define FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
  7854. #define FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
  7855. #define FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
  7856. #define FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
  7857. #define FMC_PATT2_ATTHIZ2_Pos (24U)
  7858. #define FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
  7859. #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
  7860. #define FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
  7861. #define FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
  7862. #define FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
  7863. #define FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
  7864. #define FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
  7865. #define FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
  7866. #define FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
  7867. #define FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
  7868. /****************** Bit definition for FMC_PATT3 register ******************/
  7869. #define FMC_PATT3_ATTSET3_Pos (0U)
  7870. #define FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
  7871. #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
  7872. #define FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
  7873. #define FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
  7874. #define FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
  7875. #define FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
  7876. #define FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
  7877. #define FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
  7878. #define FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
  7879. #define FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
  7880. #define FMC_PATT3_ATTWAIT3_Pos (8U)
  7881. #define FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
  7882. #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
  7883. #define FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
  7884. #define FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
  7885. #define FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
  7886. #define FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
  7887. #define FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
  7888. #define FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
  7889. #define FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
  7890. #define FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
  7891. #define FMC_PATT3_ATTHOLD3_Pos (16U)
  7892. #define FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
  7893. #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
  7894. #define FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
  7895. #define FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
  7896. #define FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
  7897. #define FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
  7898. #define FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
  7899. #define FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
  7900. #define FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
  7901. #define FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
  7902. #define FMC_PATT3_ATTHIZ3_Pos (24U)
  7903. #define FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
  7904. #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
  7905. #define FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
  7906. #define FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
  7907. #define FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
  7908. #define FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
  7909. #define FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
  7910. #define FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
  7911. #define FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
  7912. #define FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
  7913. /****************** Bit definition for FMC_PATT4 register ******************/
  7914. #define FMC_PATT4_ATTSET4_Pos (0U)
  7915. #define FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
  7916. #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
  7917. #define FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
  7918. #define FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
  7919. #define FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
  7920. #define FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
  7921. #define FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
  7922. #define FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
  7923. #define FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
  7924. #define FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
  7925. #define FMC_PATT4_ATTWAIT4_Pos (8U)
  7926. #define FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
  7927. #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
  7928. #define FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
  7929. #define FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
  7930. #define FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
  7931. #define FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
  7932. #define FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
  7933. #define FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
  7934. #define FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
  7935. #define FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
  7936. #define FMC_PATT4_ATTHOLD4_Pos (16U)
  7937. #define FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
  7938. #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
  7939. #define FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
  7940. #define FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
  7941. #define FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
  7942. #define FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
  7943. #define FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
  7944. #define FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
  7945. #define FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
  7946. #define FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
  7947. #define FMC_PATT4_ATTHIZ4_Pos (24U)
  7948. #define FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
  7949. #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
  7950. #define FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
  7951. #define FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
  7952. #define FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
  7953. #define FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
  7954. #define FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
  7955. #define FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
  7956. #define FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
  7957. #define FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
  7958. /****************** Bit definition for FMC_PIO4 register *******************/
  7959. #define FMC_PIO4_IOSET4_Pos (0U)
  7960. #define FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
  7961. #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
  7962. #define FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
  7963. #define FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
  7964. #define FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
  7965. #define FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
  7966. #define FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
  7967. #define FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
  7968. #define FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
  7969. #define FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
  7970. #define FMC_PIO4_IOWAIT4_Pos (8U)
  7971. #define FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
  7972. #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
  7973. #define FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
  7974. #define FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
  7975. #define FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
  7976. #define FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
  7977. #define FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
  7978. #define FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
  7979. #define FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
  7980. #define FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
  7981. #define FMC_PIO4_IOHOLD4_Pos (16U)
  7982. #define FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
  7983. #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
  7984. #define FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
  7985. #define FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
  7986. #define FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
  7987. #define FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
  7988. #define FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
  7989. #define FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
  7990. #define FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
  7991. #define FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
  7992. #define FMC_PIO4_IOHIZ4_Pos (24U)
  7993. #define FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
  7994. #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
  7995. #define FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
  7996. #define FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
  7997. #define FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
  7998. #define FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
  7999. #define FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
  8000. #define FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
  8001. #define FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
  8002. #define FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
  8003. /****************** Bit definition for FMC_ECCR2 register ******************/
  8004. #define FMC_ECCR2_ECC2_Pos (0U)
  8005. #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
  8006. #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
  8007. /****************** Bit definition for FMC_ECCR3 register ******************/
  8008. #define FMC_ECCR3_ECC3_Pos (0U)
  8009. #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
  8010. #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
  8011. /****************** Bit definition for FMC_SDCR1 register ******************/
  8012. #define FMC_SDCR1_NC_Pos (0U)
  8013. #define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
  8014. #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
  8015. #define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
  8016. #define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
  8017. #define FMC_SDCR1_NR_Pos (2U)
  8018. #define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
  8019. #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
  8020. #define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
  8021. #define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
  8022. #define FMC_SDCR1_MWID_Pos (4U)
  8023. #define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
  8024. #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
  8025. #define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
  8026. #define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
  8027. #define FMC_SDCR1_NB_Pos (6U)
  8028. #define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
  8029. #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
  8030. #define FMC_SDCR1_CAS_Pos (7U)
  8031. #define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
  8032. #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
  8033. #define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
  8034. #define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
  8035. #define FMC_SDCR1_WP_Pos (9U)
  8036. #define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
  8037. #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
  8038. #define FMC_SDCR1_SDCLK_Pos (10U)
  8039. #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
  8040. #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
  8041. #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
  8042. #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
  8043. #define FMC_SDCR1_RBURST_Pos (12U)
  8044. #define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
  8045. #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
  8046. #define FMC_SDCR1_RPIPE_Pos (13U)
  8047. #define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
  8048. #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
  8049. #define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
  8050. #define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
  8051. /****************** Bit definition for FMC_SDCR2 register ******************/
  8052. #define FMC_SDCR2_NC_Pos (0U)
  8053. #define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
  8054. #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
  8055. #define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
  8056. #define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
  8057. #define FMC_SDCR2_NR_Pos (2U)
  8058. #define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
  8059. #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
  8060. #define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
  8061. #define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
  8062. #define FMC_SDCR2_MWID_Pos (4U)
  8063. #define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
  8064. #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
  8065. #define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
  8066. #define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
  8067. #define FMC_SDCR2_NB_Pos (6U)
  8068. #define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
  8069. #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
  8070. #define FMC_SDCR2_CAS_Pos (7U)
  8071. #define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
  8072. #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
  8073. #define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
  8074. #define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
  8075. #define FMC_SDCR2_WP_Pos (9U)
  8076. #define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
  8077. #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
  8078. #define FMC_SDCR2_SDCLK_Pos (10U)
  8079. #define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
  8080. #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
  8081. #define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
  8082. #define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
  8083. #define FMC_SDCR2_RBURST_Pos (12U)
  8084. #define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
  8085. #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
  8086. #define FMC_SDCR2_RPIPE_Pos (13U)
  8087. #define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
  8088. #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
  8089. #define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
  8090. #define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
  8091. /****************** Bit definition for FMC_SDTR1 register ******************/
  8092. #define FMC_SDTR1_TMRD_Pos (0U)
  8093. #define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
  8094. #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
  8095. #define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
  8096. #define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
  8097. #define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
  8098. #define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
  8099. #define FMC_SDTR1_TXSR_Pos (4U)
  8100. #define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
  8101. #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
  8102. #define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
  8103. #define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
  8104. #define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
  8105. #define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
  8106. #define FMC_SDTR1_TRAS_Pos (8U)
  8107. #define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
  8108. #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
  8109. #define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
  8110. #define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
  8111. #define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
  8112. #define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
  8113. #define FMC_SDTR1_TRC_Pos (12U)
  8114. #define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
  8115. #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
  8116. #define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
  8117. #define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
  8118. #define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
  8119. #define FMC_SDTR1_TWR_Pos (16U)
  8120. #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
  8121. #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
  8122. #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
  8123. #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
  8124. #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
  8125. #define FMC_SDTR1_TRP_Pos (20U)
  8126. #define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
  8127. #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
  8128. #define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
  8129. #define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
  8130. #define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
  8131. #define FMC_SDTR1_TRCD_Pos (24U)
  8132. #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
  8133. #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
  8134. #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
  8135. #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
  8136. #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
  8137. /****************** Bit definition for FMC_SDTR2 register ******************/
  8138. #define FMC_SDTR2_TMRD_Pos (0U)
  8139. #define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
  8140. #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
  8141. #define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
  8142. #define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
  8143. #define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
  8144. #define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
  8145. #define FMC_SDTR2_TXSR_Pos (4U)
  8146. #define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
  8147. #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
  8148. #define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
  8149. #define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
  8150. #define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
  8151. #define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
  8152. #define FMC_SDTR2_TRAS_Pos (8U)
  8153. #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
  8154. #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
  8155. #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
  8156. #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
  8157. #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
  8158. #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
  8159. #define FMC_SDTR2_TRC_Pos (12U)
  8160. #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
  8161. #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
  8162. #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
  8163. #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
  8164. #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
  8165. #define FMC_SDTR2_TWR_Pos (16U)
  8166. #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
  8167. #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
  8168. #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
  8169. #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
  8170. #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
  8171. #define FMC_SDTR2_TRP_Pos (20U)
  8172. #define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
  8173. #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
  8174. #define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
  8175. #define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
  8176. #define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
  8177. #define FMC_SDTR2_TRCD_Pos (24U)
  8178. #define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
  8179. #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
  8180. #define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
  8181. #define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
  8182. #define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
  8183. /****************** Bit definition for FMC_SDCMR register ******************/
  8184. #define FMC_SDCMR_MODE_Pos (0U)
  8185. #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
  8186. #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
  8187. #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
  8188. #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
  8189. #define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
  8190. #define FMC_SDCMR_CTB2_Pos (3U)
  8191. #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
  8192. #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
  8193. #define FMC_SDCMR_CTB1_Pos (4U)
  8194. #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
  8195. #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
  8196. #define FMC_SDCMR_NRFS_Pos (5U)
  8197. #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
  8198. #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
  8199. #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
  8200. #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
  8201. #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
  8202. #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
  8203. #define FMC_SDCMR_MRD_Pos (9U)
  8204. #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
  8205. #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
  8206. /****************** Bit definition for FMC_SDRTR register ******************/
  8207. #define FMC_SDRTR_CRE_Pos (0U)
  8208. #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
  8209. #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
  8210. #define FMC_SDRTR_COUNT_Pos (1U)
  8211. #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
  8212. #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
  8213. #define FMC_SDRTR_REIE_Pos (14U)
  8214. #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
  8215. #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
  8216. /****************** Bit definition for FMC_SDSR register ******************/
  8217. #define FMC_SDSR_RE_Pos (0U)
  8218. #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
  8219. #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
  8220. #define FMC_SDSR_MODES1_Pos (1U)
  8221. #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
  8222. #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
  8223. #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
  8224. #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
  8225. #define FMC_SDSR_MODES2_Pos (3U)
  8226. #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
  8227. #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
  8228. #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
  8229. #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
  8230. #define FMC_SDSR_BUSY_Pos (5U)
  8231. #define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
  8232. #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
  8233. /******************************************************************************/
  8234. /* */
  8235. /* General Purpose I/O */
  8236. /* */
  8237. /******************************************************************************/
  8238. /****************** Bits definition for GPIO_MODER register *****************/
  8239. #define GPIO_MODER_MODER0_Pos (0U)
  8240. #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  8241. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  8242. #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  8243. #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  8244. #define GPIO_MODER_MODER1_Pos (2U)
  8245. #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  8246. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  8247. #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  8248. #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  8249. #define GPIO_MODER_MODER2_Pos (4U)
  8250. #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  8251. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  8252. #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  8253. #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  8254. #define GPIO_MODER_MODER3_Pos (6U)
  8255. #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  8256. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  8257. #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  8258. #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  8259. #define GPIO_MODER_MODER4_Pos (8U)
  8260. #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  8261. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  8262. #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  8263. #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  8264. #define GPIO_MODER_MODER5_Pos (10U)
  8265. #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  8266. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  8267. #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  8268. #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  8269. #define GPIO_MODER_MODER6_Pos (12U)
  8270. #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  8271. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  8272. #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  8273. #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  8274. #define GPIO_MODER_MODER7_Pos (14U)
  8275. #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  8276. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  8277. #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  8278. #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  8279. #define GPIO_MODER_MODER8_Pos (16U)
  8280. #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  8281. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  8282. #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  8283. #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  8284. #define GPIO_MODER_MODER9_Pos (18U)
  8285. #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  8286. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  8287. #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  8288. #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  8289. #define GPIO_MODER_MODER10_Pos (20U)
  8290. #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  8291. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  8292. #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  8293. #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  8294. #define GPIO_MODER_MODER11_Pos (22U)
  8295. #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  8296. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  8297. #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  8298. #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  8299. #define GPIO_MODER_MODER12_Pos (24U)
  8300. #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  8301. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  8302. #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  8303. #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  8304. #define GPIO_MODER_MODER13_Pos (26U)
  8305. #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  8306. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  8307. #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  8308. #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  8309. #define GPIO_MODER_MODER14_Pos (28U)
  8310. #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  8311. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  8312. #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  8313. #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  8314. #define GPIO_MODER_MODER15_Pos (30U)
  8315. #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  8316. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  8317. #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  8318. #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  8319. /* Legacy defines */
  8320. #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
  8321. #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
  8322. #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
  8323. #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
  8324. #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
  8325. #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
  8326. #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
  8327. #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
  8328. #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
  8329. #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
  8330. #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
  8331. #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
  8332. #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
  8333. #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
  8334. #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
  8335. #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
  8336. #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
  8337. #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
  8338. #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
  8339. #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
  8340. #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
  8341. #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
  8342. #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
  8343. #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
  8344. #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
  8345. #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
  8346. #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
  8347. #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
  8348. #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
  8349. #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
  8350. #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
  8351. #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
  8352. #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
  8353. #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
  8354. #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
  8355. #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
  8356. #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
  8357. #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
  8358. #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
  8359. #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
  8360. #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
  8361. #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
  8362. #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
  8363. #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
  8364. #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
  8365. #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
  8366. #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
  8367. #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
  8368. #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
  8369. #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
  8370. #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
  8371. #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
  8372. #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
  8373. #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
  8374. #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
  8375. #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
  8376. #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
  8377. #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
  8378. #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
  8379. #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
  8380. #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
  8381. #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
  8382. #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
  8383. #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
  8384. #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
  8385. #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
  8386. #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
  8387. #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
  8388. #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
  8389. #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
  8390. #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
  8391. #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
  8392. #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
  8393. #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
  8394. #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
  8395. #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
  8396. #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
  8397. #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
  8398. #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
  8399. #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
  8400. /****************** Bits definition for GPIO_OTYPER register ****************/
  8401. #define GPIO_OTYPER_OT0_Pos (0U)
  8402. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  8403. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  8404. #define GPIO_OTYPER_OT1_Pos (1U)
  8405. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  8406. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  8407. #define GPIO_OTYPER_OT2_Pos (2U)
  8408. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  8409. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  8410. #define GPIO_OTYPER_OT3_Pos (3U)
  8411. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  8412. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  8413. #define GPIO_OTYPER_OT4_Pos (4U)
  8414. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  8415. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  8416. #define GPIO_OTYPER_OT5_Pos (5U)
  8417. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  8418. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  8419. #define GPIO_OTYPER_OT6_Pos (6U)
  8420. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  8421. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  8422. #define GPIO_OTYPER_OT7_Pos (7U)
  8423. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  8424. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  8425. #define GPIO_OTYPER_OT8_Pos (8U)
  8426. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  8427. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  8428. #define GPIO_OTYPER_OT9_Pos (9U)
  8429. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  8430. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  8431. #define GPIO_OTYPER_OT10_Pos (10U)
  8432. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  8433. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  8434. #define GPIO_OTYPER_OT11_Pos (11U)
  8435. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  8436. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  8437. #define GPIO_OTYPER_OT12_Pos (12U)
  8438. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  8439. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  8440. #define GPIO_OTYPER_OT13_Pos (13U)
  8441. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  8442. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  8443. #define GPIO_OTYPER_OT14_Pos (14U)
  8444. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  8445. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  8446. #define GPIO_OTYPER_OT15_Pos (15U)
  8447. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  8448. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  8449. /* Legacy defines */
  8450. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  8451. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  8452. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  8453. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  8454. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  8455. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  8456. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  8457. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  8458. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  8459. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  8460. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  8461. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  8462. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  8463. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  8464. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  8465. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  8466. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  8467. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  8468. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  8469. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  8470. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  8471. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  8472. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  8473. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  8474. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  8475. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  8476. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  8477. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  8478. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  8479. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  8480. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  8481. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  8482. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  8483. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  8484. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  8485. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  8486. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  8487. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  8488. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  8489. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  8490. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  8491. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  8492. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  8493. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  8494. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  8495. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  8496. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  8497. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  8498. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  8499. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  8500. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  8501. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  8502. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  8503. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  8504. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  8505. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  8506. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  8507. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  8508. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  8509. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  8510. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  8511. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  8512. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  8513. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  8514. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  8515. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  8516. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  8517. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  8518. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  8519. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  8520. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  8521. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  8522. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  8523. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  8524. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  8525. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  8526. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  8527. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  8528. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  8529. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  8530. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  8531. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  8532. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  8533. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  8534. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  8535. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  8536. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  8537. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  8538. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  8539. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  8540. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  8541. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  8542. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  8543. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  8544. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  8545. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  8546. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  8547. /* Legacy defines */
  8548. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  8549. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  8550. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  8551. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  8552. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  8553. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  8554. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  8555. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  8556. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  8557. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  8558. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  8559. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  8560. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  8561. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  8562. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  8563. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  8564. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  8565. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  8566. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  8567. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  8568. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  8569. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  8570. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  8571. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  8572. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  8573. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  8574. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  8575. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  8576. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  8577. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  8578. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  8579. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  8580. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  8581. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  8582. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  8583. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  8584. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  8585. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  8586. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  8587. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  8588. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  8589. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  8590. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  8591. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  8592. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  8593. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  8594. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  8595. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  8596. /****************** Bits definition for GPIO_PUPDR register *****************/
  8597. #define GPIO_PUPDR_PUPD0_Pos (0U)
  8598. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  8599. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  8600. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  8601. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  8602. #define GPIO_PUPDR_PUPD1_Pos (2U)
  8603. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  8604. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  8605. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  8606. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  8607. #define GPIO_PUPDR_PUPD2_Pos (4U)
  8608. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  8609. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  8610. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  8611. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  8612. #define GPIO_PUPDR_PUPD3_Pos (6U)
  8613. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  8614. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  8615. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  8616. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  8617. #define GPIO_PUPDR_PUPD4_Pos (8U)
  8618. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  8619. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  8620. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  8621. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  8622. #define GPIO_PUPDR_PUPD5_Pos (10U)
  8623. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  8624. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  8625. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  8626. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  8627. #define GPIO_PUPDR_PUPD6_Pos (12U)
  8628. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  8629. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  8630. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  8631. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  8632. #define GPIO_PUPDR_PUPD7_Pos (14U)
  8633. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  8634. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  8635. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  8636. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  8637. #define GPIO_PUPDR_PUPD8_Pos (16U)
  8638. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  8639. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  8640. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  8641. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  8642. #define GPIO_PUPDR_PUPD9_Pos (18U)
  8643. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  8644. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  8645. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  8646. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  8647. #define GPIO_PUPDR_PUPD10_Pos (20U)
  8648. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  8649. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  8650. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  8651. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  8652. #define GPIO_PUPDR_PUPD11_Pos (22U)
  8653. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  8654. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  8655. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  8656. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  8657. #define GPIO_PUPDR_PUPD12_Pos (24U)
  8658. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  8659. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  8660. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  8661. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  8662. #define GPIO_PUPDR_PUPD13_Pos (26U)
  8663. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  8664. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  8665. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  8666. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  8667. #define GPIO_PUPDR_PUPD14_Pos (28U)
  8668. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  8669. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  8670. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  8671. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  8672. #define GPIO_PUPDR_PUPD15_Pos (30U)
  8673. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  8674. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  8675. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  8676. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  8677. /* Legacy defines */
  8678. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  8679. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  8680. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  8681. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  8682. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  8683. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  8684. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  8685. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  8686. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  8687. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  8688. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  8689. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  8690. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  8691. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  8692. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  8693. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  8694. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  8695. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  8696. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  8697. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  8698. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  8699. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  8700. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  8701. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  8702. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  8703. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  8704. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  8705. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  8706. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  8707. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  8708. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  8709. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  8710. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  8711. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  8712. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  8713. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  8714. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  8715. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  8716. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  8717. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  8718. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  8719. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  8720. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  8721. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  8722. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  8723. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  8724. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  8725. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  8726. /****************** Bits definition for GPIO_IDR register *******************/
  8727. #define GPIO_IDR_ID0_Pos (0U)
  8728. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  8729. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  8730. #define GPIO_IDR_ID1_Pos (1U)
  8731. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  8732. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  8733. #define GPIO_IDR_ID2_Pos (2U)
  8734. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  8735. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  8736. #define GPIO_IDR_ID3_Pos (3U)
  8737. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  8738. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  8739. #define GPIO_IDR_ID4_Pos (4U)
  8740. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  8741. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  8742. #define GPIO_IDR_ID5_Pos (5U)
  8743. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  8744. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  8745. #define GPIO_IDR_ID6_Pos (6U)
  8746. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  8747. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  8748. #define GPIO_IDR_ID7_Pos (7U)
  8749. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  8750. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  8751. #define GPIO_IDR_ID8_Pos (8U)
  8752. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  8753. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  8754. #define GPIO_IDR_ID9_Pos (9U)
  8755. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  8756. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  8757. #define GPIO_IDR_ID10_Pos (10U)
  8758. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  8759. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  8760. #define GPIO_IDR_ID11_Pos (11U)
  8761. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  8762. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  8763. #define GPIO_IDR_ID12_Pos (12U)
  8764. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  8765. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  8766. #define GPIO_IDR_ID13_Pos (13U)
  8767. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  8768. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  8769. #define GPIO_IDR_ID14_Pos (14U)
  8770. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  8771. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  8772. #define GPIO_IDR_ID15_Pos (15U)
  8773. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  8774. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  8775. /* Legacy defines */
  8776. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  8777. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  8778. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  8779. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  8780. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  8781. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  8782. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  8783. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  8784. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  8785. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  8786. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  8787. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  8788. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  8789. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  8790. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  8791. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  8792. /****************** Bits definition for GPIO_ODR register *******************/
  8793. #define GPIO_ODR_OD0_Pos (0U)
  8794. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  8795. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  8796. #define GPIO_ODR_OD1_Pos (1U)
  8797. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  8798. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  8799. #define GPIO_ODR_OD2_Pos (2U)
  8800. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  8801. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  8802. #define GPIO_ODR_OD3_Pos (3U)
  8803. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  8804. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  8805. #define GPIO_ODR_OD4_Pos (4U)
  8806. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  8807. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  8808. #define GPIO_ODR_OD5_Pos (5U)
  8809. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  8810. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  8811. #define GPIO_ODR_OD6_Pos (6U)
  8812. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  8813. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  8814. #define GPIO_ODR_OD7_Pos (7U)
  8815. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  8816. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  8817. #define GPIO_ODR_OD8_Pos (8U)
  8818. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  8819. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  8820. #define GPIO_ODR_OD9_Pos (9U)
  8821. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  8822. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  8823. #define GPIO_ODR_OD10_Pos (10U)
  8824. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  8825. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  8826. #define GPIO_ODR_OD11_Pos (11U)
  8827. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  8828. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  8829. #define GPIO_ODR_OD12_Pos (12U)
  8830. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  8831. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  8832. #define GPIO_ODR_OD13_Pos (13U)
  8833. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  8834. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  8835. #define GPIO_ODR_OD14_Pos (14U)
  8836. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  8837. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  8838. #define GPIO_ODR_OD15_Pos (15U)
  8839. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  8840. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  8841. /* Legacy defines */
  8842. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  8843. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  8844. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  8845. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  8846. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  8847. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  8848. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  8849. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  8850. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  8851. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  8852. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  8853. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  8854. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  8855. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  8856. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  8857. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  8858. /****************** Bits definition for GPIO_BSRR register ******************/
  8859. #define GPIO_BSRR_BS0_Pos (0U)
  8860. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  8861. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  8862. #define GPIO_BSRR_BS1_Pos (1U)
  8863. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  8864. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  8865. #define GPIO_BSRR_BS2_Pos (2U)
  8866. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  8867. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  8868. #define GPIO_BSRR_BS3_Pos (3U)
  8869. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  8870. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  8871. #define GPIO_BSRR_BS4_Pos (4U)
  8872. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  8873. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  8874. #define GPIO_BSRR_BS5_Pos (5U)
  8875. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  8876. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  8877. #define GPIO_BSRR_BS6_Pos (6U)
  8878. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  8879. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  8880. #define GPIO_BSRR_BS7_Pos (7U)
  8881. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  8882. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  8883. #define GPIO_BSRR_BS8_Pos (8U)
  8884. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  8885. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  8886. #define GPIO_BSRR_BS9_Pos (9U)
  8887. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  8888. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  8889. #define GPIO_BSRR_BS10_Pos (10U)
  8890. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  8891. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  8892. #define GPIO_BSRR_BS11_Pos (11U)
  8893. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  8894. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  8895. #define GPIO_BSRR_BS12_Pos (12U)
  8896. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  8897. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  8898. #define GPIO_BSRR_BS13_Pos (13U)
  8899. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  8900. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  8901. #define GPIO_BSRR_BS14_Pos (14U)
  8902. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  8903. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  8904. #define GPIO_BSRR_BS15_Pos (15U)
  8905. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  8906. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  8907. #define GPIO_BSRR_BR0_Pos (16U)
  8908. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  8909. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  8910. #define GPIO_BSRR_BR1_Pos (17U)
  8911. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  8912. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  8913. #define GPIO_BSRR_BR2_Pos (18U)
  8914. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  8915. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  8916. #define GPIO_BSRR_BR3_Pos (19U)
  8917. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  8918. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  8919. #define GPIO_BSRR_BR4_Pos (20U)
  8920. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  8921. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  8922. #define GPIO_BSRR_BR5_Pos (21U)
  8923. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  8924. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  8925. #define GPIO_BSRR_BR6_Pos (22U)
  8926. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  8927. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  8928. #define GPIO_BSRR_BR7_Pos (23U)
  8929. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  8930. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  8931. #define GPIO_BSRR_BR8_Pos (24U)
  8932. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  8933. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  8934. #define GPIO_BSRR_BR9_Pos (25U)
  8935. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  8936. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  8937. #define GPIO_BSRR_BR10_Pos (26U)
  8938. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  8939. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  8940. #define GPIO_BSRR_BR11_Pos (27U)
  8941. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  8942. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  8943. #define GPIO_BSRR_BR12_Pos (28U)
  8944. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  8945. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  8946. #define GPIO_BSRR_BR13_Pos (29U)
  8947. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  8948. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  8949. #define GPIO_BSRR_BR14_Pos (30U)
  8950. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  8951. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  8952. #define GPIO_BSRR_BR15_Pos (31U)
  8953. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  8954. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  8955. /* Legacy defines */
  8956. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  8957. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  8958. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  8959. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  8960. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  8961. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  8962. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  8963. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  8964. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  8965. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  8966. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  8967. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  8968. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  8969. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  8970. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  8971. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  8972. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  8973. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  8974. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  8975. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  8976. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  8977. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  8978. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  8979. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  8980. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  8981. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  8982. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  8983. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  8984. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  8985. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  8986. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  8987. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  8988. #define GPIO_BRR_BR0 GPIO_BSRR_BR0
  8989. #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
  8990. #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
  8991. #define GPIO_BRR_BR1 GPIO_BSRR_BR1
  8992. #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
  8993. #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
  8994. #define GPIO_BRR_BR2 GPIO_BSRR_BR2
  8995. #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
  8996. #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
  8997. #define GPIO_BRR_BR3 GPIO_BSRR_BR3
  8998. #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
  8999. #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
  9000. #define GPIO_BRR_BR4 GPIO_BSRR_BR4
  9001. #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
  9002. #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
  9003. #define GPIO_BRR_BR5 GPIO_BSRR_BR5
  9004. #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
  9005. #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
  9006. #define GPIO_BRR_BR6 GPIO_BSRR_BR6
  9007. #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
  9008. #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
  9009. #define GPIO_BRR_BR7 GPIO_BSRR_BR7
  9010. #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
  9011. #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
  9012. #define GPIO_BRR_BR8 GPIO_BSRR_BR8
  9013. #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
  9014. #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
  9015. #define GPIO_BRR_BR9 GPIO_BSRR_BR9
  9016. #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
  9017. #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
  9018. #define GPIO_BRR_BR10 GPIO_BSRR_BR10
  9019. #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
  9020. #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
  9021. #define GPIO_BRR_BR11 GPIO_BSRR_BR11
  9022. #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
  9023. #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
  9024. #define GPIO_BRR_BR12 GPIO_BSRR_BR12
  9025. #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
  9026. #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
  9027. #define GPIO_BRR_BR13 GPIO_BSRR_BR13
  9028. #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
  9029. #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
  9030. #define GPIO_BRR_BR14 GPIO_BSRR_BR14
  9031. #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
  9032. #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
  9033. #define GPIO_BRR_BR15 GPIO_BSRR_BR15
  9034. #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
  9035. #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
  9036. /****************** Bit definition for GPIO_LCKR register *********************/
  9037. #define GPIO_LCKR_LCK0_Pos (0U)
  9038. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  9039. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  9040. #define GPIO_LCKR_LCK1_Pos (1U)
  9041. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  9042. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  9043. #define GPIO_LCKR_LCK2_Pos (2U)
  9044. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  9045. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  9046. #define GPIO_LCKR_LCK3_Pos (3U)
  9047. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  9048. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  9049. #define GPIO_LCKR_LCK4_Pos (4U)
  9050. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  9051. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  9052. #define GPIO_LCKR_LCK5_Pos (5U)
  9053. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  9054. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  9055. #define GPIO_LCKR_LCK6_Pos (6U)
  9056. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  9057. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  9058. #define GPIO_LCKR_LCK7_Pos (7U)
  9059. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  9060. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  9061. #define GPIO_LCKR_LCK8_Pos (8U)
  9062. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  9063. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  9064. #define GPIO_LCKR_LCK9_Pos (9U)
  9065. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  9066. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  9067. #define GPIO_LCKR_LCK10_Pos (10U)
  9068. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  9069. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  9070. #define GPIO_LCKR_LCK11_Pos (11U)
  9071. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  9072. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  9073. #define GPIO_LCKR_LCK12_Pos (12U)
  9074. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  9075. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  9076. #define GPIO_LCKR_LCK13_Pos (13U)
  9077. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  9078. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  9079. #define GPIO_LCKR_LCK14_Pos (14U)
  9080. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  9081. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  9082. #define GPIO_LCKR_LCK15_Pos (15U)
  9083. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  9084. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  9085. #define GPIO_LCKR_LCKK_Pos (16U)
  9086. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  9087. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  9088. /****************** Bit definition for GPIO_AFRL register *********************/
  9089. #define GPIO_AFRL_AFSEL0_Pos (0U)
  9090. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  9091. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  9092. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  9093. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  9094. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  9095. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  9096. #define GPIO_AFRL_AFSEL1_Pos (4U)
  9097. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  9098. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  9099. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  9100. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  9101. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  9102. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  9103. #define GPIO_AFRL_AFSEL2_Pos (8U)
  9104. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  9105. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  9106. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  9107. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  9108. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  9109. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  9110. #define GPIO_AFRL_AFSEL3_Pos (12U)
  9111. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  9112. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  9113. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  9114. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  9115. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  9116. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  9117. #define GPIO_AFRL_AFSEL4_Pos (16U)
  9118. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  9119. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  9120. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  9121. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  9122. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  9123. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  9124. #define GPIO_AFRL_AFSEL5_Pos (20U)
  9125. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  9126. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  9127. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  9128. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  9129. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  9130. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  9131. #define GPIO_AFRL_AFSEL6_Pos (24U)
  9132. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  9133. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  9134. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  9135. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  9136. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  9137. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  9138. #define GPIO_AFRL_AFSEL7_Pos (28U)
  9139. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  9140. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  9141. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  9142. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  9143. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  9144. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  9145. /* Legacy defines */
  9146. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  9147. #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
  9148. #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
  9149. #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
  9150. #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
  9151. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  9152. #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
  9153. #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
  9154. #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
  9155. #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
  9156. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  9157. #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
  9158. #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
  9159. #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
  9160. #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
  9161. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  9162. #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
  9163. #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
  9164. #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
  9165. #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
  9166. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  9167. #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
  9168. #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
  9169. #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
  9170. #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
  9171. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  9172. #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
  9173. #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
  9174. #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
  9175. #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
  9176. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  9177. #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
  9178. #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
  9179. #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
  9180. #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
  9181. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  9182. #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
  9183. #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
  9184. #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
  9185. #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
  9186. /****************** Bit definition for GPIO_AFRH register *********************/
  9187. #define GPIO_AFRH_AFSEL8_Pos (0U)
  9188. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  9189. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  9190. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  9191. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  9192. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  9193. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  9194. #define GPIO_AFRH_AFSEL9_Pos (4U)
  9195. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  9196. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  9197. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  9198. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  9199. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  9200. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  9201. #define GPIO_AFRH_AFSEL10_Pos (8U)
  9202. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  9203. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  9204. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  9205. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  9206. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  9207. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  9208. #define GPIO_AFRH_AFSEL11_Pos (12U)
  9209. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  9210. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  9211. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  9212. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  9213. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  9214. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  9215. #define GPIO_AFRH_AFSEL12_Pos (16U)
  9216. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  9217. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  9218. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  9219. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  9220. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  9221. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  9222. #define GPIO_AFRH_AFSEL13_Pos (20U)
  9223. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  9224. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  9225. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  9226. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  9227. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  9228. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  9229. #define GPIO_AFRH_AFSEL14_Pos (24U)
  9230. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  9231. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  9232. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  9233. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  9234. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  9235. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  9236. #define GPIO_AFRH_AFSEL15_Pos (28U)
  9237. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  9238. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  9239. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  9240. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  9241. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  9242. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  9243. /* Legacy defines */
  9244. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  9245. #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
  9246. #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
  9247. #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
  9248. #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
  9249. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  9250. #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
  9251. #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
  9252. #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
  9253. #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
  9254. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  9255. #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
  9256. #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
  9257. #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
  9258. #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
  9259. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  9260. #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
  9261. #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
  9262. #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
  9263. #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
  9264. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  9265. #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
  9266. #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
  9267. #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
  9268. #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
  9269. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  9270. #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
  9271. #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
  9272. #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
  9273. #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
  9274. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  9275. #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
  9276. #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
  9277. #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
  9278. #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
  9279. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  9280. #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
  9281. #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
  9282. #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
  9283. #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
  9284. /******************************************************************************/
  9285. /* */
  9286. /* Inter-integrated Circuit Interface */
  9287. /* */
  9288. /******************************************************************************/
  9289. /******************* Bit definition for I2C_CR1 register ********************/
  9290. #define I2C_CR1_PE_Pos (0U)
  9291. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  9292. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
  9293. #define I2C_CR1_SMBUS_Pos (1U)
  9294. #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
  9295. #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
  9296. #define I2C_CR1_SMBTYPE_Pos (3U)
  9297. #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
  9298. #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
  9299. #define I2C_CR1_ENARP_Pos (4U)
  9300. #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
  9301. #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
  9302. #define I2C_CR1_ENPEC_Pos (5U)
  9303. #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
  9304. #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
  9305. #define I2C_CR1_ENGC_Pos (6U)
  9306. #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
  9307. #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
  9308. #define I2C_CR1_NOSTRETCH_Pos (7U)
  9309. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
  9310. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
  9311. #define I2C_CR1_START_Pos (8U)
  9312. #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
  9313. #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
  9314. #define I2C_CR1_STOP_Pos (9U)
  9315. #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
  9316. #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
  9317. #define I2C_CR1_ACK_Pos (10U)
  9318. #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
  9319. #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
  9320. #define I2C_CR1_POS_Pos (11U)
  9321. #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
  9322. #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
  9323. #define I2C_CR1_PEC_Pos (12U)
  9324. #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
  9325. #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
  9326. #define I2C_CR1_ALERT_Pos (13U)
  9327. #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
  9328. #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
  9329. #define I2C_CR1_SWRST_Pos (15U)
  9330. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
  9331. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
  9332. /******************* Bit definition for I2C_CR2 register ********************/
  9333. #define I2C_CR2_FREQ_Pos (0U)
  9334. #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
  9335. #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
  9336. #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
  9337. #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
  9338. #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
  9339. #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
  9340. #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
  9341. #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
  9342. #define I2C_CR2_ITERREN_Pos (8U)
  9343. #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
  9344. #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
  9345. #define I2C_CR2_ITEVTEN_Pos (9U)
  9346. #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
  9347. #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
  9348. #define I2C_CR2_ITBUFEN_Pos (10U)
  9349. #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
  9350. #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
  9351. #define I2C_CR2_DMAEN_Pos (11U)
  9352. #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
  9353. #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
  9354. #define I2C_CR2_LAST_Pos (12U)
  9355. #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
  9356. #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
  9357. /******************* Bit definition for I2C_OAR1 register *******************/
  9358. #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
  9359. #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
  9360. #define I2C_OAR1_ADD0_Pos (0U)
  9361. #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
  9362. #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
  9363. #define I2C_OAR1_ADD1_Pos (1U)
  9364. #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
  9365. #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
  9366. #define I2C_OAR1_ADD2_Pos (2U)
  9367. #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
  9368. #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
  9369. #define I2C_OAR1_ADD3_Pos (3U)
  9370. #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
  9371. #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
  9372. #define I2C_OAR1_ADD4_Pos (4U)
  9373. #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
  9374. #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
  9375. #define I2C_OAR1_ADD5_Pos (5U)
  9376. #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
  9377. #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
  9378. #define I2C_OAR1_ADD6_Pos (6U)
  9379. #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
  9380. #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
  9381. #define I2C_OAR1_ADD7_Pos (7U)
  9382. #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
  9383. #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
  9384. #define I2C_OAR1_ADD8_Pos (8U)
  9385. #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
  9386. #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
  9387. #define I2C_OAR1_ADD9_Pos (9U)
  9388. #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
  9389. #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
  9390. #define I2C_OAR1_ADDMODE_Pos (15U)
  9391. #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
  9392. #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
  9393. /******************* Bit definition for I2C_OAR2 register *******************/
  9394. #define I2C_OAR2_ENDUAL_Pos (0U)
  9395. #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
  9396. #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
  9397. #define I2C_OAR2_ADD2_Pos (1U)
  9398. #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
  9399. #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
  9400. /******************** Bit definition for I2C_DR register ********************/
  9401. #define I2C_DR_DR_Pos (0U)
  9402. #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
  9403. #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
  9404. /******************* Bit definition for I2C_SR1 register ********************/
  9405. #define I2C_SR1_SB_Pos (0U)
  9406. #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
  9407. #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
  9408. #define I2C_SR1_ADDR_Pos (1U)
  9409. #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
  9410. #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
  9411. #define I2C_SR1_BTF_Pos (2U)
  9412. #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
  9413. #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
  9414. #define I2C_SR1_ADD10_Pos (3U)
  9415. #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
  9416. #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
  9417. #define I2C_SR1_STOPF_Pos (4U)
  9418. #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
  9419. #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
  9420. #define I2C_SR1_RXNE_Pos (6U)
  9421. #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
  9422. #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
  9423. #define I2C_SR1_TXE_Pos (7U)
  9424. #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
  9425. #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
  9426. #define I2C_SR1_BERR_Pos (8U)
  9427. #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
  9428. #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
  9429. #define I2C_SR1_ARLO_Pos (9U)
  9430. #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
  9431. #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
  9432. #define I2C_SR1_AF_Pos (10U)
  9433. #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
  9434. #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
  9435. #define I2C_SR1_OVR_Pos (11U)
  9436. #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
  9437. #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
  9438. #define I2C_SR1_PECERR_Pos (12U)
  9439. #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
  9440. #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
  9441. #define I2C_SR1_TIMEOUT_Pos (14U)
  9442. #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
  9443. #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
  9444. #define I2C_SR1_SMBALERT_Pos (15U)
  9445. #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
  9446. #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
  9447. /******************* Bit definition for I2C_SR2 register ********************/
  9448. #define I2C_SR2_MSL_Pos (0U)
  9449. #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
  9450. #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
  9451. #define I2C_SR2_BUSY_Pos (1U)
  9452. #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
  9453. #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
  9454. #define I2C_SR2_TRA_Pos (2U)
  9455. #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
  9456. #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
  9457. #define I2C_SR2_GENCALL_Pos (4U)
  9458. #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
  9459. #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
  9460. #define I2C_SR2_SMBDEFAULT_Pos (5U)
  9461. #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
  9462. #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
  9463. #define I2C_SR2_SMBHOST_Pos (6U)
  9464. #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
  9465. #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
  9466. #define I2C_SR2_DUALF_Pos (7U)
  9467. #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
  9468. #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
  9469. #define I2C_SR2_PEC_Pos (8U)
  9470. #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
  9471. #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
  9472. /******************* Bit definition for I2C_CCR register ********************/
  9473. #define I2C_CCR_CCR_Pos (0U)
  9474. #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
  9475. #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
  9476. #define I2C_CCR_DUTY_Pos (14U)
  9477. #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
  9478. #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
  9479. #define I2C_CCR_FS_Pos (15U)
  9480. #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
  9481. #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
  9482. /****************** Bit definition for I2C_TRISE register *******************/
  9483. #define I2C_TRISE_TRISE_Pos (0U)
  9484. #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
  9485. #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
  9486. /****************** Bit definition for I2C_FLTR register *******************/
  9487. #define I2C_FLTR_DNF_Pos (0U)
  9488. #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
  9489. #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
  9490. #define I2C_FLTR_ANOFF_Pos (4U)
  9491. #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
  9492. #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
  9493. /******************************************************************************/
  9494. /* */
  9495. /* Independent WATCHDOG */
  9496. /* */
  9497. /******************************************************************************/
  9498. /******************* Bit definition for IWDG_KR register ********************/
  9499. #define IWDG_KR_KEY_Pos (0U)
  9500. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  9501. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  9502. /******************* Bit definition for IWDG_PR register ********************/
  9503. #define IWDG_PR_PR_Pos (0U)
  9504. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  9505. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  9506. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
  9507. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
  9508. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
  9509. /******************* Bit definition for IWDG_RLR register *******************/
  9510. #define IWDG_RLR_RL_Pos (0U)
  9511. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  9512. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  9513. /******************* Bit definition for IWDG_SR register ********************/
  9514. #define IWDG_SR_PVU_Pos (0U)
  9515. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  9516. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
  9517. #define IWDG_SR_RVU_Pos (1U)
  9518. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  9519. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
  9520. /******************************************************************************/
  9521. /* */
  9522. /* Power Control */
  9523. /* */
  9524. /******************************************************************************/
  9525. /******************** Bit definition for PWR_CR register ********************/
  9526. #define PWR_CR_LPDS_Pos (0U)
  9527. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  9528. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  9529. #define PWR_CR_PDDS_Pos (1U)
  9530. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  9531. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  9532. #define PWR_CR_CWUF_Pos (2U)
  9533. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  9534. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  9535. #define PWR_CR_CSBF_Pos (3U)
  9536. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  9537. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  9538. #define PWR_CR_PVDE_Pos (4U)
  9539. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  9540. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  9541. #define PWR_CR_PLS_Pos (5U)
  9542. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  9543. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  9544. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  9545. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  9546. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  9547. /*!< PVD level configuration */
  9548. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
  9549. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
  9550. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
  9551. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
  9552. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
  9553. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
  9554. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
  9555. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
  9556. #define PWR_CR_DBP_Pos (8U)
  9557. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  9558. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  9559. #define PWR_CR_FPDS_Pos (9U)
  9560. #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
  9561. #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
  9562. #define PWR_CR_LPLVDS_Pos (10U)
  9563. #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
  9564. #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
  9565. #define PWR_CR_MRLVDS_Pos (11U)
  9566. #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
  9567. #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
  9568. #define PWR_CR_ADCDC1_Pos (13U)
  9569. #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
  9570. #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
  9571. #define PWR_CR_VOS_Pos (14U)
  9572. #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
  9573. #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  9574. #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
  9575. #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
  9576. #define PWR_CR_ODEN_Pos (16U)
  9577. #define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
  9578. #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
  9579. #define PWR_CR_ODSWEN_Pos (17U)
  9580. #define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
  9581. #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
  9582. #define PWR_CR_UDEN_Pos (18U)
  9583. #define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
  9584. #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
  9585. #define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
  9586. #define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
  9587. /* Legacy define */
  9588. #define PWR_CR_PMODE PWR_CR_VOS
  9589. #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
  9590. #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
  9591. /******************* Bit definition for PWR_CSR register ********************/
  9592. #define PWR_CSR_WUF_Pos (0U)
  9593. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  9594. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  9595. #define PWR_CSR_SBF_Pos (1U)
  9596. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  9597. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  9598. #define PWR_CSR_PVDO_Pos (2U)
  9599. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  9600. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  9601. #define PWR_CSR_BRR_Pos (3U)
  9602. #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
  9603. #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
  9604. #define PWR_CSR_EWUP_Pos (8U)
  9605. #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
  9606. #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
  9607. #define PWR_CSR_BRE_Pos (9U)
  9608. #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
  9609. #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
  9610. #define PWR_CSR_VOSRDY_Pos (14U)
  9611. #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
  9612. #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
  9613. #define PWR_CSR_ODRDY_Pos (16U)
  9614. #define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
  9615. #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
  9616. #define PWR_CSR_ODSWRDY_Pos (17U)
  9617. #define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
  9618. #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
  9619. #define PWR_CSR_UDRDY_Pos (18U)
  9620. #define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
  9621. #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
  9622. /* Legacy define */
  9623. #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
  9624. /* Legacy define */
  9625. #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
  9626. /******************************************************************************/
  9627. /* */
  9628. /* Reset and Clock Control */
  9629. /* */
  9630. /******************************************************************************/
  9631. /******************** Bit definition for RCC_CR register ********************/
  9632. #define RCC_CR_HSION_Pos (0U)
  9633. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  9634. #define RCC_CR_HSION RCC_CR_HSION_Msk
  9635. #define RCC_CR_HSIRDY_Pos (1U)
  9636. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  9637. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
  9638. #define RCC_CR_HSITRIM_Pos (3U)
  9639. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  9640. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
  9641. #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  9642. #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  9643. #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  9644. #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  9645. #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  9646. #define RCC_CR_HSICAL_Pos (8U)
  9647. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  9648. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
  9649. #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  9650. #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  9651. #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  9652. #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  9653. #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  9654. #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  9655. #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  9656. #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  9657. #define RCC_CR_HSEON_Pos (16U)
  9658. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  9659. #define RCC_CR_HSEON RCC_CR_HSEON_Msk
  9660. #define RCC_CR_HSERDY_Pos (17U)
  9661. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  9662. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
  9663. #define RCC_CR_HSEBYP_Pos (18U)
  9664. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  9665. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
  9666. #define RCC_CR_CSSON_Pos (19U)
  9667. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  9668. #define RCC_CR_CSSON RCC_CR_CSSON_Msk
  9669. #define RCC_CR_PLLON_Pos (24U)
  9670. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  9671. #define RCC_CR_PLLON RCC_CR_PLLON_Msk
  9672. #define RCC_CR_PLLRDY_Pos (25U)
  9673. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  9674. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
  9675. /*
  9676. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9677. */
  9678. #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
  9679. #define RCC_CR_PLLI2SON_Pos (26U)
  9680. #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
  9681. #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
  9682. #define RCC_CR_PLLI2SRDY_Pos (27U)
  9683. #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
  9684. #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
  9685. /*
  9686. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  9687. */
  9688. #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
  9689. #define RCC_CR_PLLSAION_Pos (28U)
  9690. #define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
  9691. #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
  9692. #define RCC_CR_PLLSAIRDY_Pos (29U)
  9693. #define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
  9694. #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
  9695. /******************** Bit definition for RCC_PLLCFGR register ***************/
  9696. #define RCC_PLLCFGR_PLLM_Pos (0U)
  9697. #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
  9698. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  9699. #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
  9700. #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
  9701. #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
  9702. #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
  9703. #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  9704. #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  9705. #define RCC_PLLCFGR_PLLN_Pos (6U)
  9706. #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
  9707. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  9708. #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
  9709. #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
  9710. #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  9711. #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  9712. #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  9713. #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  9714. #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  9715. #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  9716. #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  9717. #define RCC_PLLCFGR_PLLP_Pos (16U)
  9718. #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
  9719. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  9720. #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
  9721. #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  9722. #define RCC_PLLCFGR_PLLSRC_Pos (22U)
  9723. #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
  9724. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  9725. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
  9726. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
  9727. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
  9728. #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
  9729. #define RCC_PLLCFGR_PLLQ_Pos (24U)
  9730. #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
  9731. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  9732. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
  9733. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  9734. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  9735. #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  9736. /******************** Bit definition for RCC_CFGR register ******************/
  9737. /*!< SW configuration */
  9738. #define RCC_CFGR_SW_Pos (0U)
  9739. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  9740. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  9741. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  9742. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  9743. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  9744. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  9745. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  9746. /*!< SWS configuration */
  9747. #define RCC_CFGR_SWS_Pos (2U)
  9748. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  9749. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  9750. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  9751. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  9752. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  9753. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  9754. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  9755. /*!< HPRE configuration */
  9756. #define RCC_CFGR_HPRE_Pos (4U)
  9757. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  9758. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  9759. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  9760. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  9761. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  9762. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  9763. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  9764. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  9765. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  9766. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  9767. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  9768. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  9769. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  9770. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  9771. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  9772. /*!< PPRE1 configuration */
  9773. #define RCC_CFGR_PPRE1_Pos (10U)
  9774. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
  9775. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  9776. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  9777. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
  9778. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
  9779. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  9780. #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
  9781. #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
  9782. #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
  9783. #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
  9784. /*!< PPRE2 configuration */
  9785. #define RCC_CFGR_PPRE2_Pos (13U)
  9786. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
  9787. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  9788. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  9789. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
  9790. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
  9791. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  9792. #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
  9793. #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
  9794. #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
  9795. #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
  9796. /*!< RTCPRE configuration */
  9797. #define RCC_CFGR_RTCPRE_Pos (16U)
  9798. #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
  9799. #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
  9800. #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
  9801. #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
  9802. #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
  9803. #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
  9804. #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
  9805. /*!< MCO1 configuration */
  9806. #define RCC_CFGR_MCO1_Pos (21U)
  9807. #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
  9808. #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
  9809. #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
  9810. #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
  9811. #define RCC_CFGR_I2SSRC_Pos (23U)
  9812. #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
  9813. #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
  9814. #define RCC_CFGR_MCO1PRE_Pos (24U)
  9815. #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
  9816. #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
  9817. #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
  9818. #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
  9819. #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
  9820. #define RCC_CFGR_MCO2PRE_Pos (27U)
  9821. #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
  9822. #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
  9823. #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
  9824. #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
  9825. #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
  9826. #define RCC_CFGR_MCO2_Pos (30U)
  9827. #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
  9828. #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
  9829. #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
  9830. #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
  9831. /******************** Bit definition for RCC_CIR register *******************/
  9832. #define RCC_CIR_LSIRDYF_Pos (0U)
  9833. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  9834. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
  9835. #define RCC_CIR_LSERDYF_Pos (1U)
  9836. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  9837. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
  9838. #define RCC_CIR_HSIRDYF_Pos (2U)
  9839. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  9840. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
  9841. #define RCC_CIR_HSERDYF_Pos (3U)
  9842. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  9843. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
  9844. #define RCC_CIR_PLLRDYF_Pos (4U)
  9845. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  9846. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
  9847. #define RCC_CIR_PLLI2SRDYF_Pos (5U)
  9848. #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
  9849. #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
  9850. #define RCC_CIR_PLLSAIRDYF_Pos (6U)
  9851. #define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
  9852. #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
  9853. #define RCC_CIR_CSSF_Pos (7U)
  9854. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  9855. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
  9856. #define RCC_CIR_LSIRDYIE_Pos (8U)
  9857. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  9858. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
  9859. #define RCC_CIR_LSERDYIE_Pos (9U)
  9860. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  9861. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
  9862. #define RCC_CIR_HSIRDYIE_Pos (10U)
  9863. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  9864. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
  9865. #define RCC_CIR_HSERDYIE_Pos (11U)
  9866. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  9867. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
  9868. #define RCC_CIR_PLLRDYIE_Pos (12U)
  9869. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  9870. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
  9871. #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
  9872. #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
  9873. #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
  9874. #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
  9875. #define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
  9876. #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
  9877. #define RCC_CIR_LSIRDYC_Pos (16U)
  9878. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  9879. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
  9880. #define RCC_CIR_LSERDYC_Pos (17U)
  9881. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  9882. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
  9883. #define RCC_CIR_HSIRDYC_Pos (18U)
  9884. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  9885. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
  9886. #define RCC_CIR_HSERDYC_Pos (19U)
  9887. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  9888. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
  9889. #define RCC_CIR_PLLRDYC_Pos (20U)
  9890. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  9891. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
  9892. #define RCC_CIR_PLLI2SRDYC_Pos (21U)
  9893. #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
  9894. #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
  9895. #define RCC_CIR_PLLSAIRDYC_Pos (22U)
  9896. #define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
  9897. #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
  9898. #define RCC_CIR_CSSC_Pos (23U)
  9899. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  9900. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
  9901. /******************** Bit definition for RCC_AHB1RSTR register **************/
  9902. #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
  9903. #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  9904. #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
  9905. #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
  9906. #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  9907. #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
  9908. #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
  9909. #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  9910. #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
  9911. #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
  9912. #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
  9913. #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
  9914. #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
  9915. #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
  9916. #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
  9917. #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
  9918. #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
  9919. #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
  9920. #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
  9921. #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
  9922. #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
  9923. #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
  9924. #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  9925. #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
  9926. #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
  9927. #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
  9928. #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
  9929. #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
  9930. #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
  9931. #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
  9932. #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
  9933. #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
  9934. #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
  9935. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  9936. #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  9937. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  9938. #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
  9939. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
  9940. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  9941. #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
  9942. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
  9943. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  9944. #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
  9945. #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
  9946. #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
  9947. #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
  9948. #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
  9949. #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
  9950. #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
  9951. #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
  9952. #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
  9953. /******************** Bit definition for RCC_AHB2RSTR register **************/
  9954. #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
  9955. #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
  9956. #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
  9957. #define RCC_AHB2RSTR_RNGRST_Pos (6U)
  9958. #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
  9959. #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
  9960. #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
  9961. #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
  9962. #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
  9963. /******************** Bit definition for RCC_AHB3RSTR register **************/
  9964. #define RCC_AHB3RSTR_FMCRST_Pos (0U)
  9965. #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
  9966. #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
  9967. /******************** Bit definition for RCC_APB1RSTR register **************/
  9968. #define RCC_APB1RSTR_TIM2RST_Pos (0U)
  9969. #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
  9970. #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
  9971. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  9972. #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  9973. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
  9974. #define RCC_APB1RSTR_TIM4RST_Pos (2U)
  9975. #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
  9976. #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
  9977. #define RCC_APB1RSTR_TIM5RST_Pos (3U)
  9978. #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
  9979. #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
  9980. #define RCC_APB1RSTR_TIM6RST_Pos (4U)
  9981. #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
  9982. #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
  9983. #define RCC_APB1RSTR_TIM7RST_Pos (5U)
  9984. #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
  9985. #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
  9986. #define RCC_APB1RSTR_TIM12RST_Pos (6U)
  9987. #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
  9988. #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
  9989. #define RCC_APB1RSTR_TIM13RST_Pos (7U)
  9990. #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
  9991. #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
  9992. #define RCC_APB1RSTR_TIM14RST_Pos (8U)
  9993. #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
  9994. #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
  9995. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  9996. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  9997. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
  9998. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  9999. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  10000. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
  10001. #define RCC_APB1RSTR_SPI3RST_Pos (15U)
  10002. #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
  10003. #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
  10004. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  10005. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  10006. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
  10007. #define RCC_APB1RSTR_USART3RST_Pos (18U)
  10008. #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
  10009. #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
  10010. #define RCC_APB1RSTR_UART4RST_Pos (19U)
  10011. #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
  10012. #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
  10013. #define RCC_APB1RSTR_UART5RST_Pos (20U)
  10014. #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
  10015. #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
  10016. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  10017. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  10018. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
  10019. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  10020. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  10021. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
  10022. #define RCC_APB1RSTR_I2C3RST_Pos (23U)
  10023. #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
  10024. #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
  10025. #define RCC_APB1RSTR_CAN1RST_Pos (25U)
  10026. #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
  10027. #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
  10028. #define RCC_APB1RSTR_CAN2RST_Pos (26U)
  10029. #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
  10030. #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
  10031. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  10032. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  10033. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
  10034. #define RCC_APB1RSTR_DACRST_Pos (29U)
  10035. #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
  10036. #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
  10037. #define RCC_APB1RSTR_UART7RST_Pos (30U)
  10038. #define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
  10039. #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
  10040. #define RCC_APB1RSTR_UART8RST_Pos (31U)
  10041. #define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
  10042. #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
  10043. /******************** Bit definition for RCC_APB2RSTR register **************/
  10044. #define RCC_APB2RSTR_TIM1RST_Pos (0U)
  10045. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
  10046. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  10047. #define RCC_APB2RSTR_TIM8RST_Pos (1U)
  10048. #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
  10049. #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
  10050. #define RCC_APB2RSTR_USART1RST_Pos (4U)
  10051. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
  10052. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  10053. #define RCC_APB2RSTR_USART6RST_Pos (5U)
  10054. #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
  10055. #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
  10056. #define RCC_APB2RSTR_ADCRST_Pos (8U)
  10057. #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
  10058. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
  10059. #define RCC_APB2RSTR_SDIORST_Pos (11U)
  10060. #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
  10061. #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
  10062. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  10063. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  10064. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  10065. #define RCC_APB2RSTR_SPI4RST_Pos (13U)
  10066. #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
  10067. #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
  10068. #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
  10069. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
  10070. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  10071. #define RCC_APB2RSTR_TIM9RST_Pos (16U)
  10072. #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
  10073. #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
  10074. #define RCC_APB2RSTR_TIM10RST_Pos (17U)
  10075. #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
  10076. #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
  10077. #define RCC_APB2RSTR_TIM11RST_Pos (18U)
  10078. #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
  10079. #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
  10080. #define RCC_APB2RSTR_SPI5RST_Pos (20U)
  10081. #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
  10082. #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
  10083. #define RCC_APB2RSTR_SPI6RST_Pos (21U)
  10084. #define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
  10085. #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
  10086. #define RCC_APB2RSTR_SAI1RST_Pos (22U)
  10087. #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
  10088. #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
  10089. /* Old SPI1RST bit definition, maintained for legacy purpose */
  10090. #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
  10091. /******************** Bit definition for RCC_AHB1ENR register ***************/
  10092. #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
  10093. #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  10094. #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
  10095. #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
  10096. #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  10097. #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
  10098. #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
  10099. #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  10100. #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
  10101. #define RCC_AHB1ENR_GPIODEN_Pos (3U)
  10102. #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
  10103. #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
  10104. #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
  10105. #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
  10106. #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
  10107. #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
  10108. #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
  10109. #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
  10110. #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
  10111. #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
  10112. #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
  10113. #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
  10114. #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  10115. #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
  10116. #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
  10117. #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
  10118. #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
  10119. #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
  10120. #define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
  10121. #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
  10122. #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
  10123. #define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
  10124. #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
  10125. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  10126. #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  10127. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  10128. #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
  10129. #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
  10130. #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
  10131. #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
  10132. #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
  10133. #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
  10134. #define RCC_AHB1ENR_DMA1EN_Pos (21U)
  10135. #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
  10136. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  10137. #define RCC_AHB1ENR_DMA2EN_Pos (22U)
  10138. #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
  10139. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  10140. #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
  10141. #define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
  10142. #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
  10143. #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
  10144. #define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
  10145. #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
  10146. #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
  10147. #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
  10148. #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
  10149. #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
  10150. #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
  10151. #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
  10152. #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
  10153. #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
  10154. #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
  10155. #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
  10156. #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
  10157. #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
  10158. #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
  10159. #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
  10160. #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
  10161. /******************** Bit definition for RCC_AHB2ENR register ***************/
  10162. /*
  10163. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  10164. */
  10165. #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
  10166. #define RCC_AHB2ENR_DCMIEN_Pos (0U)
  10167. #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
  10168. #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
  10169. #define RCC_AHB2ENR_RNGEN_Pos (6U)
  10170. #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
  10171. #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
  10172. #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
  10173. #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
  10174. #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
  10175. /******************** Bit definition for RCC_AHB3ENR register ***************/
  10176. /*
  10177. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  10178. */
  10179. #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
  10180. #define RCC_AHB3ENR_FMCEN_Pos (0U)
  10181. #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
  10182. #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
  10183. /******************** Bit definition for RCC_APB1ENR register ***************/
  10184. #define RCC_APB1ENR_TIM2EN_Pos (0U)
  10185. #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
  10186. #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
  10187. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  10188. #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  10189. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
  10190. #define RCC_APB1ENR_TIM4EN_Pos (2U)
  10191. #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
  10192. #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
  10193. #define RCC_APB1ENR_TIM5EN_Pos (3U)
  10194. #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
  10195. #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
  10196. #define RCC_APB1ENR_TIM6EN_Pos (4U)
  10197. #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
  10198. #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
  10199. #define RCC_APB1ENR_TIM7EN_Pos (5U)
  10200. #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
  10201. #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
  10202. #define RCC_APB1ENR_TIM12EN_Pos (6U)
  10203. #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
  10204. #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
  10205. #define RCC_APB1ENR_TIM13EN_Pos (7U)
  10206. #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
  10207. #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
  10208. #define RCC_APB1ENR_TIM14EN_Pos (8U)
  10209. #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
  10210. #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
  10211. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  10212. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  10213. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
  10214. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  10215. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  10216. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
  10217. #define RCC_APB1ENR_SPI3EN_Pos (15U)
  10218. #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
  10219. #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
  10220. #define RCC_APB1ENR_USART2EN_Pos (17U)
  10221. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  10222. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
  10223. #define RCC_APB1ENR_USART3EN_Pos (18U)
  10224. #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
  10225. #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
  10226. #define RCC_APB1ENR_UART4EN_Pos (19U)
  10227. #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
  10228. #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
  10229. #define RCC_APB1ENR_UART5EN_Pos (20U)
  10230. #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
  10231. #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
  10232. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  10233. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  10234. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
  10235. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  10236. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  10237. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
  10238. #define RCC_APB1ENR_I2C3EN_Pos (23U)
  10239. #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
  10240. #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
  10241. #define RCC_APB1ENR_CAN1EN_Pos (25U)
  10242. #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
  10243. #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
  10244. #define RCC_APB1ENR_CAN2EN_Pos (26U)
  10245. #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
  10246. #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
  10247. #define RCC_APB1ENR_PWREN_Pos (28U)
  10248. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  10249. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
  10250. #define RCC_APB1ENR_DACEN_Pos (29U)
  10251. #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
  10252. #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
  10253. #define RCC_APB1ENR_UART7EN_Pos (30U)
  10254. #define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
  10255. #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
  10256. #define RCC_APB1ENR_UART8EN_Pos (31U)
  10257. #define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
  10258. #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
  10259. /******************** Bit definition for RCC_APB2ENR register ***************/
  10260. #define RCC_APB2ENR_TIM1EN_Pos (0U)
  10261. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
  10262. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  10263. #define RCC_APB2ENR_TIM8EN_Pos (1U)
  10264. #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
  10265. #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
  10266. #define RCC_APB2ENR_USART1EN_Pos (4U)
  10267. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
  10268. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  10269. #define RCC_APB2ENR_USART6EN_Pos (5U)
  10270. #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
  10271. #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
  10272. #define RCC_APB2ENR_ADC1EN_Pos (8U)
  10273. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
  10274. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
  10275. #define RCC_APB2ENR_ADC2EN_Pos (9U)
  10276. #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
  10277. #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
  10278. #define RCC_APB2ENR_ADC3EN_Pos (10U)
  10279. #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
  10280. #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
  10281. #define RCC_APB2ENR_SDIOEN_Pos (11U)
  10282. #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
  10283. #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
  10284. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  10285. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  10286. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  10287. #define RCC_APB2ENR_SPI4EN_Pos (13U)
  10288. #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
  10289. #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
  10290. #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
  10291. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
  10292. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  10293. #define RCC_APB2ENR_TIM9EN_Pos (16U)
  10294. #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
  10295. #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
  10296. #define RCC_APB2ENR_TIM10EN_Pos (17U)
  10297. #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
  10298. #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
  10299. #define RCC_APB2ENR_TIM11EN_Pos (18U)
  10300. #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
  10301. #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
  10302. #define RCC_APB2ENR_SPI5EN_Pos (20U)
  10303. #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
  10304. #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
  10305. #define RCC_APB2ENR_SPI6EN_Pos (21U)
  10306. #define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
  10307. #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
  10308. #define RCC_APB2ENR_SAI1EN_Pos (22U)
  10309. #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
  10310. #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
  10311. /******************** Bit definition for RCC_AHB1LPENR register *************/
  10312. #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
  10313. #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
  10314. #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
  10315. #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
  10316. #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
  10317. #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
  10318. #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
  10319. #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
  10320. #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
  10321. #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
  10322. #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
  10323. #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
  10324. #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
  10325. #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
  10326. #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
  10327. #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
  10328. #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
  10329. #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
  10330. #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
  10331. #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
  10332. #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
  10333. #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
  10334. #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
  10335. #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
  10336. #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
  10337. #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
  10338. #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
  10339. #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
  10340. #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
  10341. #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
  10342. #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
  10343. #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
  10344. #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
  10345. #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
  10346. #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
  10347. #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
  10348. #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
  10349. #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
  10350. #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
  10351. #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
  10352. #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
  10353. #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
  10354. #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
  10355. #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
  10356. #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
  10357. #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
  10358. #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
  10359. #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
  10360. #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
  10361. #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
  10362. #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
  10363. #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
  10364. #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
  10365. #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
  10366. #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
  10367. #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
  10368. #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
  10369. #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
  10370. #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
  10371. #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
  10372. #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
  10373. #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
  10374. #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
  10375. #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
  10376. #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
  10377. #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
  10378. #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
  10379. #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
  10380. #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
  10381. #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
  10382. #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
  10383. #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
  10384. #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
  10385. #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
  10386. #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
  10387. /******************** Bit definition for RCC_AHB2LPENR register *************/
  10388. #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
  10389. #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
  10390. #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
  10391. #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
  10392. #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
  10393. #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
  10394. #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
  10395. #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
  10396. #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
  10397. /******************** Bit definition for RCC_AHB3LPENR register *************/
  10398. #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
  10399. #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
  10400. #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
  10401. /******************** Bit definition for RCC_APB1LPENR register *************/
  10402. #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
  10403. #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
  10404. #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
  10405. #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
  10406. #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
  10407. #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
  10408. #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
  10409. #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
  10410. #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
  10411. #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
  10412. #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
  10413. #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
  10414. #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
  10415. #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
  10416. #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
  10417. #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
  10418. #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
  10419. #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
  10420. #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
  10421. #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
  10422. #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
  10423. #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
  10424. #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
  10425. #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
  10426. #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
  10427. #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
  10428. #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
  10429. #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
  10430. #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
  10431. #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
  10432. #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
  10433. #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
  10434. #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
  10435. #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
  10436. #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
  10437. #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
  10438. #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
  10439. #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
  10440. #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
  10441. #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
  10442. #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
  10443. #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
  10444. #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
  10445. #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
  10446. #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
  10447. #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
  10448. #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
  10449. #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
  10450. #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
  10451. #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
  10452. #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
  10453. #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
  10454. #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
  10455. #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
  10456. #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
  10457. #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
  10458. #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
  10459. #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
  10460. #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
  10461. #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
  10462. #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
  10463. #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
  10464. #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
  10465. #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
  10466. #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
  10467. #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
  10468. #define RCC_APB1LPENR_DACLPEN_Pos (29U)
  10469. #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
  10470. #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
  10471. #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
  10472. #define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
  10473. #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
  10474. #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
  10475. #define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
  10476. #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
  10477. /******************** Bit definition for RCC_APB2LPENR register *************/
  10478. #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
  10479. #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
  10480. #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
  10481. #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
  10482. #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
  10483. #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
  10484. #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
  10485. #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
  10486. #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
  10487. #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
  10488. #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
  10489. #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
  10490. #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
  10491. #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
  10492. #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
  10493. #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
  10494. #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
  10495. #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
  10496. #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
  10497. #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
  10498. #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
  10499. #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
  10500. #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
  10501. #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
  10502. #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
  10503. #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
  10504. #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
  10505. #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
  10506. #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
  10507. #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
  10508. #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
  10509. #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
  10510. #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
  10511. #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
  10512. #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
  10513. #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
  10514. #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
  10515. #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
  10516. #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
  10517. #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
  10518. #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
  10519. #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
  10520. #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
  10521. #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
  10522. #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
  10523. #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
  10524. #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
  10525. #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
  10526. #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
  10527. #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
  10528. #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
  10529. /******************** Bit definition for RCC_BDCR register ******************/
  10530. #define RCC_BDCR_LSEON_Pos (0U)
  10531. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  10532. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  10533. #define RCC_BDCR_LSERDY_Pos (1U)
  10534. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  10535. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  10536. #define RCC_BDCR_LSEBYP_Pos (2U)
  10537. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  10538. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  10539. #define RCC_BDCR_RTCSEL_Pos (8U)
  10540. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  10541. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  10542. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  10543. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  10544. #define RCC_BDCR_RTCEN_Pos (15U)
  10545. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  10546. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  10547. #define RCC_BDCR_BDRST_Pos (16U)
  10548. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  10549. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  10550. /******************** Bit definition for RCC_CSR register *******************/
  10551. #define RCC_CSR_LSION_Pos (0U)
  10552. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  10553. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  10554. #define RCC_CSR_LSIRDY_Pos (1U)
  10555. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  10556. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  10557. #define RCC_CSR_RMVF_Pos (24U)
  10558. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  10559. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  10560. #define RCC_CSR_BORRSTF_Pos (25U)
  10561. #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
  10562. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  10563. #define RCC_CSR_PINRSTF_Pos (26U)
  10564. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  10565. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  10566. #define RCC_CSR_PORRSTF_Pos (27U)
  10567. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  10568. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
  10569. #define RCC_CSR_SFTRSTF_Pos (28U)
  10570. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  10571. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  10572. #define RCC_CSR_IWDGRSTF_Pos (29U)
  10573. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  10574. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  10575. #define RCC_CSR_WWDGRSTF_Pos (30U)
  10576. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  10577. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  10578. #define RCC_CSR_LPWRRSTF_Pos (31U)
  10579. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  10580. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  10581. /* Legacy defines */
  10582. #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
  10583. #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
  10584. /******************** Bit definition for RCC_SSCGR register *****************/
  10585. #define RCC_SSCGR_MODPER_Pos (0U)
  10586. #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
  10587. #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
  10588. #define RCC_SSCGR_INCSTEP_Pos (13U)
  10589. #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
  10590. #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
  10591. #define RCC_SSCGR_SPREADSEL_Pos (30U)
  10592. #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
  10593. #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
  10594. #define RCC_SSCGR_SSCGEN_Pos (31U)
  10595. #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
  10596. #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
  10597. /******************** Bit definition for RCC_PLLI2SCFGR register ************/
  10598. #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
  10599. #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
  10600. #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
  10601. #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
  10602. #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
  10603. #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
  10604. #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
  10605. #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
  10606. #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
  10607. #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
  10608. #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
  10609. #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
  10610. #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
  10611. #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
  10612. #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
  10613. #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
  10614. #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
  10615. #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
  10616. #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
  10617. #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
  10618. #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
  10619. #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
  10620. #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
  10621. #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
  10622. #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
  10623. /******************** Bit definition for RCC_PLLSAICFGR register ************/
  10624. #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
  10625. #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
  10626. #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
  10627. #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
  10628. #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
  10629. #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
  10630. #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
  10631. #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
  10632. #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
  10633. #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
  10634. #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
  10635. #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
  10636. #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
  10637. #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
  10638. #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
  10639. #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
  10640. #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
  10641. #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
  10642. #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
  10643. #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
  10644. #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
  10645. #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
  10646. #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
  10647. #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
  10648. #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
  10649. /******************** Bit definition for RCC_DCKCFGR register ***************/
  10650. #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
  10651. #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
  10652. #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
  10653. #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
  10654. #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
  10655. #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
  10656. #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
  10657. #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
  10658. #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
  10659. #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
  10660. #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
  10661. #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
  10662. #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
  10663. #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
  10664. #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
  10665. #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
  10666. #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
  10667. #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
  10668. #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
  10669. #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
  10670. #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
  10671. #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
  10672. #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
  10673. #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
  10674. #define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
  10675. #define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
  10676. #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
  10677. #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
  10678. #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
  10679. #define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
  10680. #define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
  10681. #define RCC_DCKCFGR_TIMPRE_Pos (24U)
  10682. #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
  10683. #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
  10684. /******************************************************************************/
  10685. /* */
  10686. /* RNG */
  10687. /* */
  10688. /******************************************************************************/
  10689. /******************** Bits definition for RNG_CR register *******************/
  10690. #define RNG_CR_RNGEN_Pos (2U)
  10691. #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
  10692. #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
  10693. #define RNG_CR_IE_Pos (3U)
  10694. #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
  10695. #define RNG_CR_IE RNG_CR_IE_Msk
  10696. /******************** Bits definition for RNG_SR register *******************/
  10697. #define RNG_SR_DRDY_Pos (0U)
  10698. #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
  10699. #define RNG_SR_DRDY RNG_SR_DRDY_Msk
  10700. #define RNG_SR_CECS_Pos (1U)
  10701. #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
  10702. #define RNG_SR_CECS RNG_SR_CECS_Msk
  10703. #define RNG_SR_SECS_Pos (2U)
  10704. #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
  10705. #define RNG_SR_SECS RNG_SR_SECS_Msk
  10706. #define RNG_SR_CEIS_Pos (5U)
  10707. #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
  10708. #define RNG_SR_CEIS RNG_SR_CEIS_Msk
  10709. #define RNG_SR_SEIS_Pos (6U)
  10710. #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
  10711. #define RNG_SR_SEIS RNG_SR_SEIS_Msk
  10712. /******************************************************************************/
  10713. /* */
  10714. /* Real-Time Clock (RTC) */
  10715. /* */
  10716. /******************************************************************************/
  10717. /*
  10718. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  10719. */
  10720. #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
  10721. #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
  10722. /******************** Bits definition for RTC_TR register *******************/
  10723. #define RTC_TR_PM_Pos (22U)
  10724. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  10725. #define RTC_TR_PM RTC_TR_PM_Msk
  10726. #define RTC_TR_HT_Pos (20U)
  10727. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  10728. #define RTC_TR_HT RTC_TR_HT_Msk
  10729. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  10730. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  10731. #define RTC_TR_HU_Pos (16U)
  10732. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  10733. #define RTC_TR_HU RTC_TR_HU_Msk
  10734. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  10735. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  10736. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  10737. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  10738. #define RTC_TR_MNT_Pos (12U)
  10739. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  10740. #define RTC_TR_MNT RTC_TR_MNT_Msk
  10741. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  10742. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  10743. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  10744. #define RTC_TR_MNU_Pos (8U)
  10745. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  10746. #define RTC_TR_MNU RTC_TR_MNU_Msk
  10747. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  10748. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  10749. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  10750. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  10751. #define RTC_TR_ST_Pos (4U)
  10752. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  10753. #define RTC_TR_ST RTC_TR_ST_Msk
  10754. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  10755. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  10756. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  10757. #define RTC_TR_SU_Pos (0U)
  10758. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  10759. #define RTC_TR_SU RTC_TR_SU_Msk
  10760. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  10761. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  10762. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  10763. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  10764. /******************** Bits definition for RTC_DR register *******************/
  10765. #define RTC_DR_YT_Pos (20U)
  10766. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  10767. #define RTC_DR_YT RTC_DR_YT_Msk
  10768. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  10769. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  10770. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  10771. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  10772. #define RTC_DR_YU_Pos (16U)
  10773. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  10774. #define RTC_DR_YU RTC_DR_YU_Msk
  10775. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  10776. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  10777. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  10778. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  10779. #define RTC_DR_WDU_Pos (13U)
  10780. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  10781. #define RTC_DR_WDU RTC_DR_WDU_Msk
  10782. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  10783. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  10784. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  10785. #define RTC_DR_MT_Pos (12U)
  10786. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  10787. #define RTC_DR_MT RTC_DR_MT_Msk
  10788. #define RTC_DR_MU_Pos (8U)
  10789. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  10790. #define RTC_DR_MU RTC_DR_MU_Msk
  10791. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  10792. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  10793. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  10794. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  10795. #define RTC_DR_DT_Pos (4U)
  10796. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  10797. #define RTC_DR_DT RTC_DR_DT_Msk
  10798. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  10799. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  10800. #define RTC_DR_DU_Pos (0U)
  10801. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  10802. #define RTC_DR_DU RTC_DR_DU_Msk
  10803. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  10804. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  10805. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  10806. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  10807. /******************** Bits definition for RTC_CR register *******************/
  10808. #define RTC_CR_COE_Pos (23U)
  10809. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  10810. #define RTC_CR_COE RTC_CR_COE_Msk
  10811. #define RTC_CR_OSEL_Pos (21U)
  10812. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  10813. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  10814. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  10815. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  10816. #define RTC_CR_POL_Pos (20U)
  10817. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  10818. #define RTC_CR_POL RTC_CR_POL_Msk
  10819. #define RTC_CR_COSEL_Pos (19U)
  10820. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  10821. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  10822. #define RTC_CR_BKP_Pos (18U)
  10823. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  10824. #define RTC_CR_BKP RTC_CR_BKP_Msk
  10825. #define RTC_CR_SUB1H_Pos (17U)
  10826. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  10827. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  10828. #define RTC_CR_ADD1H_Pos (16U)
  10829. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  10830. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  10831. #define RTC_CR_TSIE_Pos (15U)
  10832. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  10833. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  10834. #define RTC_CR_WUTIE_Pos (14U)
  10835. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  10836. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  10837. #define RTC_CR_ALRBIE_Pos (13U)
  10838. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  10839. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  10840. #define RTC_CR_ALRAIE_Pos (12U)
  10841. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  10842. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  10843. #define RTC_CR_TSE_Pos (11U)
  10844. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  10845. #define RTC_CR_TSE RTC_CR_TSE_Msk
  10846. #define RTC_CR_WUTE_Pos (10U)
  10847. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  10848. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  10849. #define RTC_CR_ALRBE_Pos (9U)
  10850. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  10851. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  10852. #define RTC_CR_ALRAE_Pos (8U)
  10853. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  10854. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  10855. #define RTC_CR_DCE_Pos (7U)
  10856. #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */
  10857. #define RTC_CR_DCE RTC_CR_DCE_Msk
  10858. #define RTC_CR_FMT_Pos (6U)
  10859. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  10860. #define RTC_CR_FMT RTC_CR_FMT_Msk
  10861. #define RTC_CR_BYPSHAD_Pos (5U)
  10862. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  10863. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  10864. #define RTC_CR_REFCKON_Pos (4U)
  10865. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  10866. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  10867. #define RTC_CR_TSEDGE_Pos (3U)
  10868. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  10869. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  10870. #define RTC_CR_WUCKSEL_Pos (0U)
  10871. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  10872. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  10873. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  10874. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  10875. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  10876. /* Legacy defines */
  10877. #define RTC_CR_BCK RTC_CR_BKP
  10878. /******************** Bits definition for RTC_ISR register ******************/
  10879. #define RTC_ISR_RECALPF_Pos (16U)
  10880. #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  10881. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  10882. #define RTC_ISR_TAMP1F_Pos (13U)
  10883. #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  10884. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  10885. #define RTC_ISR_TAMP2F_Pos (14U)
  10886. #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  10887. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  10888. #define RTC_ISR_TSOVF_Pos (12U)
  10889. #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  10890. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  10891. #define RTC_ISR_TSF_Pos (11U)
  10892. #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  10893. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  10894. #define RTC_ISR_WUTF_Pos (10U)
  10895. #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  10896. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  10897. #define RTC_ISR_ALRBF_Pos (9U)
  10898. #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  10899. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  10900. #define RTC_ISR_ALRAF_Pos (8U)
  10901. #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  10902. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  10903. #define RTC_ISR_INIT_Pos (7U)
  10904. #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  10905. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  10906. #define RTC_ISR_INITF_Pos (6U)
  10907. #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  10908. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  10909. #define RTC_ISR_RSF_Pos (5U)
  10910. #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  10911. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  10912. #define RTC_ISR_INITS_Pos (4U)
  10913. #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  10914. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  10915. #define RTC_ISR_SHPF_Pos (3U)
  10916. #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  10917. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  10918. #define RTC_ISR_WUTWF_Pos (2U)
  10919. #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  10920. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  10921. #define RTC_ISR_ALRBWF_Pos (1U)
  10922. #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  10923. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  10924. #define RTC_ISR_ALRAWF_Pos (0U)
  10925. #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  10926. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  10927. /******************** Bits definition for RTC_PRER register *****************/
  10928. #define RTC_PRER_PREDIV_A_Pos (16U)
  10929. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  10930. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  10931. #define RTC_PRER_PREDIV_S_Pos (0U)
  10932. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  10933. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  10934. /******************** Bits definition for RTC_WUTR register *****************/
  10935. #define RTC_WUTR_WUT_Pos (0U)
  10936. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  10937. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  10938. /******************** Bits definition for RTC_CALIBR register ***************/
  10939. #define RTC_CALIBR_DCS_Pos (7U)
  10940. #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
  10941. #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
  10942. #define RTC_CALIBR_DC_Pos (0U)
  10943. #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
  10944. #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
  10945. /******************** Bits definition for RTC_ALRMAR register ***************/
  10946. #define RTC_ALRMAR_MSK4_Pos (31U)
  10947. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  10948. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  10949. #define RTC_ALRMAR_WDSEL_Pos (30U)
  10950. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  10951. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  10952. #define RTC_ALRMAR_DT_Pos (28U)
  10953. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  10954. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  10955. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  10956. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  10957. #define RTC_ALRMAR_DU_Pos (24U)
  10958. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  10959. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  10960. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  10961. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  10962. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  10963. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  10964. #define RTC_ALRMAR_MSK3_Pos (23U)
  10965. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  10966. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  10967. #define RTC_ALRMAR_PM_Pos (22U)
  10968. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  10969. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  10970. #define RTC_ALRMAR_HT_Pos (20U)
  10971. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  10972. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  10973. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  10974. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  10975. #define RTC_ALRMAR_HU_Pos (16U)
  10976. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  10977. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  10978. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  10979. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  10980. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  10981. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  10982. #define RTC_ALRMAR_MSK2_Pos (15U)
  10983. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  10984. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  10985. #define RTC_ALRMAR_MNT_Pos (12U)
  10986. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  10987. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  10988. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  10989. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  10990. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  10991. #define RTC_ALRMAR_MNU_Pos (8U)
  10992. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  10993. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  10994. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  10995. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  10996. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  10997. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  10998. #define RTC_ALRMAR_MSK1_Pos (7U)
  10999. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  11000. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  11001. #define RTC_ALRMAR_ST_Pos (4U)
  11002. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  11003. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  11004. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  11005. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  11006. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  11007. #define RTC_ALRMAR_SU_Pos (0U)
  11008. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  11009. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  11010. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  11011. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  11012. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  11013. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  11014. /******************** Bits definition for RTC_ALRMBR register ***************/
  11015. #define RTC_ALRMBR_MSK4_Pos (31U)
  11016. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  11017. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  11018. #define RTC_ALRMBR_WDSEL_Pos (30U)
  11019. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  11020. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  11021. #define RTC_ALRMBR_DT_Pos (28U)
  11022. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  11023. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  11024. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  11025. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  11026. #define RTC_ALRMBR_DU_Pos (24U)
  11027. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  11028. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  11029. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  11030. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  11031. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  11032. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  11033. #define RTC_ALRMBR_MSK3_Pos (23U)
  11034. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  11035. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  11036. #define RTC_ALRMBR_PM_Pos (22U)
  11037. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  11038. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  11039. #define RTC_ALRMBR_HT_Pos (20U)
  11040. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  11041. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  11042. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  11043. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  11044. #define RTC_ALRMBR_HU_Pos (16U)
  11045. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  11046. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  11047. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  11048. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  11049. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  11050. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  11051. #define RTC_ALRMBR_MSK2_Pos (15U)
  11052. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  11053. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  11054. #define RTC_ALRMBR_MNT_Pos (12U)
  11055. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  11056. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  11057. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  11058. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  11059. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  11060. #define RTC_ALRMBR_MNU_Pos (8U)
  11061. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  11062. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  11063. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  11064. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  11065. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  11066. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  11067. #define RTC_ALRMBR_MSK1_Pos (7U)
  11068. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  11069. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  11070. #define RTC_ALRMBR_ST_Pos (4U)
  11071. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  11072. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  11073. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  11074. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  11075. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  11076. #define RTC_ALRMBR_SU_Pos (0U)
  11077. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  11078. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  11079. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  11080. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  11081. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  11082. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  11083. /******************** Bits definition for RTC_WPR register ******************/
  11084. #define RTC_WPR_KEY_Pos (0U)
  11085. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  11086. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  11087. /******************** Bits definition for RTC_SSR register ******************/
  11088. #define RTC_SSR_SS_Pos (0U)
  11089. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  11090. #define RTC_SSR_SS RTC_SSR_SS_Msk
  11091. /******************** Bits definition for RTC_SHIFTR register ***************/
  11092. #define RTC_SHIFTR_SUBFS_Pos (0U)
  11093. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  11094. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  11095. #define RTC_SHIFTR_ADD1S_Pos (31U)
  11096. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  11097. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  11098. /******************** Bits definition for RTC_TSTR register *****************/
  11099. #define RTC_TSTR_PM_Pos (22U)
  11100. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  11101. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  11102. #define RTC_TSTR_HT_Pos (20U)
  11103. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  11104. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  11105. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  11106. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  11107. #define RTC_TSTR_HU_Pos (16U)
  11108. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  11109. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  11110. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  11111. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  11112. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  11113. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  11114. #define RTC_TSTR_MNT_Pos (12U)
  11115. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  11116. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  11117. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  11118. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  11119. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  11120. #define RTC_TSTR_MNU_Pos (8U)
  11121. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  11122. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  11123. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  11124. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  11125. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  11126. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  11127. #define RTC_TSTR_ST_Pos (4U)
  11128. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  11129. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  11130. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  11131. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  11132. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  11133. #define RTC_TSTR_SU_Pos (0U)
  11134. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  11135. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  11136. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  11137. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  11138. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  11139. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  11140. /******************** Bits definition for RTC_TSDR register *****************/
  11141. #define RTC_TSDR_WDU_Pos (13U)
  11142. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  11143. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  11144. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  11145. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  11146. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  11147. #define RTC_TSDR_MT_Pos (12U)
  11148. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  11149. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  11150. #define RTC_TSDR_MU_Pos (8U)
  11151. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  11152. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  11153. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  11154. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  11155. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  11156. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  11157. #define RTC_TSDR_DT_Pos (4U)
  11158. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  11159. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  11160. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  11161. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  11162. #define RTC_TSDR_DU_Pos (0U)
  11163. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  11164. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  11165. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  11166. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  11167. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  11168. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  11169. /******************** Bits definition for RTC_TSSSR register ****************/
  11170. #define RTC_TSSSR_SS_Pos (0U)
  11171. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  11172. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  11173. /******************** Bits definition for RTC_CAL register *****************/
  11174. #define RTC_CALR_CALP_Pos (15U)
  11175. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  11176. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  11177. #define RTC_CALR_CALW8_Pos (14U)
  11178. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  11179. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  11180. #define RTC_CALR_CALW16_Pos (13U)
  11181. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  11182. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  11183. #define RTC_CALR_CALM_Pos (0U)
  11184. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  11185. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  11186. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  11187. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  11188. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  11189. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  11190. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  11191. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  11192. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  11193. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  11194. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  11195. /******************** Bits definition for RTC_TAFCR register ****************/
  11196. #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
  11197. #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
  11198. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
  11199. #define RTC_TAFCR_TSINSEL_Pos (17U)
  11200. #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
  11201. #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
  11202. #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
  11203. #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
  11204. #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
  11205. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  11206. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  11207. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  11208. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  11209. #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  11210. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  11211. #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  11212. #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  11213. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  11214. #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  11215. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  11216. #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  11217. #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  11218. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  11219. #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  11220. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  11221. #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  11222. #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  11223. #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  11224. #define RTC_TAFCR_TAMPTS_Pos (7U)
  11225. #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  11226. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  11227. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  11228. #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  11229. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  11230. #define RTC_TAFCR_TAMP2E_Pos (3U)
  11231. #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  11232. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  11233. #define RTC_TAFCR_TAMPIE_Pos (2U)
  11234. #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  11235. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  11236. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  11237. #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  11238. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  11239. #define RTC_TAFCR_TAMP1E_Pos (0U)
  11240. #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  11241. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  11242. /* Legacy defines */
  11243. #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
  11244. /******************** Bits definition for RTC_ALRMASSR register *************/
  11245. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  11246. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  11247. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  11248. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  11249. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  11250. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  11251. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  11252. #define RTC_ALRMASSR_SS_Pos (0U)
  11253. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  11254. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  11255. /******************** Bits definition for RTC_ALRMBSSR register *************/
  11256. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  11257. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  11258. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  11259. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  11260. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  11261. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  11262. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  11263. #define RTC_ALRMBSSR_SS_Pos (0U)
  11264. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  11265. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  11266. /******************** Bits definition for RTC_BKP0R register ****************/
  11267. #define RTC_BKP0R_Pos (0U)
  11268. #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  11269. #define RTC_BKP0R RTC_BKP0R_Msk
  11270. /******************** Bits definition for RTC_BKP1R register ****************/
  11271. #define RTC_BKP1R_Pos (0U)
  11272. #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  11273. #define RTC_BKP1R RTC_BKP1R_Msk
  11274. /******************** Bits definition for RTC_BKP2R register ****************/
  11275. #define RTC_BKP2R_Pos (0U)
  11276. #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  11277. #define RTC_BKP2R RTC_BKP2R_Msk
  11278. /******************** Bits definition for RTC_BKP3R register ****************/
  11279. #define RTC_BKP3R_Pos (0U)
  11280. #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  11281. #define RTC_BKP3R RTC_BKP3R_Msk
  11282. /******************** Bits definition for RTC_BKP4R register ****************/
  11283. #define RTC_BKP4R_Pos (0U)
  11284. #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  11285. #define RTC_BKP4R RTC_BKP4R_Msk
  11286. /******************** Bits definition for RTC_BKP5R register ****************/
  11287. #define RTC_BKP5R_Pos (0U)
  11288. #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  11289. #define RTC_BKP5R RTC_BKP5R_Msk
  11290. /******************** Bits definition for RTC_BKP6R register ****************/
  11291. #define RTC_BKP6R_Pos (0U)
  11292. #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  11293. #define RTC_BKP6R RTC_BKP6R_Msk
  11294. /******************** Bits definition for RTC_BKP7R register ****************/
  11295. #define RTC_BKP7R_Pos (0U)
  11296. #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  11297. #define RTC_BKP7R RTC_BKP7R_Msk
  11298. /******************** Bits definition for RTC_BKP8R register ****************/
  11299. #define RTC_BKP8R_Pos (0U)
  11300. #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  11301. #define RTC_BKP8R RTC_BKP8R_Msk
  11302. /******************** Bits definition for RTC_BKP9R register ****************/
  11303. #define RTC_BKP9R_Pos (0U)
  11304. #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  11305. #define RTC_BKP9R RTC_BKP9R_Msk
  11306. /******************** Bits definition for RTC_BKP10R register ***************/
  11307. #define RTC_BKP10R_Pos (0U)
  11308. #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  11309. #define RTC_BKP10R RTC_BKP10R_Msk
  11310. /******************** Bits definition for RTC_BKP11R register ***************/
  11311. #define RTC_BKP11R_Pos (0U)
  11312. #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  11313. #define RTC_BKP11R RTC_BKP11R_Msk
  11314. /******************** Bits definition for RTC_BKP12R register ***************/
  11315. #define RTC_BKP12R_Pos (0U)
  11316. #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  11317. #define RTC_BKP12R RTC_BKP12R_Msk
  11318. /******************** Bits definition for RTC_BKP13R register ***************/
  11319. #define RTC_BKP13R_Pos (0U)
  11320. #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  11321. #define RTC_BKP13R RTC_BKP13R_Msk
  11322. /******************** Bits definition for RTC_BKP14R register ***************/
  11323. #define RTC_BKP14R_Pos (0U)
  11324. #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  11325. #define RTC_BKP14R RTC_BKP14R_Msk
  11326. /******************** Bits definition for RTC_BKP15R register ***************/
  11327. #define RTC_BKP15R_Pos (0U)
  11328. #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  11329. #define RTC_BKP15R RTC_BKP15R_Msk
  11330. /******************** Bits definition for RTC_BKP16R register ***************/
  11331. #define RTC_BKP16R_Pos (0U)
  11332. #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  11333. #define RTC_BKP16R RTC_BKP16R_Msk
  11334. /******************** Bits definition for RTC_BKP17R register ***************/
  11335. #define RTC_BKP17R_Pos (0U)
  11336. #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  11337. #define RTC_BKP17R RTC_BKP17R_Msk
  11338. /******************** Bits definition for RTC_BKP18R register ***************/
  11339. #define RTC_BKP18R_Pos (0U)
  11340. #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  11341. #define RTC_BKP18R RTC_BKP18R_Msk
  11342. /******************** Bits definition for RTC_BKP19R register ***************/
  11343. #define RTC_BKP19R_Pos (0U)
  11344. #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  11345. #define RTC_BKP19R RTC_BKP19R_Msk
  11346. /******************** Number of backup registers ******************************/
  11347. #define RTC_BKP_NUMBER 0x000000014U
  11348. /******************************************************************************/
  11349. /* */
  11350. /* Serial Audio Interface */
  11351. /* */
  11352. /******************************************************************************/
  11353. /******************** Bit definition for SAI_GCR register *******************/
  11354. #define SAI_GCR_SYNCIN_Pos (0U)
  11355. #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
  11356. #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
  11357. #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
  11358. #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
  11359. #define SAI_GCR_SYNCOUT_Pos (4U)
  11360. #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
  11361. #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
  11362. #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
  11363. #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
  11364. /******************* Bit definition for SAI_xCR1 register *******************/
  11365. #define SAI_xCR1_MODE_Pos (0U)
  11366. #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
  11367. #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
  11368. #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
  11369. #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
  11370. #define SAI_xCR1_PRTCFG_Pos (2U)
  11371. #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
  11372. #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
  11373. #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
  11374. #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
  11375. #define SAI_xCR1_DS_Pos (5U)
  11376. #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
  11377. #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
  11378. #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
  11379. #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
  11380. #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
  11381. #define SAI_xCR1_LSBFIRST_Pos (8U)
  11382. #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
  11383. #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
  11384. #define SAI_xCR1_CKSTR_Pos (9U)
  11385. #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
  11386. #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
  11387. #define SAI_xCR1_SYNCEN_Pos (10U)
  11388. #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
  11389. #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
  11390. #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
  11391. #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
  11392. #define SAI_xCR1_MONO_Pos (12U)
  11393. #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
  11394. #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
  11395. #define SAI_xCR1_OUTDRIV_Pos (13U)
  11396. #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
  11397. #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
  11398. #define SAI_xCR1_SAIEN_Pos (16U)
  11399. #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
  11400. #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
  11401. #define SAI_xCR1_DMAEN_Pos (17U)
  11402. #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
  11403. #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
  11404. #define SAI_xCR1_NODIV_Pos (19U)
  11405. #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
  11406. #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
  11407. #define SAI_xCR1_MCKDIV_Pos (20U)
  11408. #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
  11409. #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
  11410. #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
  11411. #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
  11412. #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
  11413. #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
  11414. /******************* Bit definition for SAI_xCR2 register *******************/
  11415. #define SAI_xCR2_FTH_Pos (0U)
  11416. #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
  11417. #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
  11418. #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
  11419. #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
  11420. #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
  11421. #define SAI_xCR2_FFLUSH_Pos (3U)
  11422. #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
  11423. #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
  11424. #define SAI_xCR2_TRIS_Pos (4U)
  11425. #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
  11426. #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
  11427. #define SAI_xCR2_MUTE_Pos (5U)
  11428. #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
  11429. #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
  11430. #define SAI_xCR2_MUTEVAL_Pos (6U)
  11431. #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
  11432. #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
  11433. #define SAI_xCR2_MUTECNT_Pos (7U)
  11434. #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
  11435. #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
  11436. #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
  11437. #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
  11438. #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
  11439. #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
  11440. #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
  11441. #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
  11442. #define SAI_xCR2_CPL_Pos (13U)
  11443. #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
  11444. #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
  11445. #define SAI_xCR2_COMP_Pos (14U)
  11446. #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
  11447. #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
  11448. #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
  11449. #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
  11450. /****************** Bit definition for SAI_xFRCR register *******************/
  11451. #define SAI_xFRCR_FRL_Pos (0U)
  11452. #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
  11453. #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
  11454. #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
  11455. #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
  11456. #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
  11457. #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
  11458. #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
  11459. #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
  11460. #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
  11461. #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
  11462. #define SAI_xFRCR_FSALL_Pos (8U)
  11463. #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
  11464. #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
  11465. #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
  11466. #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
  11467. #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
  11468. #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
  11469. #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
  11470. #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
  11471. #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
  11472. #define SAI_xFRCR_FSDEF_Pos (16U)
  11473. #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
  11474. #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
  11475. #define SAI_xFRCR_FSPOL_Pos (17U)
  11476. #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
  11477. #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
  11478. #define SAI_xFRCR_FSOFF_Pos (18U)
  11479. #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
  11480. #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
  11481. /* Legacy defines */
  11482. #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
  11483. /****************** Bit definition for SAI_xSLOTR register *******************/
  11484. #define SAI_xSLOTR_FBOFF_Pos (0U)
  11485. #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
  11486. #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
  11487. #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
  11488. #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
  11489. #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
  11490. #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
  11491. #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
  11492. #define SAI_xSLOTR_SLOTSZ_Pos (6U)
  11493. #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
  11494. #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
  11495. #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
  11496. #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
  11497. #define SAI_xSLOTR_NBSLOT_Pos (8U)
  11498. #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
  11499. #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
  11500. #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
  11501. #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
  11502. #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
  11503. #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
  11504. #define SAI_xSLOTR_SLOTEN_Pos (16U)
  11505. #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
  11506. #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
  11507. /******************* Bit definition for SAI_xIMR register *******************/
  11508. #define SAI_xIMR_OVRUDRIE_Pos (0U)
  11509. #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
  11510. #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
  11511. #define SAI_xIMR_MUTEDETIE_Pos (1U)
  11512. #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
  11513. #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
  11514. #define SAI_xIMR_WCKCFGIE_Pos (2U)
  11515. #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
  11516. #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
  11517. #define SAI_xIMR_FREQIE_Pos (3U)
  11518. #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
  11519. #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
  11520. #define SAI_xIMR_CNRDYIE_Pos (4U)
  11521. #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
  11522. #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
  11523. #define SAI_xIMR_AFSDETIE_Pos (5U)
  11524. #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
  11525. #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
  11526. #define SAI_xIMR_LFSDETIE_Pos (6U)
  11527. #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
  11528. #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
  11529. /******************** Bit definition for SAI_xSR register *******************/
  11530. #define SAI_xSR_OVRUDR_Pos (0U)
  11531. #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
  11532. #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
  11533. #define SAI_xSR_MUTEDET_Pos (1U)
  11534. #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
  11535. #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
  11536. #define SAI_xSR_WCKCFG_Pos (2U)
  11537. #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
  11538. #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
  11539. #define SAI_xSR_FREQ_Pos (3U)
  11540. #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
  11541. #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
  11542. #define SAI_xSR_CNRDY_Pos (4U)
  11543. #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
  11544. #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
  11545. #define SAI_xSR_AFSDET_Pos (5U)
  11546. #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
  11547. #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
  11548. #define SAI_xSR_LFSDET_Pos (6U)
  11549. #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
  11550. #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
  11551. #define SAI_xSR_FLVL_Pos (16U)
  11552. #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
  11553. #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
  11554. #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
  11555. #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
  11556. #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
  11557. /****************** Bit definition for SAI_xCLRFR register ******************/
  11558. #define SAI_xCLRFR_COVRUDR_Pos (0U)
  11559. #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
  11560. #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
  11561. #define SAI_xCLRFR_CMUTEDET_Pos (1U)
  11562. #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
  11563. #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
  11564. #define SAI_xCLRFR_CWCKCFG_Pos (2U)
  11565. #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
  11566. #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
  11567. #define SAI_xCLRFR_CFREQ_Pos (3U)
  11568. #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
  11569. #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
  11570. #define SAI_xCLRFR_CCNRDY_Pos (4U)
  11571. #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
  11572. #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
  11573. #define SAI_xCLRFR_CAFSDET_Pos (5U)
  11574. #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
  11575. #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
  11576. #define SAI_xCLRFR_CLFSDET_Pos (6U)
  11577. #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
  11578. #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
  11579. /****************** Bit definition for SAI_xDR register ******************/
  11580. #define SAI_xDR_DATA_Pos (0U)
  11581. #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
  11582. #define SAI_xDR_DATA SAI_xDR_DATA_Msk
  11583. /******************************************************************************/
  11584. /* */
  11585. /* SD host Interface */
  11586. /* */
  11587. /******************************************************************************/
  11588. /****************** Bit definition for SDIO_POWER register ******************/
  11589. #define SDIO_POWER_PWRCTRL_Pos (0U)
  11590. #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
  11591. #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
  11592. #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
  11593. #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
  11594. /****************** Bit definition for SDIO_CLKCR register ******************/
  11595. #define SDIO_CLKCR_CLKDIV_Pos (0U)
  11596. #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
  11597. #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
  11598. #define SDIO_CLKCR_CLKEN_Pos (8U)
  11599. #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
  11600. #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
  11601. #define SDIO_CLKCR_PWRSAV_Pos (9U)
  11602. #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
  11603. #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
  11604. #define SDIO_CLKCR_BYPASS_Pos (10U)
  11605. #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
  11606. #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
  11607. #define SDIO_CLKCR_WIDBUS_Pos (11U)
  11608. #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
  11609. #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
  11610. #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
  11611. #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
  11612. #define SDIO_CLKCR_NEGEDGE_Pos (13U)
  11613. #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
  11614. #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
  11615. #define SDIO_CLKCR_HWFC_EN_Pos (14U)
  11616. #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
  11617. #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
  11618. /******************* Bit definition for SDIO_ARG register *******************/
  11619. #define SDIO_ARG_CMDARG_Pos (0U)
  11620. #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
  11621. #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
  11622. /******************* Bit definition for SDIO_CMD register *******************/
  11623. #define SDIO_CMD_CMDINDEX_Pos (0U)
  11624. #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
  11625. #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
  11626. #define SDIO_CMD_WAITRESP_Pos (6U)
  11627. #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
  11628. #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
  11629. #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
  11630. #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
  11631. #define SDIO_CMD_WAITINT_Pos (8U)
  11632. #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
  11633. #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
  11634. #define SDIO_CMD_WAITPEND_Pos (9U)
  11635. #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
  11636. #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
  11637. #define SDIO_CMD_CPSMEN_Pos (10U)
  11638. #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
  11639. #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
  11640. #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
  11641. #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
  11642. #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
  11643. #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
  11644. #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
  11645. #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
  11646. #define SDIO_CMD_NIEN_Pos (13U)
  11647. #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
  11648. #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
  11649. #define SDIO_CMD_CEATACMD_Pos (14U)
  11650. #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
  11651. #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
  11652. /***************** Bit definition for SDIO_RESPCMD register *****************/
  11653. #define SDIO_RESPCMD_RESPCMD_Pos (0U)
  11654. #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
  11655. #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
  11656. /****************** Bit definition for SDIO_RESP0 register ******************/
  11657. #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
  11658. #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
  11659. #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
  11660. /****************** Bit definition for SDIO_RESP1 register ******************/
  11661. #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
  11662. #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
  11663. #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
  11664. /****************** Bit definition for SDIO_RESP2 register ******************/
  11665. #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
  11666. #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
  11667. #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
  11668. /****************** Bit definition for SDIO_RESP3 register ******************/
  11669. #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
  11670. #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
  11671. #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
  11672. /****************** Bit definition for SDIO_RESP4 register ******************/
  11673. #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
  11674. #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
  11675. #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
  11676. /****************** Bit definition for SDIO_DTIMER register *****************/
  11677. #define SDIO_DTIMER_DATATIME_Pos (0U)
  11678. #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
  11679. #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
  11680. /****************** Bit definition for SDIO_DLEN register *******************/
  11681. #define SDIO_DLEN_DATALENGTH_Pos (0U)
  11682. #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
  11683. #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
  11684. /****************** Bit definition for SDIO_DCTRL register ******************/
  11685. #define SDIO_DCTRL_DTEN_Pos (0U)
  11686. #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
  11687. #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
  11688. #define SDIO_DCTRL_DTDIR_Pos (1U)
  11689. #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
  11690. #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
  11691. #define SDIO_DCTRL_DTMODE_Pos (2U)
  11692. #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
  11693. #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
  11694. #define SDIO_DCTRL_DMAEN_Pos (3U)
  11695. #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
  11696. #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
  11697. #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
  11698. #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
  11699. #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
  11700. #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
  11701. #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
  11702. #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
  11703. #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
  11704. #define SDIO_DCTRL_RWSTART_Pos (8U)
  11705. #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
  11706. #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
  11707. #define SDIO_DCTRL_RWSTOP_Pos (9U)
  11708. #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
  11709. #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
  11710. #define SDIO_DCTRL_RWMOD_Pos (10U)
  11711. #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
  11712. #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
  11713. #define SDIO_DCTRL_SDIOEN_Pos (11U)
  11714. #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
  11715. #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
  11716. /****************** Bit definition for SDIO_DCOUNT register *****************/
  11717. #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
  11718. #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
  11719. #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
  11720. /****************** Bit definition for SDIO_STA register ********************/
  11721. #define SDIO_STA_CCRCFAIL_Pos (0U)
  11722. #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
  11723. #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
  11724. #define SDIO_STA_DCRCFAIL_Pos (1U)
  11725. #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
  11726. #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
  11727. #define SDIO_STA_CTIMEOUT_Pos (2U)
  11728. #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
  11729. #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
  11730. #define SDIO_STA_DTIMEOUT_Pos (3U)
  11731. #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
  11732. #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
  11733. #define SDIO_STA_TXUNDERR_Pos (4U)
  11734. #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
  11735. #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
  11736. #define SDIO_STA_RXOVERR_Pos (5U)
  11737. #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
  11738. #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
  11739. #define SDIO_STA_CMDREND_Pos (6U)
  11740. #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
  11741. #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
  11742. #define SDIO_STA_CMDSENT_Pos (7U)
  11743. #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
  11744. #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
  11745. #define SDIO_STA_DATAEND_Pos (8U)
  11746. #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
  11747. #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
  11748. #define SDIO_STA_STBITERR_Pos (9U)
  11749. #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
  11750. #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
  11751. #define SDIO_STA_DBCKEND_Pos (10U)
  11752. #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
  11753. #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
  11754. #define SDIO_STA_CMDACT_Pos (11U)
  11755. #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
  11756. #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
  11757. #define SDIO_STA_TXACT_Pos (12U)
  11758. #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
  11759. #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
  11760. #define SDIO_STA_RXACT_Pos (13U)
  11761. #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
  11762. #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
  11763. #define SDIO_STA_TXFIFOHE_Pos (14U)
  11764. #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
  11765. #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
  11766. #define SDIO_STA_RXFIFOHF_Pos (15U)
  11767. #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
  11768. #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
  11769. #define SDIO_STA_TXFIFOF_Pos (16U)
  11770. #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
  11771. #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
  11772. #define SDIO_STA_RXFIFOF_Pos (17U)
  11773. #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
  11774. #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
  11775. #define SDIO_STA_TXFIFOE_Pos (18U)
  11776. #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
  11777. #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
  11778. #define SDIO_STA_RXFIFOE_Pos (19U)
  11779. #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
  11780. #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
  11781. #define SDIO_STA_TXDAVL_Pos (20U)
  11782. #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
  11783. #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
  11784. #define SDIO_STA_RXDAVL_Pos (21U)
  11785. #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
  11786. #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
  11787. #define SDIO_STA_SDIOIT_Pos (22U)
  11788. #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
  11789. #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
  11790. #define SDIO_STA_CEATAEND_Pos (23U)
  11791. #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
  11792. #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
  11793. /******************* Bit definition for SDIO_ICR register *******************/
  11794. #define SDIO_ICR_CCRCFAILC_Pos (0U)
  11795. #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
  11796. #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
  11797. #define SDIO_ICR_DCRCFAILC_Pos (1U)
  11798. #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
  11799. #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
  11800. #define SDIO_ICR_CTIMEOUTC_Pos (2U)
  11801. #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
  11802. #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
  11803. #define SDIO_ICR_DTIMEOUTC_Pos (3U)
  11804. #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
  11805. #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
  11806. #define SDIO_ICR_TXUNDERRC_Pos (4U)
  11807. #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
  11808. #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
  11809. #define SDIO_ICR_RXOVERRC_Pos (5U)
  11810. #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
  11811. #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
  11812. #define SDIO_ICR_CMDRENDC_Pos (6U)
  11813. #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
  11814. #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
  11815. #define SDIO_ICR_CMDSENTC_Pos (7U)
  11816. #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
  11817. #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
  11818. #define SDIO_ICR_DATAENDC_Pos (8U)
  11819. #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
  11820. #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
  11821. #define SDIO_ICR_STBITERRC_Pos (9U)
  11822. #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
  11823. #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
  11824. #define SDIO_ICR_DBCKENDC_Pos (10U)
  11825. #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
  11826. #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
  11827. #define SDIO_ICR_SDIOITC_Pos (22U)
  11828. #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
  11829. #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
  11830. #define SDIO_ICR_CEATAENDC_Pos (23U)
  11831. #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
  11832. #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
  11833. /****************** Bit definition for SDIO_MASK register *******************/
  11834. #define SDIO_MASK_CCRCFAILIE_Pos (0U)
  11835. #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
  11836. #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
  11837. #define SDIO_MASK_DCRCFAILIE_Pos (1U)
  11838. #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
  11839. #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
  11840. #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
  11841. #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
  11842. #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
  11843. #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
  11844. #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
  11845. #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
  11846. #define SDIO_MASK_TXUNDERRIE_Pos (4U)
  11847. #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
  11848. #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
  11849. #define SDIO_MASK_RXOVERRIE_Pos (5U)
  11850. #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
  11851. #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
  11852. #define SDIO_MASK_CMDRENDIE_Pos (6U)
  11853. #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
  11854. #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
  11855. #define SDIO_MASK_CMDSENTIE_Pos (7U)
  11856. #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
  11857. #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
  11858. #define SDIO_MASK_DATAENDIE_Pos (8U)
  11859. #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
  11860. #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
  11861. #define SDIO_MASK_STBITERRIE_Pos (9U)
  11862. #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
  11863. #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
  11864. #define SDIO_MASK_DBCKENDIE_Pos (10U)
  11865. #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
  11866. #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
  11867. #define SDIO_MASK_CMDACTIE_Pos (11U)
  11868. #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
  11869. #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
  11870. #define SDIO_MASK_TXACTIE_Pos (12U)
  11871. #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
  11872. #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
  11873. #define SDIO_MASK_RXACTIE_Pos (13U)
  11874. #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
  11875. #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
  11876. #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
  11877. #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
  11878. #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
  11879. #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
  11880. #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
  11881. #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
  11882. #define SDIO_MASK_TXFIFOFIE_Pos (16U)
  11883. #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
  11884. #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
  11885. #define SDIO_MASK_RXFIFOFIE_Pos (17U)
  11886. #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
  11887. #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
  11888. #define SDIO_MASK_TXFIFOEIE_Pos (18U)
  11889. #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
  11890. #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
  11891. #define SDIO_MASK_RXFIFOEIE_Pos (19U)
  11892. #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
  11893. #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
  11894. #define SDIO_MASK_TXDAVLIE_Pos (20U)
  11895. #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
  11896. #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
  11897. #define SDIO_MASK_RXDAVLIE_Pos (21U)
  11898. #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
  11899. #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
  11900. #define SDIO_MASK_SDIOITIE_Pos (22U)
  11901. #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
  11902. #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
  11903. #define SDIO_MASK_CEATAENDIE_Pos (23U)
  11904. #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
  11905. #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
  11906. /***************** Bit definition for SDIO_FIFOCNT register *****************/
  11907. #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
  11908. #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
  11909. #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
  11910. /****************** Bit definition for SDIO_FIFO register *******************/
  11911. #define SDIO_FIFO_FIFODATA_Pos (0U)
  11912. #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
  11913. #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
  11914. /******************************************************************************/
  11915. /* */
  11916. /* Serial Peripheral Interface */
  11917. /* */
  11918. /******************************************************************************/
  11919. #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
  11920. /******************* Bit definition for SPI_CR1 register ********************/
  11921. #define SPI_CR1_CPHA_Pos (0U)
  11922. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  11923. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  11924. #define SPI_CR1_CPOL_Pos (1U)
  11925. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  11926. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  11927. #define SPI_CR1_MSTR_Pos (2U)
  11928. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  11929. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  11930. #define SPI_CR1_BR_Pos (3U)
  11931. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  11932. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  11933. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  11934. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  11935. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  11936. #define SPI_CR1_SPE_Pos (6U)
  11937. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  11938. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  11939. #define SPI_CR1_LSBFIRST_Pos (7U)
  11940. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  11941. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  11942. #define SPI_CR1_SSI_Pos (8U)
  11943. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  11944. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  11945. #define SPI_CR1_SSM_Pos (9U)
  11946. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  11947. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  11948. #define SPI_CR1_RXONLY_Pos (10U)
  11949. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  11950. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  11951. #define SPI_CR1_DFF_Pos (11U)
  11952. #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
  11953. #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
  11954. #define SPI_CR1_CRCNEXT_Pos (12U)
  11955. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  11956. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  11957. #define SPI_CR1_CRCEN_Pos (13U)
  11958. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  11959. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  11960. #define SPI_CR1_BIDIOE_Pos (14U)
  11961. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  11962. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  11963. #define SPI_CR1_BIDIMODE_Pos (15U)
  11964. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  11965. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  11966. /******************* Bit definition for SPI_CR2 register ********************/
  11967. #define SPI_CR2_RXDMAEN_Pos (0U)
  11968. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  11969. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
  11970. #define SPI_CR2_TXDMAEN_Pos (1U)
  11971. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  11972. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
  11973. #define SPI_CR2_SSOE_Pos (2U)
  11974. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  11975. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
  11976. #define SPI_CR2_FRF_Pos (4U)
  11977. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  11978. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
  11979. #define SPI_CR2_ERRIE_Pos (5U)
  11980. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  11981. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
  11982. #define SPI_CR2_RXNEIE_Pos (6U)
  11983. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  11984. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
  11985. #define SPI_CR2_TXEIE_Pos (7U)
  11986. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  11987. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
  11988. /******************** Bit definition for SPI_SR register ********************/
  11989. #define SPI_SR_RXNE_Pos (0U)
  11990. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  11991. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
  11992. #define SPI_SR_TXE_Pos (1U)
  11993. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  11994. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
  11995. #define SPI_SR_CHSIDE_Pos (2U)
  11996. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  11997. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
  11998. #define SPI_SR_UDR_Pos (3U)
  11999. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  12000. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
  12001. #define SPI_SR_CRCERR_Pos (4U)
  12002. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  12003. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
  12004. #define SPI_SR_MODF_Pos (5U)
  12005. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  12006. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
  12007. #define SPI_SR_OVR_Pos (6U)
  12008. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  12009. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
  12010. #define SPI_SR_BSY_Pos (7U)
  12011. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  12012. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
  12013. #define SPI_SR_FRE_Pos (8U)
  12014. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  12015. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
  12016. /******************** Bit definition for SPI_DR register ********************/
  12017. #define SPI_DR_DR_Pos (0U)
  12018. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  12019. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  12020. /******************* Bit definition for SPI_CRCPR register ******************/
  12021. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  12022. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  12023. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  12024. /****************** Bit definition for SPI_RXCRCR register ******************/
  12025. #define SPI_RXCRCR_RXCRC_Pos (0U)
  12026. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  12027. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  12028. /****************** Bit definition for SPI_TXCRCR register ******************/
  12029. #define SPI_TXCRCR_TXCRC_Pos (0U)
  12030. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  12031. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  12032. /****************** Bit definition for SPI_I2SCFGR register *****************/
  12033. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  12034. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  12035. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  12036. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  12037. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  12038. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  12039. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  12040. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  12041. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  12042. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  12043. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  12044. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  12045. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  12046. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  12047. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  12048. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  12049. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  12050. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  12051. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  12052. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  12053. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  12054. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  12055. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  12056. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  12057. #define SPI_I2SCFGR_I2SE_Pos (10U)
  12058. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  12059. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  12060. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  12061. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  12062. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  12063. /****************** Bit definition for SPI_I2SPR register *******************/
  12064. #define SPI_I2SPR_I2SDIV_Pos (0U)
  12065. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  12066. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  12067. #define SPI_I2SPR_ODD_Pos (8U)
  12068. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  12069. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  12070. #define SPI_I2SPR_MCKOE_Pos (9U)
  12071. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  12072. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  12073. /******************************************************************************/
  12074. /* */
  12075. /* SYSCFG */
  12076. /* */
  12077. /******************************************************************************/
  12078. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  12079. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  12080. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
  12081. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  12082. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  12083. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  12084. #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
  12085. #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
  12086. #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
  12087. #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
  12088. #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
  12089. #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
  12090. #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
  12091. #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
  12092. /* Legacy Defines */
  12093. #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
  12094. /****************** Bit definition for SYSCFG_PMC register ******************/
  12095. #define SYSCFG_PMC_ADCxDC2_Pos (16U)
  12096. #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
  12097. #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
  12098. #define SYSCFG_PMC_ADC1DC2_Pos (16U)
  12099. #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
  12100. #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  12101. #define SYSCFG_PMC_ADC2DC2_Pos (17U)
  12102. #define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
  12103. #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  12104. #define SYSCFG_PMC_ADC3DC2_Pos (18U)
  12105. #define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
  12106. #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  12107. #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
  12108. #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
  12109. #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
  12110. /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
  12111. #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
  12112. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  12113. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  12114. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  12115. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  12116. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  12117. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  12118. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  12119. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  12120. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  12121. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  12122. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  12123. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  12124. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  12125. /**
  12126. * @brief EXTI0 configuration
  12127. */
  12128. #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
  12129. #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
  12130. #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
  12131. #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
  12132. #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
  12133. #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
  12134. #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
  12135. #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
  12136. #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
  12137. #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
  12138. #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
  12139. /**
  12140. * @brief EXTI1 configuration
  12141. */
  12142. #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
  12143. #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
  12144. #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
  12145. #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
  12146. #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
  12147. #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
  12148. #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
  12149. #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
  12150. #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
  12151. #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
  12152. #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
  12153. /**
  12154. * @brief EXTI2 configuration
  12155. */
  12156. #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
  12157. #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
  12158. #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
  12159. #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
  12160. #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
  12161. #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
  12162. #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
  12163. #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
  12164. #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
  12165. #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
  12166. #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
  12167. /**
  12168. * @brief EXTI3 configuration
  12169. */
  12170. #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
  12171. #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
  12172. #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
  12173. #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
  12174. #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
  12175. #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
  12176. #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
  12177. #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
  12178. #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
  12179. #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
  12180. #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
  12181. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  12182. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  12183. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  12184. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  12185. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  12186. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  12187. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  12188. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  12189. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  12190. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  12191. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  12192. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  12193. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  12194. /**
  12195. * @brief EXTI4 configuration
  12196. */
  12197. #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
  12198. #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
  12199. #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
  12200. #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
  12201. #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
  12202. #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
  12203. #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
  12204. #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
  12205. #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
  12206. #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
  12207. #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
  12208. /**
  12209. * @brief EXTI5 configuration
  12210. */
  12211. #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
  12212. #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
  12213. #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
  12214. #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
  12215. #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
  12216. #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
  12217. #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
  12218. #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
  12219. #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
  12220. #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
  12221. #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
  12222. /**
  12223. * @brief EXTI6 configuration
  12224. */
  12225. #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
  12226. #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
  12227. #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
  12228. #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
  12229. #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
  12230. #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
  12231. #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
  12232. #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
  12233. #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
  12234. #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
  12235. #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
  12236. /**
  12237. * @brief EXTI7 configuration
  12238. */
  12239. #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
  12240. #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
  12241. #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
  12242. #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
  12243. #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
  12244. #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
  12245. #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
  12246. #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
  12247. #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
  12248. #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
  12249. #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
  12250. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  12251. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  12252. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  12253. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  12254. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  12255. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  12256. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  12257. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  12258. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  12259. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  12260. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  12261. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  12262. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  12263. /**
  12264. * @brief EXTI8 configuration
  12265. */
  12266. #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
  12267. #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
  12268. #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
  12269. #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
  12270. #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
  12271. #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
  12272. #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
  12273. #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
  12274. #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
  12275. #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
  12276. /**
  12277. * @brief EXTI9 configuration
  12278. */
  12279. #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
  12280. #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
  12281. #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
  12282. #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
  12283. #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
  12284. #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
  12285. #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
  12286. #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
  12287. #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
  12288. #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
  12289. /**
  12290. * @brief EXTI10 configuration
  12291. */
  12292. #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
  12293. #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
  12294. #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
  12295. #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
  12296. #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
  12297. #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
  12298. #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
  12299. #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
  12300. #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
  12301. #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
  12302. /**
  12303. * @brief EXTI11 configuration
  12304. */
  12305. #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
  12306. #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
  12307. #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
  12308. #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
  12309. #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
  12310. #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
  12311. #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
  12312. #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
  12313. #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
  12314. #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
  12315. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  12316. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  12317. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  12318. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  12319. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  12320. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  12321. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  12322. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  12323. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  12324. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  12325. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  12326. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  12327. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  12328. /**
  12329. * @brief EXTI12 configuration
  12330. */
  12331. #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
  12332. #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
  12333. #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
  12334. #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
  12335. #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
  12336. #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
  12337. #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
  12338. #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
  12339. #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
  12340. #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
  12341. /**
  12342. * @brief EXTI13 configuration
  12343. */
  12344. #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
  12345. #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
  12346. #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
  12347. #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
  12348. #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
  12349. #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
  12350. #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
  12351. #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
  12352. #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
  12353. #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
  12354. /**
  12355. * @brief EXTI14 configuration
  12356. */
  12357. #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
  12358. #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
  12359. #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
  12360. #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
  12361. #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
  12362. #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
  12363. #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
  12364. #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
  12365. #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
  12366. #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
  12367. /**
  12368. * @brief EXTI15 configuration
  12369. */
  12370. #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
  12371. #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
  12372. #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
  12373. #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
  12374. #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
  12375. #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
  12376. #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
  12377. #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
  12378. #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
  12379. #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
  12380. /****************** Bit definition for SYSCFG_CMPCR register ****************/
  12381. #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
  12382. #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
  12383. #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
  12384. #define SYSCFG_CMPCR_READY_Pos (8U)
  12385. #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
  12386. #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
  12387. /******************************************************************************/
  12388. /* */
  12389. /* TIM */
  12390. /* */
  12391. /******************************************************************************/
  12392. /******************* Bit definition for TIM_CR1 register ********************/
  12393. #define TIM_CR1_CEN_Pos (0U)
  12394. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  12395. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  12396. #define TIM_CR1_UDIS_Pos (1U)
  12397. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  12398. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  12399. #define TIM_CR1_URS_Pos (2U)
  12400. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  12401. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  12402. #define TIM_CR1_OPM_Pos (3U)
  12403. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  12404. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  12405. #define TIM_CR1_DIR_Pos (4U)
  12406. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  12407. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  12408. #define TIM_CR1_CMS_Pos (5U)
  12409. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  12410. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  12411. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
  12412. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
  12413. #define TIM_CR1_ARPE_Pos (7U)
  12414. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  12415. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  12416. #define TIM_CR1_CKD_Pos (8U)
  12417. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  12418. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  12419. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
  12420. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
  12421. /******************* Bit definition for TIM_CR2 register ********************/
  12422. #define TIM_CR2_CCPC_Pos (0U)
  12423. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  12424. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  12425. #define TIM_CR2_CCUS_Pos (2U)
  12426. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  12427. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  12428. #define TIM_CR2_CCDS_Pos (3U)
  12429. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  12430. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  12431. #define TIM_CR2_MMS_Pos (4U)
  12432. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  12433. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  12434. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
  12435. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
  12436. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
  12437. #define TIM_CR2_TI1S_Pos (7U)
  12438. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  12439. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  12440. #define TIM_CR2_OIS1_Pos (8U)
  12441. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  12442. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  12443. #define TIM_CR2_OIS1N_Pos (9U)
  12444. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  12445. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  12446. #define TIM_CR2_OIS2_Pos (10U)
  12447. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  12448. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  12449. #define TIM_CR2_OIS2N_Pos (11U)
  12450. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  12451. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  12452. #define TIM_CR2_OIS3_Pos (12U)
  12453. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  12454. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  12455. #define TIM_CR2_OIS3N_Pos (13U)
  12456. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  12457. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  12458. #define TIM_CR2_OIS4_Pos (14U)
  12459. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  12460. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  12461. /******************* Bit definition for TIM_SMCR register *******************/
  12462. #define TIM_SMCR_SMS_Pos (0U)
  12463. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  12464. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  12465. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
  12466. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
  12467. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
  12468. #define TIM_SMCR_TS_Pos (4U)
  12469. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  12470. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  12471. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
  12472. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
  12473. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
  12474. #define TIM_SMCR_MSM_Pos (7U)
  12475. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  12476. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  12477. #define TIM_SMCR_ETF_Pos (8U)
  12478. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  12479. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  12480. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
  12481. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
  12482. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
  12483. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
  12484. #define TIM_SMCR_ETPS_Pos (12U)
  12485. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  12486. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  12487. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
  12488. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
  12489. #define TIM_SMCR_ECE_Pos (14U)
  12490. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  12491. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  12492. #define TIM_SMCR_ETP_Pos (15U)
  12493. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  12494. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  12495. /******************* Bit definition for TIM_DIER register *******************/
  12496. #define TIM_DIER_UIE_Pos (0U)
  12497. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  12498. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  12499. #define TIM_DIER_CC1IE_Pos (1U)
  12500. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  12501. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  12502. #define TIM_DIER_CC2IE_Pos (2U)
  12503. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  12504. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  12505. #define TIM_DIER_CC3IE_Pos (3U)
  12506. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  12507. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  12508. #define TIM_DIER_CC4IE_Pos (4U)
  12509. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  12510. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  12511. #define TIM_DIER_COMIE_Pos (5U)
  12512. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  12513. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  12514. #define TIM_DIER_TIE_Pos (6U)
  12515. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  12516. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  12517. #define TIM_DIER_BIE_Pos (7U)
  12518. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  12519. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  12520. #define TIM_DIER_UDE_Pos (8U)
  12521. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  12522. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  12523. #define TIM_DIER_CC1DE_Pos (9U)
  12524. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  12525. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  12526. #define TIM_DIER_CC2DE_Pos (10U)
  12527. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  12528. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  12529. #define TIM_DIER_CC3DE_Pos (11U)
  12530. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  12531. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  12532. #define TIM_DIER_CC4DE_Pos (12U)
  12533. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  12534. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  12535. #define TIM_DIER_COMDE_Pos (13U)
  12536. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  12537. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  12538. #define TIM_DIER_TDE_Pos (14U)
  12539. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  12540. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  12541. /******************** Bit definition for TIM_SR register ********************/
  12542. #define TIM_SR_UIF_Pos (0U)
  12543. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  12544. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  12545. #define TIM_SR_CC1IF_Pos (1U)
  12546. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  12547. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  12548. #define TIM_SR_CC2IF_Pos (2U)
  12549. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  12550. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  12551. #define TIM_SR_CC3IF_Pos (3U)
  12552. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  12553. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  12554. #define TIM_SR_CC4IF_Pos (4U)
  12555. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  12556. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  12557. #define TIM_SR_COMIF_Pos (5U)
  12558. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  12559. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  12560. #define TIM_SR_TIF_Pos (6U)
  12561. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  12562. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  12563. #define TIM_SR_BIF_Pos (7U)
  12564. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  12565. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  12566. #define TIM_SR_CC1OF_Pos (9U)
  12567. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  12568. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  12569. #define TIM_SR_CC2OF_Pos (10U)
  12570. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  12571. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  12572. #define TIM_SR_CC3OF_Pos (11U)
  12573. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  12574. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  12575. #define TIM_SR_CC4OF_Pos (12U)
  12576. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  12577. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  12578. /******************* Bit definition for TIM_EGR register ********************/
  12579. #define TIM_EGR_UG_Pos (0U)
  12580. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  12581. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  12582. #define TIM_EGR_CC1G_Pos (1U)
  12583. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  12584. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  12585. #define TIM_EGR_CC2G_Pos (2U)
  12586. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  12587. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  12588. #define TIM_EGR_CC3G_Pos (3U)
  12589. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  12590. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  12591. #define TIM_EGR_CC4G_Pos (4U)
  12592. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  12593. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  12594. #define TIM_EGR_COMG_Pos (5U)
  12595. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  12596. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  12597. #define TIM_EGR_TG_Pos (6U)
  12598. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  12599. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  12600. #define TIM_EGR_BG_Pos (7U)
  12601. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  12602. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  12603. /****************** Bit definition for TIM_CCMR1 register *******************/
  12604. #define TIM_CCMR1_CC1S_Pos (0U)
  12605. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  12606. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  12607. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
  12608. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
  12609. #define TIM_CCMR1_OC1FE_Pos (2U)
  12610. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  12611. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  12612. #define TIM_CCMR1_OC1PE_Pos (3U)
  12613. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  12614. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  12615. #define TIM_CCMR1_OC1M_Pos (4U)
  12616. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  12617. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  12618. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
  12619. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
  12620. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
  12621. #define TIM_CCMR1_OC1CE_Pos (7U)
  12622. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  12623. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  12624. #define TIM_CCMR1_CC2S_Pos (8U)
  12625. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  12626. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  12627. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
  12628. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
  12629. #define TIM_CCMR1_OC2FE_Pos (10U)
  12630. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  12631. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  12632. #define TIM_CCMR1_OC2PE_Pos (11U)
  12633. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  12634. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  12635. #define TIM_CCMR1_OC2M_Pos (12U)
  12636. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  12637. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  12638. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
  12639. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
  12640. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
  12641. #define TIM_CCMR1_OC2CE_Pos (15U)
  12642. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  12643. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  12644. /*----------------------------------------------------------------------------*/
  12645. #define TIM_CCMR1_IC1PSC_Pos (2U)
  12646. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  12647. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  12648. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
  12649. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
  12650. #define TIM_CCMR1_IC1F_Pos (4U)
  12651. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  12652. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  12653. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
  12654. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
  12655. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
  12656. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
  12657. #define TIM_CCMR1_IC2PSC_Pos (10U)
  12658. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  12659. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  12660. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
  12661. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
  12662. #define TIM_CCMR1_IC2F_Pos (12U)
  12663. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  12664. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  12665. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
  12666. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
  12667. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
  12668. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
  12669. /****************** Bit definition for TIM_CCMR2 register *******************/
  12670. #define TIM_CCMR2_CC3S_Pos (0U)
  12671. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  12672. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  12673. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
  12674. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
  12675. #define TIM_CCMR2_OC3FE_Pos (2U)
  12676. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  12677. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  12678. #define TIM_CCMR2_OC3PE_Pos (3U)
  12679. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  12680. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  12681. #define TIM_CCMR2_OC3M_Pos (4U)
  12682. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  12683. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  12684. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
  12685. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
  12686. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
  12687. #define TIM_CCMR2_OC3CE_Pos (7U)
  12688. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  12689. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  12690. #define TIM_CCMR2_CC4S_Pos (8U)
  12691. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  12692. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  12693. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
  12694. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
  12695. #define TIM_CCMR2_OC4FE_Pos (10U)
  12696. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  12697. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  12698. #define TIM_CCMR2_OC4PE_Pos (11U)
  12699. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  12700. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  12701. #define TIM_CCMR2_OC4M_Pos (12U)
  12702. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  12703. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  12704. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
  12705. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
  12706. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
  12707. #define TIM_CCMR2_OC4CE_Pos (15U)
  12708. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  12709. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  12710. /*----------------------------------------------------------------------------*/
  12711. #define TIM_CCMR2_IC3PSC_Pos (2U)
  12712. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  12713. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  12714. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
  12715. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
  12716. #define TIM_CCMR2_IC3F_Pos (4U)
  12717. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  12718. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  12719. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
  12720. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
  12721. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
  12722. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
  12723. #define TIM_CCMR2_IC4PSC_Pos (10U)
  12724. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  12725. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  12726. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
  12727. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
  12728. #define TIM_CCMR2_IC4F_Pos (12U)
  12729. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  12730. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  12731. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
  12732. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
  12733. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
  12734. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
  12735. /******************* Bit definition for TIM_CCER register *******************/
  12736. #define TIM_CCER_CC1E_Pos (0U)
  12737. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  12738. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  12739. #define TIM_CCER_CC1P_Pos (1U)
  12740. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  12741. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  12742. #define TIM_CCER_CC1NE_Pos (2U)
  12743. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  12744. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  12745. #define TIM_CCER_CC1NP_Pos (3U)
  12746. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  12747. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  12748. #define TIM_CCER_CC2E_Pos (4U)
  12749. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  12750. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  12751. #define TIM_CCER_CC2P_Pos (5U)
  12752. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  12753. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  12754. #define TIM_CCER_CC2NE_Pos (6U)
  12755. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  12756. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  12757. #define TIM_CCER_CC2NP_Pos (7U)
  12758. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  12759. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  12760. #define TIM_CCER_CC3E_Pos (8U)
  12761. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  12762. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  12763. #define TIM_CCER_CC3P_Pos (9U)
  12764. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  12765. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  12766. #define TIM_CCER_CC3NE_Pos (10U)
  12767. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  12768. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  12769. #define TIM_CCER_CC3NP_Pos (11U)
  12770. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  12771. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  12772. #define TIM_CCER_CC4E_Pos (12U)
  12773. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  12774. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  12775. #define TIM_CCER_CC4P_Pos (13U)
  12776. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  12777. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  12778. #define TIM_CCER_CC4NP_Pos (15U)
  12779. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  12780. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  12781. /******************* Bit definition for TIM_CNT register ********************/
  12782. #define TIM_CNT_CNT_Pos (0U)
  12783. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  12784. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  12785. /******************* Bit definition for TIM_PSC register ********************/
  12786. #define TIM_PSC_PSC_Pos (0U)
  12787. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  12788. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  12789. /******************* Bit definition for TIM_ARR register ********************/
  12790. #define TIM_ARR_ARR_Pos (0U)
  12791. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  12792. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  12793. /******************* Bit definition for TIM_RCR register ********************/
  12794. #define TIM_RCR_REP_Pos (0U)
  12795. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  12796. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  12797. /******************* Bit definition for TIM_CCR1 register *******************/
  12798. #define TIM_CCR1_CCR1_Pos (0U)
  12799. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  12800. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  12801. /******************* Bit definition for TIM_CCR2 register *******************/
  12802. #define TIM_CCR2_CCR2_Pos (0U)
  12803. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  12804. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  12805. /******************* Bit definition for TIM_CCR3 register *******************/
  12806. #define TIM_CCR3_CCR3_Pos (0U)
  12807. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  12808. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  12809. /******************* Bit definition for TIM_CCR4 register *******************/
  12810. #define TIM_CCR4_CCR4_Pos (0U)
  12811. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  12812. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  12813. /******************* Bit definition for TIM_BDTR register *******************/
  12814. #define TIM_BDTR_DTG_Pos (0U)
  12815. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  12816. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  12817. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
  12818. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
  12819. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
  12820. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
  12821. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
  12822. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
  12823. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
  12824. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
  12825. #define TIM_BDTR_LOCK_Pos (8U)
  12826. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  12827. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  12828. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
  12829. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
  12830. #define TIM_BDTR_OSSI_Pos (10U)
  12831. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  12832. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  12833. #define TIM_BDTR_OSSR_Pos (11U)
  12834. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  12835. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  12836. #define TIM_BDTR_BKE_Pos (12U)
  12837. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  12838. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  12839. #define TIM_BDTR_BKP_Pos (13U)
  12840. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  12841. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  12842. #define TIM_BDTR_AOE_Pos (14U)
  12843. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  12844. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  12845. #define TIM_BDTR_MOE_Pos (15U)
  12846. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  12847. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  12848. /******************* Bit definition for TIM_DCR register ********************/
  12849. #define TIM_DCR_DBA_Pos (0U)
  12850. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  12851. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  12852. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
  12853. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
  12854. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
  12855. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
  12856. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
  12857. #define TIM_DCR_DBL_Pos (8U)
  12858. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  12859. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  12860. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
  12861. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
  12862. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
  12863. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
  12864. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
  12865. /******************* Bit definition for TIM_DMAR register *******************/
  12866. #define TIM_DMAR_DMAB_Pos (0U)
  12867. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  12868. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  12869. /******************* Bit definition for TIM_OR register *********************/
  12870. #define TIM_OR_TI1_RMP_Pos (0U)
  12871. #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  12872. #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
  12873. #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  12874. #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  12875. #define TIM_OR_TI4_RMP_Pos (6U)
  12876. #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
  12877. #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
  12878. #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
  12879. #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
  12880. #define TIM_OR_ITR1_RMP_Pos (10U)
  12881. #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
  12882. #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
  12883. #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
  12884. #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
  12885. /******************************************************************************/
  12886. /* */
  12887. /* Universal Synchronous Asynchronous Receiver Transmitter */
  12888. /* */
  12889. /******************************************************************************/
  12890. /******************* Bit definition for USART_SR register *******************/
  12891. #define USART_SR_PE_Pos (0U)
  12892. #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
  12893. #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
  12894. #define USART_SR_FE_Pos (1U)
  12895. #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
  12896. #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
  12897. #define USART_SR_NE_Pos (2U)
  12898. #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
  12899. #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
  12900. #define USART_SR_ORE_Pos (3U)
  12901. #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
  12902. #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
  12903. #define USART_SR_IDLE_Pos (4U)
  12904. #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
  12905. #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
  12906. #define USART_SR_RXNE_Pos (5U)
  12907. #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
  12908. #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
  12909. #define USART_SR_TC_Pos (6U)
  12910. #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
  12911. #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
  12912. #define USART_SR_TXE_Pos (7U)
  12913. #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
  12914. #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
  12915. #define USART_SR_LBD_Pos (8U)
  12916. #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
  12917. #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
  12918. #define USART_SR_CTS_Pos (9U)
  12919. #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
  12920. #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
  12921. /******************* Bit definition for USART_DR register *******************/
  12922. #define USART_DR_DR_Pos (0U)
  12923. #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
  12924. #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
  12925. /****************** Bit definition for USART_BRR register *******************/
  12926. #define USART_BRR_DIV_Fraction_Pos (0U)
  12927. #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
  12928. #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
  12929. #define USART_BRR_DIV_Mantissa_Pos (4U)
  12930. #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
  12931. #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
  12932. /****************** Bit definition for USART_CR1 register *******************/
  12933. #define USART_CR1_SBK_Pos (0U)
  12934. #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
  12935. #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
  12936. #define USART_CR1_RWU_Pos (1U)
  12937. #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
  12938. #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
  12939. #define USART_CR1_RE_Pos (2U)
  12940. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  12941. #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
  12942. #define USART_CR1_TE_Pos (3U)
  12943. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  12944. #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
  12945. #define USART_CR1_IDLEIE_Pos (4U)
  12946. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  12947. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
  12948. #define USART_CR1_RXNEIE_Pos (5U)
  12949. #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  12950. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
  12951. #define USART_CR1_TCIE_Pos (6U)
  12952. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  12953. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
  12954. #define USART_CR1_TXEIE_Pos (7U)
  12955. #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  12956. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
  12957. #define USART_CR1_PEIE_Pos (8U)
  12958. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  12959. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
  12960. #define USART_CR1_PS_Pos (9U)
  12961. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  12962. #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
  12963. #define USART_CR1_PCE_Pos (10U)
  12964. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  12965. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
  12966. #define USART_CR1_WAKE_Pos (11U)
  12967. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  12968. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
  12969. #define USART_CR1_M_Pos (12U)
  12970. #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
  12971. #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
  12972. #define USART_CR1_UE_Pos (13U)
  12973. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
  12974. #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
  12975. #define USART_CR1_OVER8_Pos (15U)
  12976. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  12977. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
  12978. /****************** Bit definition for USART_CR2 register *******************/
  12979. #define USART_CR2_ADD_Pos (0U)
  12980. #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
  12981. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
  12982. #define USART_CR2_LBDL_Pos (5U)
  12983. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  12984. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
  12985. #define USART_CR2_LBDIE_Pos (6U)
  12986. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  12987. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
  12988. #define USART_CR2_LBCL_Pos (8U)
  12989. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  12990. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
  12991. #define USART_CR2_CPHA_Pos (9U)
  12992. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  12993. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
  12994. #define USART_CR2_CPOL_Pos (10U)
  12995. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  12996. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
  12997. #define USART_CR2_CLKEN_Pos (11U)
  12998. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  12999. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
  13000. #define USART_CR2_STOP_Pos (12U)
  13001. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  13002. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
  13003. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
  13004. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
  13005. #define USART_CR2_LINEN_Pos (14U)
  13006. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  13007. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
  13008. /****************** Bit definition for USART_CR3 register *******************/
  13009. #define USART_CR3_EIE_Pos (0U)
  13010. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  13011. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
  13012. #define USART_CR3_IREN_Pos (1U)
  13013. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  13014. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
  13015. #define USART_CR3_IRLP_Pos (2U)
  13016. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  13017. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
  13018. #define USART_CR3_HDSEL_Pos (3U)
  13019. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  13020. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
  13021. #define USART_CR3_NACK_Pos (4U)
  13022. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  13023. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
  13024. #define USART_CR3_SCEN_Pos (5U)
  13025. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  13026. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
  13027. #define USART_CR3_DMAR_Pos (6U)
  13028. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  13029. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
  13030. #define USART_CR3_DMAT_Pos (7U)
  13031. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  13032. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
  13033. #define USART_CR3_RTSE_Pos (8U)
  13034. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  13035. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
  13036. #define USART_CR3_CTSE_Pos (9U)
  13037. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  13038. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
  13039. #define USART_CR3_CTSIE_Pos (10U)
  13040. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  13041. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
  13042. #define USART_CR3_ONEBIT_Pos (11U)
  13043. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  13044. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
  13045. /****************** Bit definition for USART_GTPR register ******************/
  13046. #define USART_GTPR_PSC_Pos (0U)
  13047. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  13048. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
  13049. #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
  13050. #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
  13051. #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
  13052. #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
  13053. #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
  13054. #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
  13055. #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
  13056. #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
  13057. #define USART_GTPR_GT_Pos (8U)
  13058. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  13059. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
  13060. /******************************************************************************/
  13061. /* */
  13062. /* Window WATCHDOG */
  13063. /* */
  13064. /******************************************************************************/
  13065. /******************* Bit definition for WWDG_CR register ********************/
  13066. #define WWDG_CR_T_Pos (0U)
  13067. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  13068. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  13069. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
  13070. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
  13071. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
  13072. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
  13073. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
  13074. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
  13075. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
  13076. /* Legacy defines */
  13077. #define WWDG_CR_T0 WWDG_CR_T_0
  13078. #define WWDG_CR_T1 WWDG_CR_T_1
  13079. #define WWDG_CR_T2 WWDG_CR_T_2
  13080. #define WWDG_CR_T3 WWDG_CR_T_3
  13081. #define WWDG_CR_T4 WWDG_CR_T_4
  13082. #define WWDG_CR_T5 WWDG_CR_T_5
  13083. #define WWDG_CR_T6 WWDG_CR_T_6
  13084. #define WWDG_CR_WDGA_Pos (7U)
  13085. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  13086. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  13087. /******************* Bit definition for WWDG_CFR register *******************/
  13088. #define WWDG_CFR_W_Pos (0U)
  13089. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  13090. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  13091. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
  13092. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
  13093. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
  13094. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
  13095. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
  13096. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
  13097. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
  13098. /* Legacy defines */
  13099. #define WWDG_CFR_W0 WWDG_CFR_W_0
  13100. #define WWDG_CFR_W1 WWDG_CFR_W_1
  13101. #define WWDG_CFR_W2 WWDG_CFR_W_2
  13102. #define WWDG_CFR_W3 WWDG_CFR_W_3
  13103. #define WWDG_CFR_W4 WWDG_CFR_W_4
  13104. #define WWDG_CFR_W5 WWDG_CFR_W_5
  13105. #define WWDG_CFR_W6 WWDG_CFR_W_6
  13106. #define WWDG_CFR_WDGTB_Pos (7U)
  13107. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  13108. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  13109. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
  13110. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
  13111. /* Legacy defines */
  13112. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  13113. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  13114. #define WWDG_CFR_EWI_Pos (9U)
  13115. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  13116. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  13117. /******************* Bit definition for WWDG_SR register ********************/
  13118. #define WWDG_SR_EWIF_Pos (0U)
  13119. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  13120. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  13121. /******************************************************************************/
  13122. /* */
  13123. /* DBG */
  13124. /* */
  13125. /******************************************************************************/
  13126. /******************** Bit definition for DBGMCU_IDCODE register *************/
  13127. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  13128. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  13129. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  13130. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  13131. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  13132. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  13133. /******************** Bit definition for DBGMCU_CR register *****************/
  13134. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  13135. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  13136. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  13137. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  13138. #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  13139. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  13140. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  13141. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  13142. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  13143. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  13144. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  13145. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  13146. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  13147. #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  13148. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  13149. #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  13150. #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  13151. /******************** Bit definition for DBGMCU_APB1_FZ register ************/
  13152. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
  13153. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  13154. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
  13155. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
  13156. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  13157. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
  13158. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
  13159. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
  13160. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
  13161. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
  13162. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
  13163. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
  13164. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
  13165. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
  13166. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
  13167. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
  13168. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
  13169. #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
  13170. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
  13171. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
  13172. #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
  13173. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
  13174. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
  13175. #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
  13176. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
  13177. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
  13178. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
  13179. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  13180. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  13181. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
  13182. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  13183. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  13184. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
  13185. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  13186. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  13187. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
  13188. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  13189. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  13190. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
  13191. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
  13192. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
  13193. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
  13194. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
  13195. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
  13196. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
  13197. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
  13198. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
  13199. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
  13200. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
  13201. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
  13202. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
  13203. /* Old IWDGSTOP bit definition, maintained for legacy purpose */
  13204. #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
  13205. /******************** Bit definition for DBGMCU_APB2_FZ register ************/
  13206. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
  13207. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
  13208. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
  13209. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
  13210. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
  13211. #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
  13212. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
  13213. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
  13214. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
  13215. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
  13216. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
  13217. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
  13218. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
  13219. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
  13220. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
  13221. /******************************************************************************/
  13222. /* */
  13223. /* Ethernet MAC Registers bits definitions */
  13224. /* */
  13225. /******************************************************************************/
  13226. /* Bit definition for Ethernet MAC Control Register register */
  13227. #define ETH_MACCR_WD_Pos (23U)
  13228. #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
  13229. #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
  13230. #define ETH_MACCR_JD_Pos (22U)
  13231. #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
  13232. #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
  13233. #define ETH_MACCR_IFG_Pos (17U)
  13234. #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
  13235. #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
  13236. #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
  13237. #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
  13238. #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
  13239. #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
  13240. #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
  13241. #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
  13242. #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
  13243. #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
  13244. #define ETH_MACCR_CSD_Pos (16U)
  13245. #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
  13246. #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
  13247. #define ETH_MACCR_FES_Pos (14U)
  13248. #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
  13249. #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
  13250. #define ETH_MACCR_ROD_Pos (13U)
  13251. #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
  13252. #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
  13253. #define ETH_MACCR_LM_Pos (12U)
  13254. #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
  13255. #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
  13256. #define ETH_MACCR_DM_Pos (11U)
  13257. #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
  13258. #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
  13259. #define ETH_MACCR_IPCO_Pos (10U)
  13260. #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
  13261. #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
  13262. #define ETH_MACCR_RD_Pos (9U)
  13263. #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
  13264. #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
  13265. #define ETH_MACCR_APCS_Pos (7U)
  13266. #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
  13267. #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
  13268. #define ETH_MACCR_BL_Pos (5U)
  13269. #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
  13270. #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
  13271. a transmission attempt during retries after a collision: 0 =< r <2^k */
  13272. #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
  13273. #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
  13274. #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
  13275. #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
  13276. #define ETH_MACCR_DC_Pos (4U)
  13277. #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
  13278. #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
  13279. #define ETH_MACCR_TE_Pos (3U)
  13280. #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
  13281. #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
  13282. #define ETH_MACCR_RE_Pos (2U)
  13283. #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
  13284. #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
  13285. /* Bit definition for Ethernet MAC Frame Filter Register */
  13286. #define ETH_MACFFR_RA_Pos (31U)
  13287. #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
  13288. #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
  13289. #define ETH_MACFFR_HPF_Pos (10U)
  13290. #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
  13291. #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
  13292. #define ETH_MACFFR_SAF_Pos (9U)
  13293. #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
  13294. #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
  13295. #define ETH_MACFFR_SAIF_Pos (8U)
  13296. #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
  13297. #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
  13298. #define ETH_MACFFR_PCF_Pos (6U)
  13299. #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
  13300. #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
  13301. #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
  13302. #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
  13303. #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
  13304. #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
  13305. #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
  13306. #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
  13307. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
  13308. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
  13309. #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
  13310. #define ETH_MACFFR_BFD_Pos (5U)
  13311. #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
  13312. #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
  13313. #define ETH_MACFFR_PAM_Pos (4U)
  13314. #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
  13315. #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
  13316. #define ETH_MACFFR_DAIF_Pos (3U)
  13317. #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
  13318. #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
  13319. #define ETH_MACFFR_HM_Pos (2U)
  13320. #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
  13321. #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
  13322. #define ETH_MACFFR_HU_Pos (1U)
  13323. #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
  13324. #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
  13325. #define ETH_MACFFR_PM_Pos (0U)
  13326. #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
  13327. #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
  13328. /* Bit definition for Ethernet MAC Hash Table High Register */
  13329. #define ETH_MACHTHR_HTH_Pos (0U)
  13330. #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
  13331. #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
  13332. /* Bit definition for Ethernet MAC Hash Table Low Register */
  13333. #define ETH_MACHTLR_HTL_Pos (0U)
  13334. #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
  13335. #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
  13336. /* Bit definition for Ethernet MAC MII Address Register */
  13337. #define ETH_MACMIIAR_PA_Pos (11U)
  13338. #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
  13339. #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
  13340. #define ETH_MACMIIAR_MR_Pos (6U)
  13341. #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
  13342. #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
  13343. #define ETH_MACMIIAR_CR_Pos (2U)
  13344. #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
  13345. #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
  13346. #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
  13347. #define ETH_MACMIIAR_CR_Div62_Pos (2U)
  13348. #define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
  13349. #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
  13350. #define ETH_MACMIIAR_CR_Div16_Pos (3U)
  13351. #define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
  13352. #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
  13353. #define ETH_MACMIIAR_CR_Div26_Pos (2U)
  13354. #define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
  13355. #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
  13356. #define ETH_MACMIIAR_CR_Div102_Pos (4U)
  13357. #define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
  13358. #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
  13359. #define ETH_MACMIIAR_MW_Pos (1U)
  13360. #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
  13361. #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
  13362. #define ETH_MACMIIAR_MB_Pos (0U)
  13363. #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
  13364. #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
  13365. /* Bit definition for Ethernet MAC MII Data Register */
  13366. #define ETH_MACMIIDR_MD_Pos (0U)
  13367. #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
  13368. #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
  13369. /* Bit definition for Ethernet MAC Flow Control Register */
  13370. #define ETH_MACFCR_PT_Pos (16U)
  13371. #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
  13372. #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
  13373. #define ETH_MACFCR_ZQPD_Pos (7U)
  13374. #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
  13375. #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
  13376. #define ETH_MACFCR_PLT_Pos (4U)
  13377. #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
  13378. #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
  13379. #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
  13380. #define ETH_MACFCR_PLT_Minus28_Pos (4U)
  13381. #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
  13382. #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
  13383. #define ETH_MACFCR_PLT_Minus144_Pos (5U)
  13384. #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
  13385. #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
  13386. #define ETH_MACFCR_PLT_Minus256_Pos (4U)
  13387. #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
  13388. #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
  13389. #define ETH_MACFCR_UPFD_Pos (3U)
  13390. #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
  13391. #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
  13392. #define ETH_MACFCR_RFCE_Pos (2U)
  13393. #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
  13394. #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
  13395. #define ETH_MACFCR_TFCE_Pos (1U)
  13396. #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
  13397. #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
  13398. #define ETH_MACFCR_FCBBPA_Pos (0U)
  13399. #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
  13400. #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
  13401. /* Bit definition for Ethernet MAC VLAN Tag Register */
  13402. #define ETH_MACVLANTR_VLANTC_Pos (16U)
  13403. #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
  13404. #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
  13405. #define ETH_MACVLANTR_VLANTI_Pos (0U)
  13406. #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
  13407. #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
  13408. /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
  13409. #define ETH_MACRWUFFR_D_Pos (0U)
  13410. #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
  13411. #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
  13412. /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
  13413. Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
  13414. /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
  13415. Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
  13416. Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
  13417. Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
  13418. Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
  13419. RSVD - Filter1 Command - RSVD - Filter0 Command
  13420. Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
  13421. Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
  13422. Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
  13423. /* Bit definition for Ethernet MAC PMT Control and Status Register */
  13424. #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
  13425. #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
  13426. #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
  13427. #define ETH_MACPMTCSR_GU_Pos (9U)
  13428. #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
  13429. #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
  13430. #define ETH_MACPMTCSR_WFR_Pos (6U)
  13431. #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
  13432. #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
  13433. #define ETH_MACPMTCSR_MPR_Pos (5U)
  13434. #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
  13435. #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
  13436. #define ETH_MACPMTCSR_WFE_Pos (2U)
  13437. #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
  13438. #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
  13439. #define ETH_MACPMTCSR_MPE_Pos (1U)
  13440. #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
  13441. #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
  13442. #define ETH_MACPMTCSR_PD_Pos (0U)
  13443. #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
  13444. #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
  13445. /* Bit definition for Ethernet MAC debug Register */
  13446. #define ETH_MACDBGR_TFF_Pos (25U)
  13447. #define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
  13448. #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
  13449. #define ETH_MACDBGR_TFNE_Pos (24U)
  13450. #define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
  13451. #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
  13452. #define ETH_MACDBGR_TFWA_Pos (22U)
  13453. #define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
  13454. #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
  13455. #define ETH_MACDBGR_TFRS_Pos (20U)
  13456. #define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
  13457. #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
  13458. #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
  13459. #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
  13460. #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
  13461. #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
  13462. #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
  13463. #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
  13464. #define ETH_MACDBGR_TFRS_READ_Pos (20U)
  13465. #define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
  13466. #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
  13467. #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
  13468. #define ETH_MACDBGR_MTP_Pos (19U)
  13469. #define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
  13470. #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
  13471. #define ETH_MACDBGR_MTFCS_Pos (17U)
  13472. #define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
  13473. #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
  13474. #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
  13475. #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
  13476. #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
  13477. #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
  13478. #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
  13479. #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
  13480. #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
  13481. #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
  13482. #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
  13483. #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
  13484. #define ETH_MACDBGR_MMTEA_Pos (16U)
  13485. #define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
  13486. #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
  13487. #define ETH_MACDBGR_RFFL_Pos (8U)
  13488. #define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
  13489. #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
  13490. #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
  13491. #define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
  13492. #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
  13493. #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
  13494. #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
  13495. #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
  13496. #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
  13497. #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
  13498. #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
  13499. #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
  13500. #define ETH_MACDBGR_RFRCS_Pos (5U)
  13501. #define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
  13502. #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
  13503. #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
  13504. #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
  13505. #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
  13506. #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
  13507. #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
  13508. #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
  13509. #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
  13510. #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
  13511. #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
  13512. #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
  13513. #define ETH_MACDBGR_RFWRA_Pos (4U)
  13514. #define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
  13515. #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
  13516. #define ETH_MACDBGR_MSFRWCS_Pos (1U)
  13517. #define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
  13518. #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
  13519. #define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
  13520. #define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
  13521. #define ETH_MACDBGR_MMRPEA_Pos (0U)
  13522. #define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
  13523. #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
  13524. /* Bit definition for Ethernet MAC Status Register */
  13525. #define ETH_MACSR_TSTS_Pos (9U)
  13526. #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
  13527. #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
  13528. #define ETH_MACSR_MMCTS_Pos (6U)
  13529. #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
  13530. #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
  13531. #define ETH_MACSR_MMMCRS_Pos (5U)
  13532. #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
  13533. #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
  13534. #define ETH_MACSR_MMCS_Pos (4U)
  13535. #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
  13536. #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
  13537. #define ETH_MACSR_PMTS_Pos (3U)
  13538. #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
  13539. #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
  13540. /* Bit definition for Ethernet MAC Interrupt Mask Register */
  13541. #define ETH_MACIMR_TSTIM_Pos (9U)
  13542. #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
  13543. #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
  13544. #define ETH_MACIMR_PMTIM_Pos (3U)
  13545. #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
  13546. #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
  13547. /* Bit definition for Ethernet MAC Address0 High Register */
  13548. #define ETH_MACA0HR_MACA0H_Pos (0U)
  13549. #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
  13550. #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
  13551. /* Bit definition for Ethernet MAC Address0 Low Register */
  13552. #define ETH_MACA0LR_MACA0L_Pos (0U)
  13553. #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
  13554. #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
  13555. /* Bit definition for Ethernet MAC Address1 High Register */
  13556. #define ETH_MACA1HR_AE_Pos (31U)
  13557. #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
  13558. #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
  13559. #define ETH_MACA1HR_SA_Pos (30U)
  13560. #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
  13561. #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
  13562. #define ETH_MACA1HR_MBC_Pos (24U)
  13563. #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
  13564. #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
  13565. #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  13566. #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  13567. #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  13568. #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  13569. #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  13570. #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
  13571. #define ETH_MACA1HR_MACA1H_Pos (0U)
  13572. #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
  13573. #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
  13574. /* Bit definition for Ethernet MAC Address1 Low Register */
  13575. #define ETH_MACA1LR_MACA1L_Pos (0U)
  13576. #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
  13577. #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
  13578. /* Bit definition for Ethernet MAC Address2 High Register */
  13579. #define ETH_MACA2HR_AE_Pos (31U)
  13580. #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
  13581. #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
  13582. #define ETH_MACA2HR_SA_Pos (30U)
  13583. #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
  13584. #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
  13585. #define ETH_MACA2HR_MBC_Pos (24U)
  13586. #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
  13587. #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
  13588. #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  13589. #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  13590. #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  13591. #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  13592. #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  13593. #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
  13594. #define ETH_MACA2HR_MACA2H_Pos (0U)
  13595. #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
  13596. #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
  13597. /* Bit definition for Ethernet MAC Address2 Low Register */
  13598. #define ETH_MACA2LR_MACA2L_Pos (0U)
  13599. #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
  13600. #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
  13601. /* Bit definition for Ethernet MAC Address3 High Register */
  13602. #define ETH_MACA3HR_AE_Pos (31U)
  13603. #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
  13604. #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
  13605. #define ETH_MACA3HR_SA_Pos (30U)
  13606. #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
  13607. #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
  13608. #define ETH_MACA3HR_MBC_Pos (24U)
  13609. #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
  13610. #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
  13611. #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
  13612. #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
  13613. #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
  13614. #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
  13615. #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
  13616. #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
  13617. #define ETH_MACA3HR_MACA3H_Pos (0U)
  13618. #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
  13619. #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
  13620. /* Bit definition for Ethernet MAC Address3 Low Register */
  13621. #define ETH_MACA3LR_MACA3L_Pos (0U)
  13622. #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
  13623. #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
  13624. /******************************************************************************/
  13625. /* Ethernet MMC Registers bits definition */
  13626. /******************************************************************************/
  13627. /* Bit definition for Ethernet MMC Contol Register */
  13628. #define ETH_MMCCR_MCFHP_Pos (5U)
  13629. #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
  13630. #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
  13631. #define ETH_MMCCR_MCP_Pos (4U)
  13632. #define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
  13633. #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
  13634. #define ETH_MMCCR_MCF_Pos (3U)
  13635. #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
  13636. #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
  13637. #define ETH_MMCCR_ROR_Pos (2U)
  13638. #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
  13639. #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
  13640. #define ETH_MMCCR_CSR_Pos (1U)
  13641. #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
  13642. #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
  13643. #define ETH_MMCCR_CR_Pos (0U)
  13644. #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
  13645. #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
  13646. /* Bit definition for Ethernet MMC Receive Interrupt Register */
  13647. #define ETH_MMCRIR_RGUFS_Pos (17U)
  13648. #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
  13649. #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
  13650. #define ETH_MMCRIR_RFAES_Pos (6U)
  13651. #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
  13652. #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
  13653. #define ETH_MMCRIR_RFCES_Pos (5U)
  13654. #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
  13655. #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
  13656. /* Bit definition for Ethernet MMC Transmit Interrupt Register */
  13657. #define ETH_MMCTIR_TGFS_Pos (21U)
  13658. #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
  13659. #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
  13660. #define ETH_MMCTIR_TGFMSCS_Pos (15U)
  13661. #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
  13662. #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
  13663. #define ETH_MMCTIR_TGFSCS_Pos (14U)
  13664. #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
  13665. #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
  13666. /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
  13667. #define ETH_MMCRIMR_RGUFM_Pos (17U)
  13668. #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
  13669. #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
  13670. #define ETH_MMCRIMR_RFAEM_Pos (6U)
  13671. #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
  13672. #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
  13673. #define ETH_MMCRIMR_RFCEM_Pos (5U)
  13674. #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
  13675. #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
  13676. /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
  13677. #define ETH_MMCTIMR_TGFM_Pos (21U)
  13678. #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
  13679. #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
  13680. #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
  13681. #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
  13682. #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
  13683. #define ETH_MMCTIMR_TGFSCM_Pos (14U)
  13684. #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
  13685. #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
  13686. /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
  13687. #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
  13688. #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
  13689. #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
  13690. /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
  13691. #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
  13692. #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
  13693. #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
  13694. /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
  13695. #define ETH_MMCTGFCR_TGFC_Pos (0U)
  13696. #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
  13697. #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
  13698. /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
  13699. #define ETH_MMCRFCECR_RFCEC_Pos (0U)
  13700. #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
  13701. #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
  13702. /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
  13703. #define ETH_MMCRFAECR_RFAEC_Pos (0U)
  13704. #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
  13705. #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
  13706. /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
  13707. #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
  13708. #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
  13709. #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
  13710. /******************************************************************************/
  13711. /* Ethernet PTP Registers bits definition */
  13712. /******************************************************************************/
  13713. /* Bit definition for Ethernet PTP Time Stamp Contol Register */
  13714. #define ETH_PTPTSCR_TSCNT_Pos (16U)
  13715. #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
  13716. #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
  13717. #define ETH_PTPTSSR_TSSMRME_Pos (15U)
  13718. #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
  13719. #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
  13720. #define ETH_PTPTSSR_TSSEME_Pos (14U)
  13721. #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
  13722. #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
  13723. #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
  13724. #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
  13725. #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
  13726. #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
  13727. #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
  13728. #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
  13729. #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
  13730. #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
  13731. #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
  13732. #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
  13733. #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
  13734. #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
  13735. #define ETH_PTPTSSR_TSSSR_Pos (9U)
  13736. #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
  13737. #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
  13738. #define ETH_PTPTSSR_TSSARFE_Pos (8U)
  13739. #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
  13740. #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
  13741. #define ETH_PTPTSCR_TSARU_Pos (5U)
  13742. #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
  13743. #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
  13744. #define ETH_PTPTSCR_TSITE_Pos (4U)
  13745. #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
  13746. #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
  13747. #define ETH_PTPTSCR_TSSTU_Pos (3U)
  13748. #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
  13749. #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
  13750. #define ETH_PTPTSCR_TSSTI_Pos (2U)
  13751. #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
  13752. #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
  13753. #define ETH_PTPTSCR_TSFCU_Pos (1U)
  13754. #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
  13755. #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
  13756. #define ETH_PTPTSCR_TSE_Pos (0U)
  13757. #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
  13758. #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
  13759. /* Bit definition for Ethernet PTP Sub-Second Increment Register */
  13760. #define ETH_PTPSSIR_STSSI_Pos (0U)
  13761. #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
  13762. #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
  13763. /* Bit definition for Ethernet PTP Time Stamp High Register */
  13764. #define ETH_PTPTSHR_STS_Pos (0U)
  13765. #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
  13766. #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
  13767. /* Bit definition for Ethernet PTP Time Stamp Low Register */
  13768. #define ETH_PTPTSLR_STPNS_Pos (31U)
  13769. #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
  13770. #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
  13771. #define ETH_PTPTSLR_STSS_Pos (0U)
  13772. #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
  13773. #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
  13774. /* Bit definition for Ethernet PTP Time Stamp High Update Register */
  13775. #define ETH_PTPTSHUR_TSUS_Pos (0U)
  13776. #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
  13777. #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
  13778. /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
  13779. #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
  13780. #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
  13781. #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
  13782. #define ETH_PTPTSLUR_TSUSS_Pos (0U)
  13783. #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
  13784. #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
  13785. /* Bit definition for Ethernet PTP Time Stamp Addend Register */
  13786. #define ETH_PTPTSAR_TSA_Pos (0U)
  13787. #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
  13788. #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
  13789. /* Bit definition for Ethernet PTP Target Time High Register */
  13790. #define ETH_PTPTTHR_TTSH_Pos (0U)
  13791. #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
  13792. #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
  13793. /* Bit definition for Ethernet PTP Target Time Low Register */
  13794. #define ETH_PTPTTLR_TTSL_Pos (0U)
  13795. #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
  13796. #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
  13797. /* Bit definition for Ethernet PTP Time Stamp Status Register */
  13798. #define ETH_PTPTSSR_TSTTR_Pos (5U)
  13799. #define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
  13800. #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
  13801. #define ETH_PTPTSSR_TSSO_Pos (4U)
  13802. #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
  13803. #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
  13804. /******************************************************************************/
  13805. /* Ethernet DMA Registers bits definition */
  13806. /******************************************************************************/
  13807. /* Bit definition for Ethernet DMA Bus Mode Register */
  13808. #define ETH_DMABMR_AAB_Pos (25U)
  13809. #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
  13810. #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
  13811. #define ETH_DMABMR_FPM_Pos (24U)
  13812. #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
  13813. #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
  13814. #define ETH_DMABMR_USP_Pos (23U)
  13815. #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
  13816. #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
  13817. #define ETH_DMABMR_RDP_Pos (17U)
  13818. #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
  13819. #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
  13820. #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
  13821. #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
  13822. #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
  13823. #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
  13824. #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
  13825. #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
  13826. #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
  13827. #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
  13828. #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
  13829. #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
  13830. #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
  13831. #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
  13832. #define ETH_DMABMR_FB_Pos (16U)
  13833. #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
  13834. #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
  13835. #define ETH_DMABMR_RTPR_Pos (14U)
  13836. #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
  13837. #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
  13838. #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
  13839. #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
  13840. #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
  13841. #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
  13842. #define ETH_DMABMR_PBL_Pos (8U)
  13843. #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
  13844. #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
  13845. #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
  13846. #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
  13847. #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
  13848. #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
  13849. #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
  13850. #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
  13851. #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
  13852. #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
  13853. #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
  13854. #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
  13855. #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
  13856. #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
  13857. #define ETH_DMABMR_EDE_Pos (7U)
  13858. #define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
  13859. #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
  13860. #define ETH_DMABMR_DSL_Pos (2U)
  13861. #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
  13862. #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
  13863. #define ETH_DMABMR_DA_Pos (1U)
  13864. #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
  13865. #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
  13866. #define ETH_DMABMR_SR_Pos (0U)
  13867. #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
  13868. #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
  13869. /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
  13870. #define ETH_DMATPDR_TPD_Pos (0U)
  13871. #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
  13872. #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
  13873. /* Bit definition for Ethernet DMA Receive Poll Demand Register */
  13874. #define ETH_DMARPDR_RPD_Pos (0U)
  13875. #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
  13876. #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
  13877. /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
  13878. #define ETH_DMARDLAR_SRL_Pos (0U)
  13879. #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
  13880. #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
  13881. /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
  13882. #define ETH_DMATDLAR_STL_Pos (0U)
  13883. #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
  13884. #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
  13885. /* Bit definition for Ethernet DMA Status Register */
  13886. #define ETH_DMASR_TSTS_Pos (29U)
  13887. #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
  13888. #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
  13889. #define ETH_DMASR_PMTS_Pos (28U)
  13890. #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
  13891. #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
  13892. #define ETH_DMASR_MMCS_Pos (27U)
  13893. #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
  13894. #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
  13895. #define ETH_DMASR_EBS_Pos (23U)
  13896. #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
  13897. #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
  13898. /* combination with EBS[2:0] for GetFlagStatus function */
  13899. #define ETH_DMASR_EBS_DescAccess_Pos (25U)
  13900. #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
  13901. #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
  13902. #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
  13903. #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
  13904. #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
  13905. #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
  13906. #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
  13907. #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
  13908. #define ETH_DMASR_TPS_Pos (20U)
  13909. #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
  13910. #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
  13911. #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
  13912. #define ETH_DMASR_TPS_Fetching_Pos (20U)
  13913. #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
  13914. #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
  13915. #define ETH_DMASR_TPS_Waiting_Pos (21U)
  13916. #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
  13917. #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
  13918. #define ETH_DMASR_TPS_Reading_Pos (20U)
  13919. #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
  13920. #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
  13921. #define ETH_DMASR_TPS_Suspended_Pos (21U)
  13922. #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
  13923. #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
  13924. #define ETH_DMASR_TPS_Closing_Pos (20U)
  13925. #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
  13926. #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
  13927. #define ETH_DMASR_RPS_Pos (17U)
  13928. #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
  13929. #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
  13930. #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
  13931. #define ETH_DMASR_RPS_Fetching_Pos (17U)
  13932. #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
  13933. #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
  13934. #define ETH_DMASR_RPS_Waiting_Pos (17U)
  13935. #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
  13936. #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
  13937. #define ETH_DMASR_RPS_Suspended_Pos (19U)
  13938. #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
  13939. #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
  13940. #define ETH_DMASR_RPS_Closing_Pos (17U)
  13941. #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
  13942. #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
  13943. #define ETH_DMASR_RPS_Queuing_Pos (17U)
  13944. #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
  13945. #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
  13946. #define ETH_DMASR_NIS_Pos (16U)
  13947. #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
  13948. #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
  13949. #define ETH_DMASR_AIS_Pos (15U)
  13950. #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
  13951. #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
  13952. #define ETH_DMASR_ERS_Pos (14U)
  13953. #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
  13954. #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
  13955. #define ETH_DMASR_FBES_Pos (13U)
  13956. #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
  13957. #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
  13958. #define ETH_DMASR_ETS_Pos (10U)
  13959. #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
  13960. #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
  13961. #define ETH_DMASR_RWTS_Pos (9U)
  13962. #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
  13963. #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
  13964. #define ETH_DMASR_RPSS_Pos (8U)
  13965. #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
  13966. #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
  13967. #define ETH_DMASR_RBUS_Pos (7U)
  13968. #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
  13969. #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
  13970. #define ETH_DMASR_RS_Pos (6U)
  13971. #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
  13972. #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
  13973. #define ETH_DMASR_TUS_Pos (5U)
  13974. #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
  13975. #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
  13976. #define ETH_DMASR_ROS_Pos (4U)
  13977. #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
  13978. #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
  13979. #define ETH_DMASR_TJTS_Pos (3U)
  13980. #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
  13981. #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
  13982. #define ETH_DMASR_TBUS_Pos (2U)
  13983. #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
  13984. #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
  13985. #define ETH_DMASR_TPSS_Pos (1U)
  13986. #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
  13987. #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
  13988. #define ETH_DMASR_TS_Pos (0U)
  13989. #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
  13990. #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
  13991. /* Bit definition for Ethernet DMA Operation Mode Register */
  13992. #define ETH_DMAOMR_DTCEFD_Pos (26U)
  13993. #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
  13994. #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
  13995. #define ETH_DMAOMR_RSF_Pos (25U)
  13996. #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
  13997. #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
  13998. #define ETH_DMAOMR_DFRF_Pos (24U)
  13999. #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
  14000. #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
  14001. #define ETH_DMAOMR_TSF_Pos (21U)
  14002. #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
  14003. #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
  14004. #define ETH_DMAOMR_FTF_Pos (20U)
  14005. #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
  14006. #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
  14007. #define ETH_DMAOMR_TTC_Pos (14U)
  14008. #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
  14009. #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
  14010. #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
  14011. #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
  14012. #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
  14013. #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
  14014. #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
  14015. #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
  14016. #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
  14017. #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
  14018. #define ETH_DMAOMR_ST_Pos (13U)
  14019. #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
  14020. #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
  14021. #define ETH_DMAOMR_FEF_Pos (7U)
  14022. #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
  14023. #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
  14024. #define ETH_DMAOMR_FUGF_Pos (6U)
  14025. #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
  14026. #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
  14027. #define ETH_DMAOMR_RTC_Pos (3U)
  14028. #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
  14029. #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
  14030. #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
  14031. #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
  14032. #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
  14033. #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
  14034. #define ETH_DMAOMR_OSF_Pos (2U)
  14035. #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
  14036. #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
  14037. #define ETH_DMAOMR_SR_Pos (1U)
  14038. #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
  14039. #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
  14040. /* Bit definition for Ethernet DMA Interrupt Enable Register */
  14041. #define ETH_DMAIER_NISE_Pos (16U)
  14042. #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
  14043. #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
  14044. #define ETH_DMAIER_AISE_Pos (15U)
  14045. #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
  14046. #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
  14047. #define ETH_DMAIER_ERIE_Pos (14U)
  14048. #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
  14049. #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
  14050. #define ETH_DMAIER_FBEIE_Pos (13U)
  14051. #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
  14052. #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
  14053. #define ETH_DMAIER_ETIE_Pos (10U)
  14054. #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
  14055. #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
  14056. #define ETH_DMAIER_RWTIE_Pos (9U)
  14057. #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
  14058. #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
  14059. #define ETH_DMAIER_RPSIE_Pos (8U)
  14060. #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
  14061. #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
  14062. #define ETH_DMAIER_RBUIE_Pos (7U)
  14063. #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
  14064. #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
  14065. #define ETH_DMAIER_RIE_Pos (6U)
  14066. #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
  14067. #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
  14068. #define ETH_DMAIER_TUIE_Pos (5U)
  14069. #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
  14070. #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
  14071. #define ETH_DMAIER_ROIE_Pos (4U)
  14072. #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
  14073. #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
  14074. #define ETH_DMAIER_TJTIE_Pos (3U)
  14075. #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
  14076. #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
  14077. #define ETH_DMAIER_TBUIE_Pos (2U)
  14078. #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
  14079. #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
  14080. #define ETH_DMAIER_TPSIE_Pos (1U)
  14081. #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
  14082. #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
  14083. #define ETH_DMAIER_TIE_Pos (0U)
  14084. #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
  14085. #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
  14086. /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
  14087. #define ETH_DMAMFBOCR_OFOC_Pos (28U)
  14088. #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
  14089. #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
  14090. #define ETH_DMAMFBOCR_MFA_Pos (17U)
  14091. #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
  14092. #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
  14093. #define ETH_DMAMFBOCR_OMFC_Pos (16U)
  14094. #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
  14095. #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
  14096. #define ETH_DMAMFBOCR_MFC_Pos (0U)
  14097. #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
  14098. #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
  14099. /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
  14100. #define ETH_DMACHTDR_HTDAP_Pos (0U)
  14101. #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
  14102. #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
  14103. /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
  14104. #define ETH_DMACHRDR_HRDAP_Pos (0U)
  14105. #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
  14106. #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
  14107. /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
  14108. #define ETH_DMACHTBAR_HTBAP_Pos (0U)
  14109. #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
  14110. #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
  14111. /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
  14112. #define ETH_DMACHRBAR_HRBAP_Pos (0U)
  14113. #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
  14114. #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
  14115. /******************************************************************************/
  14116. /* */
  14117. /* USB_OTG */
  14118. /* */
  14119. /******************************************************************************/
  14120. /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
  14121. #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
  14122. #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
  14123. #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
  14124. #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
  14125. #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
  14126. #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
  14127. #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
  14128. #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
  14129. #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
  14130. #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
  14131. #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
  14132. #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
  14133. #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
  14134. #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
  14135. #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
  14136. #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
  14137. #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
  14138. #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
  14139. #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
  14140. #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
  14141. #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
  14142. #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
  14143. #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
  14144. #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
  14145. #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
  14146. #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
  14147. #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
  14148. #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
  14149. #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
  14150. #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
  14151. /******************** Bit definition forUSB_OTG_HCFG register ********************/
  14152. #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
  14153. #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
  14154. #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
  14155. #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
  14156. #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
  14157. #define USB_OTG_HCFG_FSLSS_Pos (2U)
  14158. #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
  14159. #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
  14160. /******************** Bit definition for USB_OTG_DCFG register ********************/
  14161. #define USB_OTG_DCFG_DSPD_Pos (0U)
  14162. #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
  14163. #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
  14164. #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
  14165. #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
  14166. #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
  14167. #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
  14168. #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
  14169. #define USB_OTG_DCFG_DAD_Pos (4U)
  14170. #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
  14171. #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
  14172. #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
  14173. #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
  14174. #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
  14175. #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
  14176. #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
  14177. #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
  14178. #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
  14179. #define USB_OTG_DCFG_PFIVL_Pos (11U)
  14180. #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
  14181. #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
  14182. #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
  14183. #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
  14184. #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
  14185. #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
  14186. #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
  14187. #define USB_OTG_DCFG_ERRATIM_Pos (15U)
  14188. #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
  14189. #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
  14190. #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
  14191. #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
  14192. #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
  14193. #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
  14194. #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
  14195. /******************** Bit definition for USB_OTG_PCGCR register ********************/
  14196. #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
  14197. #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
  14198. #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
  14199. #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
  14200. #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
  14201. #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
  14202. #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
  14203. #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
  14204. #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
  14205. /******************** Bit definition for USB_OTG_GOTGINT register ********************/
  14206. #define USB_OTG_GOTGINT_SEDET_Pos (2U)
  14207. #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
  14208. #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
  14209. #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
  14210. #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
  14211. #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
  14212. #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
  14213. #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
  14214. #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
  14215. #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
  14216. #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
  14217. #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
  14218. #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
  14219. #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
  14220. #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
  14221. #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
  14222. #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
  14223. #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
  14224. /******************** Bit definition for USB_OTG_DCTL register ********************/
  14225. #define USB_OTG_DCTL_RWUSIG_Pos (0U)
  14226. #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
  14227. #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
  14228. #define USB_OTG_DCTL_SDIS_Pos (1U)
  14229. #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
  14230. #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
  14231. #define USB_OTG_DCTL_GINSTS_Pos (2U)
  14232. #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
  14233. #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
  14234. #define USB_OTG_DCTL_GONSTS_Pos (3U)
  14235. #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
  14236. #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
  14237. #define USB_OTG_DCTL_TCTL_Pos (4U)
  14238. #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
  14239. #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
  14240. #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
  14241. #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
  14242. #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
  14243. #define USB_OTG_DCTL_SGINAK_Pos (7U)
  14244. #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
  14245. #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
  14246. #define USB_OTG_DCTL_CGINAK_Pos (8U)
  14247. #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
  14248. #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
  14249. #define USB_OTG_DCTL_SGONAK_Pos (9U)
  14250. #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
  14251. #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
  14252. #define USB_OTG_DCTL_CGONAK_Pos (10U)
  14253. #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
  14254. #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
  14255. #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
  14256. #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
  14257. #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
  14258. /******************** Bit definition for USB_OTG_HFIR register ********************/
  14259. #define USB_OTG_HFIR_FRIVL_Pos (0U)
  14260. #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
  14261. #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
  14262. /******************** Bit definition for USB_OTG_HFNUM register ********************/
  14263. #define USB_OTG_HFNUM_FRNUM_Pos (0U)
  14264. #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
  14265. #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
  14266. #define USB_OTG_HFNUM_FTREM_Pos (16U)
  14267. #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
  14268. #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
  14269. /******************** Bit definition for USB_OTG_DSTS register ********************/
  14270. #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
  14271. #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
  14272. #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
  14273. #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
  14274. #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
  14275. #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
  14276. #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
  14277. #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
  14278. #define USB_OTG_DSTS_EERR_Pos (3U)
  14279. #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
  14280. #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
  14281. #define USB_OTG_DSTS_FNSOF_Pos (8U)
  14282. #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
  14283. #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
  14284. /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
  14285. #define USB_OTG_GAHBCFG_GINT_Pos (0U)
  14286. #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
  14287. #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
  14288. #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
  14289. #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
  14290. #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
  14291. #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
  14292. #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
  14293. #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
  14294. #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
  14295. #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
  14296. #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
  14297. #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
  14298. #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
  14299. #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
  14300. #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
  14301. #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
  14302. #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
  14303. #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
  14304. #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
  14305. /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
  14306. #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
  14307. #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
  14308. #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
  14309. #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
  14310. #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
  14311. #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
  14312. #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
  14313. #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
  14314. #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
  14315. #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
  14316. #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
  14317. #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
  14318. #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
  14319. #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
  14320. #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
  14321. #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
  14322. #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
  14323. #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
  14324. #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
  14325. #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
  14326. #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
  14327. #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
  14328. #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
  14329. #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
  14330. #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
  14331. #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
  14332. #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
  14333. #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
  14334. #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
  14335. #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
  14336. #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
  14337. #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
  14338. #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
  14339. #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
  14340. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
  14341. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
  14342. #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
  14343. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
  14344. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
  14345. #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
  14346. #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
  14347. #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
  14348. #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
  14349. #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
  14350. #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
  14351. #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
  14352. #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
  14353. #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
  14354. #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
  14355. #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
  14356. #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
  14357. #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
  14358. #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
  14359. #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
  14360. #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
  14361. #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
  14362. #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
  14363. #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
  14364. #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
  14365. #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
  14366. #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
  14367. /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
  14368. #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
  14369. #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
  14370. #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
  14371. #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
  14372. #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
  14373. #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
  14374. #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
  14375. #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
  14376. #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
  14377. #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
  14378. #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
  14379. #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
  14380. #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
  14381. #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
  14382. #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
  14383. #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
  14384. #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
  14385. #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
  14386. #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
  14387. #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
  14388. #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
  14389. #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
  14390. #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
  14391. #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
  14392. #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
  14393. #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
  14394. #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
  14395. #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
  14396. #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
  14397. /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
  14398. #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
  14399. #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  14400. #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  14401. #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
  14402. #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
  14403. #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  14404. #define USB_OTG_DIEPMSK_TOM_Pos (3U)
  14405. #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
  14406. #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  14407. #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
  14408. #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
  14409. #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  14410. #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
  14411. #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
  14412. #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  14413. #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
  14414. #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
  14415. #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  14416. #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
  14417. #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
  14418. #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
  14419. #define USB_OTG_DIEPMSK_BIM_Pos (9U)
  14420. #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
  14421. #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
  14422. /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
  14423. #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
  14424. #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
  14425. #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
  14426. #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
  14427. #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
  14428. #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
  14429. #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
  14430. #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
  14431. #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
  14432. #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
  14433. #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
  14434. #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
  14435. #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
  14436. #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
  14437. #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
  14438. #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
  14439. #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
  14440. #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
  14441. #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
  14442. #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
  14443. #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
  14444. #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
  14445. #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
  14446. #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
  14447. #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
  14448. /******************** Bit definition for USB_OTG_HAINT register ********************/
  14449. #define USB_OTG_HAINT_HAINT_Pos (0U)
  14450. #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
  14451. #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
  14452. /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
  14453. #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
  14454. #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  14455. #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  14456. #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
  14457. #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
  14458. #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  14459. #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
  14460. #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
  14461. #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
  14462. #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
  14463. #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
  14464. #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
  14465. #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
  14466. #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
  14467. #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
  14468. #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
  14469. #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
  14470. #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
  14471. #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
  14472. #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
  14473. #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
  14474. #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
  14475. #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
  14476. #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
  14477. #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
  14478. #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
  14479. #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
  14480. #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
  14481. #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
  14482. #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
  14483. #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
  14484. #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
  14485. #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
  14486. #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
  14487. #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
  14488. #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
  14489. /******************** Bit definition for USB_OTG_GINTSTS register ********************/
  14490. #define USB_OTG_GINTSTS_CMOD_Pos (0U)
  14491. #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
  14492. #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
  14493. #define USB_OTG_GINTSTS_MMIS_Pos (1U)
  14494. #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
  14495. #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
  14496. #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
  14497. #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
  14498. #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
  14499. #define USB_OTG_GINTSTS_SOF_Pos (3U)
  14500. #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
  14501. #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
  14502. #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
  14503. #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
  14504. #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
  14505. #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
  14506. #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
  14507. #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
  14508. #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
  14509. #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
  14510. #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
  14511. #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
  14512. #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
  14513. #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
  14514. #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
  14515. #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
  14516. #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
  14517. #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
  14518. #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
  14519. #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
  14520. #define USB_OTG_GINTSTS_USBRST_Pos (12U)
  14521. #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
  14522. #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
  14523. #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
  14524. #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
  14525. #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
  14526. #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
  14527. #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
  14528. #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
  14529. #define USB_OTG_GINTSTS_EOPF_Pos (15U)
  14530. #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
  14531. #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
  14532. #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
  14533. #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
  14534. #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
  14535. #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
  14536. #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
  14537. #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
  14538. #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
  14539. #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
  14540. #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
  14541. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
  14542. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
  14543. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
  14544. #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
  14545. #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
  14546. #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
  14547. #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
  14548. #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
  14549. #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
  14550. #define USB_OTG_GINTSTS_HCINT_Pos (25U)
  14551. #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
  14552. #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
  14553. #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
  14554. #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
  14555. #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
  14556. #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
  14557. #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
  14558. #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
  14559. #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
  14560. #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
  14561. #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
  14562. #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
  14563. #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
  14564. #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
  14565. #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
  14566. #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
  14567. #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
  14568. /******************** Bit definition for USB_OTG_GINTMSK register ********************/
  14569. #define USB_OTG_GINTMSK_MMISM_Pos (1U)
  14570. #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
  14571. #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
  14572. #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
  14573. #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
  14574. #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
  14575. #define USB_OTG_GINTMSK_SOFM_Pos (3U)
  14576. #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
  14577. #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
  14578. #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
  14579. #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
  14580. #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
  14581. #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
  14582. #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
  14583. #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
  14584. #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
  14585. #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
  14586. #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
  14587. #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
  14588. #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
  14589. #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
  14590. #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
  14591. #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
  14592. #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
  14593. #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
  14594. #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
  14595. #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
  14596. #define USB_OTG_GINTMSK_USBRST_Pos (12U)
  14597. #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
  14598. #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
  14599. #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
  14600. #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
  14601. #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
  14602. #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
  14603. #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
  14604. #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
  14605. #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
  14606. #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
  14607. #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
  14608. #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
  14609. #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
  14610. #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
  14611. #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
  14612. #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
  14613. #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
  14614. #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
  14615. #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
  14616. #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
  14617. #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
  14618. #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
  14619. #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
  14620. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
  14621. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
  14622. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
  14623. #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
  14624. #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
  14625. #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
  14626. #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
  14627. #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
  14628. #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
  14629. #define USB_OTG_GINTMSK_HCIM_Pos (25U)
  14630. #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
  14631. #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
  14632. #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
  14633. #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
  14634. #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
  14635. #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
  14636. #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
  14637. #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
  14638. #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
  14639. #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
  14640. #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
  14641. #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
  14642. #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
  14643. #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
  14644. #define USB_OTG_GINTMSK_WUIM_Pos (31U)
  14645. #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
  14646. #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
  14647. /******************** Bit definition for USB_OTG_DAINT register ********************/
  14648. #define USB_OTG_DAINT_IEPINT_Pos (0U)
  14649. #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
  14650. #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
  14651. #define USB_OTG_DAINT_OEPINT_Pos (16U)
  14652. #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
  14653. #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
  14654. /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
  14655. #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
  14656. #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
  14657. #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
  14658. /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
  14659. #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
  14660. #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
  14661. #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
  14662. #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
  14663. #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
  14664. #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
  14665. #define USB_OTG_GRXSTSP_DPID_Pos (15U)
  14666. #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
  14667. #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
  14668. #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
  14669. #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
  14670. #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
  14671. /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
  14672. #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
  14673. #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
  14674. #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
  14675. #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
  14676. #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
  14677. #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
  14678. /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
  14679. #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
  14680. #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
  14681. #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
  14682. /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
  14683. #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
  14684. #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
  14685. #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
  14686. /******************** Bit definition for OTG register ********************/
  14687. #define USB_OTG_NPTXFSA_Pos (0U)
  14688. #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
  14689. #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
  14690. #define USB_OTG_NPTXFD_Pos (16U)
  14691. #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
  14692. #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
  14693. #define USB_OTG_TX0FSA_Pos (0U)
  14694. #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
  14695. #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
  14696. #define USB_OTG_TX0FD_Pos (16U)
  14697. #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
  14698. #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
  14699. /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
  14700. #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
  14701. #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
  14702. #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
  14703. /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
  14704. #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
  14705. #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
  14706. #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
  14707. #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
  14708. #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
  14709. #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
  14710. #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
  14711. #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
  14712. #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
  14713. #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
  14714. #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
  14715. #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
  14716. #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
  14717. #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
  14718. #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
  14719. #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
  14720. #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
  14721. #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
  14722. #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
  14723. #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
  14724. #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
  14725. #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
  14726. #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
  14727. #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
  14728. /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
  14729. #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
  14730. #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
  14731. #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
  14732. #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
  14733. #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
  14734. #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
  14735. #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
  14736. #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
  14737. #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
  14738. #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
  14739. #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
  14740. #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
  14741. #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
  14742. #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
  14743. #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
  14744. #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
  14745. #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
  14746. #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
  14747. #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
  14748. #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
  14749. #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
  14750. #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
  14751. #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
  14752. #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
  14753. #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
  14754. #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
  14755. #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
  14756. #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
  14757. #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
  14758. #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
  14759. #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
  14760. #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
  14761. #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
  14762. #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
  14763. #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
  14764. #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
  14765. /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
  14766. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
  14767. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
  14768. #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
  14769. /******************** Bit definition for USB_OTG_DEACHINT register ********************/
  14770. #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
  14771. #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
  14772. #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
  14773. #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
  14774. #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
  14775. #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
  14776. /******************** Bit definition for USB_OTG_GCCFG register ********************/
  14777. #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
  14778. #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
  14779. #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
  14780. #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
  14781. #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
  14782. #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
  14783. #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
  14784. #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
  14785. #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
  14786. #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
  14787. #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
  14788. #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
  14789. #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
  14790. #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
  14791. #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
  14792. #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
  14793. #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
  14794. #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
  14795. /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
  14796. #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
  14797. #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
  14798. #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
  14799. #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
  14800. #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
  14801. #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
  14802. /******************** Bit definition for USB_OTG_CID register ********************/
  14803. #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
  14804. #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
  14805. #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
  14806. /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
  14807. #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
  14808. #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  14809. #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  14810. #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
  14811. #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  14812. #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  14813. #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
  14814. #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  14815. #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  14816. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
  14817. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  14818. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  14819. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
  14820. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  14821. #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  14822. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
  14823. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  14824. #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  14825. #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
  14826. #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  14827. #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
  14828. #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
  14829. #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  14830. #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  14831. #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
  14832. #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  14833. #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  14834. /******************** Bit definition for USB_OTG_HPRT register ********************/
  14835. #define USB_OTG_HPRT_PCSTS_Pos (0U)
  14836. #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
  14837. #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
  14838. #define USB_OTG_HPRT_PCDET_Pos (1U)
  14839. #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
  14840. #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
  14841. #define USB_OTG_HPRT_PENA_Pos (2U)
  14842. #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
  14843. #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
  14844. #define USB_OTG_HPRT_PENCHNG_Pos (3U)
  14845. #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
  14846. #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
  14847. #define USB_OTG_HPRT_POCA_Pos (4U)
  14848. #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
  14849. #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
  14850. #define USB_OTG_HPRT_POCCHNG_Pos (5U)
  14851. #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
  14852. #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
  14853. #define USB_OTG_HPRT_PRES_Pos (6U)
  14854. #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
  14855. #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
  14856. #define USB_OTG_HPRT_PSUSP_Pos (7U)
  14857. #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
  14858. #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
  14859. #define USB_OTG_HPRT_PRST_Pos (8U)
  14860. #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
  14861. #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
  14862. #define USB_OTG_HPRT_PLSTS_Pos (10U)
  14863. #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
  14864. #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
  14865. #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
  14866. #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
  14867. #define USB_OTG_HPRT_PPWR_Pos (12U)
  14868. #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
  14869. #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
  14870. #define USB_OTG_HPRT_PTCTL_Pos (13U)
  14871. #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
  14872. #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
  14873. #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
  14874. #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
  14875. #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
  14876. #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
  14877. #define USB_OTG_HPRT_PSPD_Pos (17U)
  14878. #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
  14879. #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
  14880. #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
  14881. #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
  14882. /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
  14883. #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
  14884. #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  14885. #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  14886. #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
  14887. #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  14888. #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  14889. #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
  14890. #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  14891. #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
  14892. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
  14893. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  14894. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  14895. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
  14896. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  14897. #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  14898. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
  14899. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  14900. #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  14901. #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
  14902. #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  14903. #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
  14904. #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
  14905. #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  14906. #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  14907. #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
  14908. #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
  14909. #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
  14910. #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
  14911. #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  14912. #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  14913. #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
  14914. #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
  14915. #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
  14916. /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
  14917. #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
  14918. #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
  14919. #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
  14920. #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
  14921. #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
  14922. #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
  14923. /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
  14924. #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
  14925. #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  14926. #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
  14927. #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
  14928. #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  14929. #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
  14930. #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
  14931. #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
  14932. #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
  14933. #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
  14934. #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  14935. #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
  14936. #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
  14937. #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  14938. #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
  14939. #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  14940. #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  14941. #define USB_OTG_DIEPCTL_STALL_Pos (21U)
  14942. #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
  14943. #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
  14944. #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
  14945. #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
  14946. #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
  14947. #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
  14948. #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
  14949. #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
  14950. #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
  14951. #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
  14952. #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
  14953. #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
  14954. #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
  14955. #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
  14956. #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
  14957. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
  14958. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  14959. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  14960. #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
  14961. #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  14962. #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
  14963. #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
  14964. #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  14965. #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
  14966. #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
  14967. #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
  14968. #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
  14969. /******************** Bit definition for USB_OTG_HCCHAR register ********************/
  14970. #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
  14971. #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
  14972. #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
  14973. #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
  14974. #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
  14975. #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
  14976. #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
  14977. #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
  14978. #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
  14979. #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
  14980. #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
  14981. #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
  14982. #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
  14983. #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
  14984. #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
  14985. #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
  14986. #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
  14987. #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
  14988. #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
  14989. #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
  14990. #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
  14991. #define USB_OTG_HCCHAR_MC_Pos (20U)
  14992. #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
  14993. #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
  14994. #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
  14995. #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
  14996. #define USB_OTG_HCCHAR_DAD_Pos (22U)
  14997. #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
  14998. #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
  14999. #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
  15000. #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
  15001. #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
  15002. #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
  15003. #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
  15004. #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
  15005. #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
  15006. #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
  15007. #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
  15008. #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
  15009. #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
  15010. #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
  15011. #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
  15012. #define USB_OTG_HCCHAR_CHENA_Pos (31U)
  15013. #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
  15014. #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
  15015. /******************** Bit definition for USB_OTG_HCSPLT register ********************/
  15016. #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
  15017. #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
  15018. #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
  15019. #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
  15020. #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
  15021. #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
  15022. #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
  15023. #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
  15024. #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
  15025. #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
  15026. #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
  15027. #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
  15028. #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
  15029. #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
  15030. #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
  15031. #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
  15032. #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
  15033. #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
  15034. #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
  15035. #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
  15036. #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
  15037. #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
  15038. #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
  15039. #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
  15040. #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
  15041. #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
  15042. #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
  15043. #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
  15044. #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
  15045. #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
  15046. #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
  15047. /******************** Bit definition for USB_OTG_HCINT register ********************/
  15048. #define USB_OTG_HCINT_XFRC_Pos (0U)
  15049. #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
  15050. #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
  15051. #define USB_OTG_HCINT_CHH_Pos (1U)
  15052. #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
  15053. #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
  15054. #define USB_OTG_HCINT_AHBERR_Pos (2U)
  15055. #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
  15056. #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
  15057. #define USB_OTG_HCINT_STALL_Pos (3U)
  15058. #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
  15059. #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
  15060. #define USB_OTG_HCINT_NAK_Pos (4U)
  15061. #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
  15062. #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
  15063. #define USB_OTG_HCINT_ACK_Pos (5U)
  15064. #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
  15065. #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
  15066. #define USB_OTG_HCINT_NYET_Pos (6U)
  15067. #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
  15068. #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
  15069. #define USB_OTG_HCINT_TXERR_Pos (7U)
  15070. #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
  15071. #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
  15072. #define USB_OTG_HCINT_BBERR_Pos (8U)
  15073. #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
  15074. #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
  15075. #define USB_OTG_HCINT_FRMOR_Pos (9U)
  15076. #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
  15077. #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
  15078. #define USB_OTG_HCINT_DTERR_Pos (10U)
  15079. #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
  15080. #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
  15081. /******************** Bit definition for USB_OTG_DIEPINT register ********************/
  15082. #define USB_OTG_DIEPINT_XFRC_Pos (0U)
  15083. #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
  15084. #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  15085. #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
  15086. #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
  15087. #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  15088. #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
  15089. #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
  15090. #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
  15091. #define USB_OTG_DIEPINT_TOC_Pos (3U)
  15092. #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
  15093. #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
  15094. #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
  15095. #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
  15096. #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
  15097. #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
  15098. #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
  15099. #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
  15100. #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
  15101. #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
  15102. #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
  15103. #define USB_OTG_DIEPINT_TXFE_Pos (7U)
  15104. #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
  15105. #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
  15106. #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
  15107. #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
  15108. #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
  15109. #define USB_OTG_DIEPINT_BNA_Pos (9U)
  15110. #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
  15111. #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
  15112. #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
  15113. #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
  15114. #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
  15115. #define USB_OTG_DIEPINT_BERR_Pos (12U)
  15116. #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
  15117. #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
  15118. #define USB_OTG_DIEPINT_NAK_Pos (13U)
  15119. #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
  15120. #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
  15121. /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
  15122. #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
  15123. #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
  15124. #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
  15125. #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
  15126. #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
  15127. #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
  15128. #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
  15129. #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
  15130. #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
  15131. #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
  15132. #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
  15133. #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
  15134. #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
  15135. #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
  15136. #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
  15137. #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
  15138. #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
  15139. #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
  15140. #define USB_OTG_HCINTMSK_NYET_Pos (6U)
  15141. #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
  15142. #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
  15143. #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
  15144. #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
  15145. #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
  15146. #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
  15147. #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
  15148. #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
  15149. #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
  15150. #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
  15151. #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
  15152. #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
  15153. #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
  15154. #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
  15155. /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
  15156. #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
  15157. #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  15158. #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  15159. #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
  15160. #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  15161. #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
  15162. #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
  15163. #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
  15164. #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
  15165. /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
  15166. #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
  15167. #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  15168. #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
  15169. #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
  15170. #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  15171. #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
  15172. #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
  15173. #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
  15174. #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
  15175. #define USB_OTG_HCTSIZ_DPID_Pos (29U)
  15176. #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
  15177. #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
  15178. #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
  15179. #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
  15180. /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
  15181. #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
  15182. #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  15183. #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
  15184. /******************** Bit definition for USB_OTG_HCDMA register ********************/
  15185. #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
  15186. #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  15187. #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
  15188. /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
  15189. #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
  15190. #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
  15191. #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
  15192. /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
  15193. #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
  15194. #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
  15195. #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
  15196. #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
  15197. #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
  15198. #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
  15199. /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
  15200. #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
  15201. #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  15202. #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
  15203. #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
  15204. #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  15205. #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
  15206. #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
  15207. #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  15208. #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
  15209. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
  15210. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  15211. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  15212. #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
  15213. #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  15214. #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
  15215. #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
  15216. #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  15217. #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
  15218. #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  15219. #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  15220. #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
  15221. #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
  15222. #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
  15223. #define USB_OTG_DOEPCTL_STALL_Pos (21U)
  15224. #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
  15225. #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
  15226. #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
  15227. #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
  15228. #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
  15229. #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
  15230. #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
  15231. #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
  15232. #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
  15233. #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  15234. #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
  15235. #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
  15236. #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
  15237. #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
  15238. /******************** Bit definition for USB_OTG_DOEPINT register ********************/
  15239. #define USB_OTG_DOEPINT_XFRC_Pos (0U)
  15240. #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
  15241. #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  15242. #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
  15243. #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
  15244. #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  15245. #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
  15246. #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
  15247. #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
  15248. #define USB_OTG_DOEPINT_STUP_Pos (3U)
  15249. #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
  15250. #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
  15251. #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
  15252. #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
  15253. #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
  15254. #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
  15255. #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
  15256. #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
  15257. #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
  15258. #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
  15259. #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
  15260. #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
  15261. #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
  15262. #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
  15263. #define USB_OTG_DOEPINT_NAK_Pos (13U)
  15264. #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
  15265. #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
  15266. #define USB_OTG_DOEPINT_NYET_Pos (14U)
  15267. #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
  15268. #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
  15269. #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
  15270. #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
  15271. #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
  15272. /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
  15273. #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
  15274. #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  15275. #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  15276. #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
  15277. #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  15278. #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
  15279. #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
  15280. #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
  15281. #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
  15282. #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
  15283. #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
  15284. /******************** Bit definition for PCGCCTL register ********************/
  15285. #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
  15286. #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
  15287. #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
  15288. #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
  15289. #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
  15290. #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
  15291. #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
  15292. #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
  15293. #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
  15294. /* Legacy define */
  15295. /******************** Bit definition for OTG register ********************/
  15296. #define USB_OTG_CHNUM_Pos (0U)
  15297. #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
  15298. #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
  15299. #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
  15300. #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
  15301. #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
  15302. #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
  15303. #define USB_OTG_BCNT_Pos (4U)
  15304. #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
  15305. #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
  15306. #define USB_OTG_DPID_Pos (15U)
  15307. #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
  15308. #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
  15309. #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
  15310. #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
  15311. #define USB_OTG_PKTSTS_Pos (17U)
  15312. #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
  15313. #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
  15314. #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
  15315. #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
  15316. #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
  15317. #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
  15318. #define USB_OTG_EPNUM_Pos (0U)
  15319. #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
  15320. #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
  15321. #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
  15322. #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
  15323. #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
  15324. #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
  15325. #define USB_OTG_FRMNUM_Pos (21U)
  15326. #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
  15327. #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
  15328. #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
  15329. #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
  15330. #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
  15331. #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
  15332. /**
  15333. * @}
  15334. */
  15335. /**
  15336. * @}
  15337. */
  15338. /** @addtogroup Exported_macros
  15339. * @{
  15340. */
  15341. /******************************* ADC Instances ********************************/
  15342. #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
  15343. ((INSTANCE) == ADC2) || \
  15344. ((INSTANCE) == ADC3))
  15345. #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  15346. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
  15347. /******************************* CAN Instances ********************************/
  15348. #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
  15349. ((INSTANCE) == CAN2))
  15350. /******************************* CRC Instances ********************************/
  15351. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  15352. /******************************* DAC Instances ********************************/
  15353. #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
  15354. /******************************* DCMI Instances *******************************/
  15355. #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
  15356. /******************************* DMA2D Instances *******************************/
  15357. #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
  15358. /******************************** DMA Instances *******************************/
  15359. #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
  15360. ((INSTANCE) == DMA1_Stream1) || \
  15361. ((INSTANCE) == DMA1_Stream2) || \
  15362. ((INSTANCE) == DMA1_Stream3) || \
  15363. ((INSTANCE) == DMA1_Stream4) || \
  15364. ((INSTANCE) == DMA1_Stream5) || \
  15365. ((INSTANCE) == DMA1_Stream6) || \
  15366. ((INSTANCE) == DMA1_Stream7) || \
  15367. ((INSTANCE) == DMA2_Stream0) || \
  15368. ((INSTANCE) == DMA2_Stream1) || \
  15369. ((INSTANCE) == DMA2_Stream2) || \
  15370. ((INSTANCE) == DMA2_Stream3) || \
  15371. ((INSTANCE) == DMA2_Stream4) || \
  15372. ((INSTANCE) == DMA2_Stream5) || \
  15373. ((INSTANCE) == DMA2_Stream6) || \
  15374. ((INSTANCE) == DMA2_Stream7))
  15375. /******************************* GPIO Instances *******************************/
  15376. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  15377. ((INSTANCE) == GPIOB) || \
  15378. ((INSTANCE) == GPIOC) || \
  15379. ((INSTANCE) == GPIOD) || \
  15380. ((INSTANCE) == GPIOE) || \
  15381. ((INSTANCE) == GPIOF) || \
  15382. ((INSTANCE) == GPIOG) || \
  15383. ((INSTANCE) == GPIOH) || \
  15384. ((INSTANCE) == GPIOI) || \
  15385. ((INSTANCE) == GPIOJ) || \
  15386. ((INSTANCE) == GPIOK))
  15387. /******************************** I2C Instances *******************************/
  15388. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  15389. ((INSTANCE) == I2C2) || \
  15390. ((INSTANCE) == I2C3))
  15391. /******************************* SMBUS Instances ******************************/
  15392. #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
  15393. /******************************** I2S Instances *******************************/
  15394. #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
  15395. ((INSTANCE) == SPI3))
  15396. /*************************** I2S Extended Instances ***************************/
  15397. #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
  15398. ((INSTANCE) == I2S3ext))
  15399. /* Legacy Defines */
  15400. #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
  15401. /******************************* RNG Instances ********************************/
  15402. #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
  15403. /****************************** RTC Instances *********************************/
  15404. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  15405. /******************************* SAI Instances ********************************/
  15406. #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
  15407. ((PERIPH) == SAI1_Block_B))
  15408. /* Legacy define */
  15409. #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
  15410. /******************************** SPI Instances *******************************/
  15411. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  15412. ((INSTANCE) == SPI2) || \
  15413. ((INSTANCE) == SPI3) || \
  15414. ((INSTANCE) == SPI4) || \
  15415. ((INSTANCE) == SPI5) || \
  15416. ((INSTANCE) == SPI6))
  15417. /****************** TIM Instances : All supported instances *******************/
  15418. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15419. ((INSTANCE) == TIM2) || \
  15420. ((INSTANCE) == TIM3) || \
  15421. ((INSTANCE) == TIM4) || \
  15422. ((INSTANCE) == TIM5) || \
  15423. ((INSTANCE) == TIM6) || \
  15424. ((INSTANCE) == TIM7) || \
  15425. ((INSTANCE) == TIM8) || \
  15426. ((INSTANCE) == TIM9) || \
  15427. ((INSTANCE) == TIM10)|| \
  15428. ((INSTANCE) == TIM11)|| \
  15429. ((INSTANCE) == TIM12)|| \
  15430. ((INSTANCE) == TIM13)|| \
  15431. ((INSTANCE) == TIM14))
  15432. /****************** TIM Instances : supporting synchronization ****************/
  15433. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  15434. /************* TIM Instances : at least 1 capture/compare channel *************/
  15435. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15436. ((INSTANCE) == TIM2) || \
  15437. ((INSTANCE) == TIM3) || \
  15438. ((INSTANCE) == TIM4) || \
  15439. ((INSTANCE) == TIM5) || \
  15440. ((INSTANCE) == TIM8) || \
  15441. ((INSTANCE) == TIM9) || \
  15442. ((INSTANCE) == TIM10) || \
  15443. ((INSTANCE) == TIM11) || \
  15444. ((INSTANCE) == TIM12) || \
  15445. ((INSTANCE) == TIM13) || \
  15446. ((INSTANCE) == TIM14))
  15447. /************ TIM Instances : at least 2 capture/compare channels *************/
  15448. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15449. ((INSTANCE) == TIM2) || \
  15450. ((INSTANCE) == TIM3) || \
  15451. ((INSTANCE) == TIM4) || \
  15452. ((INSTANCE) == TIM5) || \
  15453. ((INSTANCE) == TIM8) || \
  15454. ((INSTANCE) == TIM9) || \
  15455. ((INSTANCE) == TIM12))
  15456. /************ TIM Instances : at least 3 capture/compare channels *************/
  15457. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15458. ((INSTANCE) == TIM2) || \
  15459. ((INSTANCE) == TIM3) || \
  15460. ((INSTANCE) == TIM4) || \
  15461. ((INSTANCE) == TIM5) || \
  15462. ((INSTANCE) == TIM8))
  15463. /************ TIM Instances : at least 4 capture/compare channels *************/
  15464. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15465. ((INSTANCE) == TIM2) || \
  15466. ((INSTANCE) == TIM3) || \
  15467. ((INSTANCE) == TIM4) || \
  15468. ((INSTANCE) == TIM5) || \
  15469. ((INSTANCE) == TIM8))
  15470. /******************** TIM Instances : Advanced-control timers *****************/
  15471. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15472. ((INSTANCE) == TIM8))
  15473. /******************* TIM Instances : Timer input XOR function *****************/
  15474. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15475. ((INSTANCE) == TIM2) || \
  15476. ((INSTANCE) == TIM3) || \
  15477. ((INSTANCE) == TIM4) || \
  15478. ((INSTANCE) == TIM5) || \
  15479. ((INSTANCE) == TIM8))
  15480. /****************** TIM Instances : DMA requests generation (UDE) *************/
  15481. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15482. ((INSTANCE) == TIM2) || \
  15483. ((INSTANCE) == TIM3) || \
  15484. ((INSTANCE) == TIM4) || \
  15485. ((INSTANCE) == TIM5) || \
  15486. ((INSTANCE) == TIM6) || \
  15487. ((INSTANCE) == TIM7) || \
  15488. ((INSTANCE) == TIM8))
  15489. /************ TIM Instances : DMA requests generation (CCxDE) *****************/
  15490. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15491. ((INSTANCE) == TIM2) || \
  15492. ((INSTANCE) == TIM3) || \
  15493. ((INSTANCE) == TIM4) || \
  15494. ((INSTANCE) == TIM5) || \
  15495. ((INSTANCE) == TIM8))
  15496. /************ TIM Instances : DMA requests generation (COMDE) *****************/
  15497. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15498. ((INSTANCE) == TIM2) || \
  15499. ((INSTANCE) == TIM3) || \
  15500. ((INSTANCE) == TIM4) || \
  15501. ((INSTANCE) == TIM5) || \
  15502. ((INSTANCE) == TIM8))
  15503. /******************** TIM Instances : DMA burst feature ***********************/
  15504. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15505. ((INSTANCE) == TIM2) || \
  15506. ((INSTANCE) == TIM3) || \
  15507. ((INSTANCE) == TIM4) || \
  15508. ((INSTANCE) == TIM5) || \
  15509. ((INSTANCE) == TIM8))
  15510. /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
  15511. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15512. ((INSTANCE) == TIM2) || \
  15513. ((INSTANCE) == TIM3) || \
  15514. ((INSTANCE) == TIM4) || \
  15515. ((INSTANCE) == TIM5) || \
  15516. ((INSTANCE) == TIM6) || \
  15517. ((INSTANCE) == TIM7) || \
  15518. ((INSTANCE) == TIM8))
  15519. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  15520. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15521. ((INSTANCE) == TIM2) || \
  15522. ((INSTANCE) == TIM3) || \
  15523. ((INSTANCE) == TIM4) || \
  15524. ((INSTANCE) == TIM5) || \
  15525. ((INSTANCE) == TIM8) || \
  15526. ((INSTANCE) == TIM9) || \
  15527. ((INSTANCE) == TIM12))
  15528. /********************** TIM Instances : 32 bit Counter ************************/
  15529. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
  15530. ((INSTANCE) == TIM5))
  15531. /***************** TIM Instances : external trigger input availabe ************/
  15532. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15533. ((INSTANCE) == TIM2) || \
  15534. ((INSTANCE) == TIM3) || \
  15535. ((INSTANCE) == TIM4) || \
  15536. ((INSTANCE) == TIM5) || \
  15537. ((INSTANCE) == TIM8))
  15538. /****************** TIM Instances : remapping capability **********************/
  15539. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
  15540. ((INSTANCE) == TIM5) || \
  15541. ((INSTANCE) == TIM11))
  15542. /******************* TIM Instances : output(s) available **********************/
  15543. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  15544. ((((INSTANCE) == TIM1) && \
  15545. (((CHANNEL) == TIM_CHANNEL_1) || \
  15546. ((CHANNEL) == TIM_CHANNEL_2) || \
  15547. ((CHANNEL) == TIM_CHANNEL_3) || \
  15548. ((CHANNEL) == TIM_CHANNEL_4))) \
  15549. || \
  15550. (((INSTANCE) == TIM2) && \
  15551. (((CHANNEL) == TIM_CHANNEL_1) || \
  15552. ((CHANNEL) == TIM_CHANNEL_2) || \
  15553. ((CHANNEL) == TIM_CHANNEL_3) || \
  15554. ((CHANNEL) == TIM_CHANNEL_4))) \
  15555. || \
  15556. (((INSTANCE) == TIM3) && \
  15557. (((CHANNEL) == TIM_CHANNEL_1) || \
  15558. ((CHANNEL) == TIM_CHANNEL_2) || \
  15559. ((CHANNEL) == TIM_CHANNEL_3) || \
  15560. ((CHANNEL) == TIM_CHANNEL_4))) \
  15561. || \
  15562. (((INSTANCE) == TIM4) && \
  15563. (((CHANNEL) == TIM_CHANNEL_1) || \
  15564. ((CHANNEL) == TIM_CHANNEL_2) || \
  15565. ((CHANNEL) == TIM_CHANNEL_3) || \
  15566. ((CHANNEL) == TIM_CHANNEL_4))) \
  15567. || \
  15568. (((INSTANCE) == TIM5) && \
  15569. (((CHANNEL) == TIM_CHANNEL_1) || \
  15570. ((CHANNEL) == TIM_CHANNEL_2) || \
  15571. ((CHANNEL) == TIM_CHANNEL_3) || \
  15572. ((CHANNEL) == TIM_CHANNEL_4))) \
  15573. || \
  15574. (((INSTANCE) == TIM8) && \
  15575. (((CHANNEL) == TIM_CHANNEL_1) || \
  15576. ((CHANNEL) == TIM_CHANNEL_2) || \
  15577. ((CHANNEL) == TIM_CHANNEL_3) || \
  15578. ((CHANNEL) == TIM_CHANNEL_4))) \
  15579. || \
  15580. (((INSTANCE) == TIM9) && \
  15581. (((CHANNEL) == TIM_CHANNEL_1) || \
  15582. ((CHANNEL) == TIM_CHANNEL_2))) \
  15583. || \
  15584. (((INSTANCE) == TIM10) && \
  15585. (((CHANNEL) == TIM_CHANNEL_1))) \
  15586. || \
  15587. (((INSTANCE) == TIM11) && \
  15588. (((CHANNEL) == TIM_CHANNEL_1))) \
  15589. || \
  15590. (((INSTANCE) == TIM12) && \
  15591. (((CHANNEL) == TIM_CHANNEL_1) || \
  15592. ((CHANNEL) == TIM_CHANNEL_2))) \
  15593. || \
  15594. (((INSTANCE) == TIM13) && \
  15595. (((CHANNEL) == TIM_CHANNEL_1))) \
  15596. || \
  15597. (((INSTANCE) == TIM14) && \
  15598. (((CHANNEL) == TIM_CHANNEL_1))))
  15599. /************ TIM Instances : complementary output(s) available ***************/
  15600. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  15601. ((((INSTANCE) == TIM1) && \
  15602. (((CHANNEL) == TIM_CHANNEL_1) || \
  15603. ((CHANNEL) == TIM_CHANNEL_2) || \
  15604. ((CHANNEL) == TIM_CHANNEL_3))) \
  15605. || \
  15606. (((INSTANCE) == TIM8) && \
  15607. (((CHANNEL) == TIM_CHANNEL_1) || \
  15608. ((CHANNEL) == TIM_CHANNEL_2) || \
  15609. ((CHANNEL) == TIM_CHANNEL_3))))
  15610. /****************** TIM Instances : supporting counting mode selection ********/
  15611. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15612. ((INSTANCE) == TIM2) || \
  15613. ((INSTANCE) == TIM3) || \
  15614. ((INSTANCE) == TIM4) || \
  15615. ((INSTANCE) == TIM5) || \
  15616. ((INSTANCE) == TIM8))
  15617. /****************** TIM Instances : supporting clock division *****************/
  15618. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15619. ((INSTANCE) == TIM2) || \
  15620. ((INSTANCE) == TIM3) || \
  15621. ((INSTANCE) == TIM4) || \
  15622. ((INSTANCE) == TIM5) || \
  15623. ((INSTANCE) == TIM8) || \
  15624. ((INSTANCE) == TIM9) || \
  15625. ((INSTANCE) == TIM10)|| \
  15626. ((INSTANCE) == TIM11)|| \
  15627. ((INSTANCE) == TIM12)|| \
  15628. ((INSTANCE) == TIM13)|| \
  15629. ((INSTANCE) == TIM14))
  15630. /****************** TIM Instances : supporting commutation event generation ***/
  15631. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
  15632. ((INSTANCE) == TIM8))
  15633. /****************** TIM Instances : supporting OCxREF clear *******************/
  15634. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15635. ((INSTANCE) == TIM2) || \
  15636. ((INSTANCE) == TIM3) || \
  15637. ((INSTANCE) == TIM4) || \
  15638. ((INSTANCE) == TIM5) || \
  15639. ((INSTANCE) == TIM8))
  15640. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  15641. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15642. ((INSTANCE) == TIM2) || \
  15643. ((INSTANCE) == TIM3) || \
  15644. ((INSTANCE) == TIM4) || \
  15645. ((INSTANCE) == TIM5) || \
  15646. ((INSTANCE) == TIM8) || \
  15647. ((INSTANCE) == TIM9) || \
  15648. ((INSTANCE) == TIM12))
  15649. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  15650. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15651. ((INSTANCE) == TIM2) || \
  15652. ((INSTANCE) == TIM3) || \
  15653. ((INSTANCE) == TIM4) || \
  15654. ((INSTANCE) == TIM5) || \
  15655. ((INSTANCE) == TIM8))
  15656. /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
  15657. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15658. ((INSTANCE) == TIM2) || \
  15659. ((INSTANCE) == TIM3) || \
  15660. ((INSTANCE) == TIM4) || \
  15661. ((INSTANCE) == TIM5) || \
  15662. ((INSTANCE) == TIM8) || \
  15663. ((INSTANCE) == TIM9) || \
  15664. ((INSTANCE) == TIM12))
  15665. /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
  15666. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15667. ((INSTANCE) == TIM2) || \
  15668. ((INSTANCE) == TIM3) || \
  15669. ((INSTANCE) == TIM4) || \
  15670. ((INSTANCE) == TIM5) || \
  15671. ((INSTANCE) == TIM8) || \
  15672. ((INSTANCE) == TIM9) || \
  15673. ((INSTANCE) == TIM12))
  15674. /****************** TIM Instances : supporting repetition counter *************/
  15675. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15676. ((INSTANCE) == TIM8))
  15677. /****************** TIM Instances : supporting encoder interface **************/
  15678. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15679. ((INSTANCE) == TIM2) || \
  15680. ((INSTANCE) == TIM3) || \
  15681. ((INSTANCE) == TIM4) || \
  15682. ((INSTANCE) == TIM5) || \
  15683. ((INSTANCE) == TIM8) || \
  15684. ((INSTANCE) == TIM9) || \
  15685. ((INSTANCE) == TIM12))
  15686. /****************** TIM Instances : supporting Hall sensor interface **********/
  15687. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15688. ((INSTANCE) == TIM2) || \
  15689. ((INSTANCE) == TIM3) || \
  15690. ((INSTANCE) == TIM4) || \
  15691. ((INSTANCE) == TIM5) || \
  15692. ((INSTANCE) == TIM8))
  15693. /****************** TIM Instances : supporting the break function *************/
  15694. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  15695. ((INSTANCE) == TIM8))
  15696. /******************** USART Instances : Synchronous mode **********************/
  15697. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  15698. ((INSTANCE) == USART2) || \
  15699. ((INSTANCE) == USART3) || \
  15700. ((INSTANCE) == USART6))
  15701. /******************** UART Instances : Half-Duplex mode **********************/
  15702. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  15703. ((INSTANCE) == USART2) || \
  15704. ((INSTANCE) == USART3) || \
  15705. ((INSTANCE) == UART4) || \
  15706. ((INSTANCE) == UART5) || \
  15707. ((INSTANCE) == USART6) || \
  15708. ((INSTANCE) == UART7) || \
  15709. ((INSTANCE) == UART8))
  15710. /* Legacy defines */
  15711. #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  15712. /****************** UART Instances : Hardware Flow control ********************/
  15713. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  15714. ((INSTANCE) == USART2) || \
  15715. ((INSTANCE) == USART3) || \
  15716. ((INSTANCE) == USART6))
  15717. /******************** UART Instances : LIN mode **********************/
  15718. #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  15719. /********************* UART Instances : Smart card mode ***********************/
  15720. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  15721. ((INSTANCE) == USART2) || \
  15722. ((INSTANCE) == USART3) || \
  15723. ((INSTANCE) == USART6))
  15724. /*********************** UART Instances : IRDA mode ***************************/
  15725. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  15726. ((INSTANCE) == USART2) || \
  15727. ((INSTANCE) == USART3) || \
  15728. ((INSTANCE) == UART4) || \
  15729. ((INSTANCE) == UART5) || \
  15730. ((INSTANCE) == USART6) || \
  15731. ((INSTANCE) == UART7) || \
  15732. ((INSTANCE) == UART8))
  15733. /*********************** PCD Instances ****************************************/
  15734. #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
  15735. ((INSTANCE) == USB_OTG_HS))
  15736. /*********************** HCD Instances ****************************************/
  15737. #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
  15738. ((INSTANCE) == USB_OTG_HS))
  15739. /****************************** SDIO Instances ********************************/
  15740. #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
  15741. /****************************** IWDG Instances ********************************/
  15742. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  15743. /****************************** WWDG Instances ********************************/
  15744. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  15745. /****************************** USB Exported Constants ************************/
  15746. #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
  15747. #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
  15748. #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
  15749. #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
  15750. /*
  15751. * @brief Specific devices reset values definitions
  15752. */
  15753. #define RCC_PLLCFGR_RST_VALUE 0x24003010U
  15754. #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
  15755. #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
  15756. #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
  15757. #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
  15758. #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
  15759. #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  15760. #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
  15761. #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  15762. #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  15763. #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  15764. #define RCC_PLLN_MIN_VALUE 50U
  15765. #define RCC_PLLN_MAX_VALUE 432U
  15766. #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  15767. #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  15768. #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  15769. #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
  15770. #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
  15771. #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  15772. #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  15773. #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
  15774. #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
  15775. #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
  15776. #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  15777. #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  15778. #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
  15779. #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
  15780. #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
  15781. #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
  15782. #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
  15783. /******************************************************************************/
  15784. /* For a painless codes migration between the STM32F4xx device product */
  15785. /* lines, the aliases defined below are put in place to overcome the */
  15786. /* differences in the interrupt handlers and IRQn definitions. */
  15787. /* No need to update developed interrupt code when moving across */
  15788. /* product lines within the same STM32F4 Family */
  15789. /******************************************************************************/
  15790. /* Aliases for __IRQn */
  15791. #define FSMC_IRQn FMC_IRQn
  15792. /* Aliases for __IRQHandler */
  15793. #define FSMC_IRQHandler FMC_IRQHandler
  15794. /**
  15795. * @}
  15796. */
  15797. /**
  15798. * @}
  15799. */
  15800. /**
  15801. * @}
  15802. */
  15803. #ifdef __cplusplus
  15804. }
  15805. #endif /* __cplusplus */
  15806. #endif /* __STM32F427xx_H */
  15807. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/