stm32f410cx.h 591 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f410cx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32F410Cx Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - peripherals registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32f410cx
  45. * @{
  46. */
  47. #ifndef __STM32F410Cx_H
  48. #define __STM32F410Cx_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
  59. #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 1U /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32F4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  77. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  78. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  79. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  80. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  81. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  82. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  83. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  84. /****** STM32 specific Interrupt Numbers **********************************************************************/
  85. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  86. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  87. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  88. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  89. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  90. RCC_IRQn = 5, /*!< RCC global Interrupt */
  91. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  92. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  93. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  94. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  95. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  96. DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
  97. DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
  98. DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
  99. DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
  100. DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
  101. DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
  102. DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
  103. ADC_IRQn = 18, /*!< ADC1 global Interrupts */
  104. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  105. TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
  106. TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
  107. TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
  108. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  109. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  110. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  111. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  112. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  113. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  114. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  115. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  116. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  117. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  118. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  119. DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
  120. TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
  121. TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
  122. DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
  123. DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
  124. DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
  125. DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
  126. DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
  127. DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
  128. DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
  129. DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
  130. USART6_IRQn = 71, /*!< USART6 global interrupt */
  131. RNG_IRQn = 80, /*!< RNG global Interrupt */
  132. FPU_IRQn = 81, /*!< FPU global interrupt */
  133. SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
  134. FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
  135. FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
  136. LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
  137. } IRQn_Type;
  138. /**
  139. * @}
  140. */
  141. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  142. #include "system_stm32f4xx.h"
  143. #include <stdint.h>
  144. /** @addtogroup Peripheral_registers_structures
  145. * @{
  146. */
  147. /**
  148. * @brief Analog to Digital Converter
  149. */
  150. typedef struct
  151. {
  152. __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
  153. __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
  154. __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
  155. __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
  156. __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
  157. __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  158. __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  159. __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  160. __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  161. __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
  162. __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
  163. __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
  164. __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
  165. __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
  166. __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
  167. __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
  168. __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
  169. __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
  170. __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
  171. __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
  172. } ADC_TypeDef;
  173. typedef struct
  174. {
  175. __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
  176. __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
  177. __IO uint32_t CDR; /*!< ADC common regular data register for dual
  178. AND triple modes, Address offset: ADC1 base address + 0x308 */
  179. } ADC_Common_TypeDef;
  180. /**
  181. * @brief CRC calculation unit
  182. */
  183. typedef struct
  184. {
  185. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  186. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  187. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  188. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  189. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  190. } CRC_TypeDef;
  191. /**
  192. * @brief Digital to Analog Converter
  193. */
  194. typedef struct
  195. {
  196. __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
  197. __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
  198. __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  199. __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
  200. __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
  201. __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  202. __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
  203. __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
  204. __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
  205. __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
  206. __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
  207. __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
  208. __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
  209. __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
  210. } DAC_TypeDef;
  211. /**
  212. * @brief Debug MCU
  213. */
  214. typedef struct
  215. {
  216. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  217. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  218. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  219. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  220. }DBGMCU_TypeDef;
  221. /**
  222. * @brief DMA Controller
  223. */
  224. typedef struct
  225. {
  226. __IO uint32_t CR; /*!< DMA stream x configuration register */
  227. __IO uint32_t NDTR; /*!< DMA stream x number of data register */
  228. __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
  229. __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
  230. __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
  231. __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
  232. } DMA_Stream_TypeDef;
  233. typedef struct
  234. {
  235. __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
  236. __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
  237. __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
  238. __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
  239. } DMA_TypeDef;
  240. /**
  241. * @brief External Interrupt/Event Controller
  242. */
  243. typedef struct
  244. {
  245. __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
  246. __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
  247. __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
  248. __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
  249. __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
  250. __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
  251. } EXTI_TypeDef;
  252. /**
  253. * @brief FLASH Registers
  254. */
  255. typedef struct
  256. {
  257. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  258. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
  259. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
  260. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
  261. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
  262. __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
  263. __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
  264. } FLASH_TypeDef;
  265. /**
  266. * @brief General Purpose I/O
  267. */
  268. typedef struct
  269. {
  270. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  271. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  272. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  273. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  274. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  275. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  276. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  277. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  278. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  279. } GPIO_TypeDef;
  280. /**
  281. * @brief System configuration controller
  282. */
  283. typedef struct
  284. {
  285. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  286. __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
  287. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  288. uint32_t RESERVED; /*!< Reserved, 0x18 */
  289. __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */
  290. __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
  291. __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */
  292. } SYSCFG_TypeDef;
  293. /**
  294. * @brief Inter-integrated Circuit Interface
  295. */
  296. typedef struct
  297. {
  298. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  299. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  300. __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
  301. __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
  302. __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
  303. __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
  304. __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
  305. __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
  306. __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
  307. __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
  308. } I2C_TypeDef;
  309. /**
  310. * @brief Inter-integrated Circuit Interface
  311. */
  312. typedef struct
  313. {
  314. __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
  315. __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
  316. __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
  317. __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
  318. __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
  319. __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
  320. __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
  321. __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
  322. __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
  323. __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
  324. __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
  325. } FMPI2C_TypeDef;
  326. /**
  327. * @brief Independent WATCHDOG
  328. */
  329. typedef struct
  330. {
  331. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  332. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  333. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  334. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  335. } IWDG_TypeDef;
  336. /**
  337. * @brief Power Control
  338. */
  339. typedef struct
  340. {
  341. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  342. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  343. } PWR_TypeDef;
  344. /**
  345. * @brief Reset and Clock Control
  346. */
  347. typedef struct
  348. {
  349. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  350. __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
  351. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  352. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
  353. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
  354. uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
  355. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
  356. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
  357. uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
  358. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
  359. uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
  360. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
  361. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
  362. uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
  363. __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  364. uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
  365. __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  366. __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  367. uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
  368. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
  369. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
  370. uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
  371. __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
  372. uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
  373. __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
  374. __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
  375. __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
  376. } RCC_TypeDef;
  377. /**
  378. * @brief Real-Time Clock
  379. */
  380. typedef struct
  381. {
  382. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  383. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  384. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  385. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  386. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  387. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  388. __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
  389. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  390. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  391. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  392. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  393. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  394. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  395. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  396. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  397. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  398. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  399. __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
  400. __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
  401. uint32_t RESERVED7; /*!< Reserved, 0x4C */
  402. __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
  403. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  404. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  405. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  406. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  407. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  408. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  409. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  410. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  411. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  412. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  413. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  414. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  415. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  416. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  417. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  418. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  419. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  420. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  421. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  422. } RTC_TypeDef;
  423. /**
  424. * @brief Serial Peripheral Interface
  425. */
  426. typedef struct
  427. {
  428. __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
  429. __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
  430. __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
  431. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  432. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  433. __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
  434. __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
  435. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  436. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  437. } SPI_TypeDef;
  438. /**
  439. * @brief TIM
  440. */
  441. typedef struct
  442. {
  443. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  444. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  445. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  446. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  447. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  448. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  449. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  450. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  451. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  452. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  453. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  454. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  455. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  456. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  457. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  458. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  459. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  460. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  461. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  462. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  463. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  464. } TIM_TypeDef;
  465. /**
  466. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  467. */
  468. typedef struct
  469. {
  470. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  471. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  472. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  473. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  474. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  475. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  476. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  477. } USART_TypeDef;
  478. /**
  479. * @brief Window WATCHDOG
  480. */
  481. typedef struct
  482. {
  483. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  484. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  485. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  486. } WWDG_TypeDef;
  487. /**
  488. * @brief RNG
  489. */
  490. typedef struct
  491. {
  492. __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
  493. __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
  494. __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
  495. } RNG_TypeDef;
  496. /**
  497. * @brief LPTIMER
  498. */
  499. typedef struct
  500. {
  501. __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
  502. __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
  503. __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
  504. __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
  505. __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
  506. __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
  507. __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
  508. __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
  509. __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
  510. } LPTIM_TypeDef;
  511. /**
  512. * @}
  513. */
  514. /** @addtogroup Peripheral_memory_map
  515. * @{
  516. */
  517. #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
  518. #define SRAM1_BASE 0x20000000UL /*!< SRAM1(32 KB) base address in the alias region */
  519. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  520. #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(32 KB) base address in the bit-band region */
  521. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  522. #define FLASH_END 0x0801FFFFUL /*!< FLASH end address */
  523. #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
  524. #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
  525. /* Legacy defines */
  526. #define SRAM_BASE SRAM1_BASE
  527. #define SRAM_BB_BASE SRAM1_BB_BASE
  528. /*!< Peripheral memory map */
  529. #define APB1PERIPH_BASE PERIPH_BASE
  530. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  531. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  532. /*!< APB1 peripherals */
  533. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
  534. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
  535. #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
  536. #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
  537. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
  538. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
  539. #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
  540. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
  541. #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
  542. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
  543. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
  544. #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
  545. #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
  546. #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
  547. /*!< APB2 peripherals */
  548. #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
  549. #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
  550. #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
  551. #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
  552. #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
  553. /* Legacy define */
  554. #define ADC_BASE ADC1_COMMON_BASE
  555. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
  556. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
  557. #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
  558. #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
  559. #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
  560. #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
  561. /*!< AHB1 peripherals */
  562. #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
  563. #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
  564. #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
  565. #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
  566. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
  567. #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
  568. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
  569. #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
  570. #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
  571. #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
  572. #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
  573. #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
  574. #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
  575. #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
  576. #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
  577. #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
  578. #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
  579. #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
  580. #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
  581. #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
  582. #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
  583. #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
  584. #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
  585. #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
  586. #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
  587. #define RNG_BASE (PERIPH_BASE + 0x80000UL)
  588. /*!< Debug MCU registers base address */
  589. #define DBGMCU_BASE 0xE0042000UL
  590. #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
  591. #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
  592. #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
  593. /**
  594. * @}
  595. */
  596. /** @addtogroup Peripheral_declaration
  597. * @{
  598. */
  599. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  600. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  601. #define RTC ((RTC_TypeDef *) RTC_BASE)
  602. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  603. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  604. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  605. #define USART2 ((USART_TypeDef *) USART2_BASE)
  606. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  607. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  608. #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
  609. #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
  610. #define PWR ((PWR_TypeDef *) PWR_BASE)
  611. #define DAC1 ((DAC_TypeDef *) DAC_BASE)
  612. #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
  613. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  614. #define USART1 ((USART_TypeDef *) USART1_BASE)
  615. #define USART6 ((USART_TypeDef *) USART6_BASE)
  616. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  617. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
  618. /* Legacy define */
  619. #define ADC ADC1_COMMON
  620. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  621. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  622. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  623. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  624. #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
  625. #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
  626. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  627. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  628. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  629. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  630. #define CRC ((CRC_TypeDef *) CRC_BASE)
  631. #define RCC ((RCC_TypeDef *) RCC_BASE)
  632. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  633. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  634. #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  635. #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
  636. #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
  637. #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
  638. #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
  639. #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
  640. #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
  641. #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
  642. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  643. #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
  644. #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
  645. #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
  646. #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
  647. #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
  648. #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
  649. #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
  650. #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
  651. #define RNG ((RNG_TypeDef *) RNG_BASE)
  652. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  653. /**
  654. * @}
  655. */
  656. /** @addtogroup Exported_constants
  657. * @{
  658. */
  659. /** @addtogroup Peripheral_Registers_Bits_Definition
  660. * @{
  661. */
  662. /******************************************************************************/
  663. /* Peripheral Registers_Bits_Definition */
  664. /******************************************************************************/
  665. /******************************************************************************/
  666. /* */
  667. /* Analog to Digital Converter */
  668. /* */
  669. /******************************************************************************/
  670. /******************** Bit definition for ADC_SR register ********************/
  671. #define ADC_SR_AWD_Pos (0U)
  672. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  673. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
  674. #define ADC_SR_EOC_Pos (1U)
  675. #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
  676. #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
  677. #define ADC_SR_JEOC_Pos (2U)
  678. #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
  679. #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
  680. #define ADC_SR_JSTRT_Pos (3U)
  681. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  682. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
  683. #define ADC_SR_STRT_Pos (4U)
  684. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  685. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
  686. #define ADC_SR_OVR_Pos (5U)
  687. #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
  688. #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
  689. /******************* Bit definition for ADC_CR1 register ********************/
  690. #define ADC_CR1_AWDCH_Pos (0U)
  691. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  692. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
  693. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  694. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  695. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  696. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  697. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  698. #define ADC_CR1_EOCIE_Pos (5U)
  699. #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
  700. #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
  701. #define ADC_CR1_AWDIE_Pos (6U)
  702. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  703. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
  704. #define ADC_CR1_JEOCIE_Pos (7U)
  705. #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
  706. #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
  707. #define ADC_CR1_SCAN_Pos (8U)
  708. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  709. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
  710. #define ADC_CR1_AWDSGL_Pos (9U)
  711. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  712. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
  713. #define ADC_CR1_JAUTO_Pos (10U)
  714. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  715. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
  716. #define ADC_CR1_DISCEN_Pos (11U)
  717. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  718. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
  719. #define ADC_CR1_JDISCEN_Pos (12U)
  720. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  721. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
  722. #define ADC_CR1_DISCNUM_Pos (13U)
  723. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  724. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
  725. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  726. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  727. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  728. #define ADC_CR1_JAWDEN_Pos (22U)
  729. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  730. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
  731. #define ADC_CR1_AWDEN_Pos (23U)
  732. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  733. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
  734. #define ADC_CR1_RES_Pos (24U)
  735. #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
  736. #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
  737. #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
  738. #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
  739. #define ADC_CR1_OVRIE_Pos (26U)
  740. #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
  741. #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
  742. /******************* Bit definition for ADC_CR2 register ********************/
  743. #define ADC_CR2_ADON_Pos (0U)
  744. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  745. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
  746. #define ADC_CR2_CONT_Pos (1U)
  747. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  748. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
  749. #define ADC_CR2_DMA_Pos (8U)
  750. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  751. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
  752. #define ADC_CR2_DDS_Pos (9U)
  753. #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
  754. #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
  755. #define ADC_CR2_EOCS_Pos (10U)
  756. #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
  757. #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
  758. #define ADC_CR2_ALIGN_Pos (11U)
  759. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  760. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
  761. #define ADC_CR2_JEXTSEL_Pos (16U)
  762. #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
  763. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
  764. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
  765. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
  766. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
  767. #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
  768. #define ADC_CR2_JEXTEN_Pos (20U)
  769. #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
  770. #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
  771. #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
  772. #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
  773. #define ADC_CR2_JSWSTART_Pos (22U)
  774. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
  775. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
  776. #define ADC_CR2_EXTSEL_Pos (24U)
  777. #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
  778. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
  779. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
  780. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
  781. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
  782. #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
  783. #define ADC_CR2_EXTEN_Pos (28U)
  784. #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
  785. #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
  786. #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
  787. #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
  788. #define ADC_CR2_SWSTART_Pos (30U)
  789. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
  790. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
  791. /****************** Bit definition for ADC_SMPR1 register *******************/
  792. #define ADC_SMPR1_SMP10_Pos (0U)
  793. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  794. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
  795. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  796. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  797. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  798. #define ADC_SMPR1_SMP11_Pos (3U)
  799. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  800. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
  801. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  802. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  803. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  804. #define ADC_SMPR1_SMP12_Pos (6U)
  805. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  806. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
  807. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  808. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  809. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  810. #define ADC_SMPR1_SMP13_Pos (9U)
  811. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  812. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
  813. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  814. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  815. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  816. #define ADC_SMPR1_SMP14_Pos (12U)
  817. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  818. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
  819. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  820. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  821. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  822. #define ADC_SMPR1_SMP15_Pos (15U)
  823. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  824. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
  825. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  826. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  827. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  828. #define ADC_SMPR1_SMP16_Pos (18U)
  829. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  830. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
  831. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  832. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  833. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  834. #define ADC_SMPR1_SMP17_Pos (21U)
  835. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  836. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
  837. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  838. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  839. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  840. #define ADC_SMPR1_SMP18_Pos (24U)
  841. #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
  842. #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
  843. #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
  844. #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
  845. #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
  846. /****************** Bit definition for ADC_SMPR2 register *******************/
  847. #define ADC_SMPR2_SMP0_Pos (0U)
  848. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  849. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
  850. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  851. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  852. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  853. #define ADC_SMPR2_SMP1_Pos (3U)
  854. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  855. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
  856. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  857. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  858. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  859. #define ADC_SMPR2_SMP2_Pos (6U)
  860. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  861. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
  862. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  863. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  864. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  865. #define ADC_SMPR2_SMP3_Pos (9U)
  866. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  867. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
  868. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  869. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  870. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  871. #define ADC_SMPR2_SMP4_Pos (12U)
  872. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  873. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
  874. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  875. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  876. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  877. #define ADC_SMPR2_SMP5_Pos (15U)
  878. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  879. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
  880. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  881. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  882. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  883. #define ADC_SMPR2_SMP6_Pos (18U)
  884. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  885. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
  886. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  887. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  888. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  889. #define ADC_SMPR2_SMP7_Pos (21U)
  890. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  891. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
  892. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  893. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  894. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  895. #define ADC_SMPR2_SMP8_Pos (24U)
  896. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  897. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
  898. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  899. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  900. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  901. #define ADC_SMPR2_SMP9_Pos (27U)
  902. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  903. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
  904. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  905. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  906. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  907. /****************** Bit definition for ADC_JOFR1 register *******************/
  908. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  909. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  910. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
  911. /****************** Bit definition for ADC_JOFR2 register *******************/
  912. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  913. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  914. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
  915. /****************** Bit definition for ADC_JOFR3 register *******************/
  916. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  917. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  918. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
  919. /****************** Bit definition for ADC_JOFR4 register *******************/
  920. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  921. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  922. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
  923. /******************* Bit definition for ADC_HTR register ********************/
  924. #define ADC_HTR_HT_Pos (0U)
  925. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  926. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
  927. /******************* Bit definition for ADC_LTR register ********************/
  928. #define ADC_LTR_LT_Pos (0U)
  929. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  930. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
  931. /******************* Bit definition for ADC_SQR1 register *******************/
  932. #define ADC_SQR1_SQ13_Pos (0U)
  933. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  934. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
  935. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  936. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  937. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  938. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  939. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  940. #define ADC_SQR1_SQ14_Pos (5U)
  941. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  942. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
  943. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  944. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  945. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  946. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  947. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  948. #define ADC_SQR1_SQ15_Pos (10U)
  949. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  950. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
  951. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  952. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  953. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  954. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  955. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  956. #define ADC_SQR1_SQ16_Pos (15U)
  957. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  958. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
  959. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  960. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  961. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  962. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  963. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  964. #define ADC_SQR1_L_Pos (20U)
  965. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  966. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
  967. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  968. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  969. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  970. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  971. /******************* Bit definition for ADC_SQR2 register *******************/
  972. #define ADC_SQR2_SQ7_Pos (0U)
  973. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  974. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
  975. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  976. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  977. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  978. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  979. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  980. #define ADC_SQR2_SQ8_Pos (5U)
  981. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  982. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
  983. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  984. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  985. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  986. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  987. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  988. #define ADC_SQR2_SQ9_Pos (10U)
  989. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  990. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
  991. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  992. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  993. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  994. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  995. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  996. #define ADC_SQR2_SQ10_Pos (15U)
  997. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  998. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
  999. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  1000. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  1001. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  1002. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  1003. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  1004. #define ADC_SQR2_SQ11_Pos (20U)
  1005. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  1006. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
  1007. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  1008. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  1009. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  1010. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  1011. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  1012. #define ADC_SQR2_SQ12_Pos (25U)
  1013. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  1014. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
  1015. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  1016. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  1017. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  1018. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  1019. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  1020. /******************* Bit definition for ADC_SQR3 register *******************/
  1021. #define ADC_SQR3_SQ1_Pos (0U)
  1022. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  1023. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
  1024. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  1025. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  1026. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  1027. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  1028. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  1029. #define ADC_SQR3_SQ2_Pos (5U)
  1030. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  1031. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
  1032. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  1033. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  1034. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  1035. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  1036. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  1037. #define ADC_SQR3_SQ3_Pos (10U)
  1038. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  1039. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
  1040. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  1041. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  1042. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  1043. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  1044. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  1045. #define ADC_SQR3_SQ4_Pos (15U)
  1046. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  1047. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
  1048. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  1049. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  1050. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  1051. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  1052. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  1053. #define ADC_SQR3_SQ5_Pos (20U)
  1054. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  1055. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
  1056. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  1057. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  1058. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  1059. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  1060. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  1061. #define ADC_SQR3_SQ6_Pos (25U)
  1062. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  1063. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
  1064. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  1065. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  1066. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  1067. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  1068. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  1069. /******************* Bit definition for ADC_JSQR register *******************/
  1070. #define ADC_JSQR_JSQ1_Pos (0U)
  1071. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  1072. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
  1073. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  1074. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  1075. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  1076. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  1077. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  1078. #define ADC_JSQR_JSQ2_Pos (5U)
  1079. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  1080. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1081. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  1082. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  1083. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  1084. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  1085. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  1086. #define ADC_JSQR_JSQ3_Pos (10U)
  1087. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  1088. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1089. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  1090. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  1091. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  1092. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  1093. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  1094. #define ADC_JSQR_JSQ4_Pos (15U)
  1095. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  1096. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
  1097. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  1098. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  1099. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  1100. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  1101. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  1102. #define ADC_JSQR_JL_Pos (20U)
  1103. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  1104. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
  1105. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  1106. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  1107. /******************* Bit definition for ADC_JDR1 register *******************/
  1108. #define ADC_JDR1_JDATA_Pos (0U)
  1109. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1110. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
  1111. /******************* Bit definition for ADC_JDR2 register *******************/
  1112. #define ADC_JDR2_JDATA_Pos (0U)
  1113. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1114. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
  1115. /******************* Bit definition for ADC_JDR3 register *******************/
  1116. #define ADC_JDR3_JDATA_Pos (0U)
  1117. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1118. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
  1119. /******************* Bit definition for ADC_JDR4 register *******************/
  1120. #define ADC_JDR4_JDATA_Pos (0U)
  1121. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1122. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
  1123. /******************** Bit definition for ADC_DR register ********************/
  1124. #define ADC_DR_DATA_Pos (0U)
  1125. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1126. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
  1127. #define ADC_DR_ADC2DATA_Pos (16U)
  1128. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  1129. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
  1130. /******************* Bit definition for ADC_CSR register ********************/
  1131. #define ADC_CSR_AWD1_Pos (0U)
  1132. #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
  1133. #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
  1134. #define ADC_CSR_EOC1_Pos (1U)
  1135. #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
  1136. #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
  1137. #define ADC_CSR_JEOC1_Pos (2U)
  1138. #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
  1139. #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
  1140. #define ADC_CSR_JSTRT1_Pos (3U)
  1141. #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
  1142. #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
  1143. #define ADC_CSR_STRT1_Pos (4U)
  1144. #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
  1145. #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
  1146. #define ADC_CSR_OVR1_Pos (5U)
  1147. #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
  1148. #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
  1149. /* Legacy defines */
  1150. #define ADC_CSR_DOVR1 ADC_CSR_OVR1
  1151. /******************* Bit definition for ADC_CCR register ********************/
  1152. #define ADC_CCR_MULTI_Pos (0U)
  1153. #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
  1154. #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
  1155. #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
  1156. #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
  1157. #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
  1158. #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
  1159. #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
  1160. #define ADC_CCR_DELAY_Pos (8U)
  1161. #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
  1162. #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
  1163. #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
  1164. #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
  1165. #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
  1166. #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
  1167. #define ADC_CCR_DDS_Pos (13U)
  1168. #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
  1169. #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
  1170. #define ADC_CCR_DMA_Pos (14U)
  1171. #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
  1172. #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
  1173. #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
  1174. #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
  1175. #define ADC_CCR_ADCPRE_Pos (16U)
  1176. #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
  1177. #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
  1178. #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
  1179. #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
  1180. #define ADC_CCR_VBATE_Pos (22U)
  1181. #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
  1182. #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
  1183. #define ADC_CCR_TSVREFE_Pos (23U)
  1184. #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
  1185. #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
  1186. /******************* Bit definition for ADC_CDR register ********************/
  1187. #define ADC_CDR_DATA1_Pos (0U)
  1188. #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
  1189. #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
  1190. #define ADC_CDR_DATA2_Pos (16U)
  1191. #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
  1192. #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
  1193. /* Legacy defines */
  1194. #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
  1195. #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
  1196. /******************************************************************************/
  1197. /* */
  1198. /* CRC calculation unit */
  1199. /* */
  1200. /******************************************************************************/
  1201. /******************* Bit definition for CRC_DR register *********************/
  1202. #define CRC_DR_DR_Pos (0U)
  1203. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  1204. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  1205. /******************* Bit definition for CRC_IDR register ********************/
  1206. #define CRC_IDR_IDR_Pos (0U)
  1207. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  1208. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  1209. /******************** Bit definition for CRC_CR register ********************/
  1210. #define CRC_CR_RESET_Pos (0U)
  1211. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  1212. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  1213. /******************************************************************************/
  1214. /* */
  1215. /* Digital to Analog Converter */
  1216. /* */
  1217. /******************************************************************************/
  1218. /******************** Bit definition for DAC_CR register ********************/
  1219. #define DAC_CR_EN1_Pos (0U)
  1220. #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
  1221. #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
  1222. #define DAC_CR_BOFF1_Pos (1U)
  1223. #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
  1224. #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
  1225. #define DAC_CR_TEN1_Pos (2U)
  1226. #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
  1227. #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
  1228. #define DAC_CR_TSEL1_Pos (3U)
  1229. #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
  1230. #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
  1231. #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
  1232. #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
  1233. #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
  1234. #define DAC_CR_WAVE1_Pos (6U)
  1235. #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
  1236. #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  1237. #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
  1238. #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
  1239. #define DAC_CR_MAMP1_Pos (8U)
  1240. #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
  1241. #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  1242. #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
  1243. #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
  1244. #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
  1245. #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
  1246. #define DAC_CR_DMAEN1_Pos (12U)
  1247. #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
  1248. #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
  1249. #define DAC_CR_DMAUDRIE1_Pos (13U)
  1250. #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
  1251. #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
  1252. #define DAC_CR_EN2_Pos (16U)
  1253. #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
  1254. #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
  1255. #define DAC_CR_BOFF2_Pos (17U)
  1256. #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
  1257. #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
  1258. #define DAC_CR_TEN2_Pos (18U)
  1259. #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
  1260. #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
  1261. #define DAC_CR_TSEL2_Pos (19U)
  1262. #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
  1263. #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
  1264. #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
  1265. #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
  1266. #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
  1267. #define DAC_CR_WAVE2_Pos (22U)
  1268. #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
  1269. #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  1270. #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
  1271. #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
  1272. #define DAC_CR_MAMP2_Pos (24U)
  1273. #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
  1274. #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  1275. #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
  1276. #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
  1277. #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
  1278. #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
  1279. #define DAC_CR_DMAEN2_Pos (28U)
  1280. #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
  1281. #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
  1282. #define DAC_CR_DMAUDRIE2_Pos (29U)
  1283. #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
  1284. #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
  1285. /***************** Bit definition for DAC_SWTRIGR register ******************/
  1286. #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
  1287. #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
  1288. #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
  1289. #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
  1290. #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
  1291. #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
  1292. /***************** Bit definition for DAC_DHR12R1 register ******************/
  1293. #define DAC_DHR12R1_DACC1DHR_Pos (0U)
  1294. #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
  1295. #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  1296. /***************** Bit definition for DAC_DHR12L1 register ******************/
  1297. #define DAC_DHR12L1_DACC1DHR_Pos (4U)
  1298. #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  1299. #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  1300. /****************** Bit definition for DAC_DHR8R1 register ******************/
  1301. #define DAC_DHR8R1_DACC1DHR_Pos (0U)
  1302. #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
  1303. #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  1304. /***************** Bit definition for DAC_DHR12R2 register ******************/
  1305. #define DAC_DHR12R2_DACC2DHR_Pos (0U)
  1306. #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
  1307. #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  1308. /***************** Bit definition for DAC_DHR12L2 register ******************/
  1309. #define DAC_DHR12L2_DACC2DHR_Pos (4U)
  1310. #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
  1311. #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  1312. /****************** Bit definition for DAC_DHR8R2 register ******************/
  1313. #define DAC_DHR8R2_DACC2DHR_Pos (0U)
  1314. #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
  1315. #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  1316. /***************** Bit definition for DAC_DHR12RD register ******************/
  1317. #define DAC_DHR12RD_DACC1DHR_Pos (0U)
  1318. #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
  1319. #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
  1320. #define DAC_DHR12RD_DACC2DHR_Pos (16U)
  1321. #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
  1322. #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
  1323. /***************** Bit definition for DAC_DHR12LD register ******************/
  1324. #define DAC_DHR12LD_DACC1DHR_Pos (4U)
  1325. #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
  1326. #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
  1327. #define DAC_DHR12LD_DACC2DHR_Pos (20U)
  1328. #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
  1329. #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
  1330. /****************** Bit definition for DAC_DHR8RD register ******************/
  1331. #define DAC_DHR8RD_DACC1DHR_Pos (0U)
  1332. #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
  1333. #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
  1334. #define DAC_DHR8RD_DACC2DHR_Pos (8U)
  1335. #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
  1336. #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
  1337. /******************* Bit definition for DAC_DOR1 register *******************/
  1338. #define DAC_DOR1_DACC1DOR_Pos (0U)
  1339. #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
  1340. #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
  1341. /******************* Bit definition for DAC_DOR2 register *******************/
  1342. #define DAC_DOR2_DACC2DOR_Pos (0U)
  1343. #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
  1344. #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
  1345. /******************** Bit definition for DAC_SR register ********************/
  1346. #define DAC_SR_DMAUDR1_Pos (13U)
  1347. #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
  1348. #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
  1349. #define DAC_SR_DMAUDR2_Pos (29U)
  1350. #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
  1351. #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
  1352. /******************************************************************************/
  1353. /* */
  1354. /* DMA Controller */
  1355. /* */
  1356. /******************************************************************************/
  1357. /******************** Bits definition for DMA_SxCR register *****************/
  1358. #define DMA_SxCR_CHSEL_Pos (25U)
  1359. #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
  1360. #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
  1361. #define DMA_SxCR_CHSEL_0 0x02000000U
  1362. #define DMA_SxCR_CHSEL_1 0x04000000U
  1363. #define DMA_SxCR_CHSEL_2 0x08000000U
  1364. #define DMA_SxCR_MBURST_Pos (23U)
  1365. #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
  1366. #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
  1367. #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
  1368. #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
  1369. #define DMA_SxCR_PBURST_Pos (21U)
  1370. #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
  1371. #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
  1372. #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
  1373. #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
  1374. #define DMA_SxCR_CT_Pos (19U)
  1375. #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
  1376. #define DMA_SxCR_CT DMA_SxCR_CT_Msk
  1377. #define DMA_SxCR_DBM_Pos (18U)
  1378. #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
  1379. #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
  1380. #define DMA_SxCR_PL_Pos (16U)
  1381. #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
  1382. #define DMA_SxCR_PL DMA_SxCR_PL_Msk
  1383. #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
  1384. #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
  1385. #define DMA_SxCR_PINCOS_Pos (15U)
  1386. #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
  1387. #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
  1388. #define DMA_SxCR_MSIZE_Pos (13U)
  1389. #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
  1390. #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
  1391. #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
  1392. #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
  1393. #define DMA_SxCR_PSIZE_Pos (11U)
  1394. #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
  1395. #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
  1396. #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
  1397. #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
  1398. #define DMA_SxCR_MINC_Pos (10U)
  1399. #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
  1400. #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
  1401. #define DMA_SxCR_PINC_Pos (9U)
  1402. #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
  1403. #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
  1404. #define DMA_SxCR_CIRC_Pos (8U)
  1405. #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
  1406. #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
  1407. #define DMA_SxCR_DIR_Pos (6U)
  1408. #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
  1409. #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
  1410. #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
  1411. #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
  1412. #define DMA_SxCR_PFCTRL_Pos (5U)
  1413. #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
  1414. #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
  1415. #define DMA_SxCR_TCIE_Pos (4U)
  1416. #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
  1417. #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
  1418. #define DMA_SxCR_HTIE_Pos (3U)
  1419. #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
  1420. #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
  1421. #define DMA_SxCR_TEIE_Pos (2U)
  1422. #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
  1423. #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
  1424. #define DMA_SxCR_DMEIE_Pos (1U)
  1425. #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
  1426. #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
  1427. #define DMA_SxCR_EN_Pos (0U)
  1428. #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
  1429. #define DMA_SxCR_EN DMA_SxCR_EN_Msk
  1430. /* Legacy defines */
  1431. #define DMA_SxCR_ACK_Pos (20U)
  1432. #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
  1433. #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
  1434. /******************** Bits definition for DMA_SxCNDTR register **************/
  1435. #define DMA_SxNDT_Pos (0U)
  1436. #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
  1437. #define DMA_SxNDT DMA_SxNDT_Msk
  1438. #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
  1439. #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
  1440. #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
  1441. #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
  1442. #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
  1443. #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
  1444. #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
  1445. #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
  1446. #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
  1447. #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
  1448. #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
  1449. #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
  1450. #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
  1451. #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
  1452. #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
  1453. #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
  1454. /******************** Bits definition for DMA_SxFCR register ****************/
  1455. #define DMA_SxFCR_FEIE_Pos (7U)
  1456. #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
  1457. #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
  1458. #define DMA_SxFCR_FS_Pos (3U)
  1459. #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
  1460. #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
  1461. #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
  1462. #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
  1463. #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
  1464. #define DMA_SxFCR_DMDIS_Pos (2U)
  1465. #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
  1466. #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
  1467. #define DMA_SxFCR_FTH_Pos (0U)
  1468. #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
  1469. #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
  1470. #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
  1471. #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
  1472. /******************** Bits definition for DMA_LISR register *****************/
  1473. #define DMA_LISR_TCIF3_Pos (27U)
  1474. #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
  1475. #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
  1476. #define DMA_LISR_HTIF3_Pos (26U)
  1477. #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
  1478. #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
  1479. #define DMA_LISR_TEIF3_Pos (25U)
  1480. #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
  1481. #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
  1482. #define DMA_LISR_DMEIF3_Pos (24U)
  1483. #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
  1484. #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
  1485. #define DMA_LISR_FEIF3_Pos (22U)
  1486. #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
  1487. #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
  1488. #define DMA_LISR_TCIF2_Pos (21U)
  1489. #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
  1490. #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
  1491. #define DMA_LISR_HTIF2_Pos (20U)
  1492. #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
  1493. #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
  1494. #define DMA_LISR_TEIF2_Pos (19U)
  1495. #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
  1496. #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
  1497. #define DMA_LISR_DMEIF2_Pos (18U)
  1498. #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
  1499. #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
  1500. #define DMA_LISR_FEIF2_Pos (16U)
  1501. #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
  1502. #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
  1503. #define DMA_LISR_TCIF1_Pos (11U)
  1504. #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
  1505. #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
  1506. #define DMA_LISR_HTIF1_Pos (10U)
  1507. #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
  1508. #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
  1509. #define DMA_LISR_TEIF1_Pos (9U)
  1510. #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
  1511. #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
  1512. #define DMA_LISR_DMEIF1_Pos (8U)
  1513. #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
  1514. #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
  1515. #define DMA_LISR_FEIF1_Pos (6U)
  1516. #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
  1517. #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
  1518. #define DMA_LISR_TCIF0_Pos (5U)
  1519. #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
  1520. #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
  1521. #define DMA_LISR_HTIF0_Pos (4U)
  1522. #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
  1523. #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
  1524. #define DMA_LISR_TEIF0_Pos (3U)
  1525. #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
  1526. #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
  1527. #define DMA_LISR_DMEIF0_Pos (2U)
  1528. #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
  1529. #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
  1530. #define DMA_LISR_FEIF0_Pos (0U)
  1531. #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
  1532. #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
  1533. /******************** Bits definition for DMA_HISR register *****************/
  1534. #define DMA_HISR_TCIF7_Pos (27U)
  1535. #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
  1536. #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
  1537. #define DMA_HISR_HTIF7_Pos (26U)
  1538. #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
  1539. #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
  1540. #define DMA_HISR_TEIF7_Pos (25U)
  1541. #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
  1542. #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
  1543. #define DMA_HISR_DMEIF7_Pos (24U)
  1544. #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
  1545. #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
  1546. #define DMA_HISR_FEIF7_Pos (22U)
  1547. #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
  1548. #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
  1549. #define DMA_HISR_TCIF6_Pos (21U)
  1550. #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
  1551. #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
  1552. #define DMA_HISR_HTIF6_Pos (20U)
  1553. #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
  1554. #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
  1555. #define DMA_HISR_TEIF6_Pos (19U)
  1556. #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
  1557. #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
  1558. #define DMA_HISR_DMEIF6_Pos (18U)
  1559. #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
  1560. #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
  1561. #define DMA_HISR_FEIF6_Pos (16U)
  1562. #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
  1563. #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
  1564. #define DMA_HISR_TCIF5_Pos (11U)
  1565. #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
  1566. #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
  1567. #define DMA_HISR_HTIF5_Pos (10U)
  1568. #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
  1569. #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
  1570. #define DMA_HISR_TEIF5_Pos (9U)
  1571. #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
  1572. #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
  1573. #define DMA_HISR_DMEIF5_Pos (8U)
  1574. #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
  1575. #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
  1576. #define DMA_HISR_FEIF5_Pos (6U)
  1577. #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
  1578. #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
  1579. #define DMA_HISR_TCIF4_Pos (5U)
  1580. #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
  1581. #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
  1582. #define DMA_HISR_HTIF4_Pos (4U)
  1583. #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
  1584. #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
  1585. #define DMA_HISR_TEIF4_Pos (3U)
  1586. #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
  1587. #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
  1588. #define DMA_HISR_DMEIF4_Pos (2U)
  1589. #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
  1590. #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
  1591. #define DMA_HISR_FEIF4_Pos (0U)
  1592. #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
  1593. #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
  1594. /******************** Bits definition for DMA_LIFCR register ****************/
  1595. #define DMA_LIFCR_CTCIF3_Pos (27U)
  1596. #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
  1597. #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
  1598. #define DMA_LIFCR_CHTIF3_Pos (26U)
  1599. #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
  1600. #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
  1601. #define DMA_LIFCR_CTEIF3_Pos (25U)
  1602. #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
  1603. #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
  1604. #define DMA_LIFCR_CDMEIF3_Pos (24U)
  1605. #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
  1606. #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
  1607. #define DMA_LIFCR_CFEIF3_Pos (22U)
  1608. #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
  1609. #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
  1610. #define DMA_LIFCR_CTCIF2_Pos (21U)
  1611. #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
  1612. #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
  1613. #define DMA_LIFCR_CHTIF2_Pos (20U)
  1614. #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
  1615. #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
  1616. #define DMA_LIFCR_CTEIF2_Pos (19U)
  1617. #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
  1618. #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
  1619. #define DMA_LIFCR_CDMEIF2_Pos (18U)
  1620. #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
  1621. #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
  1622. #define DMA_LIFCR_CFEIF2_Pos (16U)
  1623. #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
  1624. #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
  1625. #define DMA_LIFCR_CTCIF1_Pos (11U)
  1626. #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
  1627. #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
  1628. #define DMA_LIFCR_CHTIF1_Pos (10U)
  1629. #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
  1630. #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
  1631. #define DMA_LIFCR_CTEIF1_Pos (9U)
  1632. #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
  1633. #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
  1634. #define DMA_LIFCR_CDMEIF1_Pos (8U)
  1635. #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
  1636. #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
  1637. #define DMA_LIFCR_CFEIF1_Pos (6U)
  1638. #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
  1639. #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
  1640. #define DMA_LIFCR_CTCIF0_Pos (5U)
  1641. #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
  1642. #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
  1643. #define DMA_LIFCR_CHTIF0_Pos (4U)
  1644. #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
  1645. #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
  1646. #define DMA_LIFCR_CTEIF0_Pos (3U)
  1647. #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
  1648. #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
  1649. #define DMA_LIFCR_CDMEIF0_Pos (2U)
  1650. #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
  1651. #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
  1652. #define DMA_LIFCR_CFEIF0_Pos (0U)
  1653. #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
  1654. #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
  1655. /******************** Bits definition for DMA_HIFCR register ****************/
  1656. #define DMA_HIFCR_CTCIF7_Pos (27U)
  1657. #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
  1658. #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
  1659. #define DMA_HIFCR_CHTIF7_Pos (26U)
  1660. #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
  1661. #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
  1662. #define DMA_HIFCR_CTEIF7_Pos (25U)
  1663. #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
  1664. #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
  1665. #define DMA_HIFCR_CDMEIF7_Pos (24U)
  1666. #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
  1667. #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
  1668. #define DMA_HIFCR_CFEIF7_Pos (22U)
  1669. #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
  1670. #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
  1671. #define DMA_HIFCR_CTCIF6_Pos (21U)
  1672. #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
  1673. #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
  1674. #define DMA_HIFCR_CHTIF6_Pos (20U)
  1675. #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
  1676. #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
  1677. #define DMA_HIFCR_CTEIF6_Pos (19U)
  1678. #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
  1679. #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
  1680. #define DMA_HIFCR_CDMEIF6_Pos (18U)
  1681. #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
  1682. #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
  1683. #define DMA_HIFCR_CFEIF6_Pos (16U)
  1684. #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
  1685. #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
  1686. #define DMA_HIFCR_CTCIF5_Pos (11U)
  1687. #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
  1688. #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
  1689. #define DMA_HIFCR_CHTIF5_Pos (10U)
  1690. #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
  1691. #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
  1692. #define DMA_HIFCR_CTEIF5_Pos (9U)
  1693. #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
  1694. #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
  1695. #define DMA_HIFCR_CDMEIF5_Pos (8U)
  1696. #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
  1697. #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
  1698. #define DMA_HIFCR_CFEIF5_Pos (6U)
  1699. #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
  1700. #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
  1701. #define DMA_HIFCR_CTCIF4_Pos (5U)
  1702. #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
  1703. #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
  1704. #define DMA_HIFCR_CHTIF4_Pos (4U)
  1705. #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
  1706. #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
  1707. #define DMA_HIFCR_CTEIF4_Pos (3U)
  1708. #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
  1709. #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
  1710. #define DMA_HIFCR_CDMEIF4_Pos (2U)
  1711. #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
  1712. #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
  1713. #define DMA_HIFCR_CFEIF4_Pos (0U)
  1714. #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
  1715. #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
  1716. /****************** Bit definition for DMA_SxPAR register ********************/
  1717. #define DMA_SxPAR_PA_Pos (0U)
  1718. #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
  1719. #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
  1720. /****************** Bit definition for DMA_SxM0AR register ********************/
  1721. #define DMA_SxM0AR_M0A_Pos (0U)
  1722. #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
  1723. #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
  1724. /****************** Bit definition for DMA_SxM1AR register ********************/
  1725. #define DMA_SxM1AR_M1A_Pos (0U)
  1726. #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
  1727. #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
  1728. /******************************************************************************/
  1729. /* */
  1730. /* External Interrupt/Event Controller */
  1731. /* */
  1732. /******************************************************************************/
  1733. /******************* Bit definition for EXTI_IMR register *******************/
  1734. #define EXTI_IMR_MR0_Pos (0U)
  1735. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  1736. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  1737. #define EXTI_IMR_MR1_Pos (1U)
  1738. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  1739. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  1740. #define EXTI_IMR_MR2_Pos (2U)
  1741. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  1742. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  1743. #define EXTI_IMR_MR3_Pos (3U)
  1744. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  1745. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  1746. #define EXTI_IMR_MR4_Pos (4U)
  1747. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  1748. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  1749. #define EXTI_IMR_MR5_Pos (5U)
  1750. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  1751. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  1752. #define EXTI_IMR_MR6_Pos (6U)
  1753. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  1754. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  1755. #define EXTI_IMR_MR7_Pos (7U)
  1756. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  1757. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  1758. #define EXTI_IMR_MR8_Pos (8U)
  1759. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  1760. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  1761. #define EXTI_IMR_MR9_Pos (9U)
  1762. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  1763. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  1764. #define EXTI_IMR_MR10_Pos (10U)
  1765. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  1766. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  1767. #define EXTI_IMR_MR11_Pos (11U)
  1768. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  1769. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  1770. #define EXTI_IMR_MR12_Pos (12U)
  1771. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  1772. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  1773. #define EXTI_IMR_MR13_Pos (13U)
  1774. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  1775. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  1776. #define EXTI_IMR_MR14_Pos (14U)
  1777. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  1778. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  1779. #define EXTI_IMR_MR15_Pos (15U)
  1780. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  1781. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  1782. #define EXTI_IMR_MR16_Pos (16U)
  1783. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  1784. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  1785. #define EXTI_IMR_MR17_Pos (17U)
  1786. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  1787. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  1788. #define EXTI_IMR_MR18_Pos (18U)
  1789. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  1790. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  1791. #define EXTI_IMR_MR19_Pos (19U)
  1792. #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  1793. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  1794. #define EXTI_IMR_MR20_Pos (20U)
  1795. #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
  1796. #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
  1797. #define EXTI_IMR_MR21_Pos (21U)
  1798. #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
  1799. #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
  1800. #define EXTI_IMR_MR22_Pos (22U)
  1801. #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
  1802. #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
  1803. #define EXTI_IMR_MR23_Pos (23U)
  1804. #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
  1805. #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
  1806. /* Reference Defines */
  1807. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  1808. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  1809. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  1810. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  1811. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  1812. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  1813. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  1814. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  1815. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  1816. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  1817. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  1818. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  1819. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  1820. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  1821. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  1822. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  1823. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  1824. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  1825. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  1826. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  1827. #define EXTI_IMR_IM20 EXTI_IMR_MR20
  1828. #define EXTI_IMR_IM21 EXTI_IMR_MR21
  1829. #define EXTI_IMR_IM22 EXTI_IMR_MR22
  1830. #define EXTI_IMR_IM23 EXTI_IMR_MR23
  1831. #define EXTI_IMR_IM_Pos (0U)
  1832. #define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
  1833. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  1834. /******************* Bit definition for EXTI_EMR register *******************/
  1835. #define EXTI_EMR_MR0_Pos (0U)
  1836. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  1837. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  1838. #define EXTI_EMR_MR1_Pos (1U)
  1839. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  1840. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  1841. #define EXTI_EMR_MR2_Pos (2U)
  1842. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  1843. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  1844. #define EXTI_EMR_MR3_Pos (3U)
  1845. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  1846. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  1847. #define EXTI_EMR_MR4_Pos (4U)
  1848. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  1849. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  1850. #define EXTI_EMR_MR5_Pos (5U)
  1851. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  1852. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  1853. #define EXTI_EMR_MR6_Pos (6U)
  1854. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  1855. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  1856. #define EXTI_EMR_MR7_Pos (7U)
  1857. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  1858. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  1859. #define EXTI_EMR_MR8_Pos (8U)
  1860. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  1861. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  1862. #define EXTI_EMR_MR9_Pos (9U)
  1863. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  1864. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  1865. #define EXTI_EMR_MR10_Pos (10U)
  1866. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  1867. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  1868. #define EXTI_EMR_MR11_Pos (11U)
  1869. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  1870. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  1871. #define EXTI_EMR_MR12_Pos (12U)
  1872. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  1873. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  1874. #define EXTI_EMR_MR13_Pos (13U)
  1875. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  1876. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  1877. #define EXTI_EMR_MR14_Pos (14U)
  1878. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  1879. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  1880. #define EXTI_EMR_MR15_Pos (15U)
  1881. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  1882. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  1883. #define EXTI_EMR_MR16_Pos (16U)
  1884. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  1885. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  1886. #define EXTI_EMR_MR17_Pos (17U)
  1887. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  1888. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  1889. #define EXTI_EMR_MR18_Pos (18U)
  1890. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  1891. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  1892. #define EXTI_EMR_MR19_Pos (19U)
  1893. #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  1894. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  1895. #define EXTI_EMR_MR20_Pos (20U)
  1896. #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
  1897. #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
  1898. #define EXTI_EMR_MR21_Pos (21U)
  1899. #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
  1900. #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
  1901. #define EXTI_EMR_MR22_Pos (22U)
  1902. #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
  1903. #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
  1904. #define EXTI_EMR_MR23_Pos (23U)
  1905. #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
  1906. #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
  1907. /* Reference Defines */
  1908. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  1909. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  1910. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  1911. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  1912. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  1913. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  1914. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  1915. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  1916. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  1917. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  1918. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  1919. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  1920. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  1921. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  1922. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  1923. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  1924. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  1925. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  1926. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  1927. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  1928. #define EXTI_EMR_EM20 EXTI_EMR_MR20
  1929. #define EXTI_EMR_EM21 EXTI_EMR_MR21
  1930. #define EXTI_EMR_EM22 EXTI_EMR_MR22
  1931. #define EXTI_EMR_EM23 EXTI_EMR_MR23
  1932. /****************** Bit definition for EXTI_RTSR register *******************/
  1933. #define EXTI_RTSR_TR0_Pos (0U)
  1934. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  1935. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  1936. #define EXTI_RTSR_TR1_Pos (1U)
  1937. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  1938. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  1939. #define EXTI_RTSR_TR2_Pos (2U)
  1940. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  1941. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  1942. #define EXTI_RTSR_TR3_Pos (3U)
  1943. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  1944. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  1945. #define EXTI_RTSR_TR4_Pos (4U)
  1946. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  1947. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  1948. #define EXTI_RTSR_TR5_Pos (5U)
  1949. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  1950. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  1951. #define EXTI_RTSR_TR6_Pos (6U)
  1952. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  1953. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  1954. #define EXTI_RTSR_TR7_Pos (7U)
  1955. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  1956. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  1957. #define EXTI_RTSR_TR8_Pos (8U)
  1958. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  1959. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  1960. #define EXTI_RTSR_TR9_Pos (9U)
  1961. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  1962. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  1963. #define EXTI_RTSR_TR10_Pos (10U)
  1964. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  1965. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  1966. #define EXTI_RTSR_TR11_Pos (11U)
  1967. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  1968. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  1969. #define EXTI_RTSR_TR12_Pos (12U)
  1970. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  1971. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  1972. #define EXTI_RTSR_TR13_Pos (13U)
  1973. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  1974. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  1975. #define EXTI_RTSR_TR14_Pos (14U)
  1976. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  1977. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  1978. #define EXTI_RTSR_TR15_Pos (15U)
  1979. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  1980. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  1981. #define EXTI_RTSR_TR16_Pos (16U)
  1982. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  1983. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  1984. #define EXTI_RTSR_TR17_Pos (17U)
  1985. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  1986. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  1987. #define EXTI_RTSR_TR18_Pos (18U)
  1988. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  1989. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  1990. #define EXTI_RTSR_TR19_Pos (19U)
  1991. #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  1992. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  1993. #define EXTI_RTSR_TR20_Pos (20U)
  1994. #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
  1995. #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
  1996. #define EXTI_RTSR_TR21_Pos (21U)
  1997. #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
  1998. #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
  1999. #define EXTI_RTSR_TR22_Pos (22U)
  2000. #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
  2001. #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
  2002. #define EXTI_RTSR_TR23_Pos (23U)
  2003. #define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
  2004. #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
  2005. /****************** Bit definition for EXTI_FTSR register *******************/
  2006. #define EXTI_FTSR_TR0_Pos (0U)
  2007. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  2008. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  2009. #define EXTI_FTSR_TR1_Pos (1U)
  2010. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  2011. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  2012. #define EXTI_FTSR_TR2_Pos (2U)
  2013. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  2014. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  2015. #define EXTI_FTSR_TR3_Pos (3U)
  2016. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  2017. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  2018. #define EXTI_FTSR_TR4_Pos (4U)
  2019. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  2020. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  2021. #define EXTI_FTSR_TR5_Pos (5U)
  2022. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  2023. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  2024. #define EXTI_FTSR_TR6_Pos (6U)
  2025. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  2026. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  2027. #define EXTI_FTSR_TR7_Pos (7U)
  2028. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  2029. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  2030. #define EXTI_FTSR_TR8_Pos (8U)
  2031. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  2032. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  2033. #define EXTI_FTSR_TR9_Pos (9U)
  2034. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  2035. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  2036. #define EXTI_FTSR_TR10_Pos (10U)
  2037. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  2038. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  2039. #define EXTI_FTSR_TR11_Pos (11U)
  2040. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  2041. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  2042. #define EXTI_FTSR_TR12_Pos (12U)
  2043. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  2044. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  2045. #define EXTI_FTSR_TR13_Pos (13U)
  2046. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  2047. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  2048. #define EXTI_FTSR_TR14_Pos (14U)
  2049. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  2050. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  2051. #define EXTI_FTSR_TR15_Pos (15U)
  2052. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  2053. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  2054. #define EXTI_FTSR_TR16_Pos (16U)
  2055. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  2056. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  2057. #define EXTI_FTSR_TR17_Pos (17U)
  2058. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  2059. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  2060. #define EXTI_FTSR_TR18_Pos (18U)
  2061. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  2062. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  2063. #define EXTI_FTSR_TR19_Pos (19U)
  2064. #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  2065. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  2066. #define EXTI_FTSR_TR20_Pos (20U)
  2067. #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
  2068. #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
  2069. #define EXTI_FTSR_TR21_Pos (21U)
  2070. #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
  2071. #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
  2072. #define EXTI_FTSR_TR22_Pos (22U)
  2073. #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
  2074. #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
  2075. #define EXTI_FTSR_TR23_Pos (23U)
  2076. #define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
  2077. #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
  2078. /****************** Bit definition for EXTI_SWIER register ******************/
  2079. #define EXTI_SWIER_SWIER0_Pos (0U)
  2080. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  2081. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  2082. #define EXTI_SWIER_SWIER1_Pos (1U)
  2083. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  2084. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  2085. #define EXTI_SWIER_SWIER2_Pos (2U)
  2086. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  2087. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  2088. #define EXTI_SWIER_SWIER3_Pos (3U)
  2089. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  2090. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  2091. #define EXTI_SWIER_SWIER4_Pos (4U)
  2092. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  2093. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  2094. #define EXTI_SWIER_SWIER5_Pos (5U)
  2095. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  2096. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  2097. #define EXTI_SWIER_SWIER6_Pos (6U)
  2098. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  2099. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  2100. #define EXTI_SWIER_SWIER7_Pos (7U)
  2101. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  2102. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  2103. #define EXTI_SWIER_SWIER8_Pos (8U)
  2104. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  2105. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  2106. #define EXTI_SWIER_SWIER9_Pos (9U)
  2107. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  2108. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  2109. #define EXTI_SWIER_SWIER10_Pos (10U)
  2110. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  2111. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  2112. #define EXTI_SWIER_SWIER11_Pos (11U)
  2113. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  2114. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  2115. #define EXTI_SWIER_SWIER12_Pos (12U)
  2116. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  2117. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  2118. #define EXTI_SWIER_SWIER13_Pos (13U)
  2119. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  2120. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  2121. #define EXTI_SWIER_SWIER14_Pos (14U)
  2122. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  2123. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  2124. #define EXTI_SWIER_SWIER15_Pos (15U)
  2125. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  2126. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  2127. #define EXTI_SWIER_SWIER16_Pos (16U)
  2128. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  2129. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  2130. #define EXTI_SWIER_SWIER17_Pos (17U)
  2131. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  2132. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  2133. #define EXTI_SWIER_SWIER18_Pos (18U)
  2134. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  2135. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  2136. #define EXTI_SWIER_SWIER19_Pos (19U)
  2137. #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  2138. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  2139. #define EXTI_SWIER_SWIER20_Pos (20U)
  2140. #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
  2141. #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
  2142. #define EXTI_SWIER_SWIER21_Pos (21U)
  2143. #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
  2144. #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
  2145. #define EXTI_SWIER_SWIER22_Pos (22U)
  2146. #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
  2147. #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
  2148. #define EXTI_SWIER_SWIER23_Pos (23U)
  2149. #define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
  2150. #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
  2151. /******************* Bit definition for EXTI_PR register ********************/
  2152. #define EXTI_PR_PR0_Pos (0U)
  2153. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  2154. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  2155. #define EXTI_PR_PR1_Pos (1U)
  2156. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  2157. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  2158. #define EXTI_PR_PR2_Pos (2U)
  2159. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  2160. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  2161. #define EXTI_PR_PR3_Pos (3U)
  2162. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  2163. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  2164. #define EXTI_PR_PR4_Pos (4U)
  2165. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  2166. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  2167. #define EXTI_PR_PR5_Pos (5U)
  2168. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  2169. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  2170. #define EXTI_PR_PR6_Pos (6U)
  2171. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  2172. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  2173. #define EXTI_PR_PR7_Pos (7U)
  2174. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  2175. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  2176. #define EXTI_PR_PR8_Pos (8U)
  2177. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  2178. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  2179. #define EXTI_PR_PR9_Pos (9U)
  2180. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  2181. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  2182. #define EXTI_PR_PR10_Pos (10U)
  2183. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  2184. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  2185. #define EXTI_PR_PR11_Pos (11U)
  2186. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  2187. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  2188. #define EXTI_PR_PR12_Pos (12U)
  2189. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  2190. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  2191. #define EXTI_PR_PR13_Pos (13U)
  2192. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  2193. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  2194. #define EXTI_PR_PR14_Pos (14U)
  2195. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  2196. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  2197. #define EXTI_PR_PR15_Pos (15U)
  2198. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  2199. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  2200. #define EXTI_PR_PR16_Pos (16U)
  2201. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  2202. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  2203. #define EXTI_PR_PR17_Pos (17U)
  2204. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  2205. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  2206. #define EXTI_PR_PR18_Pos (18U)
  2207. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  2208. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  2209. #define EXTI_PR_PR19_Pos (19U)
  2210. #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  2211. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
  2212. #define EXTI_PR_PR20_Pos (20U)
  2213. #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
  2214. #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
  2215. #define EXTI_PR_PR21_Pos (21U)
  2216. #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
  2217. #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
  2218. #define EXTI_PR_PR22_Pos (22U)
  2219. #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
  2220. #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
  2221. #define EXTI_PR_PR23_Pos (23U)
  2222. #define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
  2223. #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
  2224. /******************************************************************************/
  2225. /* */
  2226. /* FLASH */
  2227. /* */
  2228. /******************************************************************************/
  2229. /******************* Bits definition for FLASH_ACR register *****************/
  2230. #define FLASH_ACR_LATENCY_Pos (0U)
  2231. #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
  2232. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  2233. #define FLASH_ACR_LATENCY_0WS 0x00000000U
  2234. #define FLASH_ACR_LATENCY_1WS 0x00000001U
  2235. #define FLASH_ACR_LATENCY_2WS 0x00000002U
  2236. #define FLASH_ACR_LATENCY_3WS 0x00000003U
  2237. #define FLASH_ACR_LATENCY_4WS 0x00000004U
  2238. #define FLASH_ACR_LATENCY_5WS 0x00000005U
  2239. #define FLASH_ACR_LATENCY_6WS 0x00000006U
  2240. #define FLASH_ACR_LATENCY_7WS 0x00000007U
  2241. #define FLASH_ACR_PRFTEN_Pos (8U)
  2242. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  2243. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  2244. #define FLASH_ACR_ICEN_Pos (9U)
  2245. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  2246. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  2247. #define FLASH_ACR_DCEN_Pos (10U)
  2248. #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  2249. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  2250. #define FLASH_ACR_ICRST_Pos (11U)
  2251. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  2252. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  2253. #define FLASH_ACR_DCRST_Pos (12U)
  2254. #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  2255. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  2256. #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
  2257. #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
  2258. #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
  2259. #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
  2260. #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
  2261. #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
  2262. /******************* Bits definition for FLASH_SR register ******************/
  2263. #define FLASH_SR_EOP_Pos (0U)
  2264. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  2265. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  2266. #define FLASH_SR_SOP_Pos (1U)
  2267. #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
  2268. #define FLASH_SR_SOP FLASH_SR_SOP_Msk
  2269. #define FLASH_SR_WRPERR_Pos (4U)
  2270. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  2271. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  2272. #define FLASH_SR_PGAERR_Pos (5U)
  2273. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  2274. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  2275. #define FLASH_SR_PGPERR_Pos (6U)
  2276. #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
  2277. #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
  2278. #define FLASH_SR_PGSERR_Pos (7U)
  2279. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  2280. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  2281. #define FLASH_SR_RDERR_Pos (8U)
  2282. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
  2283. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  2284. #define FLASH_SR_BSY_Pos (16U)
  2285. #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  2286. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  2287. /******************* Bits definition for FLASH_CR register ******************/
  2288. #define FLASH_CR_PG_Pos (0U)
  2289. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  2290. #define FLASH_CR_PG FLASH_CR_PG_Msk
  2291. #define FLASH_CR_SER_Pos (1U)
  2292. #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
  2293. #define FLASH_CR_SER FLASH_CR_SER_Msk
  2294. #define FLASH_CR_MER_Pos (2U)
  2295. #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  2296. #define FLASH_CR_MER FLASH_CR_MER_Msk
  2297. #define FLASH_CR_SNB_Pos (3U)
  2298. #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
  2299. #define FLASH_CR_SNB FLASH_CR_SNB_Msk
  2300. #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
  2301. #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
  2302. #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
  2303. #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
  2304. #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
  2305. #define FLASH_CR_PSIZE_Pos (8U)
  2306. #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
  2307. #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
  2308. #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
  2309. #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
  2310. #define FLASH_CR_STRT_Pos (16U)
  2311. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  2312. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  2313. #define FLASH_CR_EOPIE_Pos (24U)
  2314. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  2315. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  2316. #define FLASH_CR_LOCK_Pos (31U)
  2317. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  2318. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  2319. /******************* Bits definition for FLASH_OPTCR register ***************/
  2320. #define FLASH_OPTCR_OPTLOCK_Pos (0U)
  2321. #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
  2322. #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
  2323. #define FLASH_OPTCR_OPTSTRT_Pos (1U)
  2324. #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
  2325. #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
  2326. #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
  2327. #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
  2328. #define FLASH_OPTCR_BOR_LEV_Pos (2U)
  2329. #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
  2330. #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
  2331. #define FLASH_OPTCR_WDG_SW_Pos (5U)
  2332. #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
  2333. #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
  2334. #define FLASH_OPTCR_nRST_STOP_Pos (6U)
  2335. #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
  2336. #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
  2337. #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
  2338. #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
  2339. #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
  2340. #define FLASH_OPTCR_RDP_Pos (8U)
  2341. #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
  2342. #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
  2343. #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
  2344. #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
  2345. #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
  2346. #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
  2347. #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
  2348. #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
  2349. #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
  2350. #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
  2351. #define FLASH_OPTCR_nWRP_Pos (16U)
  2352. #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
  2353. #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
  2354. #define FLASH_OPTCR_nWRP_0 0x00010000U
  2355. #define FLASH_OPTCR_nWRP_1 0x00020000U
  2356. #define FLASH_OPTCR_nWRP_2 0x00040000U
  2357. #define FLASH_OPTCR_nWRP_3 0x00080000U
  2358. #define FLASH_OPTCR_nWRP_4 0x00100000U
  2359. #define FLASH_OPTCR_nWRP_5 0x00200000U
  2360. #define FLASH_OPTCR_nWRP_6 0x00400000U
  2361. #define FLASH_OPTCR_nWRP_7 0x00800000U
  2362. #define FLASH_OPTCR_nWRP_8 0x01000000U
  2363. #define FLASH_OPTCR_nWRP_9 0x02000000U
  2364. #define FLASH_OPTCR_nWRP_10 0x04000000U
  2365. #define FLASH_OPTCR_nWRP_11 0x08000000U
  2366. /****************** Bits definition for FLASH_OPTCR1 register ***************/
  2367. #define FLASH_OPTCR1_nWRP_Pos (16U)
  2368. #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
  2369. #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
  2370. #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
  2371. #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
  2372. #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
  2373. #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
  2374. #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
  2375. #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
  2376. #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
  2377. #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
  2378. #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
  2379. #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
  2380. #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
  2381. #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
  2382. /******************************************************************************/
  2383. /* */
  2384. /* General Purpose I/O */
  2385. /* */
  2386. /******************************************************************************/
  2387. /****************** Bits definition for GPIO_MODER register *****************/
  2388. #define GPIO_MODER_MODER0_Pos (0U)
  2389. #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  2390. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  2391. #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  2392. #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  2393. #define GPIO_MODER_MODER1_Pos (2U)
  2394. #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  2395. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  2396. #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  2397. #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  2398. #define GPIO_MODER_MODER2_Pos (4U)
  2399. #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  2400. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  2401. #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  2402. #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  2403. #define GPIO_MODER_MODER3_Pos (6U)
  2404. #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  2405. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  2406. #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  2407. #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  2408. #define GPIO_MODER_MODER4_Pos (8U)
  2409. #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  2410. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  2411. #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  2412. #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  2413. #define GPIO_MODER_MODER5_Pos (10U)
  2414. #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  2415. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  2416. #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  2417. #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  2418. #define GPIO_MODER_MODER6_Pos (12U)
  2419. #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  2420. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  2421. #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  2422. #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  2423. #define GPIO_MODER_MODER7_Pos (14U)
  2424. #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  2425. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  2426. #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  2427. #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  2428. #define GPIO_MODER_MODER8_Pos (16U)
  2429. #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  2430. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  2431. #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  2432. #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  2433. #define GPIO_MODER_MODER9_Pos (18U)
  2434. #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  2435. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  2436. #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  2437. #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  2438. #define GPIO_MODER_MODER10_Pos (20U)
  2439. #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  2440. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  2441. #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  2442. #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  2443. #define GPIO_MODER_MODER11_Pos (22U)
  2444. #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  2445. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  2446. #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  2447. #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  2448. #define GPIO_MODER_MODER12_Pos (24U)
  2449. #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  2450. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  2451. #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  2452. #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  2453. #define GPIO_MODER_MODER13_Pos (26U)
  2454. #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  2455. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  2456. #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  2457. #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  2458. #define GPIO_MODER_MODER14_Pos (28U)
  2459. #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  2460. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  2461. #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  2462. #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  2463. #define GPIO_MODER_MODER15_Pos (30U)
  2464. #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  2465. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  2466. #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  2467. #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  2468. /* Legacy defines */
  2469. #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
  2470. #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
  2471. #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
  2472. #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
  2473. #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
  2474. #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
  2475. #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
  2476. #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
  2477. #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
  2478. #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
  2479. #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
  2480. #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
  2481. #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
  2482. #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
  2483. #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
  2484. #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
  2485. #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
  2486. #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
  2487. #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
  2488. #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
  2489. #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
  2490. #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
  2491. #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
  2492. #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
  2493. #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
  2494. #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
  2495. #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
  2496. #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
  2497. #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
  2498. #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
  2499. #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
  2500. #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
  2501. #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
  2502. #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
  2503. #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
  2504. #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
  2505. #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
  2506. #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
  2507. #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
  2508. #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
  2509. #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
  2510. #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
  2511. #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
  2512. #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
  2513. #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
  2514. #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
  2515. #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
  2516. #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
  2517. #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
  2518. #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
  2519. #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
  2520. #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
  2521. #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
  2522. #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
  2523. #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
  2524. #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
  2525. #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
  2526. #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
  2527. #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
  2528. #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
  2529. #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
  2530. #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
  2531. #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
  2532. #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
  2533. #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
  2534. #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
  2535. #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
  2536. #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
  2537. #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
  2538. #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
  2539. #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
  2540. #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
  2541. #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
  2542. #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
  2543. #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
  2544. #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
  2545. #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
  2546. #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
  2547. #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
  2548. #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
  2549. /****************** Bits definition for GPIO_OTYPER register ****************/
  2550. #define GPIO_OTYPER_OT0_Pos (0U)
  2551. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  2552. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  2553. #define GPIO_OTYPER_OT1_Pos (1U)
  2554. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  2555. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  2556. #define GPIO_OTYPER_OT2_Pos (2U)
  2557. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  2558. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  2559. #define GPIO_OTYPER_OT3_Pos (3U)
  2560. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  2561. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  2562. #define GPIO_OTYPER_OT4_Pos (4U)
  2563. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  2564. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  2565. #define GPIO_OTYPER_OT5_Pos (5U)
  2566. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  2567. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  2568. #define GPIO_OTYPER_OT6_Pos (6U)
  2569. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  2570. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  2571. #define GPIO_OTYPER_OT7_Pos (7U)
  2572. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  2573. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  2574. #define GPIO_OTYPER_OT8_Pos (8U)
  2575. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  2576. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  2577. #define GPIO_OTYPER_OT9_Pos (9U)
  2578. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  2579. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  2580. #define GPIO_OTYPER_OT10_Pos (10U)
  2581. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  2582. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  2583. #define GPIO_OTYPER_OT11_Pos (11U)
  2584. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  2585. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  2586. #define GPIO_OTYPER_OT12_Pos (12U)
  2587. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  2588. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  2589. #define GPIO_OTYPER_OT13_Pos (13U)
  2590. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  2591. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  2592. #define GPIO_OTYPER_OT14_Pos (14U)
  2593. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  2594. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  2595. #define GPIO_OTYPER_OT15_Pos (15U)
  2596. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  2597. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  2598. /* Legacy defines */
  2599. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  2600. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  2601. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  2602. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  2603. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  2604. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  2605. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  2606. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  2607. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  2608. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  2609. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  2610. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  2611. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  2612. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  2613. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  2614. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  2615. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  2616. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  2617. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  2618. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  2619. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  2620. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  2621. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  2622. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  2623. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  2624. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  2625. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  2626. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  2627. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  2628. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  2629. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  2630. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  2631. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  2632. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  2633. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  2634. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  2635. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  2636. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  2637. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  2638. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  2639. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  2640. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  2641. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  2642. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  2643. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  2644. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  2645. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  2646. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  2647. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  2648. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  2649. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  2650. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  2651. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  2652. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  2653. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  2654. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  2655. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  2656. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  2657. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  2658. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  2659. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  2660. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  2661. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  2662. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  2663. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  2664. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  2665. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  2666. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  2667. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  2668. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  2669. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  2670. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  2671. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  2672. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  2673. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  2674. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  2675. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  2676. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  2677. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  2678. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  2679. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  2680. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  2681. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  2682. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  2683. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  2684. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  2685. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  2686. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  2687. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  2688. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  2689. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  2690. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  2691. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  2692. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  2693. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  2694. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  2695. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  2696. /* Legacy defines */
  2697. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  2698. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  2699. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  2700. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  2701. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  2702. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  2703. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  2704. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  2705. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  2706. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  2707. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  2708. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  2709. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  2710. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  2711. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  2712. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  2713. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  2714. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  2715. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  2716. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  2717. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  2718. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  2719. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  2720. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  2721. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  2722. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  2723. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  2724. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  2725. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  2726. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  2727. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  2728. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  2729. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  2730. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  2731. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  2732. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  2733. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  2734. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  2735. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  2736. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  2737. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  2738. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  2739. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  2740. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  2741. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  2742. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  2743. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  2744. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  2745. /****************** Bits definition for GPIO_PUPDR register *****************/
  2746. #define GPIO_PUPDR_PUPD0_Pos (0U)
  2747. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  2748. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  2749. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  2750. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  2751. #define GPIO_PUPDR_PUPD1_Pos (2U)
  2752. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  2753. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  2754. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  2755. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  2756. #define GPIO_PUPDR_PUPD2_Pos (4U)
  2757. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  2758. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  2759. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  2760. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  2761. #define GPIO_PUPDR_PUPD3_Pos (6U)
  2762. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  2763. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  2764. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  2765. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  2766. #define GPIO_PUPDR_PUPD4_Pos (8U)
  2767. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  2768. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  2769. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  2770. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  2771. #define GPIO_PUPDR_PUPD5_Pos (10U)
  2772. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  2773. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  2774. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  2775. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  2776. #define GPIO_PUPDR_PUPD6_Pos (12U)
  2777. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  2778. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  2779. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  2780. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  2781. #define GPIO_PUPDR_PUPD7_Pos (14U)
  2782. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  2783. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  2784. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  2785. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  2786. #define GPIO_PUPDR_PUPD8_Pos (16U)
  2787. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  2788. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  2789. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  2790. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  2791. #define GPIO_PUPDR_PUPD9_Pos (18U)
  2792. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  2793. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  2794. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  2795. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  2796. #define GPIO_PUPDR_PUPD10_Pos (20U)
  2797. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  2798. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  2799. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  2800. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  2801. #define GPIO_PUPDR_PUPD11_Pos (22U)
  2802. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  2803. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  2804. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  2805. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  2806. #define GPIO_PUPDR_PUPD12_Pos (24U)
  2807. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  2808. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  2809. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  2810. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  2811. #define GPIO_PUPDR_PUPD13_Pos (26U)
  2812. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  2813. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  2814. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  2815. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  2816. #define GPIO_PUPDR_PUPD14_Pos (28U)
  2817. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  2818. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  2819. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  2820. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  2821. #define GPIO_PUPDR_PUPD15_Pos (30U)
  2822. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  2823. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  2824. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  2825. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  2826. /* Legacy defines */
  2827. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  2828. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  2829. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  2830. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  2831. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  2832. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  2833. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  2834. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  2835. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  2836. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  2837. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  2838. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  2839. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  2840. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  2841. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  2842. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  2843. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  2844. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  2845. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  2846. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  2847. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  2848. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  2849. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  2850. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  2851. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  2852. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  2853. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  2854. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  2855. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  2856. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  2857. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  2858. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  2859. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  2860. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  2861. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  2862. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  2863. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  2864. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  2865. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  2866. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  2867. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  2868. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  2869. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  2870. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  2871. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  2872. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  2873. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  2874. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  2875. /****************** Bits definition for GPIO_IDR register *******************/
  2876. #define GPIO_IDR_ID0_Pos (0U)
  2877. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  2878. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  2879. #define GPIO_IDR_ID1_Pos (1U)
  2880. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  2881. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  2882. #define GPIO_IDR_ID2_Pos (2U)
  2883. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  2884. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  2885. #define GPIO_IDR_ID3_Pos (3U)
  2886. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  2887. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  2888. #define GPIO_IDR_ID4_Pos (4U)
  2889. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  2890. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  2891. #define GPIO_IDR_ID5_Pos (5U)
  2892. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  2893. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  2894. #define GPIO_IDR_ID6_Pos (6U)
  2895. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  2896. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  2897. #define GPIO_IDR_ID7_Pos (7U)
  2898. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  2899. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  2900. #define GPIO_IDR_ID8_Pos (8U)
  2901. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  2902. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  2903. #define GPIO_IDR_ID9_Pos (9U)
  2904. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  2905. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  2906. #define GPIO_IDR_ID10_Pos (10U)
  2907. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  2908. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  2909. #define GPIO_IDR_ID11_Pos (11U)
  2910. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  2911. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  2912. #define GPIO_IDR_ID12_Pos (12U)
  2913. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  2914. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  2915. #define GPIO_IDR_ID13_Pos (13U)
  2916. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  2917. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  2918. #define GPIO_IDR_ID14_Pos (14U)
  2919. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  2920. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  2921. #define GPIO_IDR_ID15_Pos (15U)
  2922. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  2923. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  2924. /* Legacy defines */
  2925. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  2926. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  2927. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  2928. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  2929. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  2930. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  2931. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  2932. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  2933. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  2934. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  2935. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  2936. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  2937. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  2938. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  2939. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  2940. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  2941. /****************** Bits definition for GPIO_ODR register *******************/
  2942. #define GPIO_ODR_OD0_Pos (0U)
  2943. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  2944. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  2945. #define GPIO_ODR_OD1_Pos (1U)
  2946. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  2947. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  2948. #define GPIO_ODR_OD2_Pos (2U)
  2949. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  2950. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  2951. #define GPIO_ODR_OD3_Pos (3U)
  2952. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  2953. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  2954. #define GPIO_ODR_OD4_Pos (4U)
  2955. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  2956. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  2957. #define GPIO_ODR_OD5_Pos (5U)
  2958. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  2959. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  2960. #define GPIO_ODR_OD6_Pos (6U)
  2961. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  2962. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  2963. #define GPIO_ODR_OD7_Pos (7U)
  2964. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  2965. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  2966. #define GPIO_ODR_OD8_Pos (8U)
  2967. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  2968. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  2969. #define GPIO_ODR_OD9_Pos (9U)
  2970. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  2971. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  2972. #define GPIO_ODR_OD10_Pos (10U)
  2973. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  2974. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  2975. #define GPIO_ODR_OD11_Pos (11U)
  2976. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  2977. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  2978. #define GPIO_ODR_OD12_Pos (12U)
  2979. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  2980. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  2981. #define GPIO_ODR_OD13_Pos (13U)
  2982. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  2983. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  2984. #define GPIO_ODR_OD14_Pos (14U)
  2985. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  2986. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  2987. #define GPIO_ODR_OD15_Pos (15U)
  2988. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  2989. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  2990. /* Legacy defines */
  2991. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  2992. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  2993. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  2994. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  2995. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  2996. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  2997. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  2998. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  2999. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  3000. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  3001. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  3002. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  3003. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  3004. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  3005. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  3006. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  3007. /****************** Bits definition for GPIO_BSRR register ******************/
  3008. #define GPIO_BSRR_BS0_Pos (0U)
  3009. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  3010. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  3011. #define GPIO_BSRR_BS1_Pos (1U)
  3012. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  3013. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  3014. #define GPIO_BSRR_BS2_Pos (2U)
  3015. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  3016. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  3017. #define GPIO_BSRR_BS3_Pos (3U)
  3018. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  3019. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  3020. #define GPIO_BSRR_BS4_Pos (4U)
  3021. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  3022. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  3023. #define GPIO_BSRR_BS5_Pos (5U)
  3024. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  3025. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  3026. #define GPIO_BSRR_BS6_Pos (6U)
  3027. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  3028. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  3029. #define GPIO_BSRR_BS7_Pos (7U)
  3030. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  3031. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  3032. #define GPIO_BSRR_BS8_Pos (8U)
  3033. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  3034. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  3035. #define GPIO_BSRR_BS9_Pos (9U)
  3036. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  3037. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  3038. #define GPIO_BSRR_BS10_Pos (10U)
  3039. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  3040. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  3041. #define GPIO_BSRR_BS11_Pos (11U)
  3042. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  3043. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  3044. #define GPIO_BSRR_BS12_Pos (12U)
  3045. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  3046. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  3047. #define GPIO_BSRR_BS13_Pos (13U)
  3048. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  3049. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  3050. #define GPIO_BSRR_BS14_Pos (14U)
  3051. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  3052. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  3053. #define GPIO_BSRR_BS15_Pos (15U)
  3054. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  3055. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  3056. #define GPIO_BSRR_BR0_Pos (16U)
  3057. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  3058. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  3059. #define GPIO_BSRR_BR1_Pos (17U)
  3060. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  3061. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  3062. #define GPIO_BSRR_BR2_Pos (18U)
  3063. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  3064. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  3065. #define GPIO_BSRR_BR3_Pos (19U)
  3066. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  3067. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  3068. #define GPIO_BSRR_BR4_Pos (20U)
  3069. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  3070. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  3071. #define GPIO_BSRR_BR5_Pos (21U)
  3072. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  3073. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  3074. #define GPIO_BSRR_BR6_Pos (22U)
  3075. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  3076. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  3077. #define GPIO_BSRR_BR7_Pos (23U)
  3078. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  3079. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  3080. #define GPIO_BSRR_BR8_Pos (24U)
  3081. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  3082. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  3083. #define GPIO_BSRR_BR9_Pos (25U)
  3084. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  3085. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  3086. #define GPIO_BSRR_BR10_Pos (26U)
  3087. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  3088. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  3089. #define GPIO_BSRR_BR11_Pos (27U)
  3090. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  3091. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  3092. #define GPIO_BSRR_BR12_Pos (28U)
  3093. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  3094. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  3095. #define GPIO_BSRR_BR13_Pos (29U)
  3096. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  3097. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  3098. #define GPIO_BSRR_BR14_Pos (30U)
  3099. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  3100. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  3101. #define GPIO_BSRR_BR15_Pos (31U)
  3102. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  3103. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  3104. /* Legacy defines */
  3105. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  3106. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  3107. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  3108. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  3109. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  3110. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  3111. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  3112. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  3113. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  3114. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  3115. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  3116. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  3117. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  3118. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  3119. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  3120. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  3121. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  3122. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  3123. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  3124. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  3125. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  3126. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  3127. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  3128. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  3129. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  3130. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  3131. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  3132. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  3133. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  3134. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  3135. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  3136. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  3137. #define GPIO_BRR_BR0 GPIO_BSRR_BR0
  3138. #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
  3139. #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
  3140. #define GPIO_BRR_BR1 GPIO_BSRR_BR1
  3141. #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
  3142. #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
  3143. #define GPIO_BRR_BR2 GPIO_BSRR_BR2
  3144. #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
  3145. #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
  3146. #define GPIO_BRR_BR3 GPIO_BSRR_BR3
  3147. #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
  3148. #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
  3149. #define GPIO_BRR_BR4 GPIO_BSRR_BR4
  3150. #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
  3151. #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
  3152. #define GPIO_BRR_BR5 GPIO_BSRR_BR5
  3153. #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
  3154. #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
  3155. #define GPIO_BRR_BR6 GPIO_BSRR_BR6
  3156. #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
  3157. #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
  3158. #define GPIO_BRR_BR7 GPIO_BSRR_BR7
  3159. #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
  3160. #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
  3161. #define GPIO_BRR_BR8 GPIO_BSRR_BR8
  3162. #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
  3163. #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
  3164. #define GPIO_BRR_BR9 GPIO_BSRR_BR9
  3165. #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
  3166. #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
  3167. #define GPIO_BRR_BR10 GPIO_BSRR_BR10
  3168. #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
  3169. #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
  3170. #define GPIO_BRR_BR11 GPIO_BSRR_BR11
  3171. #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
  3172. #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
  3173. #define GPIO_BRR_BR12 GPIO_BSRR_BR12
  3174. #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
  3175. #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
  3176. #define GPIO_BRR_BR13 GPIO_BSRR_BR13
  3177. #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
  3178. #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
  3179. #define GPIO_BRR_BR14 GPIO_BSRR_BR14
  3180. #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
  3181. #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
  3182. #define GPIO_BRR_BR15 GPIO_BSRR_BR15
  3183. #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
  3184. #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
  3185. /****************** Bit definition for GPIO_LCKR register *********************/
  3186. #define GPIO_LCKR_LCK0_Pos (0U)
  3187. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  3188. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  3189. #define GPIO_LCKR_LCK1_Pos (1U)
  3190. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  3191. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  3192. #define GPIO_LCKR_LCK2_Pos (2U)
  3193. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  3194. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  3195. #define GPIO_LCKR_LCK3_Pos (3U)
  3196. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  3197. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  3198. #define GPIO_LCKR_LCK4_Pos (4U)
  3199. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  3200. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  3201. #define GPIO_LCKR_LCK5_Pos (5U)
  3202. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  3203. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  3204. #define GPIO_LCKR_LCK6_Pos (6U)
  3205. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  3206. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  3207. #define GPIO_LCKR_LCK7_Pos (7U)
  3208. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  3209. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  3210. #define GPIO_LCKR_LCK8_Pos (8U)
  3211. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  3212. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  3213. #define GPIO_LCKR_LCK9_Pos (9U)
  3214. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  3215. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  3216. #define GPIO_LCKR_LCK10_Pos (10U)
  3217. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  3218. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  3219. #define GPIO_LCKR_LCK11_Pos (11U)
  3220. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  3221. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  3222. #define GPIO_LCKR_LCK12_Pos (12U)
  3223. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  3224. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  3225. #define GPIO_LCKR_LCK13_Pos (13U)
  3226. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  3227. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  3228. #define GPIO_LCKR_LCK14_Pos (14U)
  3229. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  3230. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  3231. #define GPIO_LCKR_LCK15_Pos (15U)
  3232. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  3233. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  3234. #define GPIO_LCKR_LCKK_Pos (16U)
  3235. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  3236. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  3237. /****************** Bit definition for GPIO_AFRL register *********************/
  3238. #define GPIO_AFRL_AFSEL0_Pos (0U)
  3239. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  3240. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  3241. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  3242. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  3243. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  3244. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  3245. #define GPIO_AFRL_AFSEL1_Pos (4U)
  3246. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  3247. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  3248. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  3249. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  3250. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  3251. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  3252. #define GPIO_AFRL_AFSEL2_Pos (8U)
  3253. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  3254. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  3255. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  3256. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  3257. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  3258. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  3259. #define GPIO_AFRL_AFSEL3_Pos (12U)
  3260. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  3261. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  3262. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  3263. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  3264. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  3265. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  3266. #define GPIO_AFRL_AFSEL4_Pos (16U)
  3267. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  3268. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  3269. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  3270. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  3271. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  3272. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  3273. #define GPIO_AFRL_AFSEL5_Pos (20U)
  3274. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  3275. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  3276. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  3277. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  3278. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  3279. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  3280. #define GPIO_AFRL_AFSEL6_Pos (24U)
  3281. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  3282. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  3283. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  3284. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  3285. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  3286. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  3287. #define GPIO_AFRL_AFSEL7_Pos (28U)
  3288. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  3289. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  3290. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  3291. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  3292. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  3293. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  3294. /* Legacy defines */
  3295. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  3296. #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
  3297. #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
  3298. #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
  3299. #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
  3300. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  3301. #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
  3302. #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
  3303. #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
  3304. #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
  3305. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  3306. #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
  3307. #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
  3308. #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
  3309. #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
  3310. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  3311. #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
  3312. #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
  3313. #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
  3314. #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
  3315. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  3316. #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
  3317. #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
  3318. #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
  3319. #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
  3320. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  3321. #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
  3322. #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
  3323. #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
  3324. #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
  3325. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  3326. #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
  3327. #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
  3328. #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
  3329. #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
  3330. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  3331. #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
  3332. #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
  3333. #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
  3334. #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
  3335. /****************** Bit definition for GPIO_AFRH register *********************/
  3336. #define GPIO_AFRH_AFSEL8_Pos (0U)
  3337. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  3338. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  3339. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  3340. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  3341. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  3342. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  3343. #define GPIO_AFRH_AFSEL9_Pos (4U)
  3344. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  3345. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  3346. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  3347. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  3348. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  3349. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  3350. #define GPIO_AFRH_AFSEL10_Pos (8U)
  3351. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  3352. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  3353. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  3354. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  3355. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  3356. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  3357. #define GPIO_AFRH_AFSEL11_Pos (12U)
  3358. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  3359. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  3360. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  3361. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  3362. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  3363. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  3364. #define GPIO_AFRH_AFSEL12_Pos (16U)
  3365. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  3366. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  3367. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  3368. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  3369. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  3370. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  3371. #define GPIO_AFRH_AFSEL13_Pos (20U)
  3372. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  3373. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  3374. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  3375. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  3376. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  3377. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  3378. #define GPIO_AFRH_AFSEL14_Pos (24U)
  3379. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  3380. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  3381. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  3382. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  3383. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  3384. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  3385. #define GPIO_AFRH_AFSEL15_Pos (28U)
  3386. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  3387. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  3388. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  3389. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  3390. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  3391. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  3392. /* Legacy defines */
  3393. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  3394. #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
  3395. #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
  3396. #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
  3397. #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
  3398. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  3399. #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
  3400. #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
  3401. #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
  3402. #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
  3403. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  3404. #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
  3405. #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
  3406. #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
  3407. #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
  3408. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  3409. #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
  3410. #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
  3411. #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
  3412. #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
  3413. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  3414. #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
  3415. #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
  3416. #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
  3417. #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
  3418. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  3419. #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
  3420. #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
  3421. #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
  3422. #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
  3423. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  3424. #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
  3425. #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
  3426. #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
  3427. #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
  3428. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  3429. #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
  3430. #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
  3431. #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
  3432. #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
  3433. /******************************************************************************/
  3434. /* */
  3435. /* Inter-integrated Circuit Interface */
  3436. /* */
  3437. /******************************************************************************/
  3438. /******************* Bit definition for I2C_CR1 register ********************/
  3439. #define I2C_CR1_PE_Pos (0U)
  3440. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  3441. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
  3442. #define I2C_CR1_SMBUS_Pos (1U)
  3443. #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
  3444. #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
  3445. #define I2C_CR1_SMBTYPE_Pos (3U)
  3446. #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
  3447. #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
  3448. #define I2C_CR1_ENARP_Pos (4U)
  3449. #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
  3450. #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
  3451. #define I2C_CR1_ENPEC_Pos (5U)
  3452. #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
  3453. #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
  3454. #define I2C_CR1_ENGC_Pos (6U)
  3455. #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
  3456. #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
  3457. #define I2C_CR1_NOSTRETCH_Pos (7U)
  3458. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
  3459. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
  3460. #define I2C_CR1_START_Pos (8U)
  3461. #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
  3462. #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
  3463. #define I2C_CR1_STOP_Pos (9U)
  3464. #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
  3465. #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
  3466. #define I2C_CR1_ACK_Pos (10U)
  3467. #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
  3468. #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
  3469. #define I2C_CR1_POS_Pos (11U)
  3470. #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
  3471. #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
  3472. #define I2C_CR1_PEC_Pos (12U)
  3473. #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
  3474. #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
  3475. #define I2C_CR1_ALERT_Pos (13U)
  3476. #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
  3477. #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
  3478. #define I2C_CR1_SWRST_Pos (15U)
  3479. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
  3480. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
  3481. /******************* Bit definition for I2C_CR2 register ********************/
  3482. #define I2C_CR2_FREQ_Pos (0U)
  3483. #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
  3484. #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
  3485. #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
  3486. #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
  3487. #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
  3488. #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
  3489. #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
  3490. #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
  3491. #define I2C_CR2_ITERREN_Pos (8U)
  3492. #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
  3493. #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
  3494. #define I2C_CR2_ITEVTEN_Pos (9U)
  3495. #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
  3496. #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
  3497. #define I2C_CR2_ITBUFEN_Pos (10U)
  3498. #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
  3499. #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
  3500. #define I2C_CR2_DMAEN_Pos (11U)
  3501. #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
  3502. #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
  3503. #define I2C_CR2_LAST_Pos (12U)
  3504. #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
  3505. #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
  3506. /******************* Bit definition for I2C_OAR1 register *******************/
  3507. #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
  3508. #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
  3509. #define I2C_OAR1_ADD0_Pos (0U)
  3510. #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
  3511. #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
  3512. #define I2C_OAR1_ADD1_Pos (1U)
  3513. #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
  3514. #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
  3515. #define I2C_OAR1_ADD2_Pos (2U)
  3516. #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
  3517. #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
  3518. #define I2C_OAR1_ADD3_Pos (3U)
  3519. #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
  3520. #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
  3521. #define I2C_OAR1_ADD4_Pos (4U)
  3522. #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
  3523. #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
  3524. #define I2C_OAR1_ADD5_Pos (5U)
  3525. #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
  3526. #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
  3527. #define I2C_OAR1_ADD6_Pos (6U)
  3528. #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
  3529. #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
  3530. #define I2C_OAR1_ADD7_Pos (7U)
  3531. #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
  3532. #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
  3533. #define I2C_OAR1_ADD8_Pos (8U)
  3534. #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
  3535. #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
  3536. #define I2C_OAR1_ADD9_Pos (9U)
  3537. #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
  3538. #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
  3539. #define I2C_OAR1_ADDMODE_Pos (15U)
  3540. #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
  3541. #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
  3542. /******************* Bit definition for I2C_OAR2 register *******************/
  3543. #define I2C_OAR2_ENDUAL_Pos (0U)
  3544. #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
  3545. #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
  3546. #define I2C_OAR2_ADD2_Pos (1U)
  3547. #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
  3548. #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
  3549. /******************** Bit definition for I2C_DR register ********************/
  3550. #define I2C_DR_DR_Pos (0U)
  3551. #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
  3552. #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
  3553. /******************* Bit definition for I2C_SR1 register ********************/
  3554. #define I2C_SR1_SB_Pos (0U)
  3555. #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
  3556. #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
  3557. #define I2C_SR1_ADDR_Pos (1U)
  3558. #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
  3559. #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
  3560. #define I2C_SR1_BTF_Pos (2U)
  3561. #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
  3562. #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
  3563. #define I2C_SR1_ADD10_Pos (3U)
  3564. #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
  3565. #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
  3566. #define I2C_SR1_STOPF_Pos (4U)
  3567. #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
  3568. #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
  3569. #define I2C_SR1_RXNE_Pos (6U)
  3570. #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
  3571. #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
  3572. #define I2C_SR1_TXE_Pos (7U)
  3573. #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
  3574. #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
  3575. #define I2C_SR1_BERR_Pos (8U)
  3576. #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
  3577. #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
  3578. #define I2C_SR1_ARLO_Pos (9U)
  3579. #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
  3580. #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
  3581. #define I2C_SR1_AF_Pos (10U)
  3582. #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
  3583. #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
  3584. #define I2C_SR1_OVR_Pos (11U)
  3585. #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
  3586. #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
  3587. #define I2C_SR1_PECERR_Pos (12U)
  3588. #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
  3589. #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
  3590. #define I2C_SR1_TIMEOUT_Pos (14U)
  3591. #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
  3592. #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
  3593. #define I2C_SR1_SMBALERT_Pos (15U)
  3594. #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
  3595. #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
  3596. /******************* Bit definition for I2C_SR2 register ********************/
  3597. #define I2C_SR2_MSL_Pos (0U)
  3598. #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
  3599. #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
  3600. #define I2C_SR2_BUSY_Pos (1U)
  3601. #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
  3602. #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
  3603. #define I2C_SR2_TRA_Pos (2U)
  3604. #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
  3605. #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
  3606. #define I2C_SR2_GENCALL_Pos (4U)
  3607. #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
  3608. #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
  3609. #define I2C_SR2_SMBDEFAULT_Pos (5U)
  3610. #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
  3611. #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
  3612. #define I2C_SR2_SMBHOST_Pos (6U)
  3613. #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
  3614. #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
  3615. #define I2C_SR2_DUALF_Pos (7U)
  3616. #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
  3617. #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
  3618. #define I2C_SR2_PEC_Pos (8U)
  3619. #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
  3620. #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
  3621. /******************* Bit definition for I2C_CCR register ********************/
  3622. #define I2C_CCR_CCR_Pos (0U)
  3623. #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
  3624. #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
  3625. #define I2C_CCR_DUTY_Pos (14U)
  3626. #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
  3627. #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
  3628. #define I2C_CCR_FS_Pos (15U)
  3629. #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
  3630. #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
  3631. /****************** Bit definition for I2C_TRISE register *******************/
  3632. #define I2C_TRISE_TRISE_Pos (0U)
  3633. #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
  3634. #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
  3635. /****************** Bit definition for I2C_FLTR register *******************/
  3636. #define I2C_FLTR_DNF_Pos (0U)
  3637. #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
  3638. #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
  3639. #define I2C_FLTR_ANOFF_Pos (4U)
  3640. #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
  3641. #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
  3642. /******************************************************************************/
  3643. /* */
  3644. /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
  3645. /* */
  3646. /******************************************************************************/
  3647. /******************* Bit definition for I2C_CR1 register *******************/
  3648. #define FMPI2C_CR1_PE_Pos (0U)
  3649. #define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
  3650. #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
  3651. #define FMPI2C_CR1_TXIE_Pos (1U)
  3652. #define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
  3653. #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
  3654. #define FMPI2C_CR1_RXIE_Pos (2U)
  3655. #define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
  3656. #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
  3657. #define FMPI2C_CR1_ADDRIE_Pos (3U)
  3658. #define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
  3659. #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
  3660. #define FMPI2C_CR1_NACKIE_Pos (4U)
  3661. #define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
  3662. #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
  3663. #define FMPI2C_CR1_STOPIE_Pos (5U)
  3664. #define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
  3665. #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
  3666. #define FMPI2C_CR1_TCIE_Pos (6U)
  3667. #define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
  3668. #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
  3669. #define FMPI2C_CR1_ERRIE_Pos (7U)
  3670. #define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
  3671. #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
  3672. #define FMPI2C_CR1_DNF_Pos (8U)
  3673. #define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos) /*!< 0x00000F00 */
  3674. #define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk /*!< Digital noise filter */
  3675. #define FMPI2C_CR1_ANFOFF_Pos (12U)
  3676. #define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
  3677. #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
  3678. #define FMPI2C_CR1_TXDMAEN_Pos (14U)
  3679. #define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
  3680. #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
  3681. #define FMPI2C_CR1_RXDMAEN_Pos (15U)
  3682. #define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
  3683. #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
  3684. #define FMPI2C_CR1_SBC_Pos (16U)
  3685. #define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
  3686. #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
  3687. #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
  3688. #define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
  3689. #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
  3690. #define FMPI2C_CR1_GCEN_Pos (19U)
  3691. #define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
  3692. #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
  3693. #define FMPI2C_CR1_SMBHEN_Pos (20U)
  3694. #define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
  3695. #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
  3696. #define FMPI2C_CR1_SMBDEN_Pos (21U)
  3697. #define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
  3698. #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
  3699. #define FMPI2C_CR1_ALERTEN_Pos (22U)
  3700. #define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
  3701. #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
  3702. #define FMPI2C_CR1_PECEN_Pos (23U)
  3703. #define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
  3704. #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
  3705. /* Legacy Defines */
  3706. #define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
  3707. #define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
  3708. #define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
  3709. /****************** Bit definition for I2C_CR2 register ********************/
  3710. #define FMPI2C_CR2_SADD_Pos (0U)
  3711. #define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
  3712. #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
  3713. #define FMPI2C_CR2_RD_WRN_Pos (10U)
  3714. #define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
  3715. #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
  3716. #define FMPI2C_CR2_ADD10_Pos (11U)
  3717. #define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
  3718. #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
  3719. #define FMPI2C_CR2_HEAD10R_Pos (12U)
  3720. #define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
  3721. #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
  3722. #define FMPI2C_CR2_START_Pos (13U)
  3723. #define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
  3724. #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
  3725. #define FMPI2C_CR2_STOP_Pos (14U)
  3726. #define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
  3727. #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
  3728. #define FMPI2C_CR2_NACK_Pos (15U)
  3729. #define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
  3730. #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
  3731. #define FMPI2C_CR2_NBYTES_Pos (16U)
  3732. #define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
  3733. #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
  3734. #define FMPI2C_CR2_RELOAD_Pos (24U)
  3735. #define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
  3736. #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
  3737. #define FMPI2C_CR2_AUTOEND_Pos (25U)
  3738. #define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
  3739. #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
  3740. #define FMPI2C_CR2_PECBYTE_Pos (26U)
  3741. #define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
  3742. #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
  3743. /******************* Bit definition for I2C_OAR1 register ******************/
  3744. #define FMPI2C_OAR1_OA1_Pos (0U)
  3745. #define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
  3746. #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
  3747. #define FMPI2C_OAR1_OA1MODE_Pos (10U)
  3748. #define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
  3749. #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
  3750. #define FMPI2C_OAR1_OA1EN_Pos (15U)
  3751. #define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
  3752. #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
  3753. /******************* Bit definition for I2C_OAR2 register ******************/
  3754. #define FMPI2C_OAR2_OA2_Pos (1U)
  3755. #define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
  3756. #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
  3757. #define FMPI2C_OAR2_OA2MSK_Pos (8U)
  3758. #define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
  3759. #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
  3760. #define FMPI2C_OAR2_OA2EN_Pos (15U)
  3761. #define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
  3762. #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
  3763. /******************* Bit definition for I2C_TIMINGR register *******************/
  3764. #define FMPI2C_TIMINGR_SCLL_Pos (0U)
  3765. #define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
  3766. #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
  3767. #define FMPI2C_TIMINGR_SCLH_Pos (8U)
  3768. #define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
  3769. #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
  3770. #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
  3771. #define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
  3772. #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
  3773. #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
  3774. #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
  3775. #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
  3776. #define FMPI2C_TIMINGR_PRESC_Pos (28U)
  3777. #define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
  3778. #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
  3779. /******************* Bit definition for I2C_TIMEOUTR register *******************/
  3780. #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
  3781. #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
  3782. #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
  3783. #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
  3784. #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
  3785. #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
  3786. #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
  3787. #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
  3788. #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
  3789. #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
  3790. #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
  3791. #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
  3792. #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
  3793. #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
  3794. #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
  3795. /****************** Bit definition for I2C_ISR register *********************/
  3796. #define FMPI2C_ISR_TXE_Pos (0U)
  3797. #define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
  3798. #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
  3799. #define FMPI2C_ISR_TXIS_Pos (1U)
  3800. #define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
  3801. #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
  3802. #define FMPI2C_ISR_RXNE_Pos (2U)
  3803. #define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
  3804. #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
  3805. #define FMPI2C_ISR_ADDR_Pos (3U)
  3806. #define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
  3807. #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
  3808. #define FMPI2C_ISR_NACKF_Pos (4U)
  3809. #define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
  3810. #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
  3811. #define FMPI2C_ISR_STOPF_Pos (5U)
  3812. #define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
  3813. #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
  3814. #define FMPI2C_ISR_TC_Pos (6U)
  3815. #define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
  3816. #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
  3817. #define FMPI2C_ISR_TCR_Pos (7U)
  3818. #define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
  3819. #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
  3820. #define FMPI2C_ISR_BERR_Pos (8U)
  3821. #define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
  3822. #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
  3823. #define FMPI2C_ISR_ARLO_Pos (9U)
  3824. #define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
  3825. #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
  3826. #define FMPI2C_ISR_OVR_Pos (10U)
  3827. #define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
  3828. #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
  3829. #define FMPI2C_ISR_PECERR_Pos (11U)
  3830. #define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
  3831. #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
  3832. #define FMPI2C_ISR_TIMEOUT_Pos (12U)
  3833. #define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
  3834. #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
  3835. #define FMPI2C_ISR_ALERT_Pos (13U)
  3836. #define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
  3837. #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
  3838. #define FMPI2C_ISR_BUSY_Pos (15U)
  3839. #define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
  3840. #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
  3841. #define FMPI2C_ISR_DIR_Pos (16U)
  3842. #define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
  3843. #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
  3844. #define FMPI2C_ISR_ADDCODE_Pos (17U)
  3845. #define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
  3846. #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
  3847. /****************** Bit definition for I2C_ICR register *********************/
  3848. #define FMPI2C_ICR_ADDRCF_Pos (3U)
  3849. #define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
  3850. #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
  3851. #define FMPI2C_ICR_NACKCF_Pos (4U)
  3852. #define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
  3853. #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
  3854. #define FMPI2C_ICR_STOPCF_Pos (5U)
  3855. #define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
  3856. #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
  3857. #define FMPI2C_ICR_BERRCF_Pos (8U)
  3858. #define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
  3859. #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
  3860. #define FMPI2C_ICR_ARLOCF_Pos (9U)
  3861. #define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
  3862. #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
  3863. #define FMPI2C_ICR_OVRCF_Pos (10U)
  3864. #define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
  3865. #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
  3866. #define FMPI2C_ICR_PECCF_Pos (11U)
  3867. #define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
  3868. #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
  3869. #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
  3870. #define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
  3871. #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
  3872. #define FMPI2C_ICR_ALERTCF_Pos (13U)
  3873. #define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
  3874. #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
  3875. /****************** Bit definition for I2C_PECR register *********************/
  3876. #define FMPI2C_PECR_PEC_Pos (0U)
  3877. #define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
  3878. #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
  3879. /****************** Bit definition for I2C_RXDR register *********************/
  3880. #define FMPI2C_RXDR_RXDATA_Pos (0U)
  3881. #define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
  3882. #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
  3883. /****************** Bit definition for I2C_TXDR register *********************/
  3884. #define FMPI2C_TXDR_TXDATA_Pos (0U)
  3885. #define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
  3886. #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
  3887. /******************************************************************************/
  3888. /* */
  3889. /* Independent WATCHDOG */
  3890. /* */
  3891. /******************************************************************************/
  3892. /******************* Bit definition for IWDG_KR register ********************/
  3893. #define IWDG_KR_KEY_Pos (0U)
  3894. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  3895. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  3896. /******************* Bit definition for IWDG_PR register ********************/
  3897. #define IWDG_PR_PR_Pos (0U)
  3898. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  3899. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  3900. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
  3901. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
  3902. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
  3903. /******************* Bit definition for IWDG_RLR register *******************/
  3904. #define IWDG_RLR_RL_Pos (0U)
  3905. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  3906. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  3907. /******************* Bit definition for IWDG_SR register ********************/
  3908. #define IWDG_SR_PVU_Pos (0U)
  3909. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  3910. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
  3911. #define IWDG_SR_RVU_Pos (1U)
  3912. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  3913. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
  3914. /******************************************************************************/
  3915. /* */
  3916. /* Power Control */
  3917. /* */
  3918. /******************************************************************************/
  3919. /******************** Bit definition for PWR_CR register ********************/
  3920. #define PWR_CR_LPDS_Pos (0U)
  3921. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  3922. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  3923. #define PWR_CR_PDDS_Pos (1U)
  3924. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  3925. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  3926. #define PWR_CR_CWUF_Pos (2U)
  3927. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  3928. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  3929. #define PWR_CR_CSBF_Pos (3U)
  3930. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  3931. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  3932. #define PWR_CR_PVDE_Pos (4U)
  3933. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  3934. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  3935. #define PWR_CR_PLS_Pos (5U)
  3936. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  3937. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  3938. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  3939. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  3940. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  3941. /*!< PVD level configuration */
  3942. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
  3943. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
  3944. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
  3945. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
  3946. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
  3947. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
  3948. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
  3949. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
  3950. #define PWR_CR_DBP_Pos (8U)
  3951. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  3952. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  3953. #define PWR_CR_FPDS_Pos (9U)
  3954. #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
  3955. #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
  3956. #define PWR_CR_LPLVDS_Pos (10U)
  3957. #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
  3958. #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
  3959. #define PWR_CR_MRLVDS_Pos (11U)
  3960. #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
  3961. #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
  3962. #define PWR_CR_ADCDC1_Pos (13U)
  3963. #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
  3964. #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
  3965. #define PWR_CR_VOS_Pos (14U)
  3966. #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
  3967. #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  3968. #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
  3969. #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
  3970. #define PWR_CR_FMSSR_Pos (20U)
  3971. #define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
  3972. #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
  3973. #define PWR_CR_FISSR_Pos (21U)
  3974. #define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
  3975. #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
  3976. /* Legacy define */
  3977. #define PWR_CR_PMODE PWR_CR_VOS
  3978. /******************* Bit definition for PWR_CSR register ********************/
  3979. #define PWR_CSR_WUF_Pos (0U)
  3980. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  3981. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  3982. #define PWR_CSR_SBF_Pos (1U)
  3983. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  3984. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  3985. #define PWR_CSR_PVDO_Pos (2U)
  3986. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  3987. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  3988. #define PWR_CSR_BRR_Pos (3U)
  3989. #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
  3990. #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
  3991. #define PWR_CSR_EWUP3_Pos (6U)
  3992. #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */
  3993. #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
  3994. #define PWR_CSR_EWUP2_Pos (7U)
  3995. #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
  3996. #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
  3997. #define PWR_CSR_EWUP1_Pos (8U)
  3998. #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
  3999. #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
  4000. #define PWR_CSR_BRE_Pos (9U)
  4001. #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
  4002. #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
  4003. #define PWR_CSR_VOSRDY_Pos (14U)
  4004. #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
  4005. #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
  4006. /* Legacy define */
  4007. #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
  4008. /******************************************************************************/
  4009. /* */
  4010. /* Reset and Clock Control */
  4011. /* */
  4012. /******************************************************************************/
  4013. /******************** Bit definition for RCC_CR register ********************/
  4014. #define RCC_CR_HSION_Pos (0U)
  4015. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  4016. #define RCC_CR_HSION RCC_CR_HSION_Msk
  4017. #define RCC_CR_HSIRDY_Pos (1U)
  4018. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  4019. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
  4020. #define RCC_CR_HSITRIM_Pos (3U)
  4021. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  4022. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
  4023. #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  4024. #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  4025. #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  4026. #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  4027. #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  4028. #define RCC_CR_HSICAL_Pos (8U)
  4029. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  4030. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
  4031. #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  4032. #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  4033. #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  4034. #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  4035. #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  4036. #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  4037. #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  4038. #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  4039. #define RCC_CR_HSEON_Pos (16U)
  4040. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  4041. #define RCC_CR_HSEON RCC_CR_HSEON_Msk
  4042. #define RCC_CR_HSERDY_Pos (17U)
  4043. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  4044. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
  4045. #define RCC_CR_HSEBYP_Pos (18U)
  4046. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  4047. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
  4048. #define RCC_CR_CSSON_Pos (19U)
  4049. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  4050. #define RCC_CR_CSSON RCC_CR_CSSON_Msk
  4051. #define RCC_CR_PLLON_Pos (24U)
  4052. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  4053. #define RCC_CR_PLLON RCC_CR_PLLON_Msk
  4054. #define RCC_CR_PLLRDY_Pos (25U)
  4055. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  4056. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
  4057. /******************** Bit definition for RCC_PLLCFGR register ***************/
  4058. #define RCC_PLLCFGR_PLLM_Pos (0U)
  4059. #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
  4060. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  4061. #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
  4062. #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
  4063. #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
  4064. #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
  4065. #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  4066. #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  4067. #define RCC_PLLCFGR_PLLN_Pos (6U)
  4068. #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
  4069. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  4070. #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
  4071. #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
  4072. #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  4073. #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  4074. #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  4075. #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  4076. #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  4077. #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  4078. #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  4079. #define RCC_PLLCFGR_PLLP_Pos (16U)
  4080. #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
  4081. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  4082. #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
  4083. #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  4084. #define RCC_PLLCFGR_PLLSRC_Pos (22U)
  4085. #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
  4086. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  4087. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
  4088. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
  4089. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
  4090. #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
  4091. #define RCC_PLLCFGR_PLLQ_Pos (24U)
  4092. #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
  4093. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  4094. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
  4095. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  4096. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  4097. #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  4098. /*
  4099. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  4100. */
  4101. #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
  4102. #define RCC_PLLCFGR_PLLR_Pos (28U)
  4103. #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
  4104. #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
  4105. #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
  4106. #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
  4107. #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
  4108. /******************** Bit definition for RCC_CFGR register ******************/
  4109. /*!< SW configuration */
  4110. #define RCC_CFGR_SW_Pos (0U)
  4111. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  4112. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  4113. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  4114. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  4115. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  4116. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  4117. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  4118. /*!< SWS configuration */
  4119. #define RCC_CFGR_SWS_Pos (2U)
  4120. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  4121. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  4122. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  4123. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  4124. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  4125. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  4126. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  4127. /*!< HPRE configuration */
  4128. #define RCC_CFGR_HPRE_Pos (4U)
  4129. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  4130. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  4131. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  4132. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  4133. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  4134. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  4135. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  4136. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  4137. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  4138. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  4139. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  4140. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  4141. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  4142. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  4143. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  4144. /*!< MCO1EN configuration */
  4145. #define RCC_CFGR_MCO1EN_Pos (8U)
  4146. #define RCC_CFGR_MCO1EN_Msk (0x1UL << RCC_CFGR_MCO1EN_Pos) /*!< 0x00000100 */
  4147. #define RCC_CFGR_MCO1EN RCC_CFGR_MCO1EN_Msk /*!< MCO1EN bit */
  4148. /*!< PPRE1 configuration */
  4149. #define RCC_CFGR_PPRE1_Pos (10U)
  4150. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
  4151. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  4152. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  4153. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
  4154. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
  4155. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  4156. #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
  4157. #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
  4158. #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
  4159. #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
  4160. /*!< PPRE2 configuration */
  4161. #define RCC_CFGR_PPRE2_Pos (13U)
  4162. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
  4163. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  4164. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  4165. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
  4166. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
  4167. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  4168. #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
  4169. #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
  4170. #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
  4171. #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
  4172. /*!< RTCPRE configuration */
  4173. #define RCC_CFGR_RTCPRE_Pos (16U)
  4174. #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
  4175. #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
  4176. #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
  4177. #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
  4178. #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
  4179. #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
  4180. #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
  4181. /*!< MCO1 configuration */
  4182. #define RCC_CFGR_MCO1_Pos (21U)
  4183. #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
  4184. #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
  4185. #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
  4186. #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
  4187. #define RCC_CFGR_MCO1PRE_Pos (24U)
  4188. #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
  4189. #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
  4190. #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
  4191. #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
  4192. #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
  4193. #define RCC_CFGR_MCO2PRE_Pos (27U)
  4194. #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
  4195. #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
  4196. #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
  4197. #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
  4198. #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
  4199. #define RCC_CFGR_MCO2_Pos (30U)
  4200. #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
  4201. #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
  4202. #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
  4203. #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
  4204. /******************** Bit definition for RCC_CIR register *******************/
  4205. #define RCC_CIR_LSIRDYF_Pos (0U)
  4206. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  4207. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
  4208. #define RCC_CIR_LSERDYF_Pos (1U)
  4209. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  4210. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
  4211. #define RCC_CIR_HSIRDYF_Pos (2U)
  4212. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  4213. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
  4214. #define RCC_CIR_HSERDYF_Pos (3U)
  4215. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  4216. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
  4217. #define RCC_CIR_PLLRDYF_Pos (4U)
  4218. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  4219. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
  4220. #define RCC_CIR_CSSF_Pos (7U)
  4221. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  4222. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
  4223. #define RCC_CIR_LSIRDYIE_Pos (8U)
  4224. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  4225. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
  4226. #define RCC_CIR_LSERDYIE_Pos (9U)
  4227. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  4228. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
  4229. #define RCC_CIR_HSIRDYIE_Pos (10U)
  4230. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  4231. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
  4232. #define RCC_CIR_HSERDYIE_Pos (11U)
  4233. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  4234. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
  4235. #define RCC_CIR_PLLRDYIE_Pos (12U)
  4236. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  4237. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
  4238. #define RCC_CIR_LSIRDYC_Pos (16U)
  4239. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  4240. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
  4241. #define RCC_CIR_LSERDYC_Pos (17U)
  4242. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  4243. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
  4244. #define RCC_CIR_HSIRDYC_Pos (18U)
  4245. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  4246. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
  4247. #define RCC_CIR_HSERDYC_Pos (19U)
  4248. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  4249. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
  4250. #define RCC_CIR_PLLRDYC_Pos (20U)
  4251. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  4252. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
  4253. #define RCC_CIR_CSSC_Pos (23U)
  4254. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  4255. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
  4256. /******************** Bit definition for RCC_AHB1RSTR register **************/
  4257. #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
  4258. #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  4259. #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
  4260. #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
  4261. #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  4262. #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
  4263. #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
  4264. #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  4265. #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
  4266. #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
  4267. #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  4268. #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
  4269. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  4270. #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  4271. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  4272. #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
  4273. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
  4274. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  4275. #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
  4276. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
  4277. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  4278. #define RCC_AHB1RSTR_RNGRST_Pos (31U)
  4279. #define RCC_AHB1RSTR_RNGRST_Msk (0x1UL << RCC_AHB1RSTR_RNGRST_Pos) /*!< 0x80000000 */
  4280. #define RCC_AHB1RSTR_RNGRST RCC_AHB1RSTR_RNGRST_Msk
  4281. /******************** Bit definition for RCC_APB1RSTR register **************/
  4282. #define RCC_APB1RSTR_TIM5RST_Pos (3U)
  4283. #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
  4284. #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
  4285. #define RCC_APB1RSTR_TIM6RST_Pos (4U)
  4286. #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
  4287. #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
  4288. #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
  4289. #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
  4290. #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
  4291. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  4292. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  4293. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
  4294. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  4295. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  4296. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
  4297. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  4298. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  4299. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
  4300. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  4301. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  4302. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
  4303. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  4304. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  4305. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
  4306. #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
  4307. #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
  4308. #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
  4309. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  4310. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  4311. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
  4312. #define RCC_APB1RSTR_DACRST_Pos (29U)
  4313. #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
  4314. #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
  4315. /******************** Bit definition for RCC_APB2RSTR register **************/
  4316. #define RCC_APB2RSTR_TIM1RST_Pos (0U)
  4317. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
  4318. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  4319. #define RCC_APB2RSTR_USART1RST_Pos (4U)
  4320. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
  4321. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  4322. #define RCC_APB2RSTR_USART6RST_Pos (5U)
  4323. #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
  4324. #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
  4325. #define RCC_APB2RSTR_ADCRST_Pos (8U)
  4326. #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
  4327. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
  4328. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  4329. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  4330. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  4331. #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
  4332. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
  4333. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  4334. #define RCC_APB2RSTR_TIM9RST_Pos (16U)
  4335. #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
  4336. #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
  4337. #define RCC_APB2RSTR_TIM11RST_Pos (18U)
  4338. #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
  4339. #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
  4340. #define RCC_APB2RSTR_SPI5RST_Pos (20U)
  4341. #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
  4342. #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
  4343. /******************** Bit definition for RCC_AHB1ENR register ***************/
  4344. #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
  4345. #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  4346. #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
  4347. #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
  4348. #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  4349. #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
  4350. #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
  4351. #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  4352. #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
  4353. #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
  4354. #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  4355. #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
  4356. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  4357. #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  4358. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  4359. #define RCC_AHB1ENR_DMA1EN_Pos (21U)
  4360. #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
  4361. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  4362. #define RCC_AHB1ENR_DMA2EN_Pos (22U)
  4363. #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
  4364. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  4365. #define RCC_AHB1ENR_RNGEN_Pos (31U)
  4366. #define RCC_AHB1ENR_RNGEN_Msk (0x1UL << RCC_AHB1ENR_RNGEN_Pos) /*!< 0x80000000 */
  4367. #define RCC_AHB1ENR_RNGEN RCC_AHB1ENR_RNGEN_Msk
  4368. /******************** Bit definition for RCC_APB1ENR register ***************/
  4369. #define RCC_APB1ENR_TIM5EN_Pos (3U)
  4370. #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
  4371. #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
  4372. #define RCC_APB1ENR_TIM6EN_Pos (4U)
  4373. #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
  4374. #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
  4375. #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
  4376. #define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
  4377. #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
  4378. #define RCC_APB1ENR_RTCAPBEN_Pos (10U)
  4379. #define RCC_APB1ENR_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos) /*!< 0x00000400 */
  4380. #define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
  4381. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  4382. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  4383. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
  4384. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  4385. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  4386. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
  4387. #define RCC_APB1ENR_USART2EN_Pos (17U)
  4388. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  4389. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
  4390. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  4391. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  4392. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
  4393. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  4394. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  4395. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
  4396. #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
  4397. #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
  4398. #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
  4399. #define RCC_APB1ENR_PWREN_Pos (28U)
  4400. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  4401. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
  4402. #define RCC_APB1ENR_DACEN_Pos (29U)
  4403. #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
  4404. #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
  4405. /******************** Bit definition for RCC_APB2ENR register ***************/
  4406. #define RCC_APB2ENR_TIM1EN_Pos (0U)
  4407. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
  4408. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  4409. #define RCC_APB2ENR_USART1EN_Pos (4U)
  4410. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
  4411. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  4412. #define RCC_APB2ENR_USART6EN_Pos (5U)
  4413. #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
  4414. #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
  4415. #define RCC_APB2ENR_ADC1EN_Pos (8U)
  4416. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
  4417. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
  4418. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  4419. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  4420. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  4421. #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
  4422. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
  4423. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  4424. #define RCC_APB2ENR_EXTITEN_Pos (15U)
  4425. #define RCC_APB2ENR_EXTITEN_Msk (0x1UL << RCC_APB2ENR_EXTITEN_Pos) /*!< 0x00008000 */
  4426. #define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
  4427. #define RCC_APB2ENR_TIM9EN_Pos (16U)
  4428. #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
  4429. #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
  4430. #define RCC_APB2ENR_TIM11EN_Pos (18U)
  4431. #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
  4432. #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
  4433. #define RCC_APB2ENR_SPI5EN_Pos (20U)
  4434. #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
  4435. #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
  4436. /******************** Bit definition for RCC_AHB1LPENR register *************/
  4437. #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
  4438. #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
  4439. #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
  4440. #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
  4441. #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
  4442. #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
  4443. #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
  4444. #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
  4445. #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
  4446. #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
  4447. #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
  4448. #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
  4449. #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
  4450. #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
  4451. #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
  4452. #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
  4453. #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
  4454. #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
  4455. #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
  4456. #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
  4457. #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
  4458. #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
  4459. #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
  4460. #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
  4461. #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
  4462. #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
  4463. #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
  4464. #define RCC_AHB1LPENR_RNGLPEN_Pos (31U)
  4465. #define RCC_AHB1LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB1LPENR_RNGLPEN_Pos) /*!< 0x80000000 */
  4466. #define RCC_AHB1LPENR_RNGLPEN RCC_AHB1LPENR_RNGLPEN_Msk
  4467. /******************** Bit definition for RCC_APB1LPENR register *************/
  4468. #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
  4469. #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
  4470. #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
  4471. #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
  4472. #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
  4473. #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
  4474. #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
  4475. #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
  4476. #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
  4477. #define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
  4478. #define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
  4479. #define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
  4480. #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
  4481. #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
  4482. #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
  4483. #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
  4484. #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
  4485. #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
  4486. #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
  4487. #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
  4488. #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
  4489. #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
  4490. #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
  4491. #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
  4492. #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
  4493. #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
  4494. #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
  4495. #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
  4496. #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
  4497. #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
  4498. #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
  4499. #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
  4500. #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
  4501. #define RCC_APB1LPENR_DACLPEN_Pos (29U)
  4502. #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
  4503. #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
  4504. /******************** Bit definition for RCC_APB2LPENR register *************/
  4505. #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
  4506. #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
  4507. #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
  4508. #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
  4509. #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
  4510. #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
  4511. #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
  4512. #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
  4513. #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
  4514. #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
  4515. #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
  4516. #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
  4517. #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
  4518. #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
  4519. #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
  4520. #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
  4521. #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
  4522. #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
  4523. #define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
  4524. #define RCC_APB2LPENR_EXTITLPEN_Msk (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
  4525. #define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
  4526. #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
  4527. #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
  4528. #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
  4529. #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
  4530. #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
  4531. #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
  4532. #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
  4533. #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
  4534. #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
  4535. /******************** Bit definition for RCC_BDCR register ******************/
  4536. #define RCC_BDCR_LSEON_Pos (0U)
  4537. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  4538. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  4539. #define RCC_BDCR_LSERDY_Pos (1U)
  4540. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  4541. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  4542. #define RCC_BDCR_LSEBYP_Pos (2U)
  4543. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  4544. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  4545. #define RCC_BDCR_LSEMOD_Pos (3U)
  4546. #define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
  4547. #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
  4548. #define RCC_BDCR_RTCSEL_Pos (8U)
  4549. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  4550. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  4551. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  4552. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  4553. #define RCC_BDCR_RTCEN_Pos (15U)
  4554. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  4555. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  4556. #define RCC_BDCR_BDRST_Pos (16U)
  4557. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  4558. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  4559. /******************** Bit definition for RCC_CSR register *******************/
  4560. #define RCC_CSR_LSION_Pos (0U)
  4561. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  4562. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  4563. #define RCC_CSR_LSIRDY_Pos (1U)
  4564. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  4565. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  4566. #define RCC_CSR_RMVF_Pos (24U)
  4567. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  4568. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  4569. #define RCC_CSR_BORRSTF_Pos (25U)
  4570. #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
  4571. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  4572. #define RCC_CSR_PINRSTF_Pos (26U)
  4573. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  4574. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  4575. #define RCC_CSR_PORRSTF_Pos (27U)
  4576. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  4577. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
  4578. #define RCC_CSR_SFTRSTF_Pos (28U)
  4579. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  4580. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  4581. #define RCC_CSR_IWDGRSTF_Pos (29U)
  4582. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  4583. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  4584. #define RCC_CSR_WWDGRSTF_Pos (30U)
  4585. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  4586. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  4587. #define RCC_CSR_LPWRRSTF_Pos (31U)
  4588. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  4589. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  4590. /* Legacy defines */
  4591. #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
  4592. #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
  4593. /******************** Bit definition for RCC_SSCGR register *****************/
  4594. #define RCC_SSCGR_MODPER_Pos (0U)
  4595. #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
  4596. #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
  4597. #define RCC_SSCGR_INCSTEP_Pos (13U)
  4598. #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
  4599. #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
  4600. #define RCC_SSCGR_SPREADSEL_Pos (30U)
  4601. #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
  4602. #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
  4603. #define RCC_SSCGR_SSCGEN_Pos (31U)
  4604. #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
  4605. #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
  4606. /******************** Bit definition for RCC_DCKCFGR register ***************/
  4607. #define RCC_DCKCFGR_TIMPRE_Pos (24U)
  4608. #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
  4609. #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
  4610. #define RCC_DCKCFGR_I2SSRC_Pos (25U)
  4611. #define RCC_DCKCFGR_I2SSRC_Msk (0x3UL << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x06000000 */
  4612. #define RCC_DCKCFGR_I2SSRC RCC_DCKCFGR_I2SSRC_Msk
  4613. #define RCC_DCKCFGR_I2SSRC_0 (0x1UL << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x02000000 */
  4614. #define RCC_DCKCFGR_I2SSRC_1 (0x2UL << RCC_DCKCFGR_I2SSRC_Pos) /*!< 0x04000000 */
  4615. /******************** Bit definition for RCC_DCKCFGR2 register ***************/
  4616. #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
  4617. #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
  4618. #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
  4619. #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
  4620. #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
  4621. #define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
  4622. #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
  4623. #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
  4624. #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
  4625. #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
  4626. /******************************************************************************/
  4627. /* */
  4628. /* RNG */
  4629. /* */
  4630. /******************************************************************************/
  4631. /******************** Bits definition for RNG_CR register *******************/
  4632. #define RNG_CR_RNGEN_Pos (2U)
  4633. #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
  4634. #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
  4635. #define RNG_CR_IE_Pos (3U)
  4636. #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
  4637. #define RNG_CR_IE RNG_CR_IE_Msk
  4638. /******************** Bits definition for RNG_SR register *******************/
  4639. #define RNG_SR_DRDY_Pos (0U)
  4640. #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
  4641. #define RNG_SR_DRDY RNG_SR_DRDY_Msk
  4642. #define RNG_SR_CECS_Pos (1U)
  4643. #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
  4644. #define RNG_SR_CECS RNG_SR_CECS_Msk
  4645. #define RNG_SR_SECS_Pos (2U)
  4646. #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
  4647. #define RNG_SR_SECS RNG_SR_SECS_Msk
  4648. #define RNG_SR_CEIS_Pos (5U)
  4649. #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
  4650. #define RNG_SR_CEIS RNG_SR_CEIS_Msk
  4651. #define RNG_SR_SEIS_Pos (6U)
  4652. #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
  4653. #define RNG_SR_SEIS RNG_SR_SEIS_Msk
  4654. /******************************************************************************/
  4655. /* */
  4656. /* Real-Time Clock (RTC) */
  4657. /* */
  4658. /******************************************************************************/
  4659. /*
  4660. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  4661. */
  4662. #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
  4663. /******************** Bits definition for RTC_TR register *******************/
  4664. #define RTC_TR_PM_Pos (22U)
  4665. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  4666. #define RTC_TR_PM RTC_TR_PM_Msk
  4667. #define RTC_TR_HT_Pos (20U)
  4668. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  4669. #define RTC_TR_HT RTC_TR_HT_Msk
  4670. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  4671. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  4672. #define RTC_TR_HU_Pos (16U)
  4673. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  4674. #define RTC_TR_HU RTC_TR_HU_Msk
  4675. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  4676. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  4677. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  4678. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  4679. #define RTC_TR_MNT_Pos (12U)
  4680. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  4681. #define RTC_TR_MNT RTC_TR_MNT_Msk
  4682. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  4683. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  4684. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  4685. #define RTC_TR_MNU_Pos (8U)
  4686. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  4687. #define RTC_TR_MNU RTC_TR_MNU_Msk
  4688. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  4689. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  4690. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  4691. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  4692. #define RTC_TR_ST_Pos (4U)
  4693. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  4694. #define RTC_TR_ST RTC_TR_ST_Msk
  4695. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  4696. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  4697. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  4698. #define RTC_TR_SU_Pos (0U)
  4699. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  4700. #define RTC_TR_SU RTC_TR_SU_Msk
  4701. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  4702. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  4703. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  4704. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  4705. /******************** Bits definition for RTC_DR register *******************/
  4706. #define RTC_DR_YT_Pos (20U)
  4707. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  4708. #define RTC_DR_YT RTC_DR_YT_Msk
  4709. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  4710. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  4711. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  4712. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  4713. #define RTC_DR_YU_Pos (16U)
  4714. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  4715. #define RTC_DR_YU RTC_DR_YU_Msk
  4716. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  4717. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  4718. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  4719. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  4720. #define RTC_DR_WDU_Pos (13U)
  4721. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  4722. #define RTC_DR_WDU RTC_DR_WDU_Msk
  4723. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  4724. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  4725. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  4726. #define RTC_DR_MT_Pos (12U)
  4727. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  4728. #define RTC_DR_MT RTC_DR_MT_Msk
  4729. #define RTC_DR_MU_Pos (8U)
  4730. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  4731. #define RTC_DR_MU RTC_DR_MU_Msk
  4732. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  4733. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  4734. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  4735. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  4736. #define RTC_DR_DT_Pos (4U)
  4737. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  4738. #define RTC_DR_DT RTC_DR_DT_Msk
  4739. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  4740. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  4741. #define RTC_DR_DU_Pos (0U)
  4742. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  4743. #define RTC_DR_DU RTC_DR_DU_Msk
  4744. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  4745. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  4746. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  4747. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  4748. /******************** Bits definition for RTC_CR register *******************/
  4749. #define RTC_CR_COE_Pos (23U)
  4750. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  4751. #define RTC_CR_COE RTC_CR_COE_Msk
  4752. #define RTC_CR_OSEL_Pos (21U)
  4753. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  4754. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  4755. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  4756. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  4757. #define RTC_CR_POL_Pos (20U)
  4758. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  4759. #define RTC_CR_POL RTC_CR_POL_Msk
  4760. #define RTC_CR_COSEL_Pos (19U)
  4761. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  4762. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  4763. #define RTC_CR_BKP_Pos (18U)
  4764. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  4765. #define RTC_CR_BKP RTC_CR_BKP_Msk
  4766. #define RTC_CR_SUB1H_Pos (17U)
  4767. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  4768. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  4769. #define RTC_CR_ADD1H_Pos (16U)
  4770. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  4771. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  4772. #define RTC_CR_TSIE_Pos (15U)
  4773. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  4774. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  4775. #define RTC_CR_WUTIE_Pos (14U)
  4776. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  4777. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  4778. #define RTC_CR_ALRBIE_Pos (13U)
  4779. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  4780. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  4781. #define RTC_CR_ALRAIE_Pos (12U)
  4782. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  4783. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  4784. #define RTC_CR_TSE_Pos (11U)
  4785. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  4786. #define RTC_CR_TSE RTC_CR_TSE_Msk
  4787. #define RTC_CR_WUTE_Pos (10U)
  4788. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  4789. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  4790. #define RTC_CR_ALRBE_Pos (9U)
  4791. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  4792. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  4793. #define RTC_CR_ALRAE_Pos (8U)
  4794. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  4795. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  4796. #define RTC_CR_DCE_Pos (7U)
  4797. #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */
  4798. #define RTC_CR_DCE RTC_CR_DCE_Msk
  4799. #define RTC_CR_FMT_Pos (6U)
  4800. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  4801. #define RTC_CR_FMT RTC_CR_FMT_Msk
  4802. #define RTC_CR_BYPSHAD_Pos (5U)
  4803. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  4804. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  4805. #define RTC_CR_REFCKON_Pos (4U)
  4806. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  4807. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  4808. #define RTC_CR_TSEDGE_Pos (3U)
  4809. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  4810. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  4811. #define RTC_CR_WUCKSEL_Pos (0U)
  4812. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  4813. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  4814. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  4815. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  4816. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  4817. /* Legacy defines */
  4818. #define RTC_CR_BCK RTC_CR_BKP
  4819. /******************** Bits definition for RTC_ISR register ******************/
  4820. #define RTC_ISR_RECALPF_Pos (16U)
  4821. #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  4822. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  4823. #define RTC_ISR_TAMP1F_Pos (13U)
  4824. #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  4825. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  4826. #define RTC_ISR_TAMP2F_Pos (14U)
  4827. #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  4828. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  4829. #define RTC_ISR_TSOVF_Pos (12U)
  4830. #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  4831. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  4832. #define RTC_ISR_TSF_Pos (11U)
  4833. #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  4834. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  4835. #define RTC_ISR_WUTF_Pos (10U)
  4836. #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  4837. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  4838. #define RTC_ISR_ALRBF_Pos (9U)
  4839. #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  4840. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  4841. #define RTC_ISR_ALRAF_Pos (8U)
  4842. #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  4843. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  4844. #define RTC_ISR_INIT_Pos (7U)
  4845. #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  4846. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  4847. #define RTC_ISR_INITF_Pos (6U)
  4848. #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  4849. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  4850. #define RTC_ISR_RSF_Pos (5U)
  4851. #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  4852. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  4853. #define RTC_ISR_INITS_Pos (4U)
  4854. #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  4855. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  4856. #define RTC_ISR_SHPF_Pos (3U)
  4857. #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  4858. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  4859. #define RTC_ISR_WUTWF_Pos (2U)
  4860. #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  4861. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  4862. #define RTC_ISR_ALRBWF_Pos (1U)
  4863. #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  4864. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  4865. #define RTC_ISR_ALRAWF_Pos (0U)
  4866. #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  4867. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  4868. /******************** Bits definition for RTC_PRER register *****************/
  4869. #define RTC_PRER_PREDIV_A_Pos (16U)
  4870. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  4871. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  4872. #define RTC_PRER_PREDIV_S_Pos (0U)
  4873. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  4874. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  4875. /******************** Bits definition for RTC_WUTR register *****************/
  4876. #define RTC_WUTR_WUT_Pos (0U)
  4877. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  4878. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  4879. /******************** Bits definition for RTC_CALIBR register ***************/
  4880. #define RTC_CALIBR_DCS_Pos (7U)
  4881. #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
  4882. #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
  4883. #define RTC_CALIBR_DC_Pos (0U)
  4884. #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
  4885. #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
  4886. /******************** Bits definition for RTC_ALRMAR register ***************/
  4887. #define RTC_ALRMAR_MSK4_Pos (31U)
  4888. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  4889. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  4890. #define RTC_ALRMAR_WDSEL_Pos (30U)
  4891. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  4892. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  4893. #define RTC_ALRMAR_DT_Pos (28U)
  4894. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  4895. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  4896. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  4897. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  4898. #define RTC_ALRMAR_DU_Pos (24U)
  4899. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  4900. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  4901. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  4902. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  4903. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  4904. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  4905. #define RTC_ALRMAR_MSK3_Pos (23U)
  4906. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  4907. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  4908. #define RTC_ALRMAR_PM_Pos (22U)
  4909. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  4910. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  4911. #define RTC_ALRMAR_HT_Pos (20U)
  4912. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  4913. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  4914. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  4915. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  4916. #define RTC_ALRMAR_HU_Pos (16U)
  4917. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  4918. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  4919. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  4920. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  4921. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  4922. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  4923. #define RTC_ALRMAR_MSK2_Pos (15U)
  4924. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  4925. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  4926. #define RTC_ALRMAR_MNT_Pos (12U)
  4927. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  4928. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  4929. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  4930. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  4931. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  4932. #define RTC_ALRMAR_MNU_Pos (8U)
  4933. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  4934. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  4935. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  4936. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  4937. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  4938. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  4939. #define RTC_ALRMAR_MSK1_Pos (7U)
  4940. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  4941. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  4942. #define RTC_ALRMAR_ST_Pos (4U)
  4943. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  4944. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  4945. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  4946. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  4947. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  4948. #define RTC_ALRMAR_SU_Pos (0U)
  4949. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  4950. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  4951. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  4952. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  4953. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  4954. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  4955. /******************** Bits definition for RTC_ALRMBR register ***************/
  4956. #define RTC_ALRMBR_MSK4_Pos (31U)
  4957. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  4958. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  4959. #define RTC_ALRMBR_WDSEL_Pos (30U)
  4960. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  4961. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  4962. #define RTC_ALRMBR_DT_Pos (28U)
  4963. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  4964. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  4965. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  4966. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  4967. #define RTC_ALRMBR_DU_Pos (24U)
  4968. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  4969. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  4970. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  4971. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  4972. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  4973. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  4974. #define RTC_ALRMBR_MSK3_Pos (23U)
  4975. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  4976. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  4977. #define RTC_ALRMBR_PM_Pos (22U)
  4978. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  4979. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  4980. #define RTC_ALRMBR_HT_Pos (20U)
  4981. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  4982. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  4983. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  4984. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  4985. #define RTC_ALRMBR_HU_Pos (16U)
  4986. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  4987. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  4988. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  4989. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  4990. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  4991. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  4992. #define RTC_ALRMBR_MSK2_Pos (15U)
  4993. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  4994. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  4995. #define RTC_ALRMBR_MNT_Pos (12U)
  4996. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  4997. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  4998. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  4999. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  5000. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  5001. #define RTC_ALRMBR_MNU_Pos (8U)
  5002. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  5003. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  5004. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  5005. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  5006. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  5007. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  5008. #define RTC_ALRMBR_MSK1_Pos (7U)
  5009. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  5010. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  5011. #define RTC_ALRMBR_ST_Pos (4U)
  5012. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  5013. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  5014. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  5015. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  5016. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  5017. #define RTC_ALRMBR_SU_Pos (0U)
  5018. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  5019. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  5020. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  5021. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  5022. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  5023. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  5024. /******************** Bits definition for RTC_WPR register ******************/
  5025. #define RTC_WPR_KEY_Pos (0U)
  5026. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  5027. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  5028. /******************** Bits definition for RTC_SSR register ******************/
  5029. #define RTC_SSR_SS_Pos (0U)
  5030. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  5031. #define RTC_SSR_SS RTC_SSR_SS_Msk
  5032. /******************** Bits definition for RTC_SHIFTR register ***************/
  5033. #define RTC_SHIFTR_SUBFS_Pos (0U)
  5034. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  5035. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  5036. #define RTC_SHIFTR_ADD1S_Pos (31U)
  5037. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  5038. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  5039. /******************** Bits definition for RTC_TSTR register *****************/
  5040. #define RTC_TSTR_PM_Pos (22U)
  5041. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  5042. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  5043. #define RTC_TSTR_HT_Pos (20U)
  5044. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  5045. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  5046. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  5047. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  5048. #define RTC_TSTR_HU_Pos (16U)
  5049. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  5050. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  5051. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  5052. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  5053. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  5054. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  5055. #define RTC_TSTR_MNT_Pos (12U)
  5056. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  5057. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  5058. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  5059. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  5060. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  5061. #define RTC_TSTR_MNU_Pos (8U)
  5062. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  5063. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  5064. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  5065. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  5066. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  5067. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  5068. #define RTC_TSTR_ST_Pos (4U)
  5069. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  5070. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  5071. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  5072. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  5073. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  5074. #define RTC_TSTR_SU_Pos (0U)
  5075. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  5076. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  5077. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  5078. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  5079. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  5080. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  5081. /******************** Bits definition for RTC_TSDR register *****************/
  5082. #define RTC_TSDR_WDU_Pos (13U)
  5083. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  5084. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  5085. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  5086. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  5087. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  5088. #define RTC_TSDR_MT_Pos (12U)
  5089. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  5090. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  5091. #define RTC_TSDR_MU_Pos (8U)
  5092. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  5093. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  5094. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  5095. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  5096. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  5097. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  5098. #define RTC_TSDR_DT_Pos (4U)
  5099. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  5100. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  5101. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  5102. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  5103. #define RTC_TSDR_DU_Pos (0U)
  5104. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  5105. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  5106. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  5107. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  5108. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  5109. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  5110. /******************** Bits definition for RTC_TSSSR register ****************/
  5111. #define RTC_TSSSR_SS_Pos (0U)
  5112. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  5113. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  5114. /******************** Bits definition for RTC_CAL register *****************/
  5115. #define RTC_CALR_CALP_Pos (15U)
  5116. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  5117. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  5118. #define RTC_CALR_CALW8_Pos (14U)
  5119. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  5120. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  5121. #define RTC_CALR_CALW16_Pos (13U)
  5122. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  5123. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  5124. #define RTC_CALR_CALM_Pos (0U)
  5125. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  5126. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  5127. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  5128. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  5129. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  5130. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  5131. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  5132. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  5133. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  5134. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  5135. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  5136. /******************** Bits definition for RTC_TAFCR register ****************/
  5137. #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
  5138. #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
  5139. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
  5140. #define RTC_TAFCR_TSINSEL_Pos (17U)
  5141. #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
  5142. #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
  5143. #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
  5144. #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
  5145. #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
  5146. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  5147. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  5148. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  5149. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  5150. #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  5151. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  5152. #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  5153. #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  5154. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  5155. #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  5156. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  5157. #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  5158. #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  5159. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  5160. #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  5161. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  5162. #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  5163. #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  5164. #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  5165. #define RTC_TAFCR_TAMPTS_Pos (7U)
  5166. #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  5167. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  5168. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  5169. #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  5170. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  5171. #define RTC_TAFCR_TAMP2E_Pos (3U)
  5172. #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  5173. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  5174. #define RTC_TAFCR_TAMPIE_Pos (2U)
  5175. #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  5176. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  5177. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  5178. #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  5179. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  5180. #define RTC_TAFCR_TAMP1E_Pos (0U)
  5181. #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  5182. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  5183. /* Legacy defines */
  5184. #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
  5185. /******************** Bits definition for RTC_ALRMASSR register *************/
  5186. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  5187. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  5188. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  5189. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  5190. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  5191. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  5192. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  5193. #define RTC_ALRMASSR_SS_Pos (0U)
  5194. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  5195. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  5196. /******************** Bits definition for RTC_ALRMBSSR register *************/
  5197. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  5198. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  5199. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  5200. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  5201. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  5202. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  5203. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  5204. #define RTC_ALRMBSSR_SS_Pos (0U)
  5205. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  5206. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  5207. /******************** Bits definition for RTC_BKP0R register ****************/
  5208. #define RTC_BKP0R_Pos (0U)
  5209. #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  5210. #define RTC_BKP0R RTC_BKP0R_Msk
  5211. /******************** Bits definition for RTC_BKP1R register ****************/
  5212. #define RTC_BKP1R_Pos (0U)
  5213. #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  5214. #define RTC_BKP1R RTC_BKP1R_Msk
  5215. /******************** Bits definition for RTC_BKP2R register ****************/
  5216. #define RTC_BKP2R_Pos (0U)
  5217. #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  5218. #define RTC_BKP2R RTC_BKP2R_Msk
  5219. /******************** Bits definition for RTC_BKP3R register ****************/
  5220. #define RTC_BKP3R_Pos (0U)
  5221. #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  5222. #define RTC_BKP3R RTC_BKP3R_Msk
  5223. /******************** Bits definition for RTC_BKP4R register ****************/
  5224. #define RTC_BKP4R_Pos (0U)
  5225. #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  5226. #define RTC_BKP4R RTC_BKP4R_Msk
  5227. /******************** Bits definition for RTC_BKP5R register ****************/
  5228. #define RTC_BKP5R_Pos (0U)
  5229. #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  5230. #define RTC_BKP5R RTC_BKP5R_Msk
  5231. /******************** Bits definition for RTC_BKP6R register ****************/
  5232. #define RTC_BKP6R_Pos (0U)
  5233. #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  5234. #define RTC_BKP6R RTC_BKP6R_Msk
  5235. /******************** Bits definition for RTC_BKP7R register ****************/
  5236. #define RTC_BKP7R_Pos (0U)
  5237. #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  5238. #define RTC_BKP7R RTC_BKP7R_Msk
  5239. /******************** Bits definition for RTC_BKP8R register ****************/
  5240. #define RTC_BKP8R_Pos (0U)
  5241. #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  5242. #define RTC_BKP8R RTC_BKP8R_Msk
  5243. /******************** Bits definition for RTC_BKP9R register ****************/
  5244. #define RTC_BKP9R_Pos (0U)
  5245. #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  5246. #define RTC_BKP9R RTC_BKP9R_Msk
  5247. /******************** Bits definition for RTC_BKP10R register ***************/
  5248. #define RTC_BKP10R_Pos (0U)
  5249. #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  5250. #define RTC_BKP10R RTC_BKP10R_Msk
  5251. /******************** Bits definition for RTC_BKP11R register ***************/
  5252. #define RTC_BKP11R_Pos (0U)
  5253. #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  5254. #define RTC_BKP11R RTC_BKP11R_Msk
  5255. /******************** Bits definition for RTC_BKP12R register ***************/
  5256. #define RTC_BKP12R_Pos (0U)
  5257. #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  5258. #define RTC_BKP12R RTC_BKP12R_Msk
  5259. /******************** Bits definition for RTC_BKP13R register ***************/
  5260. #define RTC_BKP13R_Pos (0U)
  5261. #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  5262. #define RTC_BKP13R RTC_BKP13R_Msk
  5263. /******************** Bits definition for RTC_BKP14R register ***************/
  5264. #define RTC_BKP14R_Pos (0U)
  5265. #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  5266. #define RTC_BKP14R RTC_BKP14R_Msk
  5267. /******************** Bits definition for RTC_BKP15R register ***************/
  5268. #define RTC_BKP15R_Pos (0U)
  5269. #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  5270. #define RTC_BKP15R RTC_BKP15R_Msk
  5271. /******************** Bits definition for RTC_BKP16R register ***************/
  5272. #define RTC_BKP16R_Pos (0U)
  5273. #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  5274. #define RTC_BKP16R RTC_BKP16R_Msk
  5275. /******************** Bits definition for RTC_BKP17R register ***************/
  5276. #define RTC_BKP17R_Pos (0U)
  5277. #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  5278. #define RTC_BKP17R RTC_BKP17R_Msk
  5279. /******************** Bits definition for RTC_BKP18R register ***************/
  5280. #define RTC_BKP18R_Pos (0U)
  5281. #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  5282. #define RTC_BKP18R RTC_BKP18R_Msk
  5283. /******************** Bits definition for RTC_BKP19R register ***************/
  5284. #define RTC_BKP19R_Pos (0U)
  5285. #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  5286. #define RTC_BKP19R RTC_BKP19R_Msk
  5287. /******************** Number of backup registers ******************************/
  5288. #define RTC_BKP_NUMBER 0x000000014U
  5289. /******************************************************************************/
  5290. /* */
  5291. /* Serial Peripheral Interface */
  5292. /* */
  5293. /******************************************************************************/
  5294. /******************* Bit definition for SPI_CR1 register ********************/
  5295. #define SPI_CR1_CPHA_Pos (0U)
  5296. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  5297. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  5298. #define SPI_CR1_CPOL_Pos (1U)
  5299. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  5300. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  5301. #define SPI_CR1_MSTR_Pos (2U)
  5302. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  5303. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  5304. #define SPI_CR1_BR_Pos (3U)
  5305. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  5306. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  5307. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  5308. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  5309. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  5310. #define SPI_CR1_SPE_Pos (6U)
  5311. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  5312. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  5313. #define SPI_CR1_LSBFIRST_Pos (7U)
  5314. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  5315. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  5316. #define SPI_CR1_SSI_Pos (8U)
  5317. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  5318. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  5319. #define SPI_CR1_SSM_Pos (9U)
  5320. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  5321. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  5322. #define SPI_CR1_RXONLY_Pos (10U)
  5323. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  5324. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  5325. #define SPI_CR1_DFF_Pos (11U)
  5326. #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
  5327. #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
  5328. #define SPI_CR1_CRCNEXT_Pos (12U)
  5329. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  5330. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  5331. #define SPI_CR1_CRCEN_Pos (13U)
  5332. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  5333. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  5334. #define SPI_CR1_BIDIOE_Pos (14U)
  5335. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  5336. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  5337. #define SPI_CR1_BIDIMODE_Pos (15U)
  5338. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  5339. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  5340. /******************* Bit definition for SPI_CR2 register ********************/
  5341. #define SPI_CR2_RXDMAEN_Pos (0U)
  5342. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  5343. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
  5344. #define SPI_CR2_TXDMAEN_Pos (1U)
  5345. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  5346. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
  5347. #define SPI_CR2_SSOE_Pos (2U)
  5348. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  5349. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
  5350. #define SPI_CR2_FRF_Pos (4U)
  5351. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  5352. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
  5353. #define SPI_CR2_ERRIE_Pos (5U)
  5354. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  5355. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
  5356. #define SPI_CR2_RXNEIE_Pos (6U)
  5357. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  5358. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
  5359. #define SPI_CR2_TXEIE_Pos (7U)
  5360. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  5361. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
  5362. /******************** Bit definition for SPI_SR register ********************/
  5363. #define SPI_SR_RXNE_Pos (0U)
  5364. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  5365. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
  5366. #define SPI_SR_TXE_Pos (1U)
  5367. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  5368. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
  5369. #define SPI_SR_CHSIDE_Pos (2U)
  5370. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  5371. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
  5372. #define SPI_SR_UDR_Pos (3U)
  5373. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  5374. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
  5375. #define SPI_SR_CRCERR_Pos (4U)
  5376. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  5377. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
  5378. #define SPI_SR_MODF_Pos (5U)
  5379. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  5380. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
  5381. #define SPI_SR_OVR_Pos (6U)
  5382. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  5383. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
  5384. #define SPI_SR_BSY_Pos (7U)
  5385. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  5386. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
  5387. #define SPI_SR_FRE_Pos (8U)
  5388. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  5389. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
  5390. /******************** Bit definition for SPI_DR register ********************/
  5391. #define SPI_DR_DR_Pos (0U)
  5392. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  5393. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  5394. /******************* Bit definition for SPI_CRCPR register ******************/
  5395. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  5396. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  5397. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  5398. /****************** Bit definition for SPI_RXCRCR register ******************/
  5399. #define SPI_RXCRCR_RXCRC_Pos (0U)
  5400. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  5401. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  5402. /****************** Bit definition for SPI_TXCRCR register ******************/
  5403. #define SPI_TXCRCR_TXCRC_Pos (0U)
  5404. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  5405. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  5406. /****************** Bit definition for SPI_I2SCFGR register *****************/
  5407. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  5408. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  5409. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  5410. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  5411. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  5412. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  5413. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  5414. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  5415. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  5416. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  5417. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  5418. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  5419. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  5420. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  5421. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  5422. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  5423. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  5424. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  5425. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  5426. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  5427. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  5428. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  5429. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  5430. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  5431. #define SPI_I2SCFGR_I2SE_Pos (10U)
  5432. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  5433. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  5434. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  5435. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  5436. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  5437. /****************** Bit definition for SPI_I2SPR register *******************/
  5438. #define SPI_I2SPR_I2SDIV_Pos (0U)
  5439. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  5440. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  5441. #define SPI_I2SPR_ODD_Pos (8U)
  5442. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  5443. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  5444. #define SPI_I2SPR_MCKOE_Pos (9U)
  5445. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  5446. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  5447. /******************************************************************************/
  5448. /* */
  5449. /* SYSCFG */
  5450. /* */
  5451. /******************************************************************************/
  5452. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  5453. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  5454. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
  5455. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  5456. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  5457. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  5458. /****************** Bit definition for SYSCFG_PMC register ******************/
  5459. #define SYSCFG_PMC_ADC1DC2_Pos (16U)
  5460. #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
  5461. #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  5462. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  5463. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  5464. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  5465. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  5466. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  5467. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  5468. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  5469. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  5470. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  5471. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  5472. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  5473. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  5474. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  5475. /**
  5476. * @brief EXTI0 configuration
  5477. */
  5478. #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
  5479. #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
  5480. #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
  5481. #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
  5482. /**
  5483. * @brief EXTI1 configuration
  5484. */
  5485. #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
  5486. #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
  5487. #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
  5488. #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
  5489. /**
  5490. * @brief EXTI2 configuration
  5491. */
  5492. #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
  5493. #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
  5494. #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
  5495. #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
  5496. /**
  5497. * @brief EXTI3 configuration
  5498. */
  5499. #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
  5500. #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
  5501. #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
  5502. #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
  5503. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  5504. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  5505. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  5506. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  5507. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  5508. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  5509. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  5510. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  5511. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  5512. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  5513. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  5514. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  5515. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  5516. /**
  5517. * @brief EXTI4 configuration
  5518. */
  5519. #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
  5520. #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
  5521. #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
  5522. #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
  5523. /**
  5524. * @brief EXTI5 configuration
  5525. */
  5526. #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
  5527. #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
  5528. #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
  5529. #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
  5530. /**
  5531. * @brief EXTI6 configuration
  5532. */
  5533. #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
  5534. #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
  5535. #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
  5536. #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
  5537. /**
  5538. * @brief EXTI7 configuration
  5539. */
  5540. #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
  5541. #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
  5542. #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
  5543. #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
  5544. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  5545. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  5546. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  5547. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  5548. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  5549. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  5550. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  5551. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  5552. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  5553. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  5554. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  5555. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  5556. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  5557. /**
  5558. * @brief EXTI8 configuration
  5559. */
  5560. #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
  5561. #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
  5562. #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
  5563. #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
  5564. /**
  5565. * @brief EXTI9 configuration
  5566. */
  5567. #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
  5568. #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
  5569. #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
  5570. #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
  5571. /**
  5572. * @brief EXTI10 configuration
  5573. */
  5574. #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
  5575. #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
  5576. #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
  5577. #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
  5578. /**
  5579. * @brief EXTI11 configuration
  5580. */
  5581. #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
  5582. #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
  5583. #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
  5584. #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
  5585. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  5586. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  5587. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  5588. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  5589. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  5590. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  5591. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  5592. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  5593. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  5594. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  5595. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  5596. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  5597. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  5598. /**
  5599. * @brief EXTI12 configuration
  5600. */
  5601. #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
  5602. #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
  5603. #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
  5604. #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
  5605. /**
  5606. * @brief EXTI13 configuration
  5607. */
  5608. #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
  5609. #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
  5610. #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
  5611. #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
  5612. /**
  5613. * @brief EXTI14 configuration
  5614. */
  5615. #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
  5616. #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
  5617. #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
  5618. #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
  5619. /**
  5620. * @brief EXTI15 configuration
  5621. */
  5622. #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
  5623. #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
  5624. #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
  5625. #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
  5626. /****************** Bit definition for SYSCFG_CMPCR register ****************/
  5627. #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
  5628. #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
  5629. #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
  5630. #define SYSCFG_CMPCR_READY_Pos (8U)
  5631. #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
  5632. #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
  5633. /****************** Bit definition for SYSCFG_CFGR register *****************/
  5634. #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
  5635. #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
  5636. #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
  5637. #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
  5638. #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
  5639. #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
  5640. /****************** Bit definition for SYSCFG_CFGR2 register *****************/
  5641. #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
  5642. #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
  5643. #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */
  5644. #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
  5645. #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
  5646. #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */
  5647. /******************************************************************************/
  5648. /* */
  5649. /* TIM */
  5650. /* */
  5651. /******************************************************************************/
  5652. /******************* Bit definition for TIM_CR1 register ********************/
  5653. #define TIM_CR1_CEN_Pos (0U)
  5654. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  5655. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  5656. #define TIM_CR1_UDIS_Pos (1U)
  5657. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  5658. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  5659. #define TIM_CR1_URS_Pos (2U)
  5660. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  5661. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  5662. #define TIM_CR1_OPM_Pos (3U)
  5663. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  5664. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  5665. #define TIM_CR1_DIR_Pos (4U)
  5666. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  5667. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  5668. #define TIM_CR1_CMS_Pos (5U)
  5669. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  5670. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  5671. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
  5672. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
  5673. #define TIM_CR1_ARPE_Pos (7U)
  5674. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  5675. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  5676. #define TIM_CR1_CKD_Pos (8U)
  5677. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  5678. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  5679. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
  5680. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
  5681. /******************* Bit definition for TIM_CR2 register ********************/
  5682. #define TIM_CR2_CCPC_Pos (0U)
  5683. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  5684. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  5685. #define TIM_CR2_CCUS_Pos (2U)
  5686. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  5687. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  5688. #define TIM_CR2_CCDS_Pos (3U)
  5689. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  5690. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  5691. #define TIM_CR2_MMS_Pos (4U)
  5692. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  5693. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  5694. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
  5695. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
  5696. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
  5697. #define TIM_CR2_TI1S_Pos (7U)
  5698. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  5699. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  5700. #define TIM_CR2_OIS1_Pos (8U)
  5701. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  5702. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  5703. #define TIM_CR2_OIS1N_Pos (9U)
  5704. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  5705. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  5706. #define TIM_CR2_OIS2_Pos (10U)
  5707. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  5708. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  5709. #define TIM_CR2_OIS2N_Pos (11U)
  5710. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  5711. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  5712. #define TIM_CR2_OIS3_Pos (12U)
  5713. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  5714. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  5715. #define TIM_CR2_OIS3N_Pos (13U)
  5716. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  5717. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  5718. #define TIM_CR2_OIS4_Pos (14U)
  5719. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  5720. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  5721. /******************* Bit definition for TIM_SMCR register *******************/
  5722. #define TIM_SMCR_SMS_Pos (0U)
  5723. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  5724. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  5725. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
  5726. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
  5727. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
  5728. #define TIM_SMCR_TS_Pos (4U)
  5729. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  5730. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  5731. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
  5732. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
  5733. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
  5734. #define TIM_SMCR_MSM_Pos (7U)
  5735. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  5736. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  5737. #define TIM_SMCR_ETF_Pos (8U)
  5738. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  5739. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  5740. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
  5741. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
  5742. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
  5743. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
  5744. #define TIM_SMCR_ETPS_Pos (12U)
  5745. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  5746. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  5747. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
  5748. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
  5749. #define TIM_SMCR_ECE_Pos (14U)
  5750. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  5751. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  5752. #define TIM_SMCR_ETP_Pos (15U)
  5753. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  5754. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  5755. /******************* Bit definition for TIM_DIER register *******************/
  5756. #define TIM_DIER_UIE_Pos (0U)
  5757. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  5758. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  5759. #define TIM_DIER_CC1IE_Pos (1U)
  5760. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  5761. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  5762. #define TIM_DIER_CC2IE_Pos (2U)
  5763. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  5764. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  5765. #define TIM_DIER_CC3IE_Pos (3U)
  5766. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  5767. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  5768. #define TIM_DIER_CC4IE_Pos (4U)
  5769. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  5770. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  5771. #define TIM_DIER_COMIE_Pos (5U)
  5772. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  5773. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  5774. #define TIM_DIER_TIE_Pos (6U)
  5775. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  5776. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  5777. #define TIM_DIER_BIE_Pos (7U)
  5778. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  5779. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  5780. #define TIM_DIER_UDE_Pos (8U)
  5781. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  5782. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  5783. #define TIM_DIER_CC1DE_Pos (9U)
  5784. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  5785. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  5786. #define TIM_DIER_CC2DE_Pos (10U)
  5787. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  5788. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  5789. #define TIM_DIER_CC3DE_Pos (11U)
  5790. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  5791. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  5792. #define TIM_DIER_CC4DE_Pos (12U)
  5793. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  5794. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  5795. #define TIM_DIER_COMDE_Pos (13U)
  5796. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  5797. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  5798. #define TIM_DIER_TDE_Pos (14U)
  5799. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  5800. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  5801. /******************** Bit definition for TIM_SR register ********************/
  5802. #define TIM_SR_UIF_Pos (0U)
  5803. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  5804. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  5805. #define TIM_SR_CC1IF_Pos (1U)
  5806. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  5807. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  5808. #define TIM_SR_CC2IF_Pos (2U)
  5809. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  5810. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  5811. #define TIM_SR_CC3IF_Pos (3U)
  5812. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  5813. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  5814. #define TIM_SR_CC4IF_Pos (4U)
  5815. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  5816. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  5817. #define TIM_SR_COMIF_Pos (5U)
  5818. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  5819. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  5820. #define TIM_SR_TIF_Pos (6U)
  5821. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  5822. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  5823. #define TIM_SR_BIF_Pos (7U)
  5824. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  5825. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  5826. #define TIM_SR_CC1OF_Pos (9U)
  5827. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  5828. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  5829. #define TIM_SR_CC2OF_Pos (10U)
  5830. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  5831. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  5832. #define TIM_SR_CC3OF_Pos (11U)
  5833. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  5834. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  5835. #define TIM_SR_CC4OF_Pos (12U)
  5836. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  5837. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  5838. /******************* Bit definition for TIM_EGR register ********************/
  5839. #define TIM_EGR_UG_Pos (0U)
  5840. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  5841. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  5842. #define TIM_EGR_CC1G_Pos (1U)
  5843. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  5844. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  5845. #define TIM_EGR_CC2G_Pos (2U)
  5846. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  5847. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  5848. #define TIM_EGR_CC3G_Pos (3U)
  5849. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  5850. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  5851. #define TIM_EGR_CC4G_Pos (4U)
  5852. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  5853. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  5854. #define TIM_EGR_COMG_Pos (5U)
  5855. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  5856. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  5857. #define TIM_EGR_TG_Pos (6U)
  5858. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  5859. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  5860. #define TIM_EGR_BG_Pos (7U)
  5861. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  5862. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  5863. /****************** Bit definition for TIM_CCMR1 register *******************/
  5864. #define TIM_CCMR1_CC1S_Pos (0U)
  5865. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  5866. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  5867. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
  5868. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
  5869. #define TIM_CCMR1_OC1FE_Pos (2U)
  5870. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  5871. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  5872. #define TIM_CCMR1_OC1PE_Pos (3U)
  5873. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  5874. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  5875. #define TIM_CCMR1_OC1M_Pos (4U)
  5876. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  5877. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  5878. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
  5879. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
  5880. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
  5881. #define TIM_CCMR1_OC1CE_Pos (7U)
  5882. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  5883. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  5884. #define TIM_CCMR1_CC2S_Pos (8U)
  5885. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  5886. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  5887. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
  5888. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
  5889. #define TIM_CCMR1_OC2FE_Pos (10U)
  5890. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  5891. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  5892. #define TIM_CCMR1_OC2PE_Pos (11U)
  5893. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  5894. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  5895. #define TIM_CCMR1_OC2M_Pos (12U)
  5896. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  5897. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  5898. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
  5899. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
  5900. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
  5901. #define TIM_CCMR1_OC2CE_Pos (15U)
  5902. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  5903. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  5904. /*----------------------------------------------------------------------------*/
  5905. #define TIM_CCMR1_IC1PSC_Pos (2U)
  5906. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  5907. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  5908. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
  5909. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
  5910. #define TIM_CCMR1_IC1F_Pos (4U)
  5911. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  5912. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  5913. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
  5914. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
  5915. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
  5916. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
  5917. #define TIM_CCMR1_IC2PSC_Pos (10U)
  5918. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  5919. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  5920. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
  5921. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
  5922. #define TIM_CCMR1_IC2F_Pos (12U)
  5923. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  5924. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  5925. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
  5926. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
  5927. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
  5928. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
  5929. /****************** Bit definition for TIM_CCMR2 register *******************/
  5930. #define TIM_CCMR2_CC3S_Pos (0U)
  5931. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  5932. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  5933. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
  5934. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
  5935. #define TIM_CCMR2_OC3FE_Pos (2U)
  5936. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  5937. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  5938. #define TIM_CCMR2_OC3PE_Pos (3U)
  5939. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  5940. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  5941. #define TIM_CCMR2_OC3M_Pos (4U)
  5942. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  5943. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  5944. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
  5945. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
  5946. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
  5947. #define TIM_CCMR2_OC3CE_Pos (7U)
  5948. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  5949. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  5950. #define TIM_CCMR2_CC4S_Pos (8U)
  5951. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  5952. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  5953. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
  5954. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
  5955. #define TIM_CCMR2_OC4FE_Pos (10U)
  5956. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  5957. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  5958. #define TIM_CCMR2_OC4PE_Pos (11U)
  5959. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  5960. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  5961. #define TIM_CCMR2_OC4M_Pos (12U)
  5962. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  5963. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  5964. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
  5965. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
  5966. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
  5967. #define TIM_CCMR2_OC4CE_Pos (15U)
  5968. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  5969. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  5970. /*----------------------------------------------------------------------------*/
  5971. #define TIM_CCMR2_IC3PSC_Pos (2U)
  5972. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  5973. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  5974. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
  5975. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
  5976. #define TIM_CCMR2_IC3F_Pos (4U)
  5977. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  5978. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  5979. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
  5980. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
  5981. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
  5982. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
  5983. #define TIM_CCMR2_IC4PSC_Pos (10U)
  5984. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  5985. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  5986. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
  5987. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
  5988. #define TIM_CCMR2_IC4F_Pos (12U)
  5989. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  5990. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  5991. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
  5992. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
  5993. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
  5994. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
  5995. /******************* Bit definition for TIM_CCER register *******************/
  5996. #define TIM_CCER_CC1E_Pos (0U)
  5997. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  5998. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  5999. #define TIM_CCER_CC1P_Pos (1U)
  6000. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  6001. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  6002. #define TIM_CCER_CC1NE_Pos (2U)
  6003. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  6004. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  6005. #define TIM_CCER_CC1NP_Pos (3U)
  6006. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  6007. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  6008. #define TIM_CCER_CC2E_Pos (4U)
  6009. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  6010. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  6011. #define TIM_CCER_CC2P_Pos (5U)
  6012. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  6013. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  6014. #define TIM_CCER_CC2NE_Pos (6U)
  6015. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  6016. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  6017. #define TIM_CCER_CC2NP_Pos (7U)
  6018. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  6019. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  6020. #define TIM_CCER_CC3E_Pos (8U)
  6021. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  6022. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  6023. #define TIM_CCER_CC3P_Pos (9U)
  6024. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  6025. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  6026. #define TIM_CCER_CC3NE_Pos (10U)
  6027. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  6028. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  6029. #define TIM_CCER_CC3NP_Pos (11U)
  6030. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  6031. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  6032. #define TIM_CCER_CC4E_Pos (12U)
  6033. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  6034. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  6035. #define TIM_CCER_CC4P_Pos (13U)
  6036. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  6037. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  6038. #define TIM_CCER_CC4NP_Pos (15U)
  6039. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  6040. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  6041. /******************* Bit definition for TIM_CNT register ********************/
  6042. #define TIM_CNT_CNT_Pos (0U)
  6043. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  6044. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  6045. /******************* Bit definition for TIM_PSC register ********************/
  6046. #define TIM_PSC_PSC_Pos (0U)
  6047. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  6048. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  6049. /******************* Bit definition for TIM_ARR register ********************/
  6050. #define TIM_ARR_ARR_Pos (0U)
  6051. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  6052. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  6053. /******************* Bit definition for TIM_RCR register ********************/
  6054. #define TIM_RCR_REP_Pos (0U)
  6055. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  6056. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  6057. /******************* Bit definition for TIM_CCR1 register *******************/
  6058. #define TIM_CCR1_CCR1_Pos (0U)
  6059. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  6060. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  6061. /******************* Bit definition for TIM_CCR2 register *******************/
  6062. #define TIM_CCR2_CCR2_Pos (0U)
  6063. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  6064. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  6065. /******************* Bit definition for TIM_CCR3 register *******************/
  6066. #define TIM_CCR3_CCR3_Pos (0U)
  6067. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  6068. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  6069. /******************* Bit definition for TIM_CCR4 register *******************/
  6070. #define TIM_CCR4_CCR4_Pos (0U)
  6071. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  6072. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  6073. /******************* Bit definition for TIM_BDTR register *******************/
  6074. #define TIM_BDTR_DTG_Pos (0U)
  6075. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  6076. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  6077. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
  6078. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
  6079. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
  6080. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
  6081. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
  6082. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
  6083. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
  6084. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
  6085. #define TIM_BDTR_LOCK_Pos (8U)
  6086. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  6087. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  6088. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
  6089. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
  6090. #define TIM_BDTR_OSSI_Pos (10U)
  6091. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  6092. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  6093. #define TIM_BDTR_OSSR_Pos (11U)
  6094. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  6095. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  6096. #define TIM_BDTR_BKE_Pos (12U)
  6097. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  6098. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  6099. #define TIM_BDTR_BKP_Pos (13U)
  6100. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  6101. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  6102. #define TIM_BDTR_AOE_Pos (14U)
  6103. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  6104. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  6105. #define TIM_BDTR_MOE_Pos (15U)
  6106. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  6107. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  6108. /******************* Bit definition for TIM_DCR register ********************/
  6109. #define TIM_DCR_DBA_Pos (0U)
  6110. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  6111. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  6112. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
  6113. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
  6114. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
  6115. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
  6116. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
  6117. #define TIM_DCR_DBL_Pos (8U)
  6118. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  6119. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  6120. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
  6121. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
  6122. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
  6123. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
  6124. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
  6125. /******************* Bit definition for TIM_DMAR register *******************/
  6126. #define TIM_DMAR_DMAB_Pos (0U)
  6127. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  6128. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  6129. /******************* Bit definition for TIM_OR register *********************/
  6130. #define TIM_OR_TI1_RMP_Pos (0U)
  6131. #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  6132. #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
  6133. #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  6134. #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  6135. #define TIM_OR_TI4_RMP_Pos (6U)
  6136. #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
  6137. #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
  6138. #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
  6139. #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
  6140. /******************************************************************************/
  6141. /* */
  6142. /* Low Power Timer (LPTIM) */
  6143. /* */
  6144. /******************************************************************************/
  6145. /****************** Bit definition for LPTIM_ISR register *******************/
  6146. #define LPTIM_ISR_CMPM_Pos (0U)
  6147. #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
  6148. #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
  6149. #define LPTIM_ISR_ARRM_Pos (1U)
  6150. #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
  6151. #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
  6152. #define LPTIM_ISR_EXTTRIG_Pos (2U)
  6153. #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
  6154. #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
  6155. #define LPTIM_ISR_CMPOK_Pos (3U)
  6156. #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
  6157. #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
  6158. #define LPTIM_ISR_ARROK_Pos (4U)
  6159. #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
  6160. #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
  6161. #define LPTIM_ISR_UP_Pos (5U)
  6162. #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
  6163. #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
  6164. #define LPTIM_ISR_DOWN_Pos (6U)
  6165. #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
  6166. #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
  6167. /****************** Bit definition for LPTIM_ICR register *******************/
  6168. #define LPTIM_ICR_CMPMCF_Pos (0U)
  6169. #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
  6170. #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
  6171. #define LPTIM_ICR_ARRMCF_Pos (1U)
  6172. #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
  6173. #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
  6174. #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
  6175. #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
  6176. #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
  6177. #define LPTIM_ICR_CMPOKCF_Pos (3U)
  6178. #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
  6179. #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
  6180. #define LPTIM_ICR_ARROKCF_Pos (4U)
  6181. #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
  6182. #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
  6183. #define LPTIM_ICR_UPCF_Pos (5U)
  6184. #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
  6185. #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
  6186. #define LPTIM_ICR_DOWNCF_Pos (6U)
  6187. #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
  6188. #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
  6189. /****************** Bit definition for LPTIM_IER register ********************/
  6190. #define LPTIM_IER_CMPMIE_Pos (0U)
  6191. #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
  6192. #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
  6193. #define LPTIM_IER_ARRMIE_Pos (1U)
  6194. #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
  6195. #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
  6196. #define LPTIM_IER_EXTTRIGIE_Pos (2U)
  6197. #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
  6198. #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
  6199. #define LPTIM_IER_CMPOKIE_Pos (3U)
  6200. #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
  6201. #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
  6202. #define LPTIM_IER_ARROKIE_Pos (4U)
  6203. #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
  6204. #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
  6205. #define LPTIM_IER_UPIE_Pos (5U)
  6206. #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
  6207. #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
  6208. #define LPTIM_IER_DOWNIE_Pos (6U)
  6209. #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
  6210. #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
  6211. /****************** Bit definition for LPTIM_CFGR register *******************/
  6212. #define LPTIM_CFGR_CKSEL_Pos (0U)
  6213. #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
  6214. #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
  6215. #define LPTIM_CFGR_CKPOL_Pos (1U)
  6216. #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
  6217. #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
  6218. #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
  6219. #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
  6220. #define LPTIM_CFGR_CKFLT_Pos (3U)
  6221. #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
  6222. #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
  6223. #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
  6224. #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
  6225. #define LPTIM_CFGR_TRGFLT_Pos (6U)
  6226. #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
  6227. #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
  6228. #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
  6229. #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
  6230. #define LPTIM_CFGR_PRESC_Pos (9U)
  6231. #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
  6232. #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
  6233. #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
  6234. #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
  6235. #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
  6236. #define LPTIM_CFGR_TRIGSEL_Pos (13U)
  6237. #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
  6238. #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
  6239. #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
  6240. #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
  6241. #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
  6242. #define LPTIM_CFGR_TRIGEN_Pos (17U)
  6243. #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
  6244. #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
  6245. #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
  6246. #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
  6247. #define LPTIM_CFGR_TIMOUT_Pos (19U)
  6248. #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
  6249. #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
  6250. #define LPTIM_CFGR_WAVE_Pos (20U)
  6251. #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
  6252. #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
  6253. #define LPTIM_CFGR_WAVPOL_Pos (21U)
  6254. #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
  6255. #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
  6256. #define LPTIM_CFGR_PRELOAD_Pos (22U)
  6257. #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
  6258. #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
  6259. #define LPTIM_CFGR_COUNTMODE_Pos (23U)
  6260. #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
  6261. #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
  6262. #define LPTIM_CFGR_ENC_Pos (24U)
  6263. #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
  6264. #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
  6265. /****************** Bit definition for LPTIM_CR register ********************/
  6266. #define LPTIM_CR_ENABLE_Pos (0U)
  6267. #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
  6268. #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
  6269. #define LPTIM_CR_SNGSTRT_Pos (1U)
  6270. #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
  6271. #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
  6272. #define LPTIM_CR_CNTSTRT_Pos (2U)
  6273. #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
  6274. #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
  6275. /****************** Bit definition for LPTIM_CMP register *******************/
  6276. #define LPTIM_CMP_CMP_Pos (0U)
  6277. #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
  6278. #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
  6279. /****************** Bit definition for LPTIM_ARR register *******************/
  6280. #define LPTIM_ARR_ARR_Pos (0U)
  6281. #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
  6282. #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
  6283. /****************** Bit definition for LPTIM_CNT register *******************/
  6284. #define LPTIM_CNT_CNT_Pos (0U)
  6285. #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
  6286. #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
  6287. /****************** Bit definition for LPTIM_OR register *******************/
  6288. #define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
  6289. #define LPTIM_OR_LPT_IN1_RMP_Msk (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000003 */
  6290. #define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
  6291. #define LPTIM_OR_LPT_IN1_RMP_0 (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000001 */
  6292. #define LPTIM_OR_LPT_IN1_RMP_1 (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos) /*!< 0x00000002 */
  6293. /* Legacy Defines */
  6294. #define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
  6295. #define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
  6296. #define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
  6297. /******************************************************************************/
  6298. /* */
  6299. /* Universal Synchronous Asynchronous Receiver Transmitter */
  6300. /* */
  6301. /******************************************************************************/
  6302. /******************* Bit definition for USART_SR register *******************/
  6303. #define USART_SR_PE_Pos (0U)
  6304. #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
  6305. #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
  6306. #define USART_SR_FE_Pos (1U)
  6307. #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
  6308. #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
  6309. #define USART_SR_NE_Pos (2U)
  6310. #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
  6311. #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
  6312. #define USART_SR_ORE_Pos (3U)
  6313. #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
  6314. #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
  6315. #define USART_SR_IDLE_Pos (4U)
  6316. #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
  6317. #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
  6318. #define USART_SR_RXNE_Pos (5U)
  6319. #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
  6320. #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
  6321. #define USART_SR_TC_Pos (6U)
  6322. #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
  6323. #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
  6324. #define USART_SR_TXE_Pos (7U)
  6325. #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
  6326. #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
  6327. #define USART_SR_LBD_Pos (8U)
  6328. #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
  6329. #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
  6330. #define USART_SR_CTS_Pos (9U)
  6331. #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
  6332. #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
  6333. /******************* Bit definition for USART_DR register *******************/
  6334. #define USART_DR_DR_Pos (0U)
  6335. #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
  6336. #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
  6337. /****************** Bit definition for USART_BRR register *******************/
  6338. #define USART_BRR_DIV_Fraction_Pos (0U)
  6339. #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
  6340. #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
  6341. #define USART_BRR_DIV_Mantissa_Pos (4U)
  6342. #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
  6343. #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
  6344. /****************** Bit definition for USART_CR1 register *******************/
  6345. #define USART_CR1_SBK_Pos (0U)
  6346. #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
  6347. #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
  6348. #define USART_CR1_RWU_Pos (1U)
  6349. #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
  6350. #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
  6351. #define USART_CR1_RE_Pos (2U)
  6352. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  6353. #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
  6354. #define USART_CR1_TE_Pos (3U)
  6355. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  6356. #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
  6357. #define USART_CR1_IDLEIE_Pos (4U)
  6358. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  6359. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
  6360. #define USART_CR1_RXNEIE_Pos (5U)
  6361. #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  6362. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
  6363. #define USART_CR1_TCIE_Pos (6U)
  6364. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  6365. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
  6366. #define USART_CR1_TXEIE_Pos (7U)
  6367. #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  6368. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
  6369. #define USART_CR1_PEIE_Pos (8U)
  6370. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  6371. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
  6372. #define USART_CR1_PS_Pos (9U)
  6373. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  6374. #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
  6375. #define USART_CR1_PCE_Pos (10U)
  6376. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  6377. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
  6378. #define USART_CR1_WAKE_Pos (11U)
  6379. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  6380. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
  6381. #define USART_CR1_M_Pos (12U)
  6382. #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
  6383. #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
  6384. #define USART_CR1_UE_Pos (13U)
  6385. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
  6386. #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
  6387. #define USART_CR1_OVER8_Pos (15U)
  6388. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  6389. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
  6390. /****************** Bit definition for USART_CR2 register *******************/
  6391. #define USART_CR2_ADD_Pos (0U)
  6392. #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
  6393. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
  6394. #define USART_CR2_LBDL_Pos (5U)
  6395. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  6396. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
  6397. #define USART_CR2_LBDIE_Pos (6U)
  6398. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  6399. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
  6400. #define USART_CR2_LBCL_Pos (8U)
  6401. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  6402. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
  6403. #define USART_CR2_CPHA_Pos (9U)
  6404. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  6405. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
  6406. #define USART_CR2_CPOL_Pos (10U)
  6407. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  6408. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
  6409. #define USART_CR2_CLKEN_Pos (11U)
  6410. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  6411. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
  6412. #define USART_CR2_STOP_Pos (12U)
  6413. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  6414. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
  6415. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
  6416. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
  6417. #define USART_CR2_LINEN_Pos (14U)
  6418. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  6419. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
  6420. /****************** Bit definition for USART_CR3 register *******************/
  6421. #define USART_CR3_EIE_Pos (0U)
  6422. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  6423. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
  6424. #define USART_CR3_IREN_Pos (1U)
  6425. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  6426. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
  6427. #define USART_CR3_IRLP_Pos (2U)
  6428. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  6429. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
  6430. #define USART_CR3_HDSEL_Pos (3U)
  6431. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  6432. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
  6433. #define USART_CR3_NACK_Pos (4U)
  6434. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  6435. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
  6436. #define USART_CR3_SCEN_Pos (5U)
  6437. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  6438. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
  6439. #define USART_CR3_DMAR_Pos (6U)
  6440. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  6441. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
  6442. #define USART_CR3_DMAT_Pos (7U)
  6443. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  6444. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
  6445. #define USART_CR3_RTSE_Pos (8U)
  6446. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  6447. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
  6448. #define USART_CR3_CTSE_Pos (9U)
  6449. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  6450. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
  6451. #define USART_CR3_CTSIE_Pos (10U)
  6452. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  6453. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
  6454. #define USART_CR3_ONEBIT_Pos (11U)
  6455. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  6456. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
  6457. /****************** Bit definition for USART_GTPR register ******************/
  6458. #define USART_GTPR_PSC_Pos (0U)
  6459. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  6460. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
  6461. #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
  6462. #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
  6463. #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
  6464. #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
  6465. #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
  6466. #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
  6467. #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
  6468. #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
  6469. #define USART_GTPR_GT_Pos (8U)
  6470. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  6471. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
  6472. /******************************************************************************/
  6473. /* */
  6474. /* Window WATCHDOG */
  6475. /* */
  6476. /******************************************************************************/
  6477. /******************* Bit definition for WWDG_CR register ********************/
  6478. #define WWDG_CR_T_Pos (0U)
  6479. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  6480. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  6481. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
  6482. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
  6483. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
  6484. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
  6485. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
  6486. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
  6487. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
  6488. /* Legacy defines */
  6489. #define WWDG_CR_T0 WWDG_CR_T_0
  6490. #define WWDG_CR_T1 WWDG_CR_T_1
  6491. #define WWDG_CR_T2 WWDG_CR_T_2
  6492. #define WWDG_CR_T3 WWDG_CR_T_3
  6493. #define WWDG_CR_T4 WWDG_CR_T_4
  6494. #define WWDG_CR_T5 WWDG_CR_T_5
  6495. #define WWDG_CR_T6 WWDG_CR_T_6
  6496. #define WWDG_CR_WDGA_Pos (7U)
  6497. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  6498. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  6499. /******************* Bit definition for WWDG_CFR register *******************/
  6500. #define WWDG_CFR_W_Pos (0U)
  6501. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  6502. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  6503. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
  6504. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
  6505. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
  6506. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
  6507. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
  6508. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
  6509. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
  6510. /* Legacy defines */
  6511. #define WWDG_CFR_W0 WWDG_CFR_W_0
  6512. #define WWDG_CFR_W1 WWDG_CFR_W_1
  6513. #define WWDG_CFR_W2 WWDG_CFR_W_2
  6514. #define WWDG_CFR_W3 WWDG_CFR_W_3
  6515. #define WWDG_CFR_W4 WWDG_CFR_W_4
  6516. #define WWDG_CFR_W5 WWDG_CFR_W_5
  6517. #define WWDG_CFR_W6 WWDG_CFR_W_6
  6518. #define WWDG_CFR_WDGTB_Pos (7U)
  6519. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  6520. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  6521. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
  6522. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
  6523. /* Legacy defines */
  6524. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  6525. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  6526. #define WWDG_CFR_EWI_Pos (9U)
  6527. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  6528. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  6529. /******************* Bit definition for WWDG_SR register ********************/
  6530. #define WWDG_SR_EWIF_Pos (0U)
  6531. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  6532. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  6533. /******************************************************************************/
  6534. /* */
  6535. /* DBG */
  6536. /* */
  6537. /******************************************************************************/
  6538. /******************** Bit definition for DBGMCU_IDCODE register *************/
  6539. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  6540. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  6541. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  6542. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  6543. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  6544. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  6545. /******************** Bit definition for DBGMCU_CR register *****************/
  6546. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  6547. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  6548. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  6549. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  6550. #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  6551. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  6552. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  6553. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  6554. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  6555. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  6556. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  6557. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  6558. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  6559. #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  6560. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  6561. #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  6562. #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  6563. /******************** Bit definition for DBGMCU_APB1_FZ register ************/
  6564. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
  6565. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
  6566. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
  6567. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
  6568. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
  6569. #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
  6570. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  6571. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  6572. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
  6573. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  6574. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  6575. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
  6576. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  6577. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  6578. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
  6579. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  6580. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  6581. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
  6582. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
  6583. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
  6584. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
  6585. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
  6586. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
  6587. #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
  6588. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
  6589. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
  6590. #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
  6591. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
  6592. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
  6593. #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
  6594. /******************** Bit definition for DBGMCU_APB2_FZ register ************/
  6595. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
  6596. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
  6597. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
  6598. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
  6599. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
  6600. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
  6601. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
  6602. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
  6603. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
  6604. /**
  6605. * @}
  6606. */
  6607. /**
  6608. * @}
  6609. */
  6610. /** @addtogroup Exported_macros
  6611. * @{
  6612. */
  6613. /******************************* ADC Instances ********************************/
  6614. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  6615. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
  6616. /******************************* CRC Instances ********************************/
  6617. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  6618. /******************************* DAC Instances ********************************/
  6619. #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
  6620. /******************************** DMA Instances *******************************/
  6621. #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
  6622. ((INSTANCE) == DMA1_Stream1) || \
  6623. ((INSTANCE) == DMA1_Stream2) || \
  6624. ((INSTANCE) == DMA1_Stream3) || \
  6625. ((INSTANCE) == DMA1_Stream4) || \
  6626. ((INSTANCE) == DMA1_Stream5) || \
  6627. ((INSTANCE) == DMA1_Stream6) || \
  6628. ((INSTANCE) == DMA1_Stream7) || \
  6629. ((INSTANCE) == DMA2_Stream0) || \
  6630. ((INSTANCE) == DMA2_Stream1) || \
  6631. ((INSTANCE) == DMA2_Stream2) || \
  6632. ((INSTANCE) == DMA2_Stream3) || \
  6633. ((INSTANCE) == DMA2_Stream4) || \
  6634. ((INSTANCE) == DMA2_Stream5) || \
  6635. ((INSTANCE) == DMA2_Stream6) || \
  6636. ((INSTANCE) == DMA2_Stream7))
  6637. /******************************* GPIO Instances *******************************/
  6638. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  6639. ((INSTANCE) == GPIOB) || \
  6640. ((INSTANCE) == GPIOC) || \
  6641. ((INSTANCE) == GPIOH))
  6642. /******************************** I2C Instances *******************************/
  6643. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  6644. ((INSTANCE) == I2C2))
  6645. /******************************* SMBUS Instances ******************************/
  6646. #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
  6647. /******************************** I2S Instances *******************************/
  6648. #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  6649. ((INSTANCE) == SPI2) || \
  6650. ((INSTANCE) == SPI5))
  6651. /******************************* LPTIM Instances ******************************/
  6652. #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
  6653. /******************************* RNG Instances ********************************/
  6654. #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
  6655. /****************************** RTC Instances *********************************/
  6656. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  6657. /******************************** SPI Instances *******************************/
  6658. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  6659. ((INSTANCE) == SPI2) || \
  6660. ((INSTANCE) == SPI5))
  6661. /*************************** SPI Extended Instances ***************************/
  6662. #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
  6663. ((INSTANCE) == SPI2) || \
  6664. ((INSTANCE) == SPI5))
  6665. /****************** TIM Instances : All supported instances *******************/
  6666. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6667. ((INSTANCE) == TIM5) || \
  6668. ((INSTANCE) == TIM6) || \
  6669. ((INSTANCE) == TIM9) || \
  6670. ((INSTANCE) == TIM11))
  6671. /****************** TIM Instances : supporting synchronization ****************/
  6672. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  6673. /************* TIM Instances : at least 1 capture/compare channel *************/
  6674. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6675. ((INSTANCE) == TIM5) || \
  6676. ((INSTANCE) == TIM9) || \
  6677. ((INSTANCE) == TIM11))
  6678. /************ TIM Instances : at least 2 capture/compare channels *************/
  6679. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6680. ((INSTANCE) == TIM5) || \
  6681. ((INSTANCE) == TIM9))
  6682. /************ TIM Instances : at least 3 capture/compare channels *************/
  6683. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6684. ((INSTANCE) == TIM5))
  6685. /************ TIM Instances : at least 4 capture/compare channels *************/
  6686. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6687. ((INSTANCE) == TIM5))
  6688. /******************** TIM Instances : Advanced-control timers *****************/
  6689. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  6690. /******************* TIM Instances : Timer input XOR function *****************/
  6691. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6692. ((INSTANCE) == TIM5))
  6693. /****************** TIM Instances : DMA requests generation (UDE) *************/
  6694. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6695. ((INSTANCE) == TIM5) || \
  6696. ((INSTANCE) == TIM6))
  6697. /************ TIM Instances : DMA requests generation (CCxDE) *****************/
  6698. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6699. ((INSTANCE) == TIM5))
  6700. /************ TIM Instances : DMA requests generation (COMDE) *****************/
  6701. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6702. ((INSTANCE) == TIM5))
  6703. /******************** TIM Instances : DMA burst feature ***********************/
  6704. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6705. ((INSTANCE) == TIM5))
  6706. /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
  6707. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6708. ((INSTANCE) == TIM5) || \
  6709. ((INSTANCE) == TIM6))
  6710. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  6711. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6712. ((INSTANCE) == TIM5) || \
  6713. ((INSTANCE) == TIM9))
  6714. /********************** TIM Instances : 32 bit Counter ************************/
  6715. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5)
  6716. /***************** TIM Instances : external trigger input availabe ************/
  6717. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6718. ((INSTANCE) == TIM5))
  6719. /****************** TIM Instances : remapping capability **********************/
  6720. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
  6721. ((INSTANCE) == TIM11))
  6722. /******************* TIM Instances : output(s) available **********************/
  6723. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  6724. ((((INSTANCE) == TIM1) && \
  6725. (((CHANNEL) == TIM_CHANNEL_1) || \
  6726. ((CHANNEL) == TIM_CHANNEL_2) || \
  6727. ((CHANNEL) == TIM_CHANNEL_3) || \
  6728. ((CHANNEL) == TIM_CHANNEL_4))) \
  6729. || \
  6730. (((INSTANCE) == TIM5) && \
  6731. (((CHANNEL) == TIM_CHANNEL_1) || \
  6732. ((CHANNEL) == TIM_CHANNEL_2) || \
  6733. ((CHANNEL) == TIM_CHANNEL_3) || \
  6734. ((CHANNEL) == TIM_CHANNEL_4))) \
  6735. || \
  6736. (((INSTANCE) == TIM9) && \
  6737. (((CHANNEL) == TIM_CHANNEL_1) || \
  6738. ((CHANNEL) == TIM_CHANNEL_2))) \
  6739. || \
  6740. (((INSTANCE) == TIM11) && \
  6741. (((CHANNEL) == TIM_CHANNEL_1))))
  6742. /************ TIM Instances : complementary output(s) available ***************/
  6743. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  6744. ((((INSTANCE) == TIM1) && \
  6745. (((CHANNEL) == TIM_CHANNEL_1) || \
  6746. ((CHANNEL) == TIM_CHANNEL_2) || \
  6747. ((CHANNEL) == TIM_CHANNEL_3))))
  6748. /****************** TIM Instances : supporting counting mode selection ********/
  6749. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6750. ((INSTANCE) == TIM5))
  6751. /****************** TIM Instances : supporting clock division *****************/
  6752. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6753. ((INSTANCE) == TIM5) || \
  6754. ((INSTANCE) == TIM9) || \
  6755. ((INSTANCE) == TIM11))
  6756. /****************** TIM Instances : supporting commutation event generation ***/
  6757. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  6758. /****************** TIM Instances : supporting OCxREF clear *******************/
  6759. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6760. ((INSTANCE) == TIM5))
  6761. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  6762. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6763. ((INSTANCE) == TIM5) || \
  6764. ((INSTANCE) == TIM9))
  6765. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  6766. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6767. ((INSTANCE) == TIM5))
  6768. /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
  6769. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6770. ((INSTANCE) == TIM5) || \
  6771. ((INSTANCE) == TIM9))
  6772. /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
  6773. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6774. ((INSTANCE) == TIM5) || \
  6775. ((INSTANCE) == TIM9))
  6776. /****************** TIM Instances : supporting repetition counter *************/
  6777. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  6778. /****************** TIM Instances : supporting encoder interface **************/
  6779. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6780. ((INSTANCE) == TIM5) || \
  6781. ((INSTANCE) == TIM9))
  6782. /****************** TIM Instances : supporting Hall sensor interface **********/
  6783. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  6784. ((INSTANCE) == TIM5))
  6785. /****************** TIM Instances : supporting the break function *************/
  6786. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  6787. /******************** USART Instances : Synchronous mode **********************/
  6788. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  6789. ((INSTANCE) == USART2) || \
  6790. ((INSTANCE) == USART6))
  6791. /******************** UART Instances : Half-Duplex mode **********************/
  6792. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  6793. ((INSTANCE) == USART2) || \
  6794. ((INSTANCE) == USART6))
  6795. /* Legacy defines */
  6796. #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  6797. /****************** UART Instances : Hardware Flow control ********************/
  6798. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  6799. ((INSTANCE) == USART2) || \
  6800. ((INSTANCE) == USART6))
  6801. /******************** UART Instances : LIN mode **********************/
  6802. #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  6803. /********************* UART Instances : Smart card mode ***********************/
  6804. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  6805. ((INSTANCE) == USART2) || \
  6806. ((INSTANCE) == USART6))
  6807. /*********************** UART Instances : IRDA mode ***************************/
  6808. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  6809. ((INSTANCE) == USART2) || \
  6810. ((INSTANCE) == USART6))
  6811. /****************************** IWDG Instances ********************************/
  6812. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  6813. /****************************** WWDG Instances ********************************/
  6814. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  6815. /***************************** FMPI2C Instances *******************************/
  6816. #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
  6817. #define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
  6818. /*
  6819. * @brief Specific devices reset values definitions
  6820. */
  6821. #define RCC_PLLCFGR_RST_VALUE 0x7F003010U
  6822. #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
  6823. #define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/
  6824. #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
  6825. #define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
  6826. #define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  6827. #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
  6828. #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  6829. #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  6830. #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  6831. #define RCC_PLLN_MIN_VALUE 50U
  6832. #define RCC_PLLN_MAX_VALUE 432U
  6833. #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  6834. #define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  6835. #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  6836. #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  6837. #define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  6838. #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  6839. #define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  6840. /**
  6841. * @}
  6842. */
  6843. /**
  6844. * @}
  6845. */
  6846. /**
  6847. * @}
  6848. */
  6849. #ifdef __cplusplus
  6850. }
  6851. #endif /* __cplusplus */
  6852. #endif /* __STM32F410Cx_H */
  6853. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/