stm32f401xc.h 707 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f401xc.h
  4. * @author MCD Application Team
  5. * @brief CMSIS STM32F401xC Device Peripheral Access Layer Header File.
  6. *
  7. * This file contains:
  8. * - Data structures and the address mapping for all peripherals
  9. * - peripherals registers declarations and bits definition
  10. * - Macros to access peripheral’s registers hardware
  11. *
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  16. *
  17. * Redistribution and use in source and binary forms, with or without modification,
  18. * are permitted provided that the following conditions are met:
  19. * 1. Redistributions of source code must retain the above copyright notice,
  20. * this list of conditions and the following disclaimer.
  21. * 2. Redistributions in binary form must reproduce the above copyright notice,
  22. * this list of conditions and the following disclaimer in the documentation
  23. * and/or other materials provided with the distribution.
  24. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  25. * may be used to endorse or promote products derived from this software
  26. * without specific prior written permission.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. ******************************************************************************
  40. */
  41. /** @addtogroup CMSIS_Device
  42. * @{
  43. */
  44. /** @addtogroup stm32f401xc
  45. * @{
  46. */
  47. #ifndef __STM32F401xC_H
  48. #define __STM32F401xC_H
  49. #ifdef __cplusplus
  50. extern "C" {
  51. #endif /* __cplusplus */
  52. /** @addtogroup Configuration_section_for_CMSIS
  53. * @{
  54. */
  55. /**
  56. * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
  57. */
  58. #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
  59. #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
  60. #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
  61. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  62. #define __FPU_PRESENT 1U /*!< FPU present */
  63. /**
  64. * @}
  65. */
  66. /** @addtogroup Peripheral_interrupt_number_definition
  67. * @{
  68. */
  69. /**
  70. * @brief STM32F4XX Interrupt Number Definition, according to the selected device
  71. * in @ref Library_configuration_section
  72. */
  73. typedef enum
  74. {
  75. /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  76. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  77. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
  78. BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
  79. UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
  80. SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
  81. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
  82. PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
  83. SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
  84. /****** STM32 specific Interrupt Numbers **********************************************************************/
  85. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  86. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  87. TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
  88. RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
  89. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  90. RCC_IRQn = 5, /*!< RCC global Interrupt */
  91. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  92. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  93. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  94. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  95. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  96. DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
  97. DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
  98. DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
  99. DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
  100. DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
  101. DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
  102. DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
  103. ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
  104. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  105. TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
  106. TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
  107. TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
  108. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  109. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  110. TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
  111. TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
  112. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  113. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  114. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  115. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  116. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  117. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  118. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  119. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  120. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  121. RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
  122. OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
  123. DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
  124. SDIO_IRQn = 49, /*!< SDIO global Interrupt */
  125. TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
  126. SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
  127. DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
  128. DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
  129. DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
  130. DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
  131. DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
  132. OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
  133. DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
  134. DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
  135. DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
  136. USART6_IRQn = 71, /*!< USART6 global interrupt */
  137. I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
  138. I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
  139. FPU_IRQn = 81, /*!< FPU global interrupt */
  140. SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
  141. } IRQn_Type;
  142. /**
  143. * @}
  144. */
  145. #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
  146. #include "system_stm32f4xx.h"
  147. #include <stdint.h>
  148. /** @addtogroup Peripheral_registers_structures
  149. * @{
  150. */
  151. /**
  152. * @brief Analog to Digital Converter
  153. */
  154. typedef struct
  155. {
  156. __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
  157. __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
  158. __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
  159. __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
  160. __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
  161. __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  162. __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  163. __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  164. __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  165. __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
  166. __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
  167. __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
  168. __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
  169. __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
  170. __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
  171. __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
  172. __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
  173. __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
  174. __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
  175. __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
  176. } ADC_TypeDef;
  177. typedef struct
  178. {
  179. __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
  180. __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
  181. __IO uint32_t CDR; /*!< ADC common regular data register for dual
  182. AND triple modes, Address offset: ADC1 base address + 0x308 */
  183. } ADC_Common_TypeDef;
  184. /**
  185. * @brief CRC calculation unit
  186. */
  187. typedef struct
  188. {
  189. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  190. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  191. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  192. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  193. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  194. } CRC_TypeDef;
  195. /**
  196. * @brief Debug MCU
  197. */
  198. typedef struct
  199. {
  200. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  201. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  202. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  203. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  204. }DBGMCU_TypeDef;
  205. /**
  206. * @brief DMA Controller
  207. */
  208. typedef struct
  209. {
  210. __IO uint32_t CR; /*!< DMA stream x configuration register */
  211. __IO uint32_t NDTR; /*!< DMA stream x number of data register */
  212. __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
  213. __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
  214. __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
  215. __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
  216. } DMA_Stream_TypeDef;
  217. typedef struct
  218. {
  219. __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
  220. __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
  221. __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
  222. __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
  223. } DMA_TypeDef;
  224. /**
  225. * @brief External Interrupt/Event Controller
  226. */
  227. typedef struct
  228. {
  229. __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
  230. __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
  231. __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
  232. __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
  233. __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
  234. __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
  235. } EXTI_TypeDef;
  236. /**
  237. * @brief FLASH Registers
  238. */
  239. typedef struct
  240. {
  241. __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
  242. __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
  243. __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
  244. __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
  245. __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
  246. __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
  247. __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
  248. } FLASH_TypeDef;
  249. /**
  250. * @brief General Purpose I/O
  251. */
  252. typedef struct
  253. {
  254. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  255. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  256. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  257. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  258. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  259. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  260. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  261. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  262. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  263. } GPIO_TypeDef;
  264. /**
  265. * @brief System configuration controller
  266. */
  267. typedef struct
  268. {
  269. __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
  270. __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
  271. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  272. uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
  273. __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
  274. } SYSCFG_TypeDef;
  275. /**
  276. * @brief Inter-integrated Circuit Interface
  277. */
  278. typedef struct
  279. {
  280. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  281. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  282. __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
  283. __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
  284. __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
  285. __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
  286. __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
  287. __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
  288. __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
  289. __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
  290. } I2C_TypeDef;
  291. /**
  292. * @brief Independent WATCHDOG
  293. */
  294. typedef struct
  295. {
  296. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  297. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  298. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  299. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  300. } IWDG_TypeDef;
  301. /**
  302. * @brief Power Control
  303. */
  304. typedef struct
  305. {
  306. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  307. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  308. } PWR_TypeDef;
  309. /**
  310. * @brief Reset and Clock Control
  311. */
  312. typedef struct
  313. {
  314. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  315. __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
  316. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
  317. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
  318. __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
  319. __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
  320. __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
  321. uint32_t RESERVED0; /*!< Reserved, 0x1C */
  322. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
  323. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
  324. uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
  325. __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
  326. __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
  327. __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
  328. uint32_t RESERVED2; /*!< Reserved, 0x3C */
  329. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
  330. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
  331. uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
  332. __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  333. __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
  334. __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
  335. uint32_t RESERVED4; /*!< Reserved, 0x5C */
  336. __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  337. __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  338. uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
  339. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
  340. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
  341. uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
  342. __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
  343. __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
  344. uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
  345. __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
  346. } RCC_TypeDef;
  347. /**
  348. * @brief Real-Time Clock
  349. */
  350. typedef struct
  351. {
  352. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  353. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  354. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  355. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  356. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  357. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  358. __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
  359. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  360. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
  361. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  362. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  363. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  364. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  365. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  366. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  367. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  368. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  369. __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
  370. __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
  371. uint32_t RESERVED7; /*!< Reserved, 0x4C */
  372. __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
  373. __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
  374. __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
  375. __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
  376. __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
  377. __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
  378. __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
  379. __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
  380. __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
  381. __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
  382. __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
  383. __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
  384. __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
  385. __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
  386. __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
  387. __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
  388. __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
  389. __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
  390. __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
  391. __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
  392. } RTC_TypeDef;
  393. /**
  394. * @brief SD host Interface
  395. */
  396. typedef struct
  397. {
  398. __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
  399. __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
  400. __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
  401. __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
  402. __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
  403. __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
  404. __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
  405. __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
  406. __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
  407. __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
  408. __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
  409. __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
  410. __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
  411. __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
  412. __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
  413. __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
  414. uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
  415. __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
  416. uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
  417. __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
  418. } SDIO_TypeDef;
  419. /**
  420. * @brief Serial Peripheral Interface
  421. */
  422. typedef struct
  423. {
  424. __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
  425. __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
  426. __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
  427. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  428. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  429. __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
  430. __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
  431. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  432. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  433. } SPI_TypeDef;
  434. /**
  435. * @brief TIM
  436. */
  437. typedef struct
  438. {
  439. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  440. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  441. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  442. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  443. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  444. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  445. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  446. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  447. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  448. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  449. __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
  450. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  451. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  452. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  453. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  454. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  455. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  456. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  457. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  458. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  459. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  460. } TIM_TypeDef;
  461. /**
  462. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  463. */
  464. typedef struct
  465. {
  466. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  467. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  468. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  469. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  470. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  471. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  472. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  473. } USART_TypeDef;
  474. /**
  475. * @brief Window WATCHDOG
  476. */
  477. typedef struct
  478. {
  479. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  480. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  481. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  482. } WWDG_TypeDef;
  483. /**
  484. * @brief USB_OTG_Core_Registers
  485. */
  486. typedef struct
  487. {
  488. __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
  489. __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
  490. __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
  491. __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
  492. __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
  493. __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
  494. __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
  495. __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
  496. __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
  497. __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
  498. __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
  499. __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
  500. uint32_t Reserved30[2]; /*!< Reserved 030h */
  501. __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
  502. __IO uint32_t CID; /*!< User ID Register 03Ch */
  503. uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
  504. __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
  505. __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
  506. } USB_OTG_GlobalTypeDef;
  507. /**
  508. * @brief USB_OTG_device_Registers
  509. */
  510. typedef struct
  511. {
  512. __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
  513. __IO uint32_t DCTL; /*!< dev Control Register 804h */
  514. __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
  515. uint32_t Reserved0C; /*!< Reserved 80Ch */
  516. __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
  517. __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
  518. __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
  519. __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
  520. uint32_t Reserved20; /*!< Reserved 820h */
  521. uint32_t Reserved9; /*!< Reserved 824h */
  522. __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
  523. __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
  524. __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
  525. __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
  526. __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
  527. __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
  528. uint32_t Reserved40; /*!< dedicated EP mask 840h */
  529. __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
  530. uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
  531. __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
  532. } USB_OTG_DeviceTypeDef;
  533. /**
  534. * @brief USB_OTG_IN_Endpoint-Specific_Register
  535. */
  536. typedef struct
  537. {
  538. __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
  539. uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
  540. __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
  541. uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
  542. __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
  543. __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
  544. __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
  545. uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
  546. } USB_OTG_INEndpointTypeDef;
  547. /**
  548. * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  549. */
  550. typedef struct
  551. {
  552. __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
  553. uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
  554. __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
  555. uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
  556. __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
  557. __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
  558. uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
  559. } USB_OTG_OUTEndpointTypeDef;
  560. /**
  561. * @brief USB_OTG_Host_Mode_Register_Structures
  562. */
  563. typedef struct
  564. {
  565. __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
  566. __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
  567. __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
  568. uint32_t Reserved40C; /*!< Reserved 40Ch */
  569. __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
  570. __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
  571. __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
  572. } USB_OTG_HostTypeDef;
  573. /**
  574. * @brief USB_OTG_Host_Channel_Specific_Registers
  575. */
  576. typedef struct
  577. {
  578. __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
  579. __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
  580. __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
  581. __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
  582. __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
  583. __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
  584. uint32_t Reserved[2]; /*!< Reserved */
  585. } USB_OTG_HostChannelTypeDef;
  586. /**
  587. * @}
  588. */
  589. /** @addtogroup Peripheral_memory_map
  590. * @{
  591. */
  592. #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
  593. #define SRAM1_BASE 0x20000000UL /*!< SRAM1(64 KB) base address in the alias region */
  594. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  595. #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(64 KB) base address in the bit-band region */
  596. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  597. #define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
  598. #define FLASH_END 0x0803FFFFUL /*!< FLASH end address */
  599. #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
  600. #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
  601. /* Legacy defines */
  602. #define SRAM_BASE SRAM1_BASE
  603. #define SRAM_BB_BASE SRAM1_BB_BASE
  604. /*!< Peripheral memory map */
  605. #define APB1PERIPH_BASE PERIPH_BASE
  606. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  607. #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  608. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
  609. /*!< APB1 peripherals */
  610. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
  611. #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
  612. #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
  613. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
  614. #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
  615. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
  616. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
  617. #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
  618. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
  619. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
  620. #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
  621. #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
  622. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
  623. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
  624. #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
  625. #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
  626. /*!< APB2 peripherals */
  627. #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
  628. #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
  629. #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
  630. #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
  631. #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
  632. /* Legacy define */
  633. #define ADC_BASE ADC1_COMMON_BASE
  634. #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
  635. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
  636. #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
  637. #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
  638. #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
  639. #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
  640. #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
  641. #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
  642. /*!< AHB1 peripherals */
  643. #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
  644. #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
  645. #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
  646. #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
  647. #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
  648. #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
  649. #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
  650. #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
  651. #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
  652. #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
  653. #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
  654. #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
  655. #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
  656. #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
  657. #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
  658. #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
  659. #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
  660. #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
  661. #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
  662. #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
  663. #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
  664. #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
  665. #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
  666. #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
  667. #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
  668. #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
  669. #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
  670. /*!< Debug MCU registers base address */
  671. #define DBGMCU_BASE 0xE0042000UL
  672. /*!< USB registers base address */
  673. #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
  674. #define USB_OTG_GLOBAL_BASE 0x000UL
  675. #define USB_OTG_DEVICE_BASE 0x800UL
  676. #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
  677. #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
  678. #define USB_OTG_EP_REG_SIZE 0x20UL
  679. #define USB_OTG_HOST_BASE 0x400UL
  680. #define USB_OTG_HOST_PORT_BASE 0x440UL
  681. #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
  682. #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
  683. #define USB_OTG_PCGCCTL_BASE 0xE00UL
  684. #define USB_OTG_FIFO_BASE 0x1000UL
  685. #define USB_OTG_FIFO_SIZE 0x1000UL
  686. #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
  687. #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
  688. #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
  689. /**
  690. * @}
  691. */
  692. /** @addtogroup Peripheral_declaration
  693. * @{
  694. */
  695. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  696. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  697. #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
  698. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  699. #define RTC ((RTC_TypeDef *) RTC_BASE)
  700. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  701. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  702. #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
  703. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  704. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  705. #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
  706. #define USART2 ((USART_TypeDef *) USART2_BASE)
  707. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  708. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  709. #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
  710. #define PWR ((PWR_TypeDef *) PWR_BASE)
  711. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  712. #define USART1 ((USART_TypeDef *) USART1_BASE)
  713. #define USART6 ((USART_TypeDef *) USART6_BASE)
  714. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  715. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
  716. /* Legacy define */
  717. #define ADC ADC1_COMMON
  718. #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
  719. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  720. #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
  721. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  722. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  723. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  724. #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
  725. #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
  726. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  727. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  728. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  729. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  730. #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
  731. #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
  732. #define CRC ((CRC_TypeDef *) CRC_BASE)
  733. #define RCC ((RCC_TypeDef *) RCC_BASE)
  734. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  735. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  736. #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  737. #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
  738. #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
  739. #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
  740. #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
  741. #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
  742. #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
  743. #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
  744. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  745. #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
  746. #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
  747. #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
  748. #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
  749. #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
  750. #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
  751. #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
  752. #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
  753. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  754. #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
  755. /**
  756. * @}
  757. */
  758. /** @addtogroup Exported_constants
  759. * @{
  760. */
  761. /** @addtogroup Peripheral_Registers_Bits_Definition
  762. * @{
  763. */
  764. /******************************************************************************/
  765. /* Peripheral Registers_Bits_Definition */
  766. /******************************************************************************/
  767. /******************************************************************************/
  768. /* */
  769. /* Analog to Digital Converter */
  770. /* */
  771. /******************************************************************************/
  772. /******************** Bit definition for ADC_SR register ********************/
  773. #define ADC_SR_AWD_Pos (0U)
  774. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  775. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
  776. #define ADC_SR_EOC_Pos (1U)
  777. #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
  778. #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
  779. #define ADC_SR_JEOC_Pos (2U)
  780. #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
  781. #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
  782. #define ADC_SR_JSTRT_Pos (3U)
  783. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  784. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
  785. #define ADC_SR_STRT_Pos (4U)
  786. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  787. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
  788. #define ADC_SR_OVR_Pos (5U)
  789. #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
  790. #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
  791. /******************* Bit definition for ADC_CR1 register ********************/
  792. #define ADC_CR1_AWDCH_Pos (0U)
  793. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  794. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
  795. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  796. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  797. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  798. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  799. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  800. #define ADC_CR1_EOCIE_Pos (5U)
  801. #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
  802. #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
  803. #define ADC_CR1_AWDIE_Pos (6U)
  804. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  805. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
  806. #define ADC_CR1_JEOCIE_Pos (7U)
  807. #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
  808. #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
  809. #define ADC_CR1_SCAN_Pos (8U)
  810. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  811. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
  812. #define ADC_CR1_AWDSGL_Pos (9U)
  813. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  814. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
  815. #define ADC_CR1_JAUTO_Pos (10U)
  816. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  817. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
  818. #define ADC_CR1_DISCEN_Pos (11U)
  819. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  820. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
  821. #define ADC_CR1_JDISCEN_Pos (12U)
  822. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  823. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
  824. #define ADC_CR1_DISCNUM_Pos (13U)
  825. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  826. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
  827. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  828. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  829. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  830. #define ADC_CR1_JAWDEN_Pos (22U)
  831. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  832. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
  833. #define ADC_CR1_AWDEN_Pos (23U)
  834. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  835. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
  836. #define ADC_CR1_RES_Pos (24U)
  837. #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
  838. #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
  839. #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
  840. #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
  841. #define ADC_CR1_OVRIE_Pos (26U)
  842. #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
  843. #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
  844. /******************* Bit definition for ADC_CR2 register ********************/
  845. #define ADC_CR2_ADON_Pos (0U)
  846. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  847. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
  848. #define ADC_CR2_CONT_Pos (1U)
  849. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  850. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
  851. #define ADC_CR2_DMA_Pos (8U)
  852. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  853. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
  854. #define ADC_CR2_DDS_Pos (9U)
  855. #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
  856. #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
  857. #define ADC_CR2_EOCS_Pos (10U)
  858. #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
  859. #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
  860. #define ADC_CR2_ALIGN_Pos (11U)
  861. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  862. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
  863. #define ADC_CR2_JEXTSEL_Pos (16U)
  864. #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
  865. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
  866. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
  867. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
  868. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
  869. #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
  870. #define ADC_CR2_JEXTEN_Pos (20U)
  871. #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
  872. #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
  873. #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
  874. #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
  875. #define ADC_CR2_JSWSTART_Pos (22U)
  876. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
  877. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
  878. #define ADC_CR2_EXTSEL_Pos (24U)
  879. #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
  880. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
  881. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
  882. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
  883. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
  884. #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
  885. #define ADC_CR2_EXTEN_Pos (28U)
  886. #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
  887. #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
  888. #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
  889. #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
  890. #define ADC_CR2_SWSTART_Pos (30U)
  891. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
  892. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
  893. /****************** Bit definition for ADC_SMPR1 register *******************/
  894. #define ADC_SMPR1_SMP10_Pos (0U)
  895. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  896. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
  897. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  898. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  899. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  900. #define ADC_SMPR1_SMP11_Pos (3U)
  901. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  902. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
  903. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  904. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  905. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  906. #define ADC_SMPR1_SMP12_Pos (6U)
  907. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  908. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
  909. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  910. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  911. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  912. #define ADC_SMPR1_SMP13_Pos (9U)
  913. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  914. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
  915. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  916. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  917. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  918. #define ADC_SMPR1_SMP14_Pos (12U)
  919. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  920. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
  921. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  922. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  923. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  924. #define ADC_SMPR1_SMP15_Pos (15U)
  925. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  926. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
  927. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  928. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  929. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  930. #define ADC_SMPR1_SMP16_Pos (18U)
  931. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  932. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
  933. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  934. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  935. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  936. #define ADC_SMPR1_SMP17_Pos (21U)
  937. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  938. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
  939. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  940. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  941. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  942. #define ADC_SMPR1_SMP18_Pos (24U)
  943. #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
  944. #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
  945. #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
  946. #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
  947. #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
  948. /****************** Bit definition for ADC_SMPR2 register *******************/
  949. #define ADC_SMPR2_SMP0_Pos (0U)
  950. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  951. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
  952. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  953. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  954. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  955. #define ADC_SMPR2_SMP1_Pos (3U)
  956. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  957. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
  958. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  959. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  960. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  961. #define ADC_SMPR2_SMP2_Pos (6U)
  962. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  963. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
  964. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  965. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  966. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  967. #define ADC_SMPR2_SMP3_Pos (9U)
  968. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  969. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
  970. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  971. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  972. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  973. #define ADC_SMPR2_SMP4_Pos (12U)
  974. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  975. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
  976. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  977. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  978. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  979. #define ADC_SMPR2_SMP5_Pos (15U)
  980. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  981. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
  982. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  983. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  984. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  985. #define ADC_SMPR2_SMP6_Pos (18U)
  986. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  987. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
  988. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  989. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  990. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  991. #define ADC_SMPR2_SMP7_Pos (21U)
  992. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  993. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
  994. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  995. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  996. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  997. #define ADC_SMPR2_SMP8_Pos (24U)
  998. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  999. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
  1000. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  1001. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  1002. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  1003. #define ADC_SMPR2_SMP9_Pos (27U)
  1004. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  1005. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
  1006. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  1007. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  1008. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  1009. /****************** Bit definition for ADC_JOFR1 register *******************/
  1010. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  1011. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  1012. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
  1013. /****************** Bit definition for ADC_JOFR2 register *******************/
  1014. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  1015. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  1016. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
  1017. /****************** Bit definition for ADC_JOFR3 register *******************/
  1018. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  1019. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  1020. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
  1021. /****************** Bit definition for ADC_JOFR4 register *******************/
  1022. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  1023. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  1024. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
  1025. /******************* Bit definition for ADC_HTR register ********************/
  1026. #define ADC_HTR_HT_Pos (0U)
  1027. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  1028. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
  1029. /******************* Bit definition for ADC_LTR register ********************/
  1030. #define ADC_LTR_LT_Pos (0U)
  1031. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  1032. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
  1033. /******************* Bit definition for ADC_SQR1 register *******************/
  1034. #define ADC_SQR1_SQ13_Pos (0U)
  1035. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  1036. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
  1037. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  1038. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  1039. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  1040. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  1041. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  1042. #define ADC_SQR1_SQ14_Pos (5U)
  1043. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  1044. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
  1045. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  1046. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  1047. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  1048. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  1049. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  1050. #define ADC_SQR1_SQ15_Pos (10U)
  1051. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  1052. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
  1053. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  1054. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  1055. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  1056. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  1057. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  1058. #define ADC_SQR1_SQ16_Pos (15U)
  1059. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  1060. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
  1061. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  1062. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  1063. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  1064. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  1065. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  1066. #define ADC_SQR1_L_Pos (20U)
  1067. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  1068. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
  1069. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  1070. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  1071. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  1072. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  1073. /******************* Bit definition for ADC_SQR2 register *******************/
  1074. #define ADC_SQR2_SQ7_Pos (0U)
  1075. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  1076. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
  1077. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  1078. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  1079. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  1080. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  1081. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  1082. #define ADC_SQR2_SQ8_Pos (5U)
  1083. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  1084. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
  1085. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  1086. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  1087. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  1088. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  1089. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  1090. #define ADC_SQR2_SQ9_Pos (10U)
  1091. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  1092. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
  1093. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  1094. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  1095. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  1096. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  1097. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  1098. #define ADC_SQR2_SQ10_Pos (15U)
  1099. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  1100. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
  1101. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  1102. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  1103. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  1104. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  1105. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  1106. #define ADC_SQR2_SQ11_Pos (20U)
  1107. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  1108. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
  1109. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  1110. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  1111. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  1112. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  1113. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  1114. #define ADC_SQR2_SQ12_Pos (25U)
  1115. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  1116. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
  1117. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  1118. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  1119. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  1120. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  1121. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  1122. /******************* Bit definition for ADC_SQR3 register *******************/
  1123. #define ADC_SQR3_SQ1_Pos (0U)
  1124. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  1125. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
  1126. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  1127. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  1128. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  1129. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  1130. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  1131. #define ADC_SQR3_SQ2_Pos (5U)
  1132. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  1133. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
  1134. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  1135. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  1136. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  1137. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  1138. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  1139. #define ADC_SQR3_SQ3_Pos (10U)
  1140. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  1141. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
  1142. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  1143. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  1144. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  1145. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  1146. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  1147. #define ADC_SQR3_SQ4_Pos (15U)
  1148. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  1149. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
  1150. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  1151. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  1152. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  1153. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  1154. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  1155. #define ADC_SQR3_SQ5_Pos (20U)
  1156. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  1157. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
  1158. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  1159. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  1160. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  1161. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  1162. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  1163. #define ADC_SQR3_SQ6_Pos (25U)
  1164. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  1165. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
  1166. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  1167. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  1168. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  1169. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  1170. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  1171. /******************* Bit definition for ADC_JSQR register *******************/
  1172. #define ADC_JSQR_JSQ1_Pos (0U)
  1173. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  1174. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
  1175. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  1176. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  1177. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  1178. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  1179. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  1180. #define ADC_JSQR_JSQ2_Pos (5U)
  1181. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  1182. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1183. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  1184. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  1185. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  1186. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  1187. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  1188. #define ADC_JSQR_JSQ3_Pos (10U)
  1189. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  1190. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1191. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  1192. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  1193. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  1194. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  1195. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  1196. #define ADC_JSQR_JSQ4_Pos (15U)
  1197. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  1198. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
  1199. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  1200. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  1201. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  1202. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  1203. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  1204. #define ADC_JSQR_JL_Pos (20U)
  1205. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  1206. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
  1207. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  1208. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  1209. /******************* Bit definition for ADC_JDR1 register *******************/
  1210. #define ADC_JDR1_JDATA_Pos (0U)
  1211. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  1212. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
  1213. /******************* Bit definition for ADC_JDR2 register *******************/
  1214. #define ADC_JDR2_JDATA_Pos (0U)
  1215. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  1216. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
  1217. /******************* Bit definition for ADC_JDR3 register *******************/
  1218. #define ADC_JDR3_JDATA_Pos (0U)
  1219. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  1220. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
  1221. /******************* Bit definition for ADC_JDR4 register *******************/
  1222. #define ADC_JDR4_JDATA_Pos (0U)
  1223. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  1224. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
  1225. /******************** Bit definition for ADC_DR register ********************/
  1226. #define ADC_DR_DATA_Pos (0U)
  1227. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1228. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
  1229. #define ADC_DR_ADC2DATA_Pos (16U)
  1230. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  1231. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
  1232. /******************* Bit definition for ADC_CSR register ********************/
  1233. #define ADC_CSR_AWD1_Pos (0U)
  1234. #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
  1235. #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
  1236. #define ADC_CSR_EOC1_Pos (1U)
  1237. #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
  1238. #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
  1239. #define ADC_CSR_JEOC1_Pos (2U)
  1240. #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
  1241. #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
  1242. #define ADC_CSR_JSTRT1_Pos (3U)
  1243. #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
  1244. #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
  1245. #define ADC_CSR_STRT1_Pos (4U)
  1246. #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
  1247. #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
  1248. #define ADC_CSR_OVR1_Pos (5U)
  1249. #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
  1250. #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
  1251. /* Legacy defines */
  1252. #define ADC_CSR_DOVR1 ADC_CSR_OVR1
  1253. /******************* Bit definition for ADC_CCR register ********************/
  1254. #define ADC_CCR_MULTI_Pos (0U)
  1255. #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
  1256. #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
  1257. #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
  1258. #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
  1259. #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
  1260. #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
  1261. #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
  1262. #define ADC_CCR_DELAY_Pos (8U)
  1263. #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
  1264. #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
  1265. #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
  1266. #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
  1267. #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
  1268. #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
  1269. #define ADC_CCR_DDS_Pos (13U)
  1270. #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
  1271. #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
  1272. #define ADC_CCR_DMA_Pos (14U)
  1273. #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
  1274. #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
  1275. #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
  1276. #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
  1277. #define ADC_CCR_ADCPRE_Pos (16U)
  1278. #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
  1279. #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
  1280. #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
  1281. #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
  1282. #define ADC_CCR_VBATE_Pos (22U)
  1283. #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
  1284. #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
  1285. #define ADC_CCR_TSVREFE_Pos (23U)
  1286. #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
  1287. #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
  1288. /******************* Bit definition for ADC_CDR register ********************/
  1289. #define ADC_CDR_DATA1_Pos (0U)
  1290. #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
  1291. #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
  1292. #define ADC_CDR_DATA2_Pos (16U)
  1293. #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
  1294. #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
  1295. /* Legacy defines */
  1296. #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
  1297. #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
  1298. /******************************************************************************/
  1299. /* */
  1300. /* CRC calculation unit */
  1301. /* */
  1302. /******************************************************************************/
  1303. /******************* Bit definition for CRC_DR register *********************/
  1304. #define CRC_DR_DR_Pos (0U)
  1305. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  1306. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  1307. /******************* Bit definition for CRC_IDR register ********************/
  1308. #define CRC_IDR_IDR_Pos (0U)
  1309. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  1310. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  1311. /******************** Bit definition for CRC_CR register ********************/
  1312. #define CRC_CR_RESET_Pos (0U)
  1313. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  1314. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  1315. /******************************************************************************/
  1316. /* */
  1317. /* DMA Controller */
  1318. /* */
  1319. /******************************************************************************/
  1320. /******************** Bits definition for DMA_SxCR register *****************/
  1321. #define DMA_SxCR_CHSEL_Pos (25U)
  1322. #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
  1323. #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
  1324. #define DMA_SxCR_CHSEL_0 0x02000000U
  1325. #define DMA_SxCR_CHSEL_1 0x04000000U
  1326. #define DMA_SxCR_CHSEL_2 0x08000000U
  1327. #define DMA_SxCR_MBURST_Pos (23U)
  1328. #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
  1329. #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
  1330. #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
  1331. #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
  1332. #define DMA_SxCR_PBURST_Pos (21U)
  1333. #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
  1334. #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
  1335. #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
  1336. #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
  1337. #define DMA_SxCR_CT_Pos (19U)
  1338. #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
  1339. #define DMA_SxCR_CT DMA_SxCR_CT_Msk
  1340. #define DMA_SxCR_DBM_Pos (18U)
  1341. #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
  1342. #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
  1343. #define DMA_SxCR_PL_Pos (16U)
  1344. #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
  1345. #define DMA_SxCR_PL DMA_SxCR_PL_Msk
  1346. #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
  1347. #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
  1348. #define DMA_SxCR_PINCOS_Pos (15U)
  1349. #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
  1350. #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
  1351. #define DMA_SxCR_MSIZE_Pos (13U)
  1352. #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
  1353. #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
  1354. #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
  1355. #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
  1356. #define DMA_SxCR_PSIZE_Pos (11U)
  1357. #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
  1358. #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
  1359. #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
  1360. #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
  1361. #define DMA_SxCR_MINC_Pos (10U)
  1362. #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
  1363. #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
  1364. #define DMA_SxCR_PINC_Pos (9U)
  1365. #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
  1366. #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
  1367. #define DMA_SxCR_CIRC_Pos (8U)
  1368. #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
  1369. #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
  1370. #define DMA_SxCR_DIR_Pos (6U)
  1371. #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
  1372. #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
  1373. #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
  1374. #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
  1375. #define DMA_SxCR_PFCTRL_Pos (5U)
  1376. #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
  1377. #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
  1378. #define DMA_SxCR_TCIE_Pos (4U)
  1379. #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
  1380. #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
  1381. #define DMA_SxCR_HTIE_Pos (3U)
  1382. #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
  1383. #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
  1384. #define DMA_SxCR_TEIE_Pos (2U)
  1385. #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
  1386. #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
  1387. #define DMA_SxCR_DMEIE_Pos (1U)
  1388. #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
  1389. #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
  1390. #define DMA_SxCR_EN_Pos (0U)
  1391. #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
  1392. #define DMA_SxCR_EN DMA_SxCR_EN_Msk
  1393. /* Legacy defines */
  1394. #define DMA_SxCR_ACK_Pos (20U)
  1395. #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
  1396. #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
  1397. /******************** Bits definition for DMA_SxCNDTR register **************/
  1398. #define DMA_SxNDT_Pos (0U)
  1399. #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
  1400. #define DMA_SxNDT DMA_SxNDT_Msk
  1401. #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
  1402. #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
  1403. #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
  1404. #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
  1405. #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
  1406. #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
  1407. #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
  1408. #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
  1409. #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
  1410. #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
  1411. #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
  1412. #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
  1413. #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
  1414. #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
  1415. #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
  1416. #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
  1417. /******************** Bits definition for DMA_SxFCR register ****************/
  1418. #define DMA_SxFCR_FEIE_Pos (7U)
  1419. #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
  1420. #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
  1421. #define DMA_SxFCR_FS_Pos (3U)
  1422. #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
  1423. #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
  1424. #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
  1425. #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
  1426. #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
  1427. #define DMA_SxFCR_DMDIS_Pos (2U)
  1428. #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
  1429. #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
  1430. #define DMA_SxFCR_FTH_Pos (0U)
  1431. #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
  1432. #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
  1433. #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
  1434. #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
  1435. /******************** Bits definition for DMA_LISR register *****************/
  1436. #define DMA_LISR_TCIF3_Pos (27U)
  1437. #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
  1438. #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
  1439. #define DMA_LISR_HTIF3_Pos (26U)
  1440. #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
  1441. #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
  1442. #define DMA_LISR_TEIF3_Pos (25U)
  1443. #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
  1444. #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
  1445. #define DMA_LISR_DMEIF3_Pos (24U)
  1446. #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
  1447. #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
  1448. #define DMA_LISR_FEIF3_Pos (22U)
  1449. #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
  1450. #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
  1451. #define DMA_LISR_TCIF2_Pos (21U)
  1452. #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
  1453. #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
  1454. #define DMA_LISR_HTIF2_Pos (20U)
  1455. #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
  1456. #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
  1457. #define DMA_LISR_TEIF2_Pos (19U)
  1458. #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
  1459. #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
  1460. #define DMA_LISR_DMEIF2_Pos (18U)
  1461. #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
  1462. #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
  1463. #define DMA_LISR_FEIF2_Pos (16U)
  1464. #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
  1465. #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
  1466. #define DMA_LISR_TCIF1_Pos (11U)
  1467. #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
  1468. #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
  1469. #define DMA_LISR_HTIF1_Pos (10U)
  1470. #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
  1471. #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
  1472. #define DMA_LISR_TEIF1_Pos (9U)
  1473. #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
  1474. #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
  1475. #define DMA_LISR_DMEIF1_Pos (8U)
  1476. #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
  1477. #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
  1478. #define DMA_LISR_FEIF1_Pos (6U)
  1479. #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
  1480. #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
  1481. #define DMA_LISR_TCIF0_Pos (5U)
  1482. #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
  1483. #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
  1484. #define DMA_LISR_HTIF0_Pos (4U)
  1485. #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
  1486. #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
  1487. #define DMA_LISR_TEIF0_Pos (3U)
  1488. #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
  1489. #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
  1490. #define DMA_LISR_DMEIF0_Pos (2U)
  1491. #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
  1492. #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
  1493. #define DMA_LISR_FEIF0_Pos (0U)
  1494. #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
  1495. #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
  1496. /******************** Bits definition for DMA_HISR register *****************/
  1497. #define DMA_HISR_TCIF7_Pos (27U)
  1498. #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
  1499. #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
  1500. #define DMA_HISR_HTIF7_Pos (26U)
  1501. #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
  1502. #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
  1503. #define DMA_HISR_TEIF7_Pos (25U)
  1504. #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
  1505. #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
  1506. #define DMA_HISR_DMEIF7_Pos (24U)
  1507. #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
  1508. #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
  1509. #define DMA_HISR_FEIF7_Pos (22U)
  1510. #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
  1511. #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
  1512. #define DMA_HISR_TCIF6_Pos (21U)
  1513. #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
  1514. #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
  1515. #define DMA_HISR_HTIF6_Pos (20U)
  1516. #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
  1517. #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
  1518. #define DMA_HISR_TEIF6_Pos (19U)
  1519. #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
  1520. #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
  1521. #define DMA_HISR_DMEIF6_Pos (18U)
  1522. #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
  1523. #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
  1524. #define DMA_HISR_FEIF6_Pos (16U)
  1525. #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
  1526. #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
  1527. #define DMA_HISR_TCIF5_Pos (11U)
  1528. #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
  1529. #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
  1530. #define DMA_HISR_HTIF5_Pos (10U)
  1531. #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
  1532. #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
  1533. #define DMA_HISR_TEIF5_Pos (9U)
  1534. #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
  1535. #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
  1536. #define DMA_HISR_DMEIF5_Pos (8U)
  1537. #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
  1538. #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
  1539. #define DMA_HISR_FEIF5_Pos (6U)
  1540. #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
  1541. #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
  1542. #define DMA_HISR_TCIF4_Pos (5U)
  1543. #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
  1544. #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
  1545. #define DMA_HISR_HTIF4_Pos (4U)
  1546. #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
  1547. #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
  1548. #define DMA_HISR_TEIF4_Pos (3U)
  1549. #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
  1550. #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
  1551. #define DMA_HISR_DMEIF4_Pos (2U)
  1552. #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
  1553. #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
  1554. #define DMA_HISR_FEIF4_Pos (0U)
  1555. #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
  1556. #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
  1557. /******************** Bits definition for DMA_LIFCR register ****************/
  1558. #define DMA_LIFCR_CTCIF3_Pos (27U)
  1559. #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
  1560. #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
  1561. #define DMA_LIFCR_CHTIF3_Pos (26U)
  1562. #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
  1563. #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
  1564. #define DMA_LIFCR_CTEIF3_Pos (25U)
  1565. #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
  1566. #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
  1567. #define DMA_LIFCR_CDMEIF3_Pos (24U)
  1568. #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
  1569. #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
  1570. #define DMA_LIFCR_CFEIF3_Pos (22U)
  1571. #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
  1572. #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
  1573. #define DMA_LIFCR_CTCIF2_Pos (21U)
  1574. #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
  1575. #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
  1576. #define DMA_LIFCR_CHTIF2_Pos (20U)
  1577. #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
  1578. #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
  1579. #define DMA_LIFCR_CTEIF2_Pos (19U)
  1580. #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
  1581. #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
  1582. #define DMA_LIFCR_CDMEIF2_Pos (18U)
  1583. #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
  1584. #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
  1585. #define DMA_LIFCR_CFEIF2_Pos (16U)
  1586. #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
  1587. #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
  1588. #define DMA_LIFCR_CTCIF1_Pos (11U)
  1589. #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
  1590. #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
  1591. #define DMA_LIFCR_CHTIF1_Pos (10U)
  1592. #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
  1593. #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
  1594. #define DMA_LIFCR_CTEIF1_Pos (9U)
  1595. #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
  1596. #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
  1597. #define DMA_LIFCR_CDMEIF1_Pos (8U)
  1598. #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
  1599. #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
  1600. #define DMA_LIFCR_CFEIF1_Pos (6U)
  1601. #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
  1602. #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
  1603. #define DMA_LIFCR_CTCIF0_Pos (5U)
  1604. #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
  1605. #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
  1606. #define DMA_LIFCR_CHTIF0_Pos (4U)
  1607. #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
  1608. #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
  1609. #define DMA_LIFCR_CTEIF0_Pos (3U)
  1610. #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
  1611. #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
  1612. #define DMA_LIFCR_CDMEIF0_Pos (2U)
  1613. #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
  1614. #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
  1615. #define DMA_LIFCR_CFEIF0_Pos (0U)
  1616. #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
  1617. #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
  1618. /******************** Bits definition for DMA_HIFCR register ****************/
  1619. #define DMA_HIFCR_CTCIF7_Pos (27U)
  1620. #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
  1621. #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
  1622. #define DMA_HIFCR_CHTIF7_Pos (26U)
  1623. #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
  1624. #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
  1625. #define DMA_HIFCR_CTEIF7_Pos (25U)
  1626. #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
  1627. #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
  1628. #define DMA_HIFCR_CDMEIF7_Pos (24U)
  1629. #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
  1630. #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
  1631. #define DMA_HIFCR_CFEIF7_Pos (22U)
  1632. #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
  1633. #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
  1634. #define DMA_HIFCR_CTCIF6_Pos (21U)
  1635. #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
  1636. #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
  1637. #define DMA_HIFCR_CHTIF6_Pos (20U)
  1638. #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
  1639. #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
  1640. #define DMA_HIFCR_CTEIF6_Pos (19U)
  1641. #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
  1642. #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
  1643. #define DMA_HIFCR_CDMEIF6_Pos (18U)
  1644. #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
  1645. #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
  1646. #define DMA_HIFCR_CFEIF6_Pos (16U)
  1647. #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
  1648. #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
  1649. #define DMA_HIFCR_CTCIF5_Pos (11U)
  1650. #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
  1651. #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
  1652. #define DMA_HIFCR_CHTIF5_Pos (10U)
  1653. #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
  1654. #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
  1655. #define DMA_HIFCR_CTEIF5_Pos (9U)
  1656. #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
  1657. #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
  1658. #define DMA_HIFCR_CDMEIF5_Pos (8U)
  1659. #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
  1660. #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
  1661. #define DMA_HIFCR_CFEIF5_Pos (6U)
  1662. #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
  1663. #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
  1664. #define DMA_HIFCR_CTCIF4_Pos (5U)
  1665. #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
  1666. #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
  1667. #define DMA_HIFCR_CHTIF4_Pos (4U)
  1668. #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
  1669. #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
  1670. #define DMA_HIFCR_CTEIF4_Pos (3U)
  1671. #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
  1672. #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
  1673. #define DMA_HIFCR_CDMEIF4_Pos (2U)
  1674. #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
  1675. #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
  1676. #define DMA_HIFCR_CFEIF4_Pos (0U)
  1677. #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
  1678. #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
  1679. /****************** Bit definition for DMA_SxPAR register ********************/
  1680. #define DMA_SxPAR_PA_Pos (0U)
  1681. #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
  1682. #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
  1683. /****************** Bit definition for DMA_SxM0AR register ********************/
  1684. #define DMA_SxM0AR_M0A_Pos (0U)
  1685. #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
  1686. #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
  1687. /****************** Bit definition for DMA_SxM1AR register ********************/
  1688. #define DMA_SxM1AR_M1A_Pos (0U)
  1689. #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
  1690. #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
  1691. /******************************************************************************/
  1692. /* */
  1693. /* External Interrupt/Event Controller */
  1694. /* */
  1695. /******************************************************************************/
  1696. /******************* Bit definition for EXTI_IMR register *******************/
  1697. #define EXTI_IMR_MR0_Pos (0U)
  1698. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  1699. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  1700. #define EXTI_IMR_MR1_Pos (1U)
  1701. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  1702. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  1703. #define EXTI_IMR_MR2_Pos (2U)
  1704. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  1705. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  1706. #define EXTI_IMR_MR3_Pos (3U)
  1707. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  1708. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  1709. #define EXTI_IMR_MR4_Pos (4U)
  1710. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  1711. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  1712. #define EXTI_IMR_MR5_Pos (5U)
  1713. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  1714. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  1715. #define EXTI_IMR_MR6_Pos (6U)
  1716. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  1717. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  1718. #define EXTI_IMR_MR7_Pos (7U)
  1719. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  1720. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  1721. #define EXTI_IMR_MR8_Pos (8U)
  1722. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  1723. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  1724. #define EXTI_IMR_MR9_Pos (9U)
  1725. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  1726. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  1727. #define EXTI_IMR_MR10_Pos (10U)
  1728. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  1729. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  1730. #define EXTI_IMR_MR11_Pos (11U)
  1731. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  1732. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  1733. #define EXTI_IMR_MR12_Pos (12U)
  1734. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  1735. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  1736. #define EXTI_IMR_MR13_Pos (13U)
  1737. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  1738. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  1739. #define EXTI_IMR_MR14_Pos (14U)
  1740. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  1741. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  1742. #define EXTI_IMR_MR15_Pos (15U)
  1743. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  1744. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  1745. #define EXTI_IMR_MR16_Pos (16U)
  1746. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  1747. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  1748. #define EXTI_IMR_MR17_Pos (17U)
  1749. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  1750. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  1751. #define EXTI_IMR_MR18_Pos (18U)
  1752. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  1753. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  1754. #define EXTI_IMR_MR19_Pos (19U)
  1755. #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  1756. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  1757. #define EXTI_IMR_MR20_Pos (20U)
  1758. #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
  1759. #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
  1760. #define EXTI_IMR_MR21_Pos (21U)
  1761. #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
  1762. #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
  1763. #define EXTI_IMR_MR22_Pos (22U)
  1764. #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
  1765. #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
  1766. /* Reference Defines */
  1767. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  1768. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  1769. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  1770. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  1771. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  1772. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  1773. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  1774. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  1775. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  1776. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  1777. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  1778. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  1779. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  1780. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  1781. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  1782. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  1783. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  1784. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  1785. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  1786. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  1787. #define EXTI_IMR_IM20 EXTI_IMR_MR20
  1788. #define EXTI_IMR_IM21 EXTI_IMR_MR21
  1789. #define EXTI_IMR_IM22 EXTI_IMR_MR22
  1790. #define EXTI_IMR_IM_Pos (0U)
  1791. #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
  1792. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  1793. /******************* Bit definition for EXTI_EMR register *******************/
  1794. #define EXTI_EMR_MR0_Pos (0U)
  1795. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  1796. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  1797. #define EXTI_EMR_MR1_Pos (1U)
  1798. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  1799. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  1800. #define EXTI_EMR_MR2_Pos (2U)
  1801. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  1802. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  1803. #define EXTI_EMR_MR3_Pos (3U)
  1804. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  1805. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  1806. #define EXTI_EMR_MR4_Pos (4U)
  1807. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  1808. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  1809. #define EXTI_EMR_MR5_Pos (5U)
  1810. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  1811. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  1812. #define EXTI_EMR_MR6_Pos (6U)
  1813. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  1814. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  1815. #define EXTI_EMR_MR7_Pos (7U)
  1816. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  1817. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  1818. #define EXTI_EMR_MR8_Pos (8U)
  1819. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  1820. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  1821. #define EXTI_EMR_MR9_Pos (9U)
  1822. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  1823. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  1824. #define EXTI_EMR_MR10_Pos (10U)
  1825. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  1826. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  1827. #define EXTI_EMR_MR11_Pos (11U)
  1828. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  1829. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  1830. #define EXTI_EMR_MR12_Pos (12U)
  1831. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  1832. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  1833. #define EXTI_EMR_MR13_Pos (13U)
  1834. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  1835. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  1836. #define EXTI_EMR_MR14_Pos (14U)
  1837. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  1838. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  1839. #define EXTI_EMR_MR15_Pos (15U)
  1840. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  1841. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  1842. #define EXTI_EMR_MR16_Pos (16U)
  1843. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  1844. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  1845. #define EXTI_EMR_MR17_Pos (17U)
  1846. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  1847. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  1848. #define EXTI_EMR_MR18_Pos (18U)
  1849. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  1850. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  1851. #define EXTI_EMR_MR19_Pos (19U)
  1852. #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  1853. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  1854. #define EXTI_EMR_MR20_Pos (20U)
  1855. #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
  1856. #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
  1857. #define EXTI_EMR_MR21_Pos (21U)
  1858. #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
  1859. #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
  1860. #define EXTI_EMR_MR22_Pos (22U)
  1861. #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
  1862. #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
  1863. /* Reference Defines */
  1864. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  1865. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  1866. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  1867. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  1868. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  1869. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  1870. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  1871. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  1872. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  1873. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  1874. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  1875. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  1876. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  1877. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  1878. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  1879. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  1880. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  1881. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  1882. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  1883. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  1884. #define EXTI_EMR_EM20 EXTI_EMR_MR20
  1885. #define EXTI_EMR_EM21 EXTI_EMR_MR21
  1886. #define EXTI_EMR_EM22 EXTI_EMR_MR22
  1887. /****************** Bit definition for EXTI_RTSR register *******************/
  1888. #define EXTI_RTSR_TR0_Pos (0U)
  1889. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  1890. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  1891. #define EXTI_RTSR_TR1_Pos (1U)
  1892. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  1893. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  1894. #define EXTI_RTSR_TR2_Pos (2U)
  1895. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  1896. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  1897. #define EXTI_RTSR_TR3_Pos (3U)
  1898. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  1899. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  1900. #define EXTI_RTSR_TR4_Pos (4U)
  1901. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  1902. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  1903. #define EXTI_RTSR_TR5_Pos (5U)
  1904. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  1905. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  1906. #define EXTI_RTSR_TR6_Pos (6U)
  1907. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  1908. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  1909. #define EXTI_RTSR_TR7_Pos (7U)
  1910. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  1911. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  1912. #define EXTI_RTSR_TR8_Pos (8U)
  1913. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  1914. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  1915. #define EXTI_RTSR_TR9_Pos (9U)
  1916. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  1917. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  1918. #define EXTI_RTSR_TR10_Pos (10U)
  1919. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  1920. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  1921. #define EXTI_RTSR_TR11_Pos (11U)
  1922. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  1923. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  1924. #define EXTI_RTSR_TR12_Pos (12U)
  1925. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  1926. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  1927. #define EXTI_RTSR_TR13_Pos (13U)
  1928. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  1929. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  1930. #define EXTI_RTSR_TR14_Pos (14U)
  1931. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  1932. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  1933. #define EXTI_RTSR_TR15_Pos (15U)
  1934. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  1935. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  1936. #define EXTI_RTSR_TR16_Pos (16U)
  1937. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  1938. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  1939. #define EXTI_RTSR_TR17_Pos (17U)
  1940. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  1941. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  1942. #define EXTI_RTSR_TR18_Pos (18U)
  1943. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  1944. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  1945. #define EXTI_RTSR_TR19_Pos (19U)
  1946. #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  1947. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  1948. #define EXTI_RTSR_TR20_Pos (20U)
  1949. #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
  1950. #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
  1951. #define EXTI_RTSR_TR21_Pos (21U)
  1952. #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
  1953. #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
  1954. #define EXTI_RTSR_TR22_Pos (22U)
  1955. #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
  1956. #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
  1957. /****************** Bit definition for EXTI_FTSR register *******************/
  1958. #define EXTI_FTSR_TR0_Pos (0U)
  1959. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  1960. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  1961. #define EXTI_FTSR_TR1_Pos (1U)
  1962. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  1963. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  1964. #define EXTI_FTSR_TR2_Pos (2U)
  1965. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  1966. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  1967. #define EXTI_FTSR_TR3_Pos (3U)
  1968. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  1969. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  1970. #define EXTI_FTSR_TR4_Pos (4U)
  1971. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  1972. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  1973. #define EXTI_FTSR_TR5_Pos (5U)
  1974. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  1975. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  1976. #define EXTI_FTSR_TR6_Pos (6U)
  1977. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  1978. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  1979. #define EXTI_FTSR_TR7_Pos (7U)
  1980. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  1981. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  1982. #define EXTI_FTSR_TR8_Pos (8U)
  1983. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  1984. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  1985. #define EXTI_FTSR_TR9_Pos (9U)
  1986. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  1987. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  1988. #define EXTI_FTSR_TR10_Pos (10U)
  1989. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  1990. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  1991. #define EXTI_FTSR_TR11_Pos (11U)
  1992. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  1993. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  1994. #define EXTI_FTSR_TR12_Pos (12U)
  1995. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  1996. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  1997. #define EXTI_FTSR_TR13_Pos (13U)
  1998. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  1999. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  2000. #define EXTI_FTSR_TR14_Pos (14U)
  2001. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  2002. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  2003. #define EXTI_FTSR_TR15_Pos (15U)
  2004. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  2005. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  2006. #define EXTI_FTSR_TR16_Pos (16U)
  2007. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  2008. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  2009. #define EXTI_FTSR_TR17_Pos (17U)
  2010. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  2011. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  2012. #define EXTI_FTSR_TR18_Pos (18U)
  2013. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  2014. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  2015. #define EXTI_FTSR_TR19_Pos (19U)
  2016. #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  2017. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  2018. #define EXTI_FTSR_TR20_Pos (20U)
  2019. #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
  2020. #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
  2021. #define EXTI_FTSR_TR21_Pos (21U)
  2022. #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
  2023. #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
  2024. #define EXTI_FTSR_TR22_Pos (22U)
  2025. #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
  2026. #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
  2027. /****************** Bit definition for EXTI_SWIER register ******************/
  2028. #define EXTI_SWIER_SWIER0_Pos (0U)
  2029. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  2030. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  2031. #define EXTI_SWIER_SWIER1_Pos (1U)
  2032. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  2033. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  2034. #define EXTI_SWIER_SWIER2_Pos (2U)
  2035. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  2036. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  2037. #define EXTI_SWIER_SWIER3_Pos (3U)
  2038. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  2039. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  2040. #define EXTI_SWIER_SWIER4_Pos (4U)
  2041. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  2042. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  2043. #define EXTI_SWIER_SWIER5_Pos (5U)
  2044. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  2045. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  2046. #define EXTI_SWIER_SWIER6_Pos (6U)
  2047. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  2048. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  2049. #define EXTI_SWIER_SWIER7_Pos (7U)
  2050. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  2051. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  2052. #define EXTI_SWIER_SWIER8_Pos (8U)
  2053. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  2054. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  2055. #define EXTI_SWIER_SWIER9_Pos (9U)
  2056. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  2057. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  2058. #define EXTI_SWIER_SWIER10_Pos (10U)
  2059. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  2060. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  2061. #define EXTI_SWIER_SWIER11_Pos (11U)
  2062. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  2063. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  2064. #define EXTI_SWIER_SWIER12_Pos (12U)
  2065. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  2066. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  2067. #define EXTI_SWIER_SWIER13_Pos (13U)
  2068. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  2069. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  2070. #define EXTI_SWIER_SWIER14_Pos (14U)
  2071. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  2072. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  2073. #define EXTI_SWIER_SWIER15_Pos (15U)
  2074. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  2075. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  2076. #define EXTI_SWIER_SWIER16_Pos (16U)
  2077. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  2078. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  2079. #define EXTI_SWIER_SWIER17_Pos (17U)
  2080. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  2081. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  2082. #define EXTI_SWIER_SWIER18_Pos (18U)
  2083. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  2084. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  2085. #define EXTI_SWIER_SWIER19_Pos (19U)
  2086. #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  2087. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  2088. #define EXTI_SWIER_SWIER20_Pos (20U)
  2089. #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
  2090. #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
  2091. #define EXTI_SWIER_SWIER21_Pos (21U)
  2092. #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
  2093. #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
  2094. #define EXTI_SWIER_SWIER22_Pos (22U)
  2095. #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
  2096. #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
  2097. /******************* Bit definition for EXTI_PR register ********************/
  2098. #define EXTI_PR_PR0_Pos (0U)
  2099. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  2100. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  2101. #define EXTI_PR_PR1_Pos (1U)
  2102. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  2103. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  2104. #define EXTI_PR_PR2_Pos (2U)
  2105. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  2106. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  2107. #define EXTI_PR_PR3_Pos (3U)
  2108. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  2109. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  2110. #define EXTI_PR_PR4_Pos (4U)
  2111. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  2112. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  2113. #define EXTI_PR_PR5_Pos (5U)
  2114. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  2115. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  2116. #define EXTI_PR_PR6_Pos (6U)
  2117. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  2118. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  2119. #define EXTI_PR_PR7_Pos (7U)
  2120. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  2121. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  2122. #define EXTI_PR_PR8_Pos (8U)
  2123. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  2124. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  2125. #define EXTI_PR_PR9_Pos (9U)
  2126. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  2127. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  2128. #define EXTI_PR_PR10_Pos (10U)
  2129. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  2130. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  2131. #define EXTI_PR_PR11_Pos (11U)
  2132. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  2133. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  2134. #define EXTI_PR_PR12_Pos (12U)
  2135. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  2136. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  2137. #define EXTI_PR_PR13_Pos (13U)
  2138. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  2139. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  2140. #define EXTI_PR_PR14_Pos (14U)
  2141. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  2142. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  2143. #define EXTI_PR_PR15_Pos (15U)
  2144. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  2145. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  2146. #define EXTI_PR_PR16_Pos (16U)
  2147. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  2148. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  2149. #define EXTI_PR_PR17_Pos (17U)
  2150. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  2151. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  2152. #define EXTI_PR_PR18_Pos (18U)
  2153. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  2154. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  2155. #define EXTI_PR_PR19_Pos (19U)
  2156. #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  2157. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
  2158. #define EXTI_PR_PR20_Pos (20U)
  2159. #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
  2160. #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
  2161. #define EXTI_PR_PR21_Pos (21U)
  2162. #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
  2163. #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
  2164. #define EXTI_PR_PR22_Pos (22U)
  2165. #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
  2166. #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
  2167. /******************************************************************************/
  2168. /* */
  2169. /* FLASH */
  2170. /* */
  2171. /******************************************************************************/
  2172. /******************* Bits definition for FLASH_ACR register *****************/
  2173. #define FLASH_ACR_LATENCY_Pos (0U)
  2174. #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
  2175. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  2176. #define FLASH_ACR_LATENCY_0WS 0x00000000U
  2177. #define FLASH_ACR_LATENCY_1WS 0x00000001U
  2178. #define FLASH_ACR_LATENCY_2WS 0x00000002U
  2179. #define FLASH_ACR_LATENCY_3WS 0x00000003U
  2180. #define FLASH_ACR_LATENCY_4WS 0x00000004U
  2181. #define FLASH_ACR_LATENCY_5WS 0x00000005U
  2182. #define FLASH_ACR_LATENCY_6WS 0x00000006U
  2183. #define FLASH_ACR_LATENCY_7WS 0x00000007U
  2184. #define FLASH_ACR_PRFTEN_Pos (8U)
  2185. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  2186. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  2187. #define FLASH_ACR_ICEN_Pos (9U)
  2188. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  2189. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  2190. #define FLASH_ACR_DCEN_Pos (10U)
  2191. #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
  2192. #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
  2193. #define FLASH_ACR_ICRST_Pos (11U)
  2194. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  2195. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  2196. #define FLASH_ACR_DCRST_Pos (12U)
  2197. #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
  2198. #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
  2199. #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
  2200. #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
  2201. #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
  2202. #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
  2203. #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
  2204. #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
  2205. /******************* Bits definition for FLASH_SR register ******************/
  2206. #define FLASH_SR_EOP_Pos (0U)
  2207. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  2208. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  2209. #define FLASH_SR_SOP_Pos (1U)
  2210. #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
  2211. #define FLASH_SR_SOP FLASH_SR_SOP_Msk
  2212. #define FLASH_SR_WRPERR_Pos (4U)
  2213. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  2214. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  2215. #define FLASH_SR_PGAERR_Pos (5U)
  2216. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  2217. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  2218. #define FLASH_SR_PGPERR_Pos (6U)
  2219. #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
  2220. #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
  2221. #define FLASH_SR_PGSERR_Pos (7U)
  2222. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  2223. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  2224. #define FLASH_SR_RDERR_Pos (8U)
  2225. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
  2226. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  2227. #define FLASH_SR_BSY_Pos (16U)
  2228. #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
  2229. #define FLASH_SR_BSY FLASH_SR_BSY_Msk
  2230. /******************* Bits definition for FLASH_CR register ******************/
  2231. #define FLASH_CR_PG_Pos (0U)
  2232. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  2233. #define FLASH_CR_PG FLASH_CR_PG_Msk
  2234. #define FLASH_CR_SER_Pos (1U)
  2235. #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
  2236. #define FLASH_CR_SER FLASH_CR_SER_Msk
  2237. #define FLASH_CR_MER_Pos (2U)
  2238. #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  2239. #define FLASH_CR_MER FLASH_CR_MER_Msk
  2240. #define FLASH_CR_SNB_Pos (3U)
  2241. #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
  2242. #define FLASH_CR_SNB FLASH_CR_SNB_Msk
  2243. #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
  2244. #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
  2245. #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
  2246. #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
  2247. #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
  2248. #define FLASH_CR_PSIZE_Pos (8U)
  2249. #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
  2250. #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
  2251. #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
  2252. #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
  2253. #define FLASH_CR_STRT_Pos (16U)
  2254. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  2255. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  2256. #define FLASH_CR_EOPIE_Pos (24U)
  2257. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  2258. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  2259. #define FLASH_CR_LOCK_Pos (31U)
  2260. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  2261. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  2262. /******************* Bits definition for FLASH_OPTCR register ***************/
  2263. #define FLASH_OPTCR_OPTLOCK_Pos (0U)
  2264. #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
  2265. #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
  2266. #define FLASH_OPTCR_OPTSTRT_Pos (1U)
  2267. #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
  2268. #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
  2269. #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
  2270. #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
  2271. #define FLASH_OPTCR_BOR_LEV_Pos (2U)
  2272. #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
  2273. #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
  2274. #define FLASH_OPTCR_WDG_SW_Pos (5U)
  2275. #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
  2276. #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
  2277. #define FLASH_OPTCR_nRST_STOP_Pos (6U)
  2278. #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
  2279. #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
  2280. #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
  2281. #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
  2282. #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
  2283. #define FLASH_OPTCR_RDP_Pos (8U)
  2284. #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
  2285. #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
  2286. #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
  2287. #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
  2288. #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
  2289. #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
  2290. #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
  2291. #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
  2292. #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
  2293. #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
  2294. #define FLASH_OPTCR_nWRP_Pos (16U)
  2295. #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
  2296. #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
  2297. #define FLASH_OPTCR_nWRP_0 0x00010000U
  2298. #define FLASH_OPTCR_nWRP_1 0x00020000U
  2299. #define FLASH_OPTCR_nWRP_2 0x00040000U
  2300. #define FLASH_OPTCR_nWRP_3 0x00080000U
  2301. #define FLASH_OPTCR_nWRP_4 0x00100000U
  2302. #define FLASH_OPTCR_nWRP_5 0x00200000U
  2303. #define FLASH_OPTCR_nWRP_6 0x00400000U
  2304. #define FLASH_OPTCR_nWRP_7 0x00800000U
  2305. #define FLASH_OPTCR_nWRP_8 0x01000000U
  2306. #define FLASH_OPTCR_nWRP_9 0x02000000U
  2307. #define FLASH_OPTCR_nWRP_10 0x04000000U
  2308. #define FLASH_OPTCR_nWRP_11 0x08000000U
  2309. /****************** Bits definition for FLASH_OPTCR1 register ***************/
  2310. #define FLASH_OPTCR1_nWRP_Pos (16U)
  2311. #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
  2312. #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
  2313. #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
  2314. #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
  2315. #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
  2316. #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
  2317. #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
  2318. #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
  2319. #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
  2320. #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
  2321. #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
  2322. #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
  2323. #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
  2324. #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
  2325. /******************************************************************************/
  2326. /* */
  2327. /* General Purpose I/O */
  2328. /* */
  2329. /******************************************************************************/
  2330. /****************** Bits definition for GPIO_MODER register *****************/
  2331. #define GPIO_MODER_MODER0_Pos (0U)
  2332. #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  2333. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  2334. #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  2335. #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  2336. #define GPIO_MODER_MODER1_Pos (2U)
  2337. #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  2338. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  2339. #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  2340. #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  2341. #define GPIO_MODER_MODER2_Pos (4U)
  2342. #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  2343. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  2344. #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  2345. #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  2346. #define GPIO_MODER_MODER3_Pos (6U)
  2347. #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  2348. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  2349. #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  2350. #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  2351. #define GPIO_MODER_MODER4_Pos (8U)
  2352. #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  2353. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  2354. #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  2355. #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  2356. #define GPIO_MODER_MODER5_Pos (10U)
  2357. #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  2358. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  2359. #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  2360. #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  2361. #define GPIO_MODER_MODER6_Pos (12U)
  2362. #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  2363. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  2364. #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  2365. #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  2366. #define GPIO_MODER_MODER7_Pos (14U)
  2367. #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  2368. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  2369. #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  2370. #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  2371. #define GPIO_MODER_MODER8_Pos (16U)
  2372. #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  2373. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  2374. #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  2375. #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  2376. #define GPIO_MODER_MODER9_Pos (18U)
  2377. #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  2378. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  2379. #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  2380. #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  2381. #define GPIO_MODER_MODER10_Pos (20U)
  2382. #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  2383. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  2384. #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  2385. #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  2386. #define GPIO_MODER_MODER11_Pos (22U)
  2387. #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  2388. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  2389. #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  2390. #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  2391. #define GPIO_MODER_MODER12_Pos (24U)
  2392. #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  2393. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  2394. #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  2395. #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  2396. #define GPIO_MODER_MODER13_Pos (26U)
  2397. #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  2398. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  2399. #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  2400. #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  2401. #define GPIO_MODER_MODER14_Pos (28U)
  2402. #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  2403. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  2404. #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  2405. #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  2406. #define GPIO_MODER_MODER15_Pos (30U)
  2407. #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  2408. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  2409. #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  2410. #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  2411. /* Legacy defines */
  2412. #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
  2413. #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
  2414. #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
  2415. #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
  2416. #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
  2417. #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
  2418. #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
  2419. #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
  2420. #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
  2421. #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
  2422. #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
  2423. #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
  2424. #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
  2425. #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
  2426. #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
  2427. #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
  2428. #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
  2429. #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
  2430. #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
  2431. #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
  2432. #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
  2433. #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
  2434. #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
  2435. #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
  2436. #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
  2437. #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
  2438. #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
  2439. #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
  2440. #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
  2441. #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
  2442. #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
  2443. #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
  2444. #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
  2445. #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
  2446. #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
  2447. #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
  2448. #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
  2449. #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
  2450. #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
  2451. #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
  2452. #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
  2453. #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
  2454. #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
  2455. #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
  2456. #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
  2457. #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
  2458. #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
  2459. #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
  2460. #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
  2461. #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
  2462. #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
  2463. #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
  2464. #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
  2465. #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
  2466. #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
  2467. #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
  2468. #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
  2469. #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
  2470. #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
  2471. #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
  2472. #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
  2473. #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
  2474. #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
  2475. #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
  2476. #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
  2477. #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
  2478. #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
  2479. #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
  2480. #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
  2481. #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
  2482. #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
  2483. #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
  2484. #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
  2485. #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
  2486. #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
  2487. #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
  2488. #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
  2489. #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
  2490. #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
  2491. #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
  2492. /****************** Bits definition for GPIO_OTYPER register ****************/
  2493. #define GPIO_OTYPER_OT0_Pos (0U)
  2494. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  2495. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  2496. #define GPIO_OTYPER_OT1_Pos (1U)
  2497. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  2498. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  2499. #define GPIO_OTYPER_OT2_Pos (2U)
  2500. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  2501. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  2502. #define GPIO_OTYPER_OT3_Pos (3U)
  2503. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  2504. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  2505. #define GPIO_OTYPER_OT4_Pos (4U)
  2506. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  2507. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  2508. #define GPIO_OTYPER_OT5_Pos (5U)
  2509. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  2510. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  2511. #define GPIO_OTYPER_OT6_Pos (6U)
  2512. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  2513. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  2514. #define GPIO_OTYPER_OT7_Pos (7U)
  2515. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  2516. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  2517. #define GPIO_OTYPER_OT8_Pos (8U)
  2518. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  2519. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  2520. #define GPIO_OTYPER_OT9_Pos (9U)
  2521. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  2522. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  2523. #define GPIO_OTYPER_OT10_Pos (10U)
  2524. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  2525. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  2526. #define GPIO_OTYPER_OT11_Pos (11U)
  2527. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  2528. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  2529. #define GPIO_OTYPER_OT12_Pos (12U)
  2530. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  2531. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  2532. #define GPIO_OTYPER_OT13_Pos (13U)
  2533. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  2534. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  2535. #define GPIO_OTYPER_OT14_Pos (14U)
  2536. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  2537. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  2538. #define GPIO_OTYPER_OT15_Pos (15U)
  2539. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  2540. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  2541. /* Legacy defines */
  2542. #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
  2543. #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
  2544. #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
  2545. #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
  2546. #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
  2547. #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
  2548. #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
  2549. #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
  2550. #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
  2551. #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
  2552. #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
  2553. #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
  2554. #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
  2555. #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
  2556. #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
  2557. #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
  2558. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  2559. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  2560. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  2561. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  2562. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  2563. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  2564. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  2565. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  2566. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  2567. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  2568. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  2569. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  2570. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  2571. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  2572. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  2573. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  2574. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  2575. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  2576. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  2577. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  2578. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  2579. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  2580. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  2581. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  2582. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  2583. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  2584. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  2585. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  2586. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  2587. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  2588. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  2589. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  2590. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  2591. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  2592. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  2593. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  2594. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  2595. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  2596. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  2597. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  2598. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  2599. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  2600. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  2601. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  2602. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  2603. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  2604. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  2605. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  2606. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  2607. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  2608. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  2609. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  2610. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  2611. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  2612. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  2613. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  2614. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  2615. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  2616. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  2617. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  2618. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  2619. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  2620. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  2621. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  2622. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  2623. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  2624. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  2625. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  2626. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  2627. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  2628. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  2629. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  2630. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  2631. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  2632. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  2633. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  2634. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  2635. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  2636. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  2637. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  2638. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  2639. /* Legacy defines */
  2640. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
  2641. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
  2642. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
  2643. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
  2644. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
  2645. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
  2646. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
  2647. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
  2648. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
  2649. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
  2650. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
  2651. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
  2652. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
  2653. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
  2654. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
  2655. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
  2656. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
  2657. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
  2658. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
  2659. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
  2660. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
  2661. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
  2662. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
  2663. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
  2664. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
  2665. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
  2666. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
  2667. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
  2668. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
  2669. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
  2670. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
  2671. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
  2672. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
  2673. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
  2674. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
  2675. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
  2676. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
  2677. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
  2678. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
  2679. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
  2680. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
  2681. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
  2682. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
  2683. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
  2684. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
  2685. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
  2686. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
  2687. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
  2688. /****************** Bits definition for GPIO_PUPDR register *****************/
  2689. #define GPIO_PUPDR_PUPD0_Pos (0U)
  2690. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  2691. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  2692. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  2693. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  2694. #define GPIO_PUPDR_PUPD1_Pos (2U)
  2695. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  2696. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  2697. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  2698. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  2699. #define GPIO_PUPDR_PUPD2_Pos (4U)
  2700. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  2701. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  2702. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  2703. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  2704. #define GPIO_PUPDR_PUPD3_Pos (6U)
  2705. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  2706. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  2707. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  2708. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  2709. #define GPIO_PUPDR_PUPD4_Pos (8U)
  2710. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  2711. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  2712. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  2713. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  2714. #define GPIO_PUPDR_PUPD5_Pos (10U)
  2715. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  2716. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  2717. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  2718. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  2719. #define GPIO_PUPDR_PUPD6_Pos (12U)
  2720. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  2721. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  2722. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  2723. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  2724. #define GPIO_PUPDR_PUPD7_Pos (14U)
  2725. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  2726. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  2727. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  2728. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  2729. #define GPIO_PUPDR_PUPD8_Pos (16U)
  2730. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  2731. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  2732. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  2733. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  2734. #define GPIO_PUPDR_PUPD9_Pos (18U)
  2735. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  2736. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  2737. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  2738. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  2739. #define GPIO_PUPDR_PUPD10_Pos (20U)
  2740. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  2741. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  2742. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  2743. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  2744. #define GPIO_PUPDR_PUPD11_Pos (22U)
  2745. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  2746. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  2747. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  2748. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  2749. #define GPIO_PUPDR_PUPD12_Pos (24U)
  2750. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  2751. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  2752. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  2753. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  2754. #define GPIO_PUPDR_PUPD13_Pos (26U)
  2755. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  2756. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  2757. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  2758. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  2759. #define GPIO_PUPDR_PUPD14_Pos (28U)
  2760. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  2761. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  2762. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  2763. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  2764. #define GPIO_PUPDR_PUPD15_Pos (30U)
  2765. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  2766. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  2767. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  2768. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  2769. /* Legacy defines */
  2770. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
  2771. #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
  2772. #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
  2773. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
  2774. #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
  2775. #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
  2776. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
  2777. #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
  2778. #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
  2779. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
  2780. #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
  2781. #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
  2782. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
  2783. #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
  2784. #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
  2785. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
  2786. #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
  2787. #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
  2788. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
  2789. #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
  2790. #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
  2791. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
  2792. #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
  2793. #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
  2794. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
  2795. #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
  2796. #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
  2797. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
  2798. #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
  2799. #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
  2800. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
  2801. #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
  2802. #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
  2803. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
  2804. #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
  2805. #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
  2806. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
  2807. #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
  2808. #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
  2809. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
  2810. #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
  2811. #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
  2812. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
  2813. #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
  2814. #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
  2815. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
  2816. #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
  2817. #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
  2818. /****************** Bits definition for GPIO_IDR register *******************/
  2819. #define GPIO_IDR_ID0_Pos (0U)
  2820. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  2821. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  2822. #define GPIO_IDR_ID1_Pos (1U)
  2823. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  2824. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  2825. #define GPIO_IDR_ID2_Pos (2U)
  2826. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  2827. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  2828. #define GPIO_IDR_ID3_Pos (3U)
  2829. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  2830. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  2831. #define GPIO_IDR_ID4_Pos (4U)
  2832. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  2833. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  2834. #define GPIO_IDR_ID5_Pos (5U)
  2835. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  2836. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  2837. #define GPIO_IDR_ID6_Pos (6U)
  2838. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  2839. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  2840. #define GPIO_IDR_ID7_Pos (7U)
  2841. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  2842. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  2843. #define GPIO_IDR_ID8_Pos (8U)
  2844. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  2845. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  2846. #define GPIO_IDR_ID9_Pos (9U)
  2847. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  2848. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  2849. #define GPIO_IDR_ID10_Pos (10U)
  2850. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  2851. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  2852. #define GPIO_IDR_ID11_Pos (11U)
  2853. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  2854. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  2855. #define GPIO_IDR_ID12_Pos (12U)
  2856. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  2857. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  2858. #define GPIO_IDR_ID13_Pos (13U)
  2859. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  2860. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  2861. #define GPIO_IDR_ID14_Pos (14U)
  2862. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  2863. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  2864. #define GPIO_IDR_ID15_Pos (15U)
  2865. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  2866. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  2867. /* Legacy defines */
  2868. #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
  2869. #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
  2870. #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
  2871. #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
  2872. #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
  2873. #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
  2874. #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
  2875. #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
  2876. #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
  2877. #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
  2878. #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
  2879. #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
  2880. #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
  2881. #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
  2882. #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
  2883. #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
  2884. /****************** Bits definition for GPIO_ODR register *******************/
  2885. #define GPIO_ODR_OD0_Pos (0U)
  2886. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  2887. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  2888. #define GPIO_ODR_OD1_Pos (1U)
  2889. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  2890. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  2891. #define GPIO_ODR_OD2_Pos (2U)
  2892. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  2893. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  2894. #define GPIO_ODR_OD3_Pos (3U)
  2895. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  2896. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  2897. #define GPIO_ODR_OD4_Pos (4U)
  2898. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  2899. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  2900. #define GPIO_ODR_OD5_Pos (5U)
  2901. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  2902. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  2903. #define GPIO_ODR_OD6_Pos (6U)
  2904. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  2905. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  2906. #define GPIO_ODR_OD7_Pos (7U)
  2907. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  2908. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  2909. #define GPIO_ODR_OD8_Pos (8U)
  2910. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  2911. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  2912. #define GPIO_ODR_OD9_Pos (9U)
  2913. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  2914. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  2915. #define GPIO_ODR_OD10_Pos (10U)
  2916. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  2917. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  2918. #define GPIO_ODR_OD11_Pos (11U)
  2919. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  2920. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  2921. #define GPIO_ODR_OD12_Pos (12U)
  2922. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  2923. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  2924. #define GPIO_ODR_OD13_Pos (13U)
  2925. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  2926. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  2927. #define GPIO_ODR_OD14_Pos (14U)
  2928. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  2929. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  2930. #define GPIO_ODR_OD15_Pos (15U)
  2931. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  2932. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  2933. /* Legacy defines */
  2934. #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
  2935. #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
  2936. #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
  2937. #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
  2938. #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
  2939. #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
  2940. #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
  2941. #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
  2942. #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
  2943. #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
  2944. #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
  2945. #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
  2946. #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
  2947. #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
  2948. #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
  2949. #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
  2950. /****************** Bits definition for GPIO_BSRR register ******************/
  2951. #define GPIO_BSRR_BS0_Pos (0U)
  2952. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  2953. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  2954. #define GPIO_BSRR_BS1_Pos (1U)
  2955. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  2956. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  2957. #define GPIO_BSRR_BS2_Pos (2U)
  2958. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  2959. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  2960. #define GPIO_BSRR_BS3_Pos (3U)
  2961. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  2962. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  2963. #define GPIO_BSRR_BS4_Pos (4U)
  2964. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  2965. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  2966. #define GPIO_BSRR_BS5_Pos (5U)
  2967. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  2968. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  2969. #define GPIO_BSRR_BS6_Pos (6U)
  2970. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  2971. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  2972. #define GPIO_BSRR_BS7_Pos (7U)
  2973. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  2974. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  2975. #define GPIO_BSRR_BS8_Pos (8U)
  2976. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  2977. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  2978. #define GPIO_BSRR_BS9_Pos (9U)
  2979. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  2980. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  2981. #define GPIO_BSRR_BS10_Pos (10U)
  2982. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  2983. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  2984. #define GPIO_BSRR_BS11_Pos (11U)
  2985. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  2986. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  2987. #define GPIO_BSRR_BS12_Pos (12U)
  2988. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  2989. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  2990. #define GPIO_BSRR_BS13_Pos (13U)
  2991. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  2992. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  2993. #define GPIO_BSRR_BS14_Pos (14U)
  2994. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  2995. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  2996. #define GPIO_BSRR_BS15_Pos (15U)
  2997. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  2998. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  2999. #define GPIO_BSRR_BR0_Pos (16U)
  3000. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  3001. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  3002. #define GPIO_BSRR_BR1_Pos (17U)
  3003. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  3004. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  3005. #define GPIO_BSRR_BR2_Pos (18U)
  3006. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  3007. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  3008. #define GPIO_BSRR_BR3_Pos (19U)
  3009. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  3010. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  3011. #define GPIO_BSRR_BR4_Pos (20U)
  3012. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  3013. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  3014. #define GPIO_BSRR_BR5_Pos (21U)
  3015. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  3016. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  3017. #define GPIO_BSRR_BR6_Pos (22U)
  3018. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  3019. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  3020. #define GPIO_BSRR_BR7_Pos (23U)
  3021. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  3022. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  3023. #define GPIO_BSRR_BR8_Pos (24U)
  3024. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  3025. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  3026. #define GPIO_BSRR_BR9_Pos (25U)
  3027. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  3028. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  3029. #define GPIO_BSRR_BR10_Pos (26U)
  3030. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  3031. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  3032. #define GPIO_BSRR_BR11_Pos (27U)
  3033. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  3034. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  3035. #define GPIO_BSRR_BR12_Pos (28U)
  3036. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  3037. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  3038. #define GPIO_BSRR_BR13_Pos (29U)
  3039. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  3040. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  3041. #define GPIO_BSRR_BR14_Pos (30U)
  3042. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  3043. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  3044. #define GPIO_BSRR_BR15_Pos (31U)
  3045. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  3046. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  3047. /* Legacy defines */
  3048. #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
  3049. #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
  3050. #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
  3051. #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
  3052. #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
  3053. #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
  3054. #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
  3055. #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
  3056. #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
  3057. #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
  3058. #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
  3059. #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
  3060. #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
  3061. #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
  3062. #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
  3063. #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
  3064. #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
  3065. #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
  3066. #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
  3067. #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
  3068. #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
  3069. #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
  3070. #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
  3071. #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
  3072. #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
  3073. #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
  3074. #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
  3075. #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
  3076. #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
  3077. #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
  3078. #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
  3079. #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
  3080. #define GPIO_BRR_BR0 GPIO_BSRR_BR0
  3081. #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
  3082. #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
  3083. #define GPIO_BRR_BR1 GPIO_BSRR_BR1
  3084. #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
  3085. #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
  3086. #define GPIO_BRR_BR2 GPIO_BSRR_BR2
  3087. #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
  3088. #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
  3089. #define GPIO_BRR_BR3 GPIO_BSRR_BR3
  3090. #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
  3091. #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
  3092. #define GPIO_BRR_BR4 GPIO_BSRR_BR4
  3093. #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
  3094. #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
  3095. #define GPIO_BRR_BR5 GPIO_BSRR_BR5
  3096. #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
  3097. #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
  3098. #define GPIO_BRR_BR6 GPIO_BSRR_BR6
  3099. #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
  3100. #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
  3101. #define GPIO_BRR_BR7 GPIO_BSRR_BR7
  3102. #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
  3103. #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
  3104. #define GPIO_BRR_BR8 GPIO_BSRR_BR8
  3105. #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
  3106. #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
  3107. #define GPIO_BRR_BR9 GPIO_BSRR_BR9
  3108. #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
  3109. #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
  3110. #define GPIO_BRR_BR10 GPIO_BSRR_BR10
  3111. #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
  3112. #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
  3113. #define GPIO_BRR_BR11 GPIO_BSRR_BR11
  3114. #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
  3115. #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
  3116. #define GPIO_BRR_BR12 GPIO_BSRR_BR12
  3117. #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
  3118. #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
  3119. #define GPIO_BRR_BR13 GPIO_BSRR_BR13
  3120. #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
  3121. #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
  3122. #define GPIO_BRR_BR14 GPIO_BSRR_BR14
  3123. #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
  3124. #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
  3125. #define GPIO_BRR_BR15 GPIO_BSRR_BR15
  3126. #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
  3127. #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
  3128. /****************** Bit definition for GPIO_LCKR register *********************/
  3129. #define GPIO_LCKR_LCK0_Pos (0U)
  3130. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  3131. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  3132. #define GPIO_LCKR_LCK1_Pos (1U)
  3133. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  3134. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  3135. #define GPIO_LCKR_LCK2_Pos (2U)
  3136. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  3137. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  3138. #define GPIO_LCKR_LCK3_Pos (3U)
  3139. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  3140. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  3141. #define GPIO_LCKR_LCK4_Pos (4U)
  3142. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  3143. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  3144. #define GPIO_LCKR_LCK5_Pos (5U)
  3145. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  3146. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  3147. #define GPIO_LCKR_LCK6_Pos (6U)
  3148. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  3149. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  3150. #define GPIO_LCKR_LCK7_Pos (7U)
  3151. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  3152. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  3153. #define GPIO_LCKR_LCK8_Pos (8U)
  3154. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  3155. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  3156. #define GPIO_LCKR_LCK9_Pos (9U)
  3157. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  3158. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  3159. #define GPIO_LCKR_LCK10_Pos (10U)
  3160. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  3161. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  3162. #define GPIO_LCKR_LCK11_Pos (11U)
  3163. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  3164. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  3165. #define GPIO_LCKR_LCK12_Pos (12U)
  3166. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  3167. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  3168. #define GPIO_LCKR_LCK13_Pos (13U)
  3169. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  3170. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  3171. #define GPIO_LCKR_LCK14_Pos (14U)
  3172. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  3173. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  3174. #define GPIO_LCKR_LCK15_Pos (15U)
  3175. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  3176. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  3177. #define GPIO_LCKR_LCKK_Pos (16U)
  3178. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  3179. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  3180. /****************** Bit definition for GPIO_AFRL register *********************/
  3181. #define GPIO_AFRL_AFSEL0_Pos (0U)
  3182. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  3183. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  3184. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  3185. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  3186. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  3187. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  3188. #define GPIO_AFRL_AFSEL1_Pos (4U)
  3189. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  3190. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  3191. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  3192. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  3193. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  3194. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  3195. #define GPIO_AFRL_AFSEL2_Pos (8U)
  3196. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  3197. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  3198. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  3199. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  3200. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  3201. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  3202. #define GPIO_AFRL_AFSEL3_Pos (12U)
  3203. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  3204. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  3205. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  3206. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  3207. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  3208. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  3209. #define GPIO_AFRL_AFSEL4_Pos (16U)
  3210. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  3211. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  3212. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  3213. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  3214. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  3215. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  3216. #define GPIO_AFRL_AFSEL5_Pos (20U)
  3217. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  3218. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  3219. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  3220. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  3221. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  3222. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  3223. #define GPIO_AFRL_AFSEL6_Pos (24U)
  3224. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  3225. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  3226. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  3227. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  3228. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  3229. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  3230. #define GPIO_AFRL_AFSEL7_Pos (28U)
  3231. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  3232. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  3233. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  3234. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  3235. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  3236. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  3237. /* Legacy defines */
  3238. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
  3239. #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
  3240. #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
  3241. #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
  3242. #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
  3243. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
  3244. #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
  3245. #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
  3246. #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
  3247. #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
  3248. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
  3249. #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
  3250. #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
  3251. #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
  3252. #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
  3253. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
  3254. #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
  3255. #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
  3256. #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
  3257. #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
  3258. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
  3259. #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
  3260. #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
  3261. #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
  3262. #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
  3263. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
  3264. #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
  3265. #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
  3266. #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
  3267. #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
  3268. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
  3269. #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
  3270. #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
  3271. #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
  3272. #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
  3273. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
  3274. #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
  3275. #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
  3276. #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
  3277. #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
  3278. /****************** Bit definition for GPIO_AFRH register *********************/
  3279. #define GPIO_AFRH_AFSEL8_Pos (0U)
  3280. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  3281. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  3282. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  3283. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  3284. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  3285. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  3286. #define GPIO_AFRH_AFSEL9_Pos (4U)
  3287. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  3288. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  3289. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  3290. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  3291. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  3292. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  3293. #define GPIO_AFRH_AFSEL10_Pos (8U)
  3294. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  3295. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  3296. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  3297. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  3298. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  3299. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  3300. #define GPIO_AFRH_AFSEL11_Pos (12U)
  3301. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  3302. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  3303. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  3304. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  3305. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  3306. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  3307. #define GPIO_AFRH_AFSEL12_Pos (16U)
  3308. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  3309. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  3310. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  3311. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  3312. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  3313. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  3314. #define GPIO_AFRH_AFSEL13_Pos (20U)
  3315. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  3316. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  3317. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  3318. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  3319. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  3320. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  3321. #define GPIO_AFRH_AFSEL14_Pos (24U)
  3322. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  3323. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  3324. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  3325. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  3326. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  3327. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  3328. #define GPIO_AFRH_AFSEL15_Pos (28U)
  3329. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  3330. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  3331. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  3332. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  3333. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  3334. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  3335. /* Legacy defines */
  3336. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
  3337. #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
  3338. #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
  3339. #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
  3340. #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
  3341. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
  3342. #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
  3343. #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
  3344. #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
  3345. #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
  3346. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
  3347. #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
  3348. #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
  3349. #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
  3350. #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
  3351. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
  3352. #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
  3353. #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
  3354. #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
  3355. #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
  3356. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
  3357. #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
  3358. #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
  3359. #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
  3360. #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
  3361. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
  3362. #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
  3363. #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
  3364. #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
  3365. #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
  3366. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
  3367. #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
  3368. #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
  3369. #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
  3370. #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
  3371. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
  3372. #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
  3373. #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
  3374. #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
  3375. #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
  3376. /******************************************************************************/
  3377. /* */
  3378. /* Inter-integrated Circuit Interface */
  3379. /* */
  3380. /******************************************************************************/
  3381. /******************* Bit definition for I2C_CR1 register ********************/
  3382. #define I2C_CR1_PE_Pos (0U)
  3383. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  3384. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
  3385. #define I2C_CR1_SMBUS_Pos (1U)
  3386. #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
  3387. #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
  3388. #define I2C_CR1_SMBTYPE_Pos (3U)
  3389. #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
  3390. #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
  3391. #define I2C_CR1_ENARP_Pos (4U)
  3392. #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
  3393. #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
  3394. #define I2C_CR1_ENPEC_Pos (5U)
  3395. #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
  3396. #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
  3397. #define I2C_CR1_ENGC_Pos (6U)
  3398. #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
  3399. #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
  3400. #define I2C_CR1_NOSTRETCH_Pos (7U)
  3401. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
  3402. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
  3403. #define I2C_CR1_START_Pos (8U)
  3404. #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
  3405. #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
  3406. #define I2C_CR1_STOP_Pos (9U)
  3407. #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
  3408. #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
  3409. #define I2C_CR1_ACK_Pos (10U)
  3410. #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
  3411. #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
  3412. #define I2C_CR1_POS_Pos (11U)
  3413. #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
  3414. #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
  3415. #define I2C_CR1_PEC_Pos (12U)
  3416. #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
  3417. #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
  3418. #define I2C_CR1_ALERT_Pos (13U)
  3419. #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
  3420. #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
  3421. #define I2C_CR1_SWRST_Pos (15U)
  3422. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
  3423. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
  3424. /******************* Bit definition for I2C_CR2 register ********************/
  3425. #define I2C_CR2_FREQ_Pos (0U)
  3426. #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
  3427. #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
  3428. #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
  3429. #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
  3430. #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
  3431. #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
  3432. #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
  3433. #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
  3434. #define I2C_CR2_ITERREN_Pos (8U)
  3435. #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
  3436. #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
  3437. #define I2C_CR2_ITEVTEN_Pos (9U)
  3438. #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
  3439. #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
  3440. #define I2C_CR2_ITBUFEN_Pos (10U)
  3441. #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
  3442. #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
  3443. #define I2C_CR2_DMAEN_Pos (11U)
  3444. #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
  3445. #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
  3446. #define I2C_CR2_LAST_Pos (12U)
  3447. #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
  3448. #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
  3449. /******************* Bit definition for I2C_OAR1 register *******************/
  3450. #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
  3451. #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
  3452. #define I2C_OAR1_ADD0_Pos (0U)
  3453. #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
  3454. #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
  3455. #define I2C_OAR1_ADD1_Pos (1U)
  3456. #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
  3457. #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
  3458. #define I2C_OAR1_ADD2_Pos (2U)
  3459. #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
  3460. #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
  3461. #define I2C_OAR1_ADD3_Pos (3U)
  3462. #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
  3463. #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
  3464. #define I2C_OAR1_ADD4_Pos (4U)
  3465. #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
  3466. #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
  3467. #define I2C_OAR1_ADD5_Pos (5U)
  3468. #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
  3469. #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
  3470. #define I2C_OAR1_ADD6_Pos (6U)
  3471. #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
  3472. #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
  3473. #define I2C_OAR1_ADD7_Pos (7U)
  3474. #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
  3475. #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
  3476. #define I2C_OAR1_ADD8_Pos (8U)
  3477. #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
  3478. #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
  3479. #define I2C_OAR1_ADD9_Pos (9U)
  3480. #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
  3481. #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
  3482. #define I2C_OAR1_ADDMODE_Pos (15U)
  3483. #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
  3484. #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
  3485. /******************* Bit definition for I2C_OAR2 register *******************/
  3486. #define I2C_OAR2_ENDUAL_Pos (0U)
  3487. #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
  3488. #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
  3489. #define I2C_OAR2_ADD2_Pos (1U)
  3490. #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
  3491. #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
  3492. /******************** Bit definition for I2C_DR register ********************/
  3493. #define I2C_DR_DR_Pos (0U)
  3494. #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
  3495. #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
  3496. /******************* Bit definition for I2C_SR1 register ********************/
  3497. #define I2C_SR1_SB_Pos (0U)
  3498. #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
  3499. #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
  3500. #define I2C_SR1_ADDR_Pos (1U)
  3501. #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
  3502. #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
  3503. #define I2C_SR1_BTF_Pos (2U)
  3504. #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
  3505. #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
  3506. #define I2C_SR1_ADD10_Pos (3U)
  3507. #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
  3508. #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
  3509. #define I2C_SR1_STOPF_Pos (4U)
  3510. #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
  3511. #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
  3512. #define I2C_SR1_RXNE_Pos (6U)
  3513. #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
  3514. #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
  3515. #define I2C_SR1_TXE_Pos (7U)
  3516. #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
  3517. #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
  3518. #define I2C_SR1_BERR_Pos (8U)
  3519. #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
  3520. #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
  3521. #define I2C_SR1_ARLO_Pos (9U)
  3522. #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
  3523. #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
  3524. #define I2C_SR1_AF_Pos (10U)
  3525. #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
  3526. #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
  3527. #define I2C_SR1_OVR_Pos (11U)
  3528. #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
  3529. #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
  3530. #define I2C_SR1_PECERR_Pos (12U)
  3531. #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
  3532. #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
  3533. #define I2C_SR1_TIMEOUT_Pos (14U)
  3534. #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
  3535. #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
  3536. #define I2C_SR1_SMBALERT_Pos (15U)
  3537. #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
  3538. #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
  3539. /******************* Bit definition for I2C_SR2 register ********************/
  3540. #define I2C_SR2_MSL_Pos (0U)
  3541. #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
  3542. #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
  3543. #define I2C_SR2_BUSY_Pos (1U)
  3544. #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
  3545. #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
  3546. #define I2C_SR2_TRA_Pos (2U)
  3547. #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
  3548. #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
  3549. #define I2C_SR2_GENCALL_Pos (4U)
  3550. #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
  3551. #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
  3552. #define I2C_SR2_SMBDEFAULT_Pos (5U)
  3553. #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
  3554. #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
  3555. #define I2C_SR2_SMBHOST_Pos (6U)
  3556. #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
  3557. #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
  3558. #define I2C_SR2_DUALF_Pos (7U)
  3559. #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
  3560. #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
  3561. #define I2C_SR2_PEC_Pos (8U)
  3562. #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
  3563. #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
  3564. /******************* Bit definition for I2C_CCR register ********************/
  3565. #define I2C_CCR_CCR_Pos (0U)
  3566. #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
  3567. #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
  3568. #define I2C_CCR_DUTY_Pos (14U)
  3569. #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
  3570. #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
  3571. #define I2C_CCR_FS_Pos (15U)
  3572. #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
  3573. #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
  3574. /****************** Bit definition for I2C_TRISE register *******************/
  3575. #define I2C_TRISE_TRISE_Pos (0U)
  3576. #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
  3577. #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
  3578. /****************** Bit definition for I2C_FLTR register *******************/
  3579. #define I2C_FLTR_DNF_Pos (0U)
  3580. #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
  3581. #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
  3582. #define I2C_FLTR_ANOFF_Pos (4U)
  3583. #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
  3584. #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
  3585. /******************************************************************************/
  3586. /* */
  3587. /* Independent WATCHDOG */
  3588. /* */
  3589. /******************************************************************************/
  3590. /******************* Bit definition for IWDG_KR register ********************/
  3591. #define IWDG_KR_KEY_Pos (0U)
  3592. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  3593. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  3594. /******************* Bit definition for IWDG_PR register ********************/
  3595. #define IWDG_PR_PR_Pos (0U)
  3596. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  3597. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  3598. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
  3599. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
  3600. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
  3601. /******************* Bit definition for IWDG_RLR register *******************/
  3602. #define IWDG_RLR_RL_Pos (0U)
  3603. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  3604. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  3605. /******************* Bit definition for IWDG_SR register ********************/
  3606. #define IWDG_SR_PVU_Pos (0U)
  3607. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  3608. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
  3609. #define IWDG_SR_RVU_Pos (1U)
  3610. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  3611. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
  3612. /******************************************************************************/
  3613. /* */
  3614. /* Power Control */
  3615. /* */
  3616. /******************************************************************************/
  3617. /******************** Bit definition for PWR_CR register ********************/
  3618. #define PWR_CR_LPDS_Pos (0U)
  3619. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  3620. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  3621. #define PWR_CR_PDDS_Pos (1U)
  3622. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  3623. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  3624. #define PWR_CR_CWUF_Pos (2U)
  3625. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  3626. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  3627. #define PWR_CR_CSBF_Pos (3U)
  3628. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  3629. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  3630. #define PWR_CR_PVDE_Pos (4U)
  3631. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  3632. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  3633. #define PWR_CR_PLS_Pos (5U)
  3634. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  3635. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  3636. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  3637. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  3638. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  3639. /*!< PVD level configuration */
  3640. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
  3641. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
  3642. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
  3643. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
  3644. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
  3645. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
  3646. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
  3647. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
  3648. #define PWR_CR_DBP_Pos (8U)
  3649. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  3650. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  3651. #define PWR_CR_FPDS_Pos (9U)
  3652. #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
  3653. #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
  3654. #define PWR_CR_LPLVDS_Pos (10U)
  3655. #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
  3656. #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
  3657. #define PWR_CR_MRLVDS_Pos (11U)
  3658. #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
  3659. #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */
  3660. #define PWR_CR_ADCDC1_Pos (13U)
  3661. #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
  3662. #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
  3663. #define PWR_CR_VOS_Pos (14U)
  3664. #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
  3665. #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
  3666. #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
  3667. #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
  3668. /* Legacy define */
  3669. #define PWR_CR_PMODE PWR_CR_VOS
  3670. /******************* Bit definition for PWR_CSR register ********************/
  3671. #define PWR_CSR_WUF_Pos (0U)
  3672. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  3673. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  3674. #define PWR_CSR_SBF_Pos (1U)
  3675. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  3676. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  3677. #define PWR_CSR_PVDO_Pos (2U)
  3678. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  3679. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  3680. #define PWR_CSR_BRR_Pos (3U)
  3681. #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
  3682. #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
  3683. #define PWR_CSR_EWUP_Pos (8U)
  3684. #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
  3685. #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
  3686. #define PWR_CSR_BRE_Pos (9U)
  3687. #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
  3688. #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
  3689. #define PWR_CSR_VOSRDY_Pos (14U)
  3690. #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
  3691. #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
  3692. /* Legacy define */
  3693. #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
  3694. /******************************************************************************/
  3695. /* */
  3696. /* Reset and Clock Control */
  3697. /* */
  3698. /******************************************************************************/
  3699. /******************** Bit definition for RCC_CR register ********************/
  3700. #define RCC_CR_HSION_Pos (0U)
  3701. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  3702. #define RCC_CR_HSION RCC_CR_HSION_Msk
  3703. #define RCC_CR_HSIRDY_Pos (1U)
  3704. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  3705. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
  3706. #define RCC_CR_HSITRIM_Pos (3U)
  3707. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  3708. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
  3709. #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  3710. #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  3711. #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  3712. #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  3713. #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  3714. #define RCC_CR_HSICAL_Pos (8U)
  3715. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  3716. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
  3717. #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  3718. #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  3719. #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  3720. #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  3721. #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  3722. #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  3723. #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  3724. #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  3725. #define RCC_CR_HSEON_Pos (16U)
  3726. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  3727. #define RCC_CR_HSEON RCC_CR_HSEON_Msk
  3728. #define RCC_CR_HSERDY_Pos (17U)
  3729. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  3730. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
  3731. #define RCC_CR_HSEBYP_Pos (18U)
  3732. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  3733. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
  3734. #define RCC_CR_CSSON_Pos (19U)
  3735. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  3736. #define RCC_CR_CSSON RCC_CR_CSSON_Msk
  3737. #define RCC_CR_PLLON_Pos (24U)
  3738. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  3739. #define RCC_CR_PLLON RCC_CR_PLLON_Msk
  3740. #define RCC_CR_PLLRDY_Pos (25U)
  3741. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  3742. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
  3743. /*
  3744. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  3745. */
  3746. #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
  3747. #define RCC_CR_PLLI2SON_Pos (26U)
  3748. #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
  3749. #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
  3750. #define RCC_CR_PLLI2SRDY_Pos (27U)
  3751. #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
  3752. #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
  3753. /******************** Bit definition for RCC_PLLCFGR register ***************/
  3754. #define RCC_PLLCFGR_PLLM_Pos (0U)
  3755. #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
  3756. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  3757. #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
  3758. #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
  3759. #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
  3760. #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
  3761. #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  3762. #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  3763. #define RCC_PLLCFGR_PLLN_Pos (6U)
  3764. #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
  3765. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  3766. #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
  3767. #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
  3768. #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  3769. #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  3770. #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  3771. #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  3772. #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  3773. #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  3774. #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  3775. #define RCC_PLLCFGR_PLLP_Pos (16U)
  3776. #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
  3777. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  3778. #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
  3779. #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  3780. #define RCC_PLLCFGR_PLLSRC_Pos (22U)
  3781. #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
  3782. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  3783. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
  3784. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
  3785. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
  3786. #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
  3787. #define RCC_PLLCFGR_PLLQ_Pos (24U)
  3788. #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
  3789. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  3790. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
  3791. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  3792. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  3793. #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  3794. /******************** Bit definition for RCC_CFGR register ******************/
  3795. /*!< SW configuration */
  3796. #define RCC_CFGR_SW_Pos (0U)
  3797. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  3798. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  3799. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  3800. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  3801. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  3802. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  3803. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  3804. /*!< SWS configuration */
  3805. #define RCC_CFGR_SWS_Pos (2U)
  3806. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  3807. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  3808. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  3809. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  3810. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  3811. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  3812. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  3813. /*!< HPRE configuration */
  3814. #define RCC_CFGR_HPRE_Pos (4U)
  3815. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  3816. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  3817. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  3818. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  3819. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  3820. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  3821. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  3822. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  3823. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  3824. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  3825. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  3826. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  3827. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  3828. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  3829. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  3830. /*!< PPRE1 configuration */
  3831. #define RCC_CFGR_PPRE1_Pos (10U)
  3832. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
  3833. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  3834. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  3835. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
  3836. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
  3837. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  3838. #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
  3839. #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
  3840. #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
  3841. #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
  3842. /*!< PPRE2 configuration */
  3843. #define RCC_CFGR_PPRE2_Pos (13U)
  3844. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
  3845. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  3846. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  3847. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
  3848. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
  3849. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  3850. #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
  3851. #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
  3852. #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
  3853. #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
  3854. /*!< RTCPRE configuration */
  3855. #define RCC_CFGR_RTCPRE_Pos (16U)
  3856. #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
  3857. #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
  3858. #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
  3859. #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
  3860. #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
  3861. #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
  3862. #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
  3863. /*!< MCO1 configuration */
  3864. #define RCC_CFGR_MCO1_Pos (21U)
  3865. #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
  3866. #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
  3867. #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
  3868. #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
  3869. #define RCC_CFGR_I2SSRC_Pos (23U)
  3870. #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
  3871. #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
  3872. #define RCC_CFGR_MCO1PRE_Pos (24U)
  3873. #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
  3874. #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
  3875. #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
  3876. #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
  3877. #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
  3878. #define RCC_CFGR_MCO2PRE_Pos (27U)
  3879. #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
  3880. #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
  3881. #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
  3882. #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
  3883. #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
  3884. #define RCC_CFGR_MCO2_Pos (30U)
  3885. #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
  3886. #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
  3887. #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
  3888. #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
  3889. /******************** Bit definition for RCC_CIR register *******************/
  3890. #define RCC_CIR_LSIRDYF_Pos (0U)
  3891. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  3892. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
  3893. #define RCC_CIR_LSERDYF_Pos (1U)
  3894. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  3895. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
  3896. #define RCC_CIR_HSIRDYF_Pos (2U)
  3897. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  3898. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
  3899. #define RCC_CIR_HSERDYF_Pos (3U)
  3900. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  3901. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
  3902. #define RCC_CIR_PLLRDYF_Pos (4U)
  3903. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  3904. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
  3905. #define RCC_CIR_PLLI2SRDYF_Pos (5U)
  3906. #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
  3907. #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
  3908. #define RCC_CIR_CSSF_Pos (7U)
  3909. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  3910. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
  3911. #define RCC_CIR_LSIRDYIE_Pos (8U)
  3912. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  3913. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
  3914. #define RCC_CIR_LSERDYIE_Pos (9U)
  3915. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  3916. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
  3917. #define RCC_CIR_HSIRDYIE_Pos (10U)
  3918. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  3919. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
  3920. #define RCC_CIR_HSERDYIE_Pos (11U)
  3921. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  3922. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
  3923. #define RCC_CIR_PLLRDYIE_Pos (12U)
  3924. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  3925. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
  3926. #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
  3927. #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
  3928. #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
  3929. #define RCC_CIR_LSIRDYC_Pos (16U)
  3930. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  3931. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
  3932. #define RCC_CIR_LSERDYC_Pos (17U)
  3933. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  3934. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
  3935. #define RCC_CIR_HSIRDYC_Pos (18U)
  3936. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  3937. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
  3938. #define RCC_CIR_HSERDYC_Pos (19U)
  3939. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  3940. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
  3941. #define RCC_CIR_PLLRDYC_Pos (20U)
  3942. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  3943. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
  3944. #define RCC_CIR_PLLI2SRDYC_Pos (21U)
  3945. #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
  3946. #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
  3947. #define RCC_CIR_CSSC_Pos (23U)
  3948. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  3949. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
  3950. /******************** Bit definition for RCC_AHB1RSTR register **************/
  3951. #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
  3952. #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
  3953. #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
  3954. #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
  3955. #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  3956. #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
  3957. #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
  3958. #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  3959. #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
  3960. #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
  3961. #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
  3962. #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
  3963. #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
  3964. #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
  3965. #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
  3966. #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
  3967. #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
  3968. #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
  3969. #define RCC_AHB1RSTR_CRCRST_Pos (12U)
  3970. #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
  3971. #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
  3972. #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
  3973. #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
  3974. #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
  3975. #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
  3976. #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
  3977. #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
  3978. /******************** Bit definition for RCC_AHB2RSTR register **************/
  3979. #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
  3980. #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
  3981. #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
  3982. /******************** Bit definition for RCC_AHB3RSTR register **************/
  3983. /******************** Bit definition for RCC_APB1RSTR register **************/
  3984. #define RCC_APB1RSTR_TIM2RST_Pos (0U)
  3985. #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
  3986. #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
  3987. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  3988. #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  3989. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
  3990. #define RCC_APB1RSTR_TIM4RST_Pos (2U)
  3991. #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
  3992. #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
  3993. #define RCC_APB1RSTR_TIM5RST_Pos (3U)
  3994. #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
  3995. #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
  3996. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  3997. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  3998. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
  3999. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  4000. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  4001. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
  4002. #define RCC_APB1RSTR_SPI3RST_Pos (15U)
  4003. #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
  4004. #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
  4005. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  4006. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  4007. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
  4008. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  4009. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  4010. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
  4011. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  4012. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  4013. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
  4014. #define RCC_APB1RSTR_I2C3RST_Pos (23U)
  4015. #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
  4016. #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
  4017. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  4018. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  4019. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
  4020. /******************** Bit definition for RCC_APB2RSTR register **************/
  4021. #define RCC_APB2RSTR_TIM1RST_Pos (0U)
  4022. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
  4023. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
  4024. #define RCC_APB2RSTR_USART1RST_Pos (4U)
  4025. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
  4026. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
  4027. #define RCC_APB2RSTR_USART6RST_Pos (5U)
  4028. #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
  4029. #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
  4030. #define RCC_APB2RSTR_ADCRST_Pos (8U)
  4031. #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
  4032. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
  4033. #define RCC_APB2RSTR_SDIORST_Pos (11U)
  4034. #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
  4035. #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
  4036. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  4037. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  4038. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
  4039. #define RCC_APB2RSTR_SPI4RST_Pos (13U)
  4040. #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
  4041. #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
  4042. #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
  4043. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
  4044. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
  4045. #define RCC_APB2RSTR_TIM9RST_Pos (16U)
  4046. #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
  4047. #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
  4048. #define RCC_APB2RSTR_TIM10RST_Pos (17U)
  4049. #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
  4050. #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
  4051. #define RCC_APB2RSTR_TIM11RST_Pos (18U)
  4052. #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
  4053. #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
  4054. /* Old SPI1RST bit definition, maintained for legacy purpose */
  4055. #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
  4056. /******************** Bit definition for RCC_AHB1ENR register ***************/
  4057. #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
  4058. #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
  4059. #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
  4060. #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
  4061. #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
  4062. #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
  4063. #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
  4064. #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
  4065. #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
  4066. #define RCC_AHB1ENR_GPIODEN_Pos (3U)
  4067. #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
  4068. #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
  4069. #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
  4070. #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
  4071. #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
  4072. #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
  4073. #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
  4074. #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
  4075. #define RCC_AHB1ENR_CRCEN_Pos (12U)
  4076. #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
  4077. #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
  4078. #define RCC_AHB1ENR_DMA1EN_Pos (21U)
  4079. #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
  4080. #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
  4081. #define RCC_AHB1ENR_DMA2EN_Pos (22U)
  4082. #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
  4083. #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
  4084. /******************** Bit definition for RCC_AHB2ENR register ***************/
  4085. /*
  4086. * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
  4087. */
  4088. #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
  4089. #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
  4090. #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
  4091. #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
  4092. /******************** Bit definition for RCC_APB1ENR register ***************/
  4093. #define RCC_APB1ENR_TIM2EN_Pos (0U)
  4094. #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
  4095. #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
  4096. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  4097. #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  4098. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
  4099. #define RCC_APB1ENR_TIM4EN_Pos (2U)
  4100. #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
  4101. #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
  4102. #define RCC_APB1ENR_TIM5EN_Pos (3U)
  4103. #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
  4104. #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
  4105. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  4106. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  4107. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
  4108. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  4109. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  4110. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
  4111. #define RCC_APB1ENR_SPI3EN_Pos (15U)
  4112. #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
  4113. #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
  4114. #define RCC_APB1ENR_USART2EN_Pos (17U)
  4115. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  4116. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
  4117. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  4118. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  4119. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
  4120. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  4121. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  4122. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
  4123. #define RCC_APB1ENR_I2C3EN_Pos (23U)
  4124. #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
  4125. #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
  4126. #define RCC_APB1ENR_PWREN_Pos (28U)
  4127. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  4128. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
  4129. /******************** Bit definition for RCC_APB2ENR register ***************/
  4130. #define RCC_APB2ENR_TIM1EN_Pos (0U)
  4131. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
  4132. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
  4133. #define RCC_APB2ENR_USART1EN_Pos (4U)
  4134. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
  4135. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
  4136. #define RCC_APB2ENR_USART6EN_Pos (5U)
  4137. #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
  4138. #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
  4139. #define RCC_APB2ENR_ADC1EN_Pos (8U)
  4140. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
  4141. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
  4142. #define RCC_APB2ENR_SDIOEN_Pos (11U)
  4143. #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
  4144. #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
  4145. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  4146. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  4147. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
  4148. #define RCC_APB2ENR_SPI4EN_Pos (13U)
  4149. #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
  4150. #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
  4151. #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
  4152. #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
  4153. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
  4154. #define RCC_APB2ENR_TIM9EN_Pos (16U)
  4155. #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
  4156. #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
  4157. #define RCC_APB2ENR_TIM10EN_Pos (17U)
  4158. #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
  4159. #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
  4160. #define RCC_APB2ENR_TIM11EN_Pos (18U)
  4161. #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
  4162. #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
  4163. /******************** Bit definition for RCC_AHB1LPENR register *************/
  4164. #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
  4165. #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
  4166. #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
  4167. #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
  4168. #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
  4169. #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
  4170. #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
  4171. #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
  4172. #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
  4173. #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
  4174. #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
  4175. #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
  4176. #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
  4177. #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
  4178. #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
  4179. #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
  4180. #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
  4181. #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
  4182. #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
  4183. #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
  4184. #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
  4185. #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
  4186. #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
  4187. #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
  4188. #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
  4189. #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
  4190. #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
  4191. #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
  4192. #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
  4193. #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
  4194. #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
  4195. #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
  4196. #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
  4197. /******************** Bit definition for RCC_AHB2LPENR register *************/
  4198. #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
  4199. #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
  4200. #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
  4201. /******************** Bit definition for RCC_AHB3LPENR register *************/
  4202. /******************** Bit definition for RCC_APB1LPENR register *************/
  4203. #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
  4204. #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
  4205. #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
  4206. #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
  4207. #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
  4208. #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
  4209. #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
  4210. #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
  4211. #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
  4212. #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
  4213. #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
  4214. #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
  4215. #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
  4216. #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
  4217. #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
  4218. #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
  4219. #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
  4220. #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
  4221. #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
  4222. #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
  4223. #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
  4224. #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
  4225. #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
  4226. #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
  4227. #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
  4228. #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
  4229. #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
  4230. #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
  4231. #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
  4232. #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
  4233. #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
  4234. #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
  4235. #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
  4236. #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
  4237. #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
  4238. #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
  4239. /******************** Bit definition for RCC_APB2LPENR register *************/
  4240. #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
  4241. #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
  4242. #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
  4243. #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
  4244. #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
  4245. #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
  4246. #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
  4247. #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
  4248. #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
  4249. #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
  4250. #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
  4251. #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
  4252. #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
  4253. #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
  4254. #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
  4255. #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
  4256. #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
  4257. #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
  4258. #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
  4259. #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
  4260. #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
  4261. #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
  4262. #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
  4263. #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
  4264. #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
  4265. #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
  4266. #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
  4267. #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
  4268. #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
  4269. #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
  4270. #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
  4271. #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
  4272. #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
  4273. /******************** Bit definition for RCC_BDCR register ******************/
  4274. #define RCC_BDCR_LSEON_Pos (0U)
  4275. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  4276. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  4277. #define RCC_BDCR_LSERDY_Pos (1U)
  4278. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  4279. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  4280. #define RCC_BDCR_LSEBYP_Pos (2U)
  4281. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  4282. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  4283. #define RCC_BDCR_RTCSEL_Pos (8U)
  4284. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  4285. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  4286. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  4287. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  4288. #define RCC_BDCR_RTCEN_Pos (15U)
  4289. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  4290. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  4291. #define RCC_BDCR_BDRST_Pos (16U)
  4292. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  4293. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  4294. /******************** Bit definition for RCC_CSR register *******************/
  4295. #define RCC_CSR_LSION_Pos (0U)
  4296. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  4297. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  4298. #define RCC_CSR_LSIRDY_Pos (1U)
  4299. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  4300. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  4301. #define RCC_CSR_RMVF_Pos (24U)
  4302. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  4303. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  4304. #define RCC_CSR_BORRSTF_Pos (25U)
  4305. #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
  4306. #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
  4307. #define RCC_CSR_PINRSTF_Pos (26U)
  4308. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  4309. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  4310. #define RCC_CSR_PORRSTF_Pos (27U)
  4311. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  4312. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
  4313. #define RCC_CSR_SFTRSTF_Pos (28U)
  4314. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  4315. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  4316. #define RCC_CSR_IWDGRSTF_Pos (29U)
  4317. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  4318. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  4319. #define RCC_CSR_WWDGRSTF_Pos (30U)
  4320. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  4321. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  4322. #define RCC_CSR_LPWRRSTF_Pos (31U)
  4323. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  4324. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  4325. /* Legacy defines */
  4326. #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
  4327. #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
  4328. /******************** Bit definition for RCC_SSCGR register *****************/
  4329. #define RCC_SSCGR_MODPER_Pos (0U)
  4330. #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
  4331. #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
  4332. #define RCC_SSCGR_INCSTEP_Pos (13U)
  4333. #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
  4334. #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
  4335. #define RCC_SSCGR_SPREADSEL_Pos (30U)
  4336. #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
  4337. #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
  4338. #define RCC_SSCGR_SSCGEN_Pos (31U)
  4339. #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
  4340. #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
  4341. /******************** Bit definition for RCC_PLLI2SCFGR register ************/
  4342. #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
  4343. #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
  4344. #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
  4345. #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
  4346. #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
  4347. #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
  4348. #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
  4349. #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
  4350. #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
  4351. #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
  4352. #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
  4353. #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
  4354. #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
  4355. #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
  4356. #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
  4357. #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
  4358. #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
  4359. #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
  4360. /******************** Bit definition for RCC_DCKCFGR register ***************/
  4361. #define RCC_DCKCFGR_TIMPRE_Pos (24U)
  4362. #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
  4363. #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
  4364. /******************************************************************************/
  4365. /* */
  4366. /* Real-Time Clock (RTC) */
  4367. /* */
  4368. /******************************************************************************/
  4369. /******************** Bits definition for RTC_TR register *******************/
  4370. #define RTC_TR_PM_Pos (22U)
  4371. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  4372. #define RTC_TR_PM RTC_TR_PM_Msk
  4373. #define RTC_TR_HT_Pos (20U)
  4374. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  4375. #define RTC_TR_HT RTC_TR_HT_Msk
  4376. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  4377. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  4378. #define RTC_TR_HU_Pos (16U)
  4379. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  4380. #define RTC_TR_HU RTC_TR_HU_Msk
  4381. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  4382. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  4383. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  4384. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  4385. #define RTC_TR_MNT_Pos (12U)
  4386. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  4387. #define RTC_TR_MNT RTC_TR_MNT_Msk
  4388. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  4389. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  4390. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  4391. #define RTC_TR_MNU_Pos (8U)
  4392. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  4393. #define RTC_TR_MNU RTC_TR_MNU_Msk
  4394. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  4395. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  4396. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  4397. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  4398. #define RTC_TR_ST_Pos (4U)
  4399. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  4400. #define RTC_TR_ST RTC_TR_ST_Msk
  4401. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  4402. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  4403. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  4404. #define RTC_TR_SU_Pos (0U)
  4405. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  4406. #define RTC_TR_SU RTC_TR_SU_Msk
  4407. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  4408. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  4409. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  4410. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  4411. /******************** Bits definition for RTC_DR register *******************/
  4412. #define RTC_DR_YT_Pos (20U)
  4413. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  4414. #define RTC_DR_YT RTC_DR_YT_Msk
  4415. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  4416. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  4417. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  4418. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  4419. #define RTC_DR_YU_Pos (16U)
  4420. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  4421. #define RTC_DR_YU RTC_DR_YU_Msk
  4422. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  4423. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  4424. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  4425. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  4426. #define RTC_DR_WDU_Pos (13U)
  4427. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  4428. #define RTC_DR_WDU RTC_DR_WDU_Msk
  4429. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  4430. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  4431. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  4432. #define RTC_DR_MT_Pos (12U)
  4433. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  4434. #define RTC_DR_MT RTC_DR_MT_Msk
  4435. #define RTC_DR_MU_Pos (8U)
  4436. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  4437. #define RTC_DR_MU RTC_DR_MU_Msk
  4438. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  4439. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  4440. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  4441. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  4442. #define RTC_DR_DT_Pos (4U)
  4443. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  4444. #define RTC_DR_DT RTC_DR_DT_Msk
  4445. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  4446. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  4447. #define RTC_DR_DU_Pos (0U)
  4448. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  4449. #define RTC_DR_DU RTC_DR_DU_Msk
  4450. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  4451. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  4452. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  4453. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  4454. /******************** Bits definition for RTC_CR register *******************/
  4455. #define RTC_CR_COE_Pos (23U)
  4456. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  4457. #define RTC_CR_COE RTC_CR_COE_Msk
  4458. #define RTC_CR_OSEL_Pos (21U)
  4459. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  4460. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  4461. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  4462. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  4463. #define RTC_CR_POL_Pos (20U)
  4464. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  4465. #define RTC_CR_POL RTC_CR_POL_Msk
  4466. #define RTC_CR_COSEL_Pos (19U)
  4467. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  4468. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  4469. #define RTC_CR_BKP_Pos (18U)
  4470. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  4471. #define RTC_CR_BKP RTC_CR_BKP_Msk
  4472. #define RTC_CR_SUB1H_Pos (17U)
  4473. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  4474. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  4475. #define RTC_CR_ADD1H_Pos (16U)
  4476. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  4477. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  4478. #define RTC_CR_TSIE_Pos (15U)
  4479. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  4480. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  4481. #define RTC_CR_WUTIE_Pos (14U)
  4482. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  4483. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
  4484. #define RTC_CR_ALRBIE_Pos (13U)
  4485. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  4486. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  4487. #define RTC_CR_ALRAIE_Pos (12U)
  4488. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  4489. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  4490. #define RTC_CR_TSE_Pos (11U)
  4491. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  4492. #define RTC_CR_TSE RTC_CR_TSE_Msk
  4493. #define RTC_CR_WUTE_Pos (10U)
  4494. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  4495. #define RTC_CR_WUTE RTC_CR_WUTE_Msk
  4496. #define RTC_CR_ALRBE_Pos (9U)
  4497. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  4498. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  4499. #define RTC_CR_ALRAE_Pos (8U)
  4500. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  4501. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  4502. #define RTC_CR_DCE_Pos (7U)
  4503. #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */
  4504. #define RTC_CR_DCE RTC_CR_DCE_Msk
  4505. #define RTC_CR_FMT_Pos (6U)
  4506. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  4507. #define RTC_CR_FMT RTC_CR_FMT_Msk
  4508. #define RTC_CR_BYPSHAD_Pos (5U)
  4509. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  4510. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  4511. #define RTC_CR_REFCKON_Pos (4U)
  4512. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  4513. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  4514. #define RTC_CR_TSEDGE_Pos (3U)
  4515. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  4516. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  4517. #define RTC_CR_WUCKSEL_Pos (0U)
  4518. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  4519. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
  4520. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  4521. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  4522. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  4523. /* Legacy defines */
  4524. #define RTC_CR_BCK RTC_CR_BKP
  4525. /******************** Bits definition for RTC_ISR register ******************/
  4526. #define RTC_ISR_RECALPF_Pos (16U)
  4527. #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  4528. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  4529. #define RTC_ISR_TAMP1F_Pos (13U)
  4530. #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  4531. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  4532. #define RTC_ISR_TAMP2F_Pos (14U)
  4533. #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  4534. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  4535. #define RTC_ISR_TSOVF_Pos (12U)
  4536. #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  4537. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  4538. #define RTC_ISR_TSF_Pos (11U)
  4539. #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  4540. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  4541. #define RTC_ISR_WUTF_Pos (10U)
  4542. #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
  4543. #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
  4544. #define RTC_ISR_ALRBF_Pos (9U)
  4545. #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
  4546. #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
  4547. #define RTC_ISR_ALRAF_Pos (8U)
  4548. #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  4549. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  4550. #define RTC_ISR_INIT_Pos (7U)
  4551. #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  4552. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  4553. #define RTC_ISR_INITF_Pos (6U)
  4554. #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  4555. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  4556. #define RTC_ISR_RSF_Pos (5U)
  4557. #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  4558. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  4559. #define RTC_ISR_INITS_Pos (4U)
  4560. #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  4561. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  4562. #define RTC_ISR_SHPF_Pos (3U)
  4563. #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  4564. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  4565. #define RTC_ISR_WUTWF_Pos (2U)
  4566. #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
  4567. #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
  4568. #define RTC_ISR_ALRBWF_Pos (1U)
  4569. #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
  4570. #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
  4571. #define RTC_ISR_ALRAWF_Pos (0U)
  4572. #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  4573. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  4574. /******************** Bits definition for RTC_PRER register *****************/
  4575. #define RTC_PRER_PREDIV_A_Pos (16U)
  4576. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  4577. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  4578. #define RTC_PRER_PREDIV_S_Pos (0U)
  4579. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  4580. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  4581. /******************** Bits definition for RTC_WUTR register *****************/
  4582. #define RTC_WUTR_WUT_Pos (0U)
  4583. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  4584. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
  4585. /******************** Bits definition for RTC_CALIBR register ***************/
  4586. #define RTC_CALIBR_DCS_Pos (7U)
  4587. #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
  4588. #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
  4589. #define RTC_CALIBR_DC_Pos (0U)
  4590. #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
  4591. #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
  4592. /******************** Bits definition for RTC_ALRMAR register ***************/
  4593. #define RTC_ALRMAR_MSK4_Pos (31U)
  4594. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  4595. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  4596. #define RTC_ALRMAR_WDSEL_Pos (30U)
  4597. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  4598. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  4599. #define RTC_ALRMAR_DT_Pos (28U)
  4600. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  4601. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  4602. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  4603. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  4604. #define RTC_ALRMAR_DU_Pos (24U)
  4605. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  4606. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  4607. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  4608. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  4609. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  4610. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  4611. #define RTC_ALRMAR_MSK3_Pos (23U)
  4612. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  4613. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  4614. #define RTC_ALRMAR_PM_Pos (22U)
  4615. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  4616. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  4617. #define RTC_ALRMAR_HT_Pos (20U)
  4618. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  4619. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  4620. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  4621. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  4622. #define RTC_ALRMAR_HU_Pos (16U)
  4623. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  4624. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  4625. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  4626. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  4627. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  4628. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  4629. #define RTC_ALRMAR_MSK2_Pos (15U)
  4630. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  4631. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  4632. #define RTC_ALRMAR_MNT_Pos (12U)
  4633. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  4634. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  4635. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  4636. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  4637. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  4638. #define RTC_ALRMAR_MNU_Pos (8U)
  4639. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  4640. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  4641. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  4642. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  4643. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  4644. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  4645. #define RTC_ALRMAR_MSK1_Pos (7U)
  4646. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  4647. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  4648. #define RTC_ALRMAR_ST_Pos (4U)
  4649. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  4650. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  4651. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  4652. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  4653. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  4654. #define RTC_ALRMAR_SU_Pos (0U)
  4655. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  4656. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  4657. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  4658. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  4659. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  4660. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  4661. /******************** Bits definition for RTC_ALRMBR register ***************/
  4662. #define RTC_ALRMBR_MSK4_Pos (31U)
  4663. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  4664. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  4665. #define RTC_ALRMBR_WDSEL_Pos (30U)
  4666. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  4667. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  4668. #define RTC_ALRMBR_DT_Pos (28U)
  4669. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  4670. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  4671. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  4672. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  4673. #define RTC_ALRMBR_DU_Pos (24U)
  4674. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  4675. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  4676. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  4677. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  4678. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  4679. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  4680. #define RTC_ALRMBR_MSK3_Pos (23U)
  4681. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  4682. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  4683. #define RTC_ALRMBR_PM_Pos (22U)
  4684. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  4685. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  4686. #define RTC_ALRMBR_HT_Pos (20U)
  4687. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  4688. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  4689. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  4690. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  4691. #define RTC_ALRMBR_HU_Pos (16U)
  4692. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  4693. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  4694. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  4695. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  4696. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  4697. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  4698. #define RTC_ALRMBR_MSK2_Pos (15U)
  4699. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  4700. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  4701. #define RTC_ALRMBR_MNT_Pos (12U)
  4702. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  4703. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  4704. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  4705. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  4706. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  4707. #define RTC_ALRMBR_MNU_Pos (8U)
  4708. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  4709. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  4710. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  4711. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  4712. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  4713. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  4714. #define RTC_ALRMBR_MSK1_Pos (7U)
  4715. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  4716. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  4717. #define RTC_ALRMBR_ST_Pos (4U)
  4718. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  4719. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  4720. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  4721. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  4722. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  4723. #define RTC_ALRMBR_SU_Pos (0U)
  4724. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  4725. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  4726. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  4727. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  4728. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  4729. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  4730. /******************** Bits definition for RTC_WPR register ******************/
  4731. #define RTC_WPR_KEY_Pos (0U)
  4732. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  4733. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  4734. /******************** Bits definition for RTC_SSR register ******************/
  4735. #define RTC_SSR_SS_Pos (0U)
  4736. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  4737. #define RTC_SSR_SS RTC_SSR_SS_Msk
  4738. /******************** Bits definition for RTC_SHIFTR register ***************/
  4739. #define RTC_SHIFTR_SUBFS_Pos (0U)
  4740. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  4741. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  4742. #define RTC_SHIFTR_ADD1S_Pos (31U)
  4743. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  4744. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  4745. /******************** Bits definition for RTC_TSTR register *****************/
  4746. #define RTC_TSTR_PM_Pos (22U)
  4747. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  4748. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  4749. #define RTC_TSTR_HT_Pos (20U)
  4750. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  4751. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  4752. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  4753. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  4754. #define RTC_TSTR_HU_Pos (16U)
  4755. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  4756. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  4757. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  4758. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  4759. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  4760. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  4761. #define RTC_TSTR_MNT_Pos (12U)
  4762. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  4763. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  4764. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  4765. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  4766. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  4767. #define RTC_TSTR_MNU_Pos (8U)
  4768. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  4769. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  4770. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  4771. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  4772. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  4773. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  4774. #define RTC_TSTR_ST_Pos (4U)
  4775. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  4776. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  4777. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  4778. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  4779. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  4780. #define RTC_TSTR_SU_Pos (0U)
  4781. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  4782. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  4783. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  4784. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  4785. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  4786. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  4787. /******************** Bits definition for RTC_TSDR register *****************/
  4788. #define RTC_TSDR_WDU_Pos (13U)
  4789. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  4790. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  4791. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  4792. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  4793. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  4794. #define RTC_TSDR_MT_Pos (12U)
  4795. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  4796. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  4797. #define RTC_TSDR_MU_Pos (8U)
  4798. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  4799. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  4800. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  4801. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  4802. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  4803. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  4804. #define RTC_TSDR_DT_Pos (4U)
  4805. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  4806. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  4807. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  4808. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  4809. #define RTC_TSDR_DU_Pos (0U)
  4810. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  4811. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  4812. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  4813. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  4814. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  4815. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  4816. /******************** Bits definition for RTC_TSSSR register ****************/
  4817. #define RTC_TSSSR_SS_Pos (0U)
  4818. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  4819. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  4820. /******************** Bits definition for RTC_CAL register *****************/
  4821. #define RTC_CALR_CALP_Pos (15U)
  4822. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  4823. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  4824. #define RTC_CALR_CALW8_Pos (14U)
  4825. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  4826. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  4827. #define RTC_CALR_CALW16_Pos (13U)
  4828. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  4829. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  4830. #define RTC_CALR_CALM_Pos (0U)
  4831. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  4832. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  4833. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  4834. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  4835. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  4836. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  4837. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  4838. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  4839. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  4840. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  4841. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  4842. /******************** Bits definition for RTC_TAFCR register ****************/
  4843. #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
  4844. #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
  4845. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
  4846. #define RTC_TAFCR_TSINSEL_Pos (17U)
  4847. #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
  4848. #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
  4849. #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
  4850. #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
  4851. #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
  4852. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  4853. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  4854. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  4855. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  4856. #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  4857. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  4858. #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  4859. #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  4860. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  4861. #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  4862. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  4863. #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  4864. #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  4865. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  4866. #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  4867. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  4868. #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  4869. #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  4870. #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  4871. #define RTC_TAFCR_TAMPTS_Pos (7U)
  4872. #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  4873. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  4874. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  4875. #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  4876. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  4877. #define RTC_TAFCR_TAMP2E_Pos (3U)
  4878. #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  4879. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  4880. #define RTC_TAFCR_TAMPIE_Pos (2U)
  4881. #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  4882. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  4883. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  4884. #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  4885. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  4886. #define RTC_TAFCR_TAMP1E_Pos (0U)
  4887. #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  4888. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  4889. /* Legacy defines */
  4890. #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
  4891. /******************** Bits definition for RTC_ALRMASSR register *************/
  4892. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  4893. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  4894. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  4895. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  4896. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  4897. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  4898. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  4899. #define RTC_ALRMASSR_SS_Pos (0U)
  4900. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  4901. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  4902. /******************** Bits definition for RTC_ALRMBSSR register *************/
  4903. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  4904. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  4905. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  4906. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  4907. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  4908. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  4909. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  4910. #define RTC_ALRMBSSR_SS_Pos (0U)
  4911. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  4912. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  4913. /******************** Bits definition for RTC_BKP0R register ****************/
  4914. #define RTC_BKP0R_Pos (0U)
  4915. #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
  4916. #define RTC_BKP0R RTC_BKP0R_Msk
  4917. /******************** Bits definition for RTC_BKP1R register ****************/
  4918. #define RTC_BKP1R_Pos (0U)
  4919. #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
  4920. #define RTC_BKP1R RTC_BKP1R_Msk
  4921. /******************** Bits definition for RTC_BKP2R register ****************/
  4922. #define RTC_BKP2R_Pos (0U)
  4923. #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
  4924. #define RTC_BKP2R RTC_BKP2R_Msk
  4925. /******************** Bits definition for RTC_BKP3R register ****************/
  4926. #define RTC_BKP3R_Pos (0U)
  4927. #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
  4928. #define RTC_BKP3R RTC_BKP3R_Msk
  4929. /******************** Bits definition for RTC_BKP4R register ****************/
  4930. #define RTC_BKP4R_Pos (0U)
  4931. #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
  4932. #define RTC_BKP4R RTC_BKP4R_Msk
  4933. /******************** Bits definition for RTC_BKP5R register ****************/
  4934. #define RTC_BKP5R_Pos (0U)
  4935. #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
  4936. #define RTC_BKP5R RTC_BKP5R_Msk
  4937. /******************** Bits definition for RTC_BKP6R register ****************/
  4938. #define RTC_BKP6R_Pos (0U)
  4939. #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
  4940. #define RTC_BKP6R RTC_BKP6R_Msk
  4941. /******************** Bits definition for RTC_BKP7R register ****************/
  4942. #define RTC_BKP7R_Pos (0U)
  4943. #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
  4944. #define RTC_BKP7R RTC_BKP7R_Msk
  4945. /******************** Bits definition for RTC_BKP8R register ****************/
  4946. #define RTC_BKP8R_Pos (0U)
  4947. #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
  4948. #define RTC_BKP8R RTC_BKP8R_Msk
  4949. /******************** Bits definition for RTC_BKP9R register ****************/
  4950. #define RTC_BKP9R_Pos (0U)
  4951. #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
  4952. #define RTC_BKP9R RTC_BKP9R_Msk
  4953. /******************** Bits definition for RTC_BKP10R register ***************/
  4954. #define RTC_BKP10R_Pos (0U)
  4955. #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
  4956. #define RTC_BKP10R RTC_BKP10R_Msk
  4957. /******************** Bits definition for RTC_BKP11R register ***************/
  4958. #define RTC_BKP11R_Pos (0U)
  4959. #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
  4960. #define RTC_BKP11R RTC_BKP11R_Msk
  4961. /******************** Bits definition for RTC_BKP12R register ***************/
  4962. #define RTC_BKP12R_Pos (0U)
  4963. #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
  4964. #define RTC_BKP12R RTC_BKP12R_Msk
  4965. /******************** Bits definition for RTC_BKP13R register ***************/
  4966. #define RTC_BKP13R_Pos (0U)
  4967. #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
  4968. #define RTC_BKP13R RTC_BKP13R_Msk
  4969. /******************** Bits definition for RTC_BKP14R register ***************/
  4970. #define RTC_BKP14R_Pos (0U)
  4971. #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
  4972. #define RTC_BKP14R RTC_BKP14R_Msk
  4973. /******************** Bits definition for RTC_BKP15R register ***************/
  4974. #define RTC_BKP15R_Pos (0U)
  4975. #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
  4976. #define RTC_BKP15R RTC_BKP15R_Msk
  4977. /******************** Bits definition for RTC_BKP16R register ***************/
  4978. #define RTC_BKP16R_Pos (0U)
  4979. #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
  4980. #define RTC_BKP16R RTC_BKP16R_Msk
  4981. /******************** Bits definition for RTC_BKP17R register ***************/
  4982. #define RTC_BKP17R_Pos (0U)
  4983. #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
  4984. #define RTC_BKP17R RTC_BKP17R_Msk
  4985. /******************** Bits definition for RTC_BKP18R register ***************/
  4986. #define RTC_BKP18R_Pos (0U)
  4987. #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
  4988. #define RTC_BKP18R RTC_BKP18R_Msk
  4989. /******************** Bits definition for RTC_BKP19R register ***************/
  4990. #define RTC_BKP19R_Pos (0U)
  4991. #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
  4992. #define RTC_BKP19R RTC_BKP19R_Msk
  4993. /******************** Number of backup registers ******************************/
  4994. #define RTC_BKP_NUMBER 0x000000014U
  4995. /******************************************************************************/
  4996. /* */
  4997. /* SD host Interface */
  4998. /* */
  4999. /******************************************************************************/
  5000. /****************** Bit definition for SDIO_POWER register ******************/
  5001. #define SDIO_POWER_PWRCTRL_Pos (0U)
  5002. #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
  5003. #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
  5004. #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
  5005. #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
  5006. /****************** Bit definition for SDIO_CLKCR register ******************/
  5007. #define SDIO_CLKCR_CLKDIV_Pos (0U)
  5008. #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
  5009. #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
  5010. #define SDIO_CLKCR_CLKEN_Pos (8U)
  5011. #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
  5012. #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
  5013. #define SDIO_CLKCR_PWRSAV_Pos (9U)
  5014. #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
  5015. #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
  5016. #define SDIO_CLKCR_BYPASS_Pos (10U)
  5017. #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
  5018. #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
  5019. #define SDIO_CLKCR_WIDBUS_Pos (11U)
  5020. #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
  5021. #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
  5022. #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
  5023. #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
  5024. #define SDIO_CLKCR_NEGEDGE_Pos (13U)
  5025. #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
  5026. #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
  5027. #define SDIO_CLKCR_HWFC_EN_Pos (14U)
  5028. #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
  5029. #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
  5030. /******************* Bit definition for SDIO_ARG register *******************/
  5031. #define SDIO_ARG_CMDARG_Pos (0U)
  5032. #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
  5033. #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
  5034. /******************* Bit definition for SDIO_CMD register *******************/
  5035. #define SDIO_CMD_CMDINDEX_Pos (0U)
  5036. #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
  5037. #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
  5038. #define SDIO_CMD_WAITRESP_Pos (6U)
  5039. #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
  5040. #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
  5041. #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
  5042. #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
  5043. #define SDIO_CMD_WAITINT_Pos (8U)
  5044. #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
  5045. #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
  5046. #define SDIO_CMD_WAITPEND_Pos (9U)
  5047. #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
  5048. #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
  5049. #define SDIO_CMD_CPSMEN_Pos (10U)
  5050. #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
  5051. #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
  5052. #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
  5053. #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
  5054. #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
  5055. #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
  5056. #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
  5057. #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
  5058. #define SDIO_CMD_NIEN_Pos (13U)
  5059. #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
  5060. #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
  5061. #define SDIO_CMD_CEATACMD_Pos (14U)
  5062. #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
  5063. #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
  5064. /***************** Bit definition for SDIO_RESPCMD register *****************/
  5065. #define SDIO_RESPCMD_RESPCMD_Pos (0U)
  5066. #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
  5067. #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
  5068. /****************** Bit definition for SDIO_RESP0 register ******************/
  5069. #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
  5070. #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
  5071. #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
  5072. /****************** Bit definition for SDIO_RESP1 register ******************/
  5073. #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
  5074. #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
  5075. #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
  5076. /****************** Bit definition for SDIO_RESP2 register ******************/
  5077. #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
  5078. #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
  5079. #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
  5080. /****************** Bit definition for SDIO_RESP3 register ******************/
  5081. #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
  5082. #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
  5083. #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
  5084. /****************** Bit definition for SDIO_RESP4 register ******************/
  5085. #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
  5086. #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
  5087. #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
  5088. /****************** Bit definition for SDIO_DTIMER register *****************/
  5089. #define SDIO_DTIMER_DATATIME_Pos (0U)
  5090. #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
  5091. #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
  5092. /****************** Bit definition for SDIO_DLEN register *******************/
  5093. #define SDIO_DLEN_DATALENGTH_Pos (0U)
  5094. #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
  5095. #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
  5096. /****************** Bit definition for SDIO_DCTRL register ******************/
  5097. #define SDIO_DCTRL_DTEN_Pos (0U)
  5098. #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
  5099. #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
  5100. #define SDIO_DCTRL_DTDIR_Pos (1U)
  5101. #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
  5102. #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
  5103. #define SDIO_DCTRL_DTMODE_Pos (2U)
  5104. #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
  5105. #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
  5106. #define SDIO_DCTRL_DMAEN_Pos (3U)
  5107. #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
  5108. #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
  5109. #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
  5110. #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
  5111. #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
  5112. #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
  5113. #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
  5114. #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
  5115. #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
  5116. #define SDIO_DCTRL_RWSTART_Pos (8U)
  5117. #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
  5118. #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
  5119. #define SDIO_DCTRL_RWSTOP_Pos (9U)
  5120. #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
  5121. #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
  5122. #define SDIO_DCTRL_RWMOD_Pos (10U)
  5123. #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
  5124. #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
  5125. #define SDIO_DCTRL_SDIOEN_Pos (11U)
  5126. #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
  5127. #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
  5128. /****************** Bit definition for SDIO_DCOUNT register *****************/
  5129. #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
  5130. #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
  5131. #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
  5132. /****************** Bit definition for SDIO_STA register ********************/
  5133. #define SDIO_STA_CCRCFAIL_Pos (0U)
  5134. #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
  5135. #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
  5136. #define SDIO_STA_DCRCFAIL_Pos (1U)
  5137. #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
  5138. #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
  5139. #define SDIO_STA_CTIMEOUT_Pos (2U)
  5140. #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
  5141. #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
  5142. #define SDIO_STA_DTIMEOUT_Pos (3U)
  5143. #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
  5144. #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
  5145. #define SDIO_STA_TXUNDERR_Pos (4U)
  5146. #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
  5147. #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
  5148. #define SDIO_STA_RXOVERR_Pos (5U)
  5149. #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
  5150. #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
  5151. #define SDIO_STA_CMDREND_Pos (6U)
  5152. #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
  5153. #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
  5154. #define SDIO_STA_CMDSENT_Pos (7U)
  5155. #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
  5156. #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
  5157. #define SDIO_STA_DATAEND_Pos (8U)
  5158. #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
  5159. #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
  5160. #define SDIO_STA_STBITERR_Pos (9U)
  5161. #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
  5162. #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
  5163. #define SDIO_STA_DBCKEND_Pos (10U)
  5164. #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
  5165. #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
  5166. #define SDIO_STA_CMDACT_Pos (11U)
  5167. #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
  5168. #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
  5169. #define SDIO_STA_TXACT_Pos (12U)
  5170. #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
  5171. #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
  5172. #define SDIO_STA_RXACT_Pos (13U)
  5173. #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
  5174. #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
  5175. #define SDIO_STA_TXFIFOHE_Pos (14U)
  5176. #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
  5177. #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
  5178. #define SDIO_STA_RXFIFOHF_Pos (15U)
  5179. #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
  5180. #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
  5181. #define SDIO_STA_TXFIFOF_Pos (16U)
  5182. #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
  5183. #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
  5184. #define SDIO_STA_RXFIFOF_Pos (17U)
  5185. #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
  5186. #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
  5187. #define SDIO_STA_TXFIFOE_Pos (18U)
  5188. #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
  5189. #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
  5190. #define SDIO_STA_RXFIFOE_Pos (19U)
  5191. #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
  5192. #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
  5193. #define SDIO_STA_TXDAVL_Pos (20U)
  5194. #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
  5195. #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
  5196. #define SDIO_STA_RXDAVL_Pos (21U)
  5197. #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
  5198. #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
  5199. #define SDIO_STA_SDIOIT_Pos (22U)
  5200. #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
  5201. #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
  5202. #define SDIO_STA_CEATAEND_Pos (23U)
  5203. #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
  5204. #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
  5205. /******************* Bit definition for SDIO_ICR register *******************/
  5206. #define SDIO_ICR_CCRCFAILC_Pos (0U)
  5207. #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
  5208. #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
  5209. #define SDIO_ICR_DCRCFAILC_Pos (1U)
  5210. #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
  5211. #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
  5212. #define SDIO_ICR_CTIMEOUTC_Pos (2U)
  5213. #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
  5214. #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
  5215. #define SDIO_ICR_DTIMEOUTC_Pos (3U)
  5216. #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
  5217. #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
  5218. #define SDIO_ICR_TXUNDERRC_Pos (4U)
  5219. #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
  5220. #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
  5221. #define SDIO_ICR_RXOVERRC_Pos (5U)
  5222. #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
  5223. #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
  5224. #define SDIO_ICR_CMDRENDC_Pos (6U)
  5225. #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
  5226. #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
  5227. #define SDIO_ICR_CMDSENTC_Pos (7U)
  5228. #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
  5229. #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
  5230. #define SDIO_ICR_DATAENDC_Pos (8U)
  5231. #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
  5232. #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
  5233. #define SDIO_ICR_STBITERRC_Pos (9U)
  5234. #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
  5235. #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
  5236. #define SDIO_ICR_DBCKENDC_Pos (10U)
  5237. #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
  5238. #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
  5239. #define SDIO_ICR_SDIOITC_Pos (22U)
  5240. #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
  5241. #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
  5242. #define SDIO_ICR_CEATAENDC_Pos (23U)
  5243. #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
  5244. #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
  5245. /****************** Bit definition for SDIO_MASK register *******************/
  5246. #define SDIO_MASK_CCRCFAILIE_Pos (0U)
  5247. #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
  5248. #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
  5249. #define SDIO_MASK_DCRCFAILIE_Pos (1U)
  5250. #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
  5251. #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
  5252. #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
  5253. #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
  5254. #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
  5255. #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
  5256. #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
  5257. #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
  5258. #define SDIO_MASK_TXUNDERRIE_Pos (4U)
  5259. #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
  5260. #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
  5261. #define SDIO_MASK_RXOVERRIE_Pos (5U)
  5262. #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
  5263. #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
  5264. #define SDIO_MASK_CMDRENDIE_Pos (6U)
  5265. #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
  5266. #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
  5267. #define SDIO_MASK_CMDSENTIE_Pos (7U)
  5268. #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
  5269. #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
  5270. #define SDIO_MASK_DATAENDIE_Pos (8U)
  5271. #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
  5272. #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
  5273. #define SDIO_MASK_STBITERRIE_Pos (9U)
  5274. #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
  5275. #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
  5276. #define SDIO_MASK_DBCKENDIE_Pos (10U)
  5277. #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
  5278. #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
  5279. #define SDIO_MASK_CMDACTIE_Pos (11U)
  5280. #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
  5281. #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
  5282. #define SDIO_MASK_TXACTIE_Pos (12U)
  5283. #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
  5284. #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
  5285. #define SDIO_MASK_RXACTIE_Pos (13U)
  5286. #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
  5287. #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
  5288. #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
  5289. #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
  5290. #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
  5291. #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
  5292. #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
  5293. #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
  5294. #define SDIO_MASK_TXFIFOFIE_Pos (16U)
  5295. #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
  5296. #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
  5297. #define SDIO_MASK_RXFIFOFIE_Pos (17U)
  5298. #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
  5299. #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
  5300. #define SDIO_MASK_TXFIFOEIE_Pos (18U)
  5301. #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
  5302. #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
  5303. #define SDIO_MASK_RXFIFOEIE_Pos (19U)
  5304. #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
  5305. #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
  5306. #define SDIO_MASK_TXDAVLIE_Pos (20U)
  5307. #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
  5308. #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
  5309. #define SDIO_MASK_RXDAVLIE_Pos (21U)
  5310. #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
  5311. #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
  5312. #define SDIO_MASK_SDIOITIE_Pos (22U)
  5313. #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
  5314. #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
  5315. #define SDIO_MASK_CEATAENDIE_Pos (23U)
  5316. #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
  5317. #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
  5318. /***************** Bit definition for SDIO_FIFOCNT register *****************/
  5319. #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
  5320. #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
  5321. #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
  5322. /****************** Bit definition for SDIO_FIFO register *******************/
  5323. #define SDIO_FIFO_FIFODATA_Pos (0U)
  5324. #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
  5325. #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
  5326. /******************************************************************************/
  5327. /* */
  5328. /* Serial Peripheral Interface */
  5329. /* */
  5330. /******************************************************************************/
  5331. #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
  5332. /******************* Bit definition for SPI_CR1 register ********************/
  5333. #define SPI_CR1_CPHA_Pos (0U)
  5334. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  5335. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  5336. #define SPI_CR1_CPOL_Pos (1U)
  5337. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  5338. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  5339. #define SPI_CR1_MSTR_Pos (2U)
  5340. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  5341. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  5342. #define SPI_CR1_BR_Pos (3U)
  5343. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  5344. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  5345. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  5346. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  5347. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  5348. #define SPI_CR1_SPE_Pos (6U)
  5349. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  5350. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  5351. #define SPI_CR1_LSBFIRST_Pos (7U)
  5352. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  5353. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  5354. #define SPI_CR1_SSI_Pos (8U)
  5355. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  5356. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  5357. #define SPI_CR1_SSM_Pos (9U)
  5358. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  5359. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  5360. #define SPI_CR1_RXONLY_Pos (10U)
  5361. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  5362. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  5363. #define SPI_CR1_DFF_Pos (11U)
  5364. #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
  5365. #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
  5366. #define SPI_CR1_CRCNEXT_Pos (12U)
  5367. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  5368. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  5369. #define SPI_CR1_CRCEN_Pos (13U)
  5370. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  5371. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  5372. #define SPI_CR1_BIDIOE_Pos (14U)
  5373. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  5374. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  5375. #define SPI_CR1_BIDIMODE_Pos (15U)
  5376. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  5377. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  5378. /******************* Bit definition for SPI_CR2 register ********************/
  5379. #define SPI_CR2_RXDMAEN_Pos (0U)
  5380. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  5381. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
  5382. #define SPI_CR2_TXDMAEN_Pos (1U)
  5383. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  5384. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
  5385. #define SPI_CR2_SSOE_Pos (2U)
  5386. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  5387. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
  5388. #define SPI_CR2_FRF_Pos (4U)
  5389. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  5390. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
  5391. #define SPI_CR2_ERRIE_Pos (5U)
  5392. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  5393. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
  5394. #define SPI_CR2_RXNEIE_Pos (6U)
  5395. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  5396. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
  5397. #define SPI_CR2_TXEIE_Pos (7U)
  5398. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  5399. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
  5400. /******************** Bit definition for SPI_SR register ********************/
  5401. #define SPI_SR_RXNE_Pos (0U)
  5402. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  5403. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
  5404. #define SPI_SR_TXE_Pos (1U)
  5405. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  5406. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
  5407. #define SPI_SR_CHSIDE_Pos (2U)
  5408. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  5409. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
  5410. #define SPI_SR_UDR_Pos (3U)
  5411. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  5412. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
  5413. #define SPI_SR_CRCERR_Pos (4U)
  5414. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  5415. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
  5416. #define SPI_SR_MODF_Pos (5U)
  5417. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  5418. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
  5419. #define SPI_SR_OVR_Pos (6U)
  5420. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  5421. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
  5422. #define SPI_SR_BSY_Pos (7U)
  5423. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  5424. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
  5425. #define SPI_SR_FRE_Pos (8U)
  5426. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  5427. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
  5428. /******************** Bit definition for SPI_DR register ********************/
  5429. #define SPI_DR_DR_Pos (0U)
  5430. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  5431. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  5432. /******************* Bit definition for SPI_CRCPR register ******************/
  5433. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  5434. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  5435. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  5436. /****************** Bit definition for SPI_RXCRCR register ******************/
  5437. #define SPI_RXCRCR_RXCRC_Pos (0U)
  5438. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  5439. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  5440. /****************** Bit definition for SPI_TXCRCR register ******************/
  5441. #define SPI_TXCRCR_TXCRC_Pos (0U)
  5442. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  5443. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  5444. /****************** Bit definition for SPI_I2SCFGR register *****************/
  5445. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  5446. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  5447. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  5448. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  5449. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  5450. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  5451. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  5452. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  5453. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  5454. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  5455. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  5456. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  5457. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  5458. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  5459. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  5460. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  5461. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  5462. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  5463. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  5464. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  5465. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  5466. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  5467. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  5468. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  5469. #define SPI_I2SCFGR_I2SE_Pos (10U)
  5470. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  5471. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  5472. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  5473. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  5474. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  5475. /****************** Bit definition for SPI_I2SPR register *******************/
  5476. #define SPI_I2SPR_I2SDIV_Pos (0U)
  5477. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  5478. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  5479. #define SPI_I2SPR_ODD_Pos (8U)
  5480. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  5481. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  5482. #define SPI_I2SPR_MCKOE_Pos (9U)
  5483. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  5484. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  5485. /******************************************************************************/
  5486. /* */
  5487. /* SYSCFG */
  5488. /* */
  5489. /******************************************************************************/
  5490. /****************** Bit definition for SYSCFG_MEMRMP register ***************/
  5491. #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
  5492. #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
  5493. #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  5494. #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
  5495. #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
  5496. /****************** Bit definition for SYSCFG_PMC register ******************/
  5497. #define SYSCFG_PMC_ADC1DC2_Pos (16U)
  5498. #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
  5499. #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
  5500. /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
  5501. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  5502. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  5503. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
  5504. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  5505. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  5506. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
  5507. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  5508. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  5509. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
  5510. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  5511. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  5512. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
  5513. /**
  5514. * @brief EXTI0 configuration
  5515. */
  5516. #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
  5517. #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
  5518. #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
  5519. #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
  5520. #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
  5521. #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
  5522. /**
  5523. * @brief EXTI1 configuration
  5524. */
  5525. #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
  5526. #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
  5527. #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
  5528. #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
  5529. #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
  5530. #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
  5531. /**
  5532. * @brief EXTI2 configuration
  5533. */
  5534. #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
  5535. #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
  5536. #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
  5537. #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
  5538. #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
  5539. #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
  5540. /**
  5541. * @brief EXTI3 configuration
  5542. */
  5543. #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
  5544. #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
  5545. #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
  5546. #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
  5547. #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
  5548. #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
  5549. /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
  5550. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  5551. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  5552. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
  5553. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  5554. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  5555. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
  5556. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  5557. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  5558. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
  5559. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  5560. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  5561. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
  5562. /**
  5563. * @brief EXTI4 configuration
  5564. */
  5565. #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
  5566. #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
  5567. #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
  5568. #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
  5569. #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
  5570. #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
  5571. /**
  5572. * @brief EXTI5 configuration
  5573. */
  5574. #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
  5575. #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
  5576. #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
  5577. #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
  5578. #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
  5579. #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
  5580. /**
  5581. * @brief EXTI6 configuration
  5582. */
  5583. #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
  5584. #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
  5585. #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
  5586. #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
  5587. #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
  5588. #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
  5589. /**
  5590. * @brief EXTI7 configuration
  5591. */
  5592. #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
  5593. #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
  5594. #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
  5595. #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
  5596. #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
  5597. #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
  5598. /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
  5599. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  5600. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  5601. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
  5602. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  5603. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  5604. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
  5605. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  5606. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  5607. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
  5608. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  5609. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  5610. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
  5611. /**
  5612. * @brief EXTI8 configuration
  5613. */
  5614. #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
  5615. #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
  5616. #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
  5617. #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
  5618. #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
  5619. #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
  5620. /**
  5621. * @brief EXTI9 configuration
  5622. */
  5623. #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
  5624. #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
  5625. #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
  5626. #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
  5627. #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
  5628. #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
  5629. /**
  5630. * @brief EXTI10 configuration
  5631. */
  5632. #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
  5633. #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
  5634. #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
  5635. #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
  5636. #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
  5637. #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
  5638. /**
  5639. * @brief EXTI11 configuration
  5640. */
  5641. #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
  5642. #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
  5643. #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
  5644. #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
  5645. #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
  5646. #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
  5647. /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
  5648. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  5649. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  5650. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
  5651. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  5652. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  5653. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
  5654. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  5655. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  5656. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
  5657. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  5658. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  5659. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
  5660. /**
  5661. * @brief EXTI12 configuration
  5662. */
  5663. #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
  5664. #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
  5665. #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
  5666. #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
  5667. #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
  5668. #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
  5669. /**
  5670. * @brief EXTI13 configuration
  5671. */
  5672. #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
  5673. #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
  5674. #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
  5675. #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
  5676. #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
  5677. #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
  5678. /**
  5679. * @brief EXTI14 configuration
  5680. */
  5681. #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
  5682. #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
  5683. #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
  5684. #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
  5685. #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
  5686. #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
  5687. /**
  5688. * @brief EXTI15 configuration
  5689. */
  5690. #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
  5691. #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
  5692. #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
  5693. #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
  5694. #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
  5695. #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
  5696. /****************** Bit definition for SYSCFG_CMPCR register ****************/
  5697. #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
  5698. #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
  5699. #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
  5700. #define SYSCFG_CMPCR_READY_Pos (8U)
  5701. #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
  5702. #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
  5703. /******************************************************************************/
  5704. /* */
  5705. /* TIM */
  5706. /* */
  5707. /******************************************************************************/
  5708. /******************* Bit definition for TIM_CR1 register ********************/
  5709. #define TIM_CR1_CEN_Pos (0U)
  5710. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  5711. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  5712. #define TIM_CR1_UDIS_Pos (1U)
  5713. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  5714. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  5715. #define TIM_CR1_URS_Pos (2U)
  5716. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  5717. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  5718. #define TIM_CR1_OPM_Pos (3U)
  5719. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  5720. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  5721. #define TIM_CR1_DIR_Pos (4U)
  5722. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  5723. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  5724. #define TIM_CR1_CMS_Pos (5U)
  5725. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  5726. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  5727. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
  5728. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
  5729. #define TIM_CR1_ARPE_Pos (7U)
  5730. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  5731. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  5732. #define TIM_CR1_CKD_Pos (8U)
  5733. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  5734. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  5735. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
  5736. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
  5737. /******************* Bit definition for TIM_CR2 register ********************/
  5738. #define TIM_CR2_CCPC_Pos (0U)
  5739. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  5740. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  5741. #define TIM_CR2_CCUS_Pos (2U)
  5742. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  5743. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  5744. #define TIM_CR2_CCDS_Pos (3U)
  5745. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  5746. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  5747. #define TIM_CR2_MMS_Pos (4U)
  5748. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  5749. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  5750. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
  5751. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
  5752. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
  5753. #define TIM_CR2_TI1S_Pos (7U)
  5754. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  5755. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  5756. #define TIM_CR2_OIS1_Pos (8U)
  5757. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  5758. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  5759. #define TIM_CR2_OIS1N_Pos (9U)
  5760. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  5761. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  5762. #define TIM_CR2_OIS2_Pos (10U)
  5763. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  5764. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  5765. #define TIM_CR2_OIS2N_Pos (11U)
  5766. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  5767. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  5768. #define TIM_CR2_OIS3_Pos (12U)
  5769. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  5770. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  5771. #define TIM_CR2_OIS3N_Pos (13U)
  5772. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  5773. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  5774. #define TIM_CR2_OIS4_Pos (14U)
  5775. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  5776. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  5777. /******************* Bit definition for TIM_SMCR register *******************/
  5778. #define TIM_SMCR_SMS_Pos (0U)
  5779. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  5780. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  5781. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
  5782. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
  5783. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
  5784. #define TIM_SMCR_TS_Pos (4U)
  5785. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  5786. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  5787. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
  5788. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
  5789. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
  5790. #define TIM_SMCR_MSM_Pos (7U)
  5791. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  5792. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  5793. #define TIM_SMCR_ETF_Pos (8U)
  5794. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  5795. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  5796. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
  5797. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
  5798. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
  5799. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
  5800. #define TIM_SMCR_ETPS_Pos (12U)
  5801. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  5802. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  5803. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
  5804. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
  5805. #define TIM_SMCR_ECE_Pos (14U)
  5806. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  5807. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  5808. #define TIM_SMCR_ETP_Pos (15U)
  5809. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  5810. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  5811. /******************* Bit definition for TIM_DIER register *******************/
  5812. #define TIM_DIER_UIE_Pos (0U)
  5813. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  5814. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  5815. #define TIM_DIER_CC1IE_Pos (1U)
  5816. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  5817. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  5818. #define TIM_DIER_CC2IE_Pos (2U)
  5819. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  5820. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  5821. #define TIM_DIER_CC3IE_Pos (3U)
  5822. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  5823. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  5824. #define TIM_DIER_CC4IE_Pos (4U)
  5825. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  5826. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  5827. #define TIM_DIER_COMIE_Pos (5U)
  5828. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  5829. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  5830. #define TIM_DIER_TIE_Pos (6U)
  5831. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  5832. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  5833. #define TIM_DIER_BIE_Pos (7U)
  5834. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  5835. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  5836. #define TIM_DIER_UDE_Pos (8U)
  5837. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  5838. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  5839. #define TIM_DIER_CC1DE_Pos (9U)
  5840. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  5841. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  5842. #define TIM_DIER_CC2DE_Pos (10U)
  5843. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  5844. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  5845. #define TIM_DIER_CC3DE_Pos (11U)
  5846. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  5847. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  5848. #define TIM_DIER_CC4DE_Pos (12U)
  5849. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  5850. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  5851. #define TIM_DIER_COMDE_Pos (13U)
  5852. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  5853. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  5854. #define TIM_DIER_TDE_Pos (14U)
  5855. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  5856. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  5857. /******************** Bit definition for TIM_SR register ********************/
  5858. #define TIM_SR_UIF_Pos (0U)
  5859. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  5860. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  5861. #define TIM_SR_CC1IF_Pos (1U)
  5862. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  5863. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  5864. #define TIM_SR_CC2IF_Pos (2U)
  5865. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  5866. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  5867. #define TIM_SR_CC3IF_Pos (3U)
  5868. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  5869. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  5870. #define TIM_SR_CC4IF_Pos (4U)
  5871. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  5872. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  5873. #define TIM_SR_COMIF_Pos (5U)
  5874. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  5875. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  5876. #define TIM_SR_TIF_Pos (6U)
  5877. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  5878. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  5879. #define TIM_SR_BIF_Pos (7U)
  5880. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  5881. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  5882. #define TIM_SR_CC1OF_Pos (9U)
  5883. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  5884. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  5885. #define TIM_SR_CC2OF_Pos (10U)
  5886. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  5887. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  5888. #define TIM_SR_CC3OF_Pos (11U)
  5889. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  5890. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  5891. #define TIM_SR_CC4OF_Pos (12U)
  5892. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  5893. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  5894. /******************* Bit definition for TIM_EGR register ********************/
  5895. #define TIM_EGR_UG_Pos (0U)
  5896. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  5897. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  5898. #define TIM_EGR_CC1G_Pos (1U)
  5899. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  5900. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  5901. #define TIM_EGR_CC2G_Pos (2U)
  5902. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  5903. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  5904. #define TIM_EGR_CC3G_Pos (3U)
  5905. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  5906. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  5907. #define TIM_EGR_CC4G_Pos (4U)
  5908. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  5909. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  5910. #define TIM_EGR_COMG_Pos (5U)
  5911. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  5912. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  5913. #define TIM_EGR_TG_Pos (6U)
  5914. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  5915. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  5916. #define TIM_EGR_BG_Pos (7U)
  5917. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  5918. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  5919. /****************** Bit definition for TIM_CCMR1 register *******************/
  5920. #define TIM_CCMR1_CC1S_Pos (0U)
  5921. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  5922. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  5923. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
  5924. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
  5925. #define TIM_CCMR1_OC1FE_Pos (2U)
  5926. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  5927. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  5928. #define TIM_CCMR1_OC1PE_Pos (3U)
  5929. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  5930. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  5931. #define TIM_CCMR1_OC1M_Pos (4U)
  5932. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  5933. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  5934. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
  5935. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
  5936. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
  5937. #define TIM_CCMR1_OC1CE_Pos (7U)
  5938. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  5939. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  5940. #define TIM_CCMR1_CC2S_Pos (8U)
  5941. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  5942. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  5943. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
  5944. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
  5945. #define TIM_CCMR1_OC2FE_Pos (10U)
  5946. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  5947. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  5948. #define TIM_CCMR1_OC2PE_Pos (11U)
  5949. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  5950. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  5951. #define TIM_CCMR1_OC2M_Pos (12U)
  5952. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  5953. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  5954. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
  5955. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
  5956. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
  5957. #define TIM_CCMR1_OC2CE_Pos (15U)
  5958. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  5959. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  5960. /*----------------------------------------------------------------------------*/
  5961. #define TIM_CCMR1_IC1PSC_Pos (2U)
  5962. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  5963. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  5964. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
  5965. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
  5966. #define TIM_CCMR1_IC1F_Pos (4U)
  5967. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  5968. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  5969. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
  5970. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
  5971. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
  5972. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
  5973. #define TIM_CCMR1_IC2PSC_Pos (10U)
  5974. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  5975. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  5976. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
  5977. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
  5978. #define TIM_CCMR1_IC2F_Pos (12U)
  5979. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  5980. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  5981. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
  5982. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
  5983. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
  5984. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
  5985. /****************** Bit definition for TIM_CCMR2 register *******************/
  5986. #define TIM_CCMR2_CC3S_Pos (0U)
  5987. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  5988. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  5989. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
  5990. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
  5991. #define TIM_CCMR2_OC3FE_Pos (2U)
  5992. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  5993. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  5994. #define TIM_CCMR2_OC3PE_Pos (3U)
  5995. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  5996. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  5997. #define TIM_CCMR2_OC3M_Pos (4U)
  5998. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  5999. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  6000. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
  6001. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
  6002. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
  6003. #define TIM_CCMR2_OC3CE_Pos (7U)
  6004. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  6005. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  6006. #define TIM_CCMR2_CC4S_Pos (8U)
  6007. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  6008. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  6009. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
  6010. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
  6011. #define TIM_CCMR2_OC4FE_Pos (10U)
  6012. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  6013. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  6014. #define TIM_CCMR2_OC4PE_Pos (11U)
  6015. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  6016. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  6017. #define TIM_CCMR2_OC4M_Pos (12U)
  6018. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  6019. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  6020. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
  6021. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
  6022. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
  6023. #define TIM_CCMR2_OC4CE_Pos (15U)
  6024. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  6025. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  6026. /*----------------------------------------------------------------------------*/
  6027. #define TIM_CCMR2_IC3PSC_Pos (2U)
  6028. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  6029. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  6030. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
  6031. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
  6032. #define TIM_CCMR2_IC3F_Pos (4U)
  6033. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  6034. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  6035. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
  6036. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
  6037. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
  6038. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
  6039. #define TIM_CCMR2_IC4PSC_Pos (10U)
  6040. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  6041. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  6042. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
  6043. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
  6044. #define TIM_CCMR2_IC4F_Pos (12U)
  6045. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  6046. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  6047. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
  6048. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
  6049. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
  6050. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
  6051. /******************* Bit definition for TIM_CCER register *******************/
  6052. #define TIM_CCER_CC1E_Pos (0U)
  6053. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  6054. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  6055. #define TIM_CCER_CC1P_Pos (1U)
  6056. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  6057. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  6058. #define TIM_CCER_CC1NE_Pos (2U)
  6059. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  6060. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  6061. #define TIM_CCER_CC1NP_Pos (3U)
  6062. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  6063. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  6064. #define TIM_CCER_CC2E_Pos (4U)
  6065. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  6066. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  6067. #define TIM_CCER_CC2P_Pos (5U)
  6068. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  6069. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  6070. #define TIM_CCER_CC2NE_Pos (6U)
  6071. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  6072. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  6073. #define TIM_CCER_CC2NP_Pos (7U)
  6074. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  6075. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  6076. #define TIM_CCER_CC3E_Pos (8U)
  6077. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  6078. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  6079. #define TIM_CCER_CC3P_Pos (9U)
  6080. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  6081. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  6082. #define TIM_CCER_CC3NE_Pos (10U)
  6083. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  6084. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  6085. #define TIM_CCER_CC3NP_Pos (11U)
  6086. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  6087. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  6088. #define TIM_CCER_CC4E_Pos (12U)
  6089. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  6090. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  6091. #define TIM_CCER_CC4P_Pos (13U)
  6092. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  6093. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  6094. #define TIM_CCER_CC4NP_Pos (15U)
  6095. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  6096. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  6097. /******************* Bit definition for TIM_CNT register ********************/
  6098. #define TIM_CNT_CNT_Pos (0U)
  6099. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  6100. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  6101. /******************* Bit definition for TIM_PSC register ********************/
  6102. #define TIM_PSC_PSC_Pos (0U)
  6103. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  6104. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  6105. /******************* Bit definition for TIM_ARR register ********************/
  6106. #define TIM_ARR_ARR_Pos (0U)
  6107. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  6108. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  6109. /******************* Bit definition for TIM_RCR register ********************/
  6110. #define TIM_RCR_REP_Pos (0U)
  6111. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  6112. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  6113. /******************* Bit definition for TIM_CCR1 register *******************/
  6114. #define TIM_CCR1_CCR1_Pos (0U)
  6115. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  6116. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  6117. /******************* Bit definition for TIM_CCR2 register *******************/
  6118. #define TIM_CCR2_CCR2_Pos (0U)
  6119. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  6120. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  6121. /******************* Bit definition for TIM_CCR3 register *******************/
  6122. #define TIM_CCR3_CCR3_Pos (0U)
  6123. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  6124. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  6125. /******************* Bit definition for TIM_CCR4 register *******************/
  6126. #define TIM_CCR4_CCR4_Pos (0U)
  6127. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  6128. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  6129. /******************* Bit definition for TIM_BDTR register *******************/
  6130. #define TIM_BDTR_DTG_Pos (0U)
  6131. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  6132. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  6133. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
  6134. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
  6135. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
  6136. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
  6137. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
  6138. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
  6139. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
  6140. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
  6141. #define TIM_BDTR_LOCK_Pos (8U)
  6142. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  6143. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  6144. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
  6145. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
  6146. #define TIM_BDTR_OSSI_Pos (10U)
  6147. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  6148. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  6149. #define TIM_BDTR_OSSR_Pos (11U)
  6150. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  6151. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  6152. #define TIM_BDTR_BKE_Pos (12U)
  6153. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  6154. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  6155. #define TIM_BDTR_BKP_Pos (13U)
  6156. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  6157. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  6158. #define TIM_BDTR_AOE_Pos (14U)
  6159. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  6160. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  6161. #define TIM_BDTR_MOE_Pos (15U)
  6162. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  6163. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  6164. /******************* Bit definition for TIM_DCR register ********************/
  6165. #define TIM_DCR_DBA_Pos (0U)
  6166. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  6167. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  6168. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
  6169. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
  6170. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
  6171. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
  6172. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
  6173. #define TIM_DCR_DBL_Pos (8U)
  6174. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  6175. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  6176. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
  6177. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
  6178. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
  6179. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
  6180. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
  6181. /******************* Bit definition for TIM_DMAR register *******************/
  6182. #define TIM_DMAR_DMAB_Pos (0U)
  6183. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  6184. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  6185. /******************* Bit definition for TIM_OR register *********************/
  6186. #define TIM_OR_TI1_RMP_Pos (0U)
  6187. #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  6188. #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
  6189. #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  6190. #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  6191. #define TIM_OR_TI4_RMP_Pos (6U)
  6192. #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
  6193. #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
  6194. #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
  6195. #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
  6196. #define TIM_OR_ITR1_RMP_Pos (10U)
  6197. #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
  6198. #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
  6199. #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
  6200. #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
  6201. /******************************************************************************/
  6202. /* */
  6203. /* Universal Synchronous Asynchronous Receiver Transmitter */
  6204. /* */
  6205. /******************************************************************************/
  6206. /******************* Bit definition for USART_SR register *******************/
  6207. #define USART_SR_PE_Pos (0U)
  6208. #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
  6209. #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
  6210. #define USART_SR_FE_Pos (1U)
  6211. #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
  6212. #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
  6213. #define USART_SR_NE_Pos (2U)
  6214. #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
  6215. #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
  6216. #define USART_SR_ORE_Pos (3U)
  6217. #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
  6218. #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
  6219. #define USART_SR_IDLE_Pos (4U)
  6220. #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
  6221. #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
  6222. #define USART_SR_RXNE_Pos (5U)
  6223. #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
  6224. #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
  6225. #define USART_SR_TC_Pos (6U)
  6226. #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
  6227. #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
  6228. #define USART_SR_TXE_Pos (7U)
  6229. #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
  6230. #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
  6231. #define USART_SR_LBD_Pos (8U)
  6232. #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
  6233. #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
  6234. #define USART_SR_CTS_Pos (9U)
  6235. #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
  6236. #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
  6237. /******************* Bit definition for USART_DR register *******************/
  6238. #define USART_DR_DR_Pos (0U)
  6239. #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
  6240. #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
  6241. /****************** Bit definition for USART_BRR register *******************/
  6242. #define USART_BRR_DIV_Fraction_Pos (0U)
  6243. #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
  6244. #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
  6245. #define USART_BRR_DIV_Mantissa_Pos (4U)
  6246. #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
  6247. #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
  6248. /****************** Bit definition for USART_CR1 register *******************/
  6249. #define USART_CR1_SBK_Pos (0U)
  6250. #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
  6251. #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
  6252. #define USART_CR1_RWU_Pos (1U)
  6253. #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
  6254. #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
  6255. #define USART_CR1_RE_Pos (2U)
  6256. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  6257. #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
  6258. #define USART_CR1_TE_Pos (3U)
  6259. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  6260. #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
  6261. #define USART_CR1_IDLEIE_Pos (4U)
  6262. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  6263. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
  6264. #define USART_CR1_RXNEIE_Pos (5U)
  6265. #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  6266. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
  6267. #define USART_CR1_TCIE_Pos (6U)
  6268. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  6269. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
  6270. #define USART_CR1_TXEIE_Pos (7U)
  6271. #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  6272. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
  6273. #define USART_CR1_PEIE_Pos (8U)
  6274. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  6275. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
  6276. #define USART_CR1_PS_Pos (9U)
  6277. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  6278. #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
  6279. #define USART_CR1_PCE_Pos (10U)
  6280. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  6281. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
  6282. #define USART_CR1_WAKE_Pos (11U)
  6283. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  6284. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
  6285. #define USART_CR1_M_Pos (12U)
  6286. #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
  6287. #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
  6288. #define USART_CR1_UE_Pos (13U)
  6289. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
  6290. #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
  6291. #define USART_CR1_OVER8_Pos (15U)
  6292. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  6293. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
  6294. /****************** Bit definition for USART_CR2 register *******************/
  6295. #define USART_CR2_ADD_Pos (0U)
  6296. #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
  6297. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
  6298. #define USART_CR2_LBDL_Pos (5U)
  6299. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  6300. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
  6301. #define USART_CR2_LBDIE_Pos (6U)
  6302. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  6303. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
  6304. #define USART_CR2_LBCL_Pos (8U)
  6305. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  6306. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
  6307. #define USART_CR2_CPHA_Pos (9U)
  6308. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  6309. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
  6310. #define USART_CR2_CPOL_Pos (10U)
  6311. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  6312. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
  6313. #define USART_CR2_CLKEN_Pos (11U)
  6314. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  6315. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
  6316. #define USART_CR2_STOP_Pos (12U)
  6317. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  6318. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
  6319. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x1000 */
  6320. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x2000 */
  6321. #define USART_CR2_LINEN_Pos (14U)
  6322. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  6323. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
  6324. /****************** Bit definition for USART_CR3 register *******************/
  6325. #define USART_CR3_EIE_Pos (0U)
  6326. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  6327. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
  6328. #define USART_CR3_IREN_Pos (1U)
  6329. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  6330. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
  6331. #define USART_CR3_IRLP_Pos (2U)
  6332. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  6333. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
  6334. #define USART_CR3_HDSEL_Pos (3U)
  6335. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  6336. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
  6337. #define USART_CR3_NACK_Pos (4U)
  6338. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  6339. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
  6340. #define USART_CR3_SCEN_Pos (5U)
  6341. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  6342. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
  6343. #define USART_CR3_DMAR_Pos (6U)
  6344. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  6345. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
  6346. #define USART_CR3_DMAT_Pos (7U)
  6347. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  6348. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
  6349. #define USART_CR3_RTSE_Pos (8U)
  6350. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  6351. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
  6352. #define USART_CR3_CTSE_Pos (9U)
  6353. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  6354. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
  6355. #define USART_CR3_CTSIE_Pos (10U)
  6356. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  6357. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
  6358. #define USART_CR3_ONEBIT_Pos (11U)
  6359. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  6360. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
  6361. /****************** Bit definition for USART_GTPR register ******************/
  6362. #define USART_GTPR_PSC_Pos (0U)
  6363. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  6364. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
  6365. #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x0001 */
  6366. #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x0002 */
  6367. #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x0004 */
  6368. #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x0008 */
  6369. #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x0010 */
  6370. #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x0020 */
  6371. #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x0040 */
  6372. #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x0080 */
  6373. #define USART_GTPR_GT_Pos (8U)
  6374. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  6375. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
  6376. /******************************************************************************/
  6377. /* */
  6378. /* Window WATCHDOG */
  6379. /* */
  6380. /******************************************************************************/
  6381. /******************* Bit definition for WWDG_CR register ********************/
  6382. #define WWDG_CR_T_Pos (0U)
  6383. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  6384. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  6385. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
  6386. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
  6387. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
  6388. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
  6389. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
  6390. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
  6391. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
  6392. /* Legacy defines */
  6393. #define WWDG_CR_T0 WWDG_CR_T_0
  6394. #define WWDG_CR_T1 WWDG_CR_T_1
  6395. #define WWDG_CR_T2 WWDG_CR_T_2
  6396. #define WWDG_CR_T3 WWDG_CR_T_3
  6397. #define WWDG_CR_T4 WWDG_CR_T_4
  6398. #define WWDG_CR_T5 WWDG_CR_T_5
  6399. #define WWDG_CR_T6 WWDG_CR_T_6
  6400. #define WWDG_CR_WDGA_Pos (7U)
  6401. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  6402. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  6403. /******************* Bit definition for WWDG_CFR register *******************/
  6404. #define WWDG_CFR_W_Pos (0U)
  6405. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  6406. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  6407. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
  6408. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
  6409. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
  6410. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
  6411. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
  6412. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
  6413. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
  6414. /* Legacy defines */
  6415. #define WWDG_CFR_W0 WWDG_CFR_W_0
  6416. #define WWDG_CFR_W1 WWDG_CFR_W_1
  6417. #define WWDG_CFR_W2 WWDG_CFR_W_2
  6418. #define WWDG_CFR_W3 WWDG_CFR_W_3
  6419. #define WWDG_CFR_W4 WWDG_CFR_W_4
  6420. #define WWDG_CFR_W5 WWDG_CFR_W_5
  6421. #define WWDG_CFR_W6 WWDG_CFR_W_6
  6422. #define WWDG_CFR_WDGTB_Pos (7U)
  6423. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  6424. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
  6425. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
  6426. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
  6427. /* Legacy defines */
  6428. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  6429. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  6430. #define WWDG_CFR_EWI_Pos (9U)
  6431. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  6432. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  6433. /******************* Bit definition for WWDG_SR register ********************/
  6434. #define WWDG_SR_EWIF_Pos (0U)
  6435. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  6436. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  6437. /******************************************************************************/
  6438. /* */
  6439. /* DBG */
  6440. /* */
  6441. /******************************************************************************/
  6442. /******************** Bit definition for DBGMCU_IDCODE register *************/
  6443. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  6444. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  6445. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
  6446. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  6447. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  6448. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
  6449. /******************** Bit definition for DBGMCU_CR register *****************/
  6450. #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
  6451. #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
  6452. #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
  6453. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  6454. #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  6455. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
  6456. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  6457. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  6458. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
  6459. #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
  6460. #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
  6461. #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
  6462. #define DBGMCU_CR_TRACE_MODE_Pos (6U)
  6463. #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
  6464. #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
  6465. #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
  6466. #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
  6467. /******************** Bit definition for DBGMCU_APB1_FZ register ************/
  6468. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
  6469. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  6470. #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
  6471. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
  6472. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  6473. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
  6474. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
  6475. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
  6476. #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
  6477. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
  6478. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
  6479. #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
  6480. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  6481. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  6482. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
  6483. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  6484. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  6485. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
  6486. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  6487. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  6488. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
  6489. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  6490. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  6491. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
  6492. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
  6493. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
  6494. #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
  6495. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
  6496. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
  6497. #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
  6498. /* Old IWDGSTOP bit definition, maintained for legacy purpose */
  6499. #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
  6500. /******************** Bit definition for DBGMCU_APB2_FZ register ************/
  6501. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
  6502. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
  6503. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
  6504. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
  6505. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
  6506. #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
  6507. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
  6508. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
  6509. #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
  6510. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
  6511. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
  6512. #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
  6513. /******************************************************************************/
  6514. /* */
  6515. /* USB_OTG */
  6516. /* */
  6517. /******************************************************************************/
  6518. /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
  6519. #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
  6520. #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
  6521. #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
  6522. #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
  6523. #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
  6524. #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
  6525. #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
  6526. #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
  6527. #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
  6528. #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
  6529. #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
  6530. #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
  6531. #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
  6532. #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
  6533. #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
  6534. #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
  6535. #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
  6536. #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
  6537. #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
  6538. #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
  6539. #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
  6540. #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
  6541. #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
  6542. #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
  6543. #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
  6544. #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
  6545. #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
  6546. #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
  6547. #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
  6548. #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
  6549. /******************** Bit definition forUSB_OTG_HCFG register ********************/
  6550. #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
  6551. #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
  6552. #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
  6553. #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
  6554. #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
  6555. #define USB_OTG_HCFG_FSLSS_Pos (2U)
  6556. #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
  6557. #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
  6558. /******************** Bit definition for USB_OTG_DCFG register ********************/
  6559. #define USB_OTG_DCFG_DSPD_Pos (0U)
  6560. #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
  6561. #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
  6562. #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
  6563. #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
  6564. #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
  6565. #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
  6566. #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
  6567. #define USB_OTG_DCFG_DAD_Pos (4U)
  6568. #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
  6569. #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
  6570. #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
  6571. #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
  6572. #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
  6573. #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
  6574. #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
  6575. #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
  6576. #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
  6577. #define USB_OTG_DCFG_PFIVL_Pos (11U)
  6578. #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
  6579. #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
  6580. #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
  6581. #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
  6582. #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
  6583. #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
  6584. #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
  6585. #define USB_OTG_DCFG_ERRATIM_Pos (15U)
  6586. #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
  6587. #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
  6588. #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
  6589. #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
  6590. #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
  6591. #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
  6592. #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
  6593. /******************** Bit definition for USB_OTG_PCGCR register ********************/
  6594. #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
  6595. #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
  6596. #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
  6597. #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
  6598. #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
  6599. #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
  6600. #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
  6601. #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
  6602. #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
  6603. /******************** Bit definition for USB_OTG_GOTGINT register ********************/
  6604. #define USB_OTG_GOTGINT_SEDET_Pos (2U)
  6605. #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
  6606. #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
  6607. #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
  6608. #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
  6609. #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
  6610. #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
  6611. #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
  6612. #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
  6613. #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
  6614. #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
  6615. #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
  6616. #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
  6617. #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
  6618. #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
  6619. #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
  6620. #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
  6621. #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
  6622. /******************** Bit definition for USB_OTG_DCTL register ********************/
  6623. #define USB_OTG_DCTL_RWUSIG_Pos (0U)
  6624. #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
  6625. #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
  6626. #define USB_OTG_DCTL_SDIS_Pos (1U)
  6627. #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
  6628. #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
  6629. #define USB_OTG_DCTL_GINSTS_Pos (2U)
  6630. #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
  6631. #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
  6632. #define USB_OTG_DCTL_GONSTS_Pos (3U)
  6633. #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
  6634. #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
  6635. #define USB_OTG_DCTL_TCTL_Pos (4U)
  6636. #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
  6637. #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
  6638. #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
  6639. #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
  6640. #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
  6641. #define USB_OTG_DCTL_SGINAK_Pos (7U)
  6642. #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
  6643. #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
  6644. #define USB_OTG_DCTL_CGINAK_Pos (8U)
  6645. #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
  6646. #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
  6647. #define USB_OTG_DCTL_SGONAK_Pos (9U)
  6648. #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
  6649. #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
  6650. #define USB_OTG_DCTL_CGONAK_Pos (10U)
  6651. #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
  6652. #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
  6653. #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
  6654. #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
  6655. #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
  6656. /******************** Bit definition for USB_OTG_HFIR register ********************/
  6657. #define USB_OTG_HFIR_FRIVL_Pos (0U)
  6658. #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
  6659. #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
  6660. /******************** Bit definition for USB_OTG_HFNUM register ********************/
  6661. #define USB_OTG_HFNUM_FRNUM_Pos (0U)
  6662. #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
  6663. #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
  6664. #define USB_OTG_HFNUM_FTREM_Pos (16U)
  6665. #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
  6666. #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
  6667. /******************** Bit definition for USB_OTG_DSTS register ********************/
  6668. #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
  6669. #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
  6670. #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
  6671. #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
  6672. #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
  6673. #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
  6674. #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
  6675. #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
  6676. #define USB_OTG_DSTS_EERR_Pos (3U)
  6677. #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
  6678. #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
  6679. #define USB_OTG_DSTS_FNSOF_Pos (8U)
  6680. #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
  6681. #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
  6682. /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
  6683. #define USB_OTG_GAHBCFG_GINT_Pos (0U)
  6684. #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
  6685. #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
  6686. #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
  6687. #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
  6688. #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
  6689. #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
  6690. #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
  6691. #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
  6692. #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
  6693. #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
  6694. #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
  6695. #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
  6696. #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
  6697. #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
  6698. #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
  6699. #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
  6700. #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
  6701. #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
  6702. #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
  6703. /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
  6704. #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
  6705. #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
  6706. #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
  6707. #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
  6708. #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
  6709. #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
  6710. #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
  6711. #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
  6712. #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
  6713. #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
  6714. #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
  6715. #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
  6716. #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
  6717. #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
  6718. #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
  6719. #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
  6720. #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
  6721. #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
  6722. #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
  6723. #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
  6724. #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
  6725. #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
  6726. #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
  6727. #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
  6728. #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
  6729. #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
  6730. #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
  6731. #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
  6732. #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
  6733. #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
  6734. #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
  6735. #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
  6736. #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
  6737. #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
  6738. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
  6739. #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
  6740. #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
  6741. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
  6742. #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
  6743. #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
  6744. #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
  6745. #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
  6746. #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
  6747. #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
  6748. #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
  6749. #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
  6750. #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
  6751. #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
  6752. #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
  6753. #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
  6754. #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
  6755. #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
  6756. #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
  6757. #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
  6758. #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
  6759. #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
  6760. #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
  6761. #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
  6762. #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
  6763. #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
  6764. #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
  6765. /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
  6766. #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
  6767. #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
  6768. #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
  6769. #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
  6770. #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
  6771. #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
  6772. #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
  6773. #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
  6774. #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
  6775. #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
  6776. #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
  6777. #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
  6778. #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
  6779. #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
  6780. #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
  6781. #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
  6782. #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
  6783. #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
  6784. #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
  6785. #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
  6786. #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
  6787. #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
  6788. #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
  6789. #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
  6790. #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
  6791. #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
  6792. #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
  6793. #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
  6794. #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
  6795. /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
  6796. #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
  6797. #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  6798. #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  6799. #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
  6800. #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
  6801. #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  6802. #define USB_OTG_DIEPMSK_TOM_Pos (3U)
  6803. #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
  6804. #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  6805. #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
  6806. #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
  6807. #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  6808. #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
  6809. #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
  6810. #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  6811. #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
  6812. #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
  6813. #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  6814. #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
  6815. #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
  6816. #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
  6817. #define USB_OTG_DIEPMSK_BIM_Pos (9U)
  6818. #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
  6819. #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
  6820. /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
  6821. #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
  6822. #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
  6823. #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
  6824. #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
  6825. #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
  6826. #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
  6827. #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
  6828. #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
  6829. #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
  6830. #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
  6831. #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
  6832. #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
  6833. #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
  6834. #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
  6835. #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
  6836. #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
  6837. #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
  6838. #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
  6839. #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
  6840. #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
  6841. #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
  6842. #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
  6843. #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
  6844. #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
  6845. #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
  6846. /******************** Bit definition for USB_OTG_HAINT register ********************/
  6847. #define USB_OTG_HAINT_HAINT_Pos (0U)
  6848. #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
  6849. #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
  6850. /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
  6851. #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
  6852. #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
  6853. #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
  6854. #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
  6855. #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
  6856. #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  6857. #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
  6858. #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
  6859. #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
  6860. #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
  6861. #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
  6862. #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
  6863. #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
  6864. #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
  6865. #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
  6866. #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
  6867. #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
  6868. #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
  6869. #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
  6870. #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
  6871. #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
  6872. #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
  6873. #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
  6874. #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
  6875. #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
  6876. #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
  6877. #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
  6878. #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
  6879. #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
  6880. #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
  6881. #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
  6882. #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
  6883. #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
  6884. #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
  6885. #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
  6886. #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
  6887. /******************** Bit definition for USB_OTG_GINTSTS register ********************/
  6888. #define USB_OTG_GINTSTS_CMOD_Pos (0U)
  6889. #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
  6890. #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
  6891. #define USB_OTG_GINTSTS_MMIS_Pos (1U)
  6892. #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
  6893. #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
  6894. #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
  6895. #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
  6896. #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
  6897. #define USB_OTG_GINTSTS_SOF_Pos (3U)
  6898. #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
  6899. #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
  6900. #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
  6901. #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
  6902. #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
  6903. #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
  6904. #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
  6905. #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
  6906. #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
  6907. #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
  6908. #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
  6909. #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
  6910. #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
  6911. #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
  6912. #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
  6913. #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
  6914. #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
  6915. #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
  6916. #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
  6917. #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
  6918. #define USB_OTG_GINTSTS_USBRST_Pos (12U)
  6919. #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
  6920. #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
  6921. #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
  6922. #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
  6923. #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
  6924. #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
  6925. #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
  6926. #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
  6927. #define USB_OTG_GINTSTS_EOPF_Pos (15U)
  6928. #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
  6929. #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
  6930. #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
  6931. #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
  6932. #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
  6933. #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
  6934. #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
  6935. #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
  6936. #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
  6937. #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
  6938. #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
  6939. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
  6940. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
  6941. #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
  6942. #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
  6943. #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
  6944. #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
  6945. #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
  6946. #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
  6947. #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
  6948. #define USB_OTG_GINTSTS_HCINT_Pos (25U)
  6949. #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
  6950. #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
  6951. #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
  6952. #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
  6953. #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
  6954. #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
  6955. #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
  6956. #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
  6957. #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
  6958. #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
  6959. #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
  6960. #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
  6961. #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
  6962. #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
  6963. #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
  6964. #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
  6965. #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
  6966. /******************** Bit definition for USB_OTG_GINTMSK register ********************/
  6967. #define USB_OTG_GINTMSK_MMISM_Pos (1U)
  6968. #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
  6969. #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
  6970. #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
  6971. #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
  6972. #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
  6973. #define USB_OTG_GINTMSK_SOFM_Pos (3U)
  6974. #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
  6975. #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
  6976. #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
  6977. #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
  6978. #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
  6979. #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
  6980. #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
  6981. #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
  6982. #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
  6983. #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
  6984. #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
  6985. #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
  6986. #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
  6987. #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
  6988. #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
  6989. #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
  6990. #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
  6991. #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
  6992. #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
  6993. #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
  6994. #define USB_OTG_GINTMSK_USBRST_Pos (12U)
  6995. #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
  6996. #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
  6997. #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
  6998. #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
  6999. #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
  7000. #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
  7001. #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
  7002. #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
  7003. #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
  7004. #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
  7005. #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
  7006. #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
  7007. #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
  7008. #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
  7009. #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
  7010. #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
  7011. #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
  7012. #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
  7013. #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
  7014. #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
  7015. #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
  7016. #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
  7017. #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
  7018. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
  7019. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
  7020. #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
  7021. #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
  7022. #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
  7023. #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
  7024. #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
  7025. #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
  7026. #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
  7027. #define USB_OTG_GINTMSK_HCIM_Pos (25U)
  7028. #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
  7029. #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
  7030. #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
  7031. #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
  7032. #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
  7033. #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
  7034. #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
  7035. #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
  7036. #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
  7037. #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
  7038. #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
  7039. #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
  7040. #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
  7041. #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
  7042. #define USB_OTG_GINTMSK_WUIM_Pos (31U)
  7043. #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
  7044. #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
  7045. /******************** Bit definition for USB_OTG_DAINT register ********************/
  7046. #define USB_OTG_DAINT_IEPINT_Pos (0U)
  7047. #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
  7048. #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
  7049. #define USB_OTG_DAINT_OEPINT_Pos (16U)
  7050. #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
  7051. #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
  7052. /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
  7053. #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
  7054. #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
  7055. #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
  7056. /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
  7057. #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
  7058. #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
  7059. #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
  7060. #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
  7061. #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
  7062. #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
  7063. #define USB_OTG_GRXSTSP_DPID_Pos (15U)
  7064. #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
  7065. #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
  7066. #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
  7067. #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
  7068. #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
  7069. /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
  7070. #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
  7071. #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
  7072. #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
  7073. #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
  7074. #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
  7075. #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
  7076. /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
  7077. #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
  7078. #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
  7079. #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
  7080. /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
  7081. #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
  7082. #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
  7083. #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
  7084. /******************** Bit definition for OTG register ********************/
  7085. #define USB_OTG_NPTXFSA_Pos (0U)
  7086. #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
  7087. #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
  7088. #define USB_OTG_NPTXFD_Pos (16U)
  7089. #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
  7090. #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
  7091. #define USB_OTG_TX0FSA_Pos (0U)
  7092. #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
  7093. #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
  7094. #define USB_OTG_TX0FD_Pos (16U)
  7095. #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
  7096. #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
  7097. /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
  7098. #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
  7099. #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
  7100. #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
  7101. /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
  7102. #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
  7103. #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
  7104. #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
  7105. #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
  7106. #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
  7107. #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
  7108. #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
  7109. #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
  7110. #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
  7111. #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
  7112. #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
  7113. #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
  7114. #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
  7115. #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
  7116. #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
  7117. #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
  7118. #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
  7119. #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
  7120. #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
  7121. #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
  7122. #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
  7123. #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
  7124. #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
  7125. #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
  7126. /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
  7127. #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
  7128. #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
  7129. #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
  7130. #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
  7131. #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
  7132. #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
  7133. #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
  7134. #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
  7135. #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
  7136. #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
  7137. #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
  7138. #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
  7139. #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
  7140. #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
  7141. #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
  7142. #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
  7143. #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
  7144. #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
  7145. #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
  7146. #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
  7147. #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
  7148. #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
  7149. #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
  7150. #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
  7151. #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
  7152. #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
  7153. #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
  7154. #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
  7155. #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
  7156. #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
  7157. #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
  7158. #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
  7159. #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
  7160. #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
  7161. #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
  7162. #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
  7163. /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
  7164. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
  7165. #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
  7166. #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
  7167. /******************** Bit definition for USB_OTG_DEACHINT register ********************/
  7168. #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
  7169. #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
  7170. #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
  7171. #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
  7172. #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
  7173. #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
  7174. /******************** Bit definition for USB_OTG_GCCFG register ********************/
  7175. #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
  7176. #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
  7177. #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
  7178. #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
  7179. #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
  7180. #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
  7181. #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
  7182. #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
  7183. #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
  7184. #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
  7185. #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
  7186. #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
  7187. #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
  7188. #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
  7189. #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
  7190. #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
  7191. #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
  7192. #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
  7193. /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
  7194. #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
  7195. #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
  7196. #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
  7197. #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
  7198. #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
  7199. #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
  7200. /******************** Bit definition for USB_OTG_CID register ********************/
  7201. #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
  7202. #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
  7203. #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
  7204. /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
  7205. #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
  7206. #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  7207. #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  7208. #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
  7209. #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  7210. #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  7211. #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
  7212. #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  7213. #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
  7214. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
  7215. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  7216. #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  7217. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
  7218. #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  7219. #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  7220. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
  7221. #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  7222. #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  7223. #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
  7224. #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  7225. #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
  7226. #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
  7227. #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  7228. #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  7229. #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
  7230. #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  7231. #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  7232. /******************** Bit definition for USB_OTG_HPRT register ********************/
  7233. #define USB_OTG_HPRT_PCSTS_Pos (0U)
  7234. #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
  7235. #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
  7236. #define USB_OTG_HPRT_PCDET_Pos (1U)
  7237. #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
  7238. #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
  7239. #define USB_OTG_HPRT_PENA_Pos (2U)
  7240. #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
  7241. #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
  7242. #define USB_OTG_HPRT_PENCHNG_Pos (3U)
  7243. #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
  7244. #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
  7245. #define USB_OTG_HPRT_POCA_Pos (4U)
  7246. #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
  7247. #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
  7248. #define USB_OTG_HPRT_POCCHNG_Pos (5U)
  7249. #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
  7250. #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
  7251. #define USB_OTG_HPRT_PRES_Pos (6U)
  7252. #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
  7253. #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
  7254. #define USB_OTG_HPRT_PSUSP_Pos (7U)
  7255. #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
  7256. #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
  7257. #define USB_OTG_HPRT_PRST_Pos (8U)
  7258. #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
  7259. #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
  7260. #define USB_OTG_HPRT_PLSTS_Pos (10U)
  7261. #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
  7262. #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
  7263. #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
  7264. #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
  7265. #define USB_OTG_HPRT_PPWR_Pos (12U)
  7266. #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
  7267. #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
  7268. #define USB_OTG_HPRT_PTCTL_Pos (13U)
  7269. #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
  7270. #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
  7271. #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
  7272. #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
  7273. #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
  7274. #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
  7275. #define USB_OTG_HPRT_PSPD_Pos (17U)
  7276. #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
  7277. #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
  7278. #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
  7279. #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
  7280. /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
  7281. #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
  7282. #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
  7283. #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
  7284. #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
  7285. #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
  7286. #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
  7287. #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
  7288. #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
  7289. #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
  7290. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
  7291. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
  7292. #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
  7293. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
  7294. #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
  7295. #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
  7296. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
  7297. #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
  7298. #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
  7299. #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
  7300. #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
  7301. #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
  7302. #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
  7303. #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
  7304. #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
  7305. #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
  7306. #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
  7307. #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
  7308. #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
  7309. #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
  7310. #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
  7311. #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
  7312. #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
  7313. #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
  7314. /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
  7315. #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
  7316. #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
  7317. #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
  7318. #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
  7319. #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
  7320. #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
  7321. /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
  7322. #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
  7323. #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  7324. #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
  7325. #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
  7326. #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  7327. #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
  7328. #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
  7329. #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
  7330. #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
  7331. #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
  7332. #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  7333. #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
  7334. #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
  7335. #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  7336. #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
  7337. #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  7338. #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  7339. #define USB_OTG_DIEPCTL_STALL_Pos (21U)
  7340. #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
  7341. #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
  7342. #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
  7343. #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
  7344. #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
  7345. #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
  7346. #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
  7347. #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
  7348. #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
  7349. #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
  7350. #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
  7351. #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
  7352. #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
  7353. #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
  7354. #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
  7355. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
  7356. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  7357. #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  7358. #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
  7359. #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  7360. #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
  7361. #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
  7362. #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  7363. #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
  7364. #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
  7365. #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
  7366. #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
  7367. /******************** Bit definition for USB_OTG_HCCHAR register ********************/
  7368. #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
  7369. #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
  7370. #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
  7371. #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
  7372. #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
  7373. #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
  7374. #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
  7375. #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
  7376. #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
  7377. #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
  7378. #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
  7379. #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
  7380. #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
  7381. #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
  7382. #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
  7383. #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
  7384. #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
  7385. #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
  7386. #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
  7387. #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
  7388. #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
  7389. #define USB_OTG_HCCHAR_MC_Pos (20U)
  7390. #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
  7391. #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
  7392. #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
  7393. #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
  7394. #define USB_OTG_HCCHAR_DAD_Pos (22U)
  7395. #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
  7396. #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
  7397. #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
  7398. #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
  7399. #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
  7400. #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
  7401. #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
  7402. #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
  7403. #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
  7404. #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
  7405. #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
  7406. #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
  7407. #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
  7408. #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
  7409. #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
  7410. #define USB_OTG_HCCHAR_CHENA_Pos (31U)
  7411. #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
  7412. #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
  7413. /******************** Bit definition for USB_OTG_HCSPLT register ********************/
  7414. #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
  7415. #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
  7416. #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
  7417. #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
  7418. #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
  7419. #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
  7420. #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
  7421. #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
  7422. #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
  7423. #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
  7424. #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
  7425. #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
  7426. #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
  7427. #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
  7428. #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
  7429. #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
  7430. #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
  7431. #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
  7432. #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
  7433. #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
  7434. #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
  7435. #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
  7436. #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
  7437. #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
  7438. #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
  7439. #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
  7440. #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
  7441. #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
  7442. #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
  7443. #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
  7444. #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
  7445. /******************** Bit definition for USB_OTG_HCINT register ********************/
  7446. #define USB_OTG_HCINT_XFRC_Pos (0U)
  7447. #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
  7448. #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
  7449. #define USB_OTG_HCINT_CHH_Pos (1U)
  7450. #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
  7451. #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
  7452. #define USB_OTG_HCINT_AHBERR_Pos (2U)
  7453. #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
  7454. #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
  7455. #define USB_OTG_HCINT_STALL_Pos (3U)
  7456. #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
  7457. #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
  7458. #define USB_OTG_HCINT_NAK_Pos (4U)
  7459. #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
  7460. #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
  7461. #define USB_OTG_HCINT_ACK_Pos (5U)
  7462. #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
  7463. #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
  7464. #define USB_OTG_HCINT_NYET_Pos (6U)
  7465. #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
  7466. #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
  7467. #define USB_OTG_HCINT_TXERR_Pos (7U)
  7468. #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
  7469. #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
  7470. #define USB_OTG_HCINT_BBERR_Pos (8U)
  7471. #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
  7472. #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
  7473. #define USB_OTG_HCINT_FRMOR_Pos (9U)
  7474. #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
  7475. #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
  7476. #define USB_OTG_HCINT_DTERR_Pos (10U)
  7477. #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
  7478. #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
  7479. /******************** Bit definition for USB_OTG_DIEPINT register ********************/
  7480. #define USB_OTG_DIEPINT_XFRC_Pos (0U)
  7481. #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
  7482. #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  7483. #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
  7484. #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
  7485. #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  7486. #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
  7487. #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
  7488. #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
  7489. #define USB_OTG_DIEPINT_TOC_Pos (3U)
  7490. #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
  7491. #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
  7492. #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
  7493. #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
  7494. #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
  7495. #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
  7496. #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
  7497. #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
  7498. #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
  7499. #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
  7500. #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
  7501. #define USB_OTG_DIEPINT_TXFE_Pos (7U)
  7502. #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
  7503. #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
  7504. #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
  7505. #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
  7506. #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
  7507. #define USB_OTG_DIEPINT_BNA_Pos (9U)
  7508. #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
  7509. #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
  7510. #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
  7511. #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
  7512. #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
  7513. #define USB_OTG_DIEPINT_BERR_Pos (12U)
  7514. #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
  7515. #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
  7516. #define USB_OTG_DIEPINT_NAK_Pos (13U)
  7517. #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
  7518. #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
  7519. /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
  7520. #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
  7521. #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
  7522. #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
  7523. #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
  7524. #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
  7525. #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
  7526. #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
  7527. #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
  7528. #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
  7529. #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
  7530. #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
  7531. #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
  7532. #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
  7533. #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
  7534. #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
  7535. #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
  7536. #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
  7537. #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
  7538. #define USB_OTG_HCINTMSK_NYET_Pos (6U)
  7539. #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
  7540. #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
  7541. #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
  7542. #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
  7543. #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
  7544. #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
  7545. #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
  7546. #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
  7547. #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
  7548. #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
  7549. #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
  7550. #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
  7551. #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
  7552. #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
  7553. /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
  7554. #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
  7555. #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  7556. #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  7557. #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
  7558. #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  7559. #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
  7560. #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
  7561. #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
  7562. #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
  7563. /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
  7564. #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
  7565. #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  7566. #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
  7567. #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
  7568. #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  7569. #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
  7570. #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
  7571. #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
  7572. #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
  7573. #define USB_OTG_HCTSIZ_DPID_Pos (29U)
  7574. #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
  7575. #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
  7576. #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
  7577. #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
  7578. /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
  7579. #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
  7580. #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  7581. #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
  7582. /******************** Bit definition for USB_OTG_HCDMA register ********************/
  7583. #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
  7584. #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
  7585. #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
  7586. /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
  7587. #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
  7588. #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
  7589. #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
  7590. /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
  7591. #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
  7592. #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
  7593. #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
  7594. #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
  7595. #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
  7596. #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
  7597. /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
  7598. #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
  7599. #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
  7600. #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
  7601. #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
  7602. #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
  7603. #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
  7604. #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
  7605. #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
  7606. #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
  7607. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
  7608. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
  7609. #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
  7610. #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
  7611. #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
  7612. #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
  7613. #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
  7614. #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
  7615. #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
  7616. #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
  7617. #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
  7618. #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
  7619. #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
  7620. #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
  7621. #define USB_OTG_DOEPCTL_STALL_Pos (21U)
  7622. #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
  7623. #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
  7624. #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
  7625. #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
  7626. #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
  7627. #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
  7628. #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
  7629. #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
  7630. #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
  7631. #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
  7632. #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
  7633. #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
  7634. #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
  7635. #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
  7636. /******************** Bit definition for USB_OTG_DOEPINT register ********************/
  7637. #define USB_OTG_DOEPINT_XFRC_Pos (0U)
  7638. #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
  7639. #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
  7640. #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
  7641. #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
  7642. #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
  7643. #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
  7644. #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
  7645. #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
  7646. #define USB_OTG_DOEPINT_STUP_Pos (3U)
  7647. #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
  7648. #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
  7649. #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
  7650. #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
  7651. #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
  7652. #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
  7653. #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
  7654. #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
  7655. #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
  7656. #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
  7657. #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
  7658. #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
  7659. #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
  7660. #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
  7661. #define USB_OTG_DOEPINT_NAK_Pos (13U)
  7662. #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
  7663. #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
  7664. #define USB_OTG_DOEPINT_NYET_Pos (14U)
  7665. #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
  7666. #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
  7667. #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
  7668. #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
  7669. #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
  7670. /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
  7671. #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
  7672. #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
  7673. #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
  7674. #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
  7675. #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
  7676. #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
  7677. #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
  7678. #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
  7679. #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
  7680. #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
  7681. #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
  7682. /******************** Bit definition for PCGCCTL register ********************/
  7683. #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
  7684. #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
  7685. #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
  7686. #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
  7687. #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
  7688. #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
  7689. #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
  7690. #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
  7691. #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
  7692. /* Legacy define */
  7693. /******************** Bit definition for OTG register ********************/
  7694. #define USB_OTG_CHNUM_Pos (0U)
  7695. #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
  7696. #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
  7697. #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
  7698. #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
  7699. #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
  7700. #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
  7701. #define USB_OTG_BCNT_Pos (4U)
  7702. #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
  7703. #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
  7704. #define USB_OTG_DPID_Pos (15U)
  7705. #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
  7706. #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
  7707. #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
  7708. #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
  7709. #define USB_OTG_PKTSTS_Pos (17U)
  7710. #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
  7711. #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
  7712. #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
  7713. #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
  7714. #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
  7715. #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
  7716. #define USB_OTG_EPNUM_Pos (0U)
  7717. #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
  7718. #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
  7719. #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
  7720. #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
  7721. #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
  7722. #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
  7723. #define USB_OTG_FRMNUM_Pos (21U)
  7724. #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
  7725. #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
  7726. #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
  7727. #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
  7728. #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
  7729. #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
  7730. /**
  7731. * @}
  7732. */
  7733. /**
  7734. * @}
  7735. */
  7736. /** @addtogroup Exported_macros
  7737. * @{
  7738. */
  7739. /******************************* ADC Instances ********************************/
  7740. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  7741. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
  7742. /******************************* CRC Instances ********************************/
  7743. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  7744. /******************************** DMA Instances *******************************/
  7745. #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
  7746. ((INSTANCE) == DMA1_Stream1) || \
  7747. ((INSTANCE) == DMA1_Stream2) || \
  7748. ((INSTANCE) == DMA1_Stream3) || \
  7749. ((INSTANCE) == DMA1_Stream4) || \
  7750. ((INSTANCE) == DMA1_Stream5) || \
  7751. ((INSTANCE) == DMA1_Stream6) || \
  7752. ((INSTANCE) == DMA1_Stream7) || \
  7753. ((INSTANCE) == DMA2_Stream0) || \
  7754. ((INSTANCE) == DMA2_Stream1) || \
  7755. ((INSTANCE) == DMA2_Stream2) || \
  7756. ((INSTANCE) == DMA2_Stream3) || \
  7757. ((INSTANCE) == DMA2_Stream4) || \
  7758. ((INSTANCE) == DMA2_Stream5) || \
  7759. ((INSTANCE) == DMA2_Stream6) || \
  7760. ((INSTANCE) == DMA2_Stream7))
  7761. /******************************* GPIO Instances *******************************/
  7762. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  7763. ((INSTANCE) == GPIOB) || \
  7764. ((INSTANCE) == GPIOC) || \
  7765. ((INSTANCE) == GPIOD) || \
  7766. ((INSTANCE) == GPIOE) || \
  7767. ((INSTANCE) == GPIOH))
  7768. /******************************** I2C Instances *******************************/
  7769. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  7770. ((INSTANCE) == I2C2) || \
  7771. ((INSTANCE) == I2C3))
  7772. /******************************* SMBUS Instances ******************************/
  7773. #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
  7774. /******************************** I2S Instances *******************************/
  7775. #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
  7776. ((INSTANCE) == SPI3))
  7777. /*************************** I2S Extended Instances ***************************/
  7778. #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
  7779. ((INSTANCE) == I2S3ext))
  7780. /* Legacy Defines */
  7781. #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
  7782. /****************************** RTC Instances *********************************/
  7783. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  7784. /******************************** SPI Instances *******************************/
  7785. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  7786. ((INSTANCE) == SPI2) || \
  7787. ((INSTANCE) == SPI3) || \
  7788. ((INSTANCE) == SPI4))
  7789. /****************** TIM Instances : All supported instances *******************/
  7790. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7791. ((INSTANCE) == TIM2) || \
  7792. ((INSTANCE) == TIM3) || \
  7793. ((INSTANCE) == TIM4) || \
  7794. ((INSTANCE) == TIM5) || \
  7795. ((INSTANCE) == TIM9) || \
  7796. ((INSTANCE) == TIM10) || \
  7797. ((INSTANCE) == TIM11))
  7798. /************* TIM Instances : at least 1 capture/compare channel *************/
  7799. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7800. ((INSTANCE) == TIM2) || \
  7801. ((INSTANCE) == TIM3) || \
  7802. ((INSTANCE) == TIM4) || \
  7803. ((INSTANCE) == TIM5) || \
  7804. ((INSTANCE) == TIM9) || \
  7805. ((INSTANCE) == TIM10) || \
  7806. ((INSTANCE) == TIM11))
  7807. /************ TIM Instances : at least 2 capture/compare channels *************/
  7808. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7809. ((INSTANCE) == TIM2) || \
  7810. ((INSTANCE) == TIM3) || \
  7811. ((INSTANCE) == TIM4) || \
  7812. ((INSTANCE) == TIM5) || \
  7813. ((INSTANCE) == TIM9))
  7814. /************ TIM Instances : at least 3 capture/compare channels *************/
  7815. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7816. ((INSTANCE) == TIM2) || \
  7817. ((INSTANCE) == TIM3) || \
  7818. ((INSTANCE) == TIM4) || \
  7819. ((INSTANCE) == TIM5))
  7820. /************ TIM Instances : at least 4 capture/compare channels *************/
  7821. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7822. ((INSTANCE) == TIM2) || \
  7823. ((INSTANCE) == TIM3) || \
  7824. ((INSTANCE) == TIM4) || \
  7825. ((INSTANCE) == TIM5))
  7826. /******************** TIM Instances : Advanced-control timers *****************/
  7827. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7828. /******************* TIM Instances : Timer input XOR function *****************/
  7829. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7830. ((INSTANCE) == TIM2) || \
  7831. ((INSTANCE) == TIM3) || \
  7832. ((INSTANCE) == TIM4) || \
  7833. ((INSTANCE) == TIM5))
  7834. /****************** TIM Instances : DMA requests generation (UDE) *************/
  7835. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7836. ((INSTANCE) == TIM2) || \
  7837. ((INSTANCE) == TIM3) || \
  7838. ((INSTANCE) == TIM4) || \
  7839. ((INSTANCE) == TIM5))
  7840. /************ TIM Instances : DMA requests generation (CCxDE) *****************/
  7841. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7842. ((INSTANCE) == TIM2) || \
  7843. ((INSTANCE) == TIM3) || \
  7844. ((INSTANCE) == TIM4) || \
  7845. ((INSTANCE) == TIM5))
  7846. /************ TIM Instances : DMA requests generation (COMDE) *****************/
  7847. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7848. ((INSTANCE) == TIM2) || \
  7849. ((INSTANCE) == TIM3) || \
  7850. ((INSTANCE) == TIM4) || \
  7851. ((INSTANCE) == TIM5))
  7852. /******************** TIM Instances : DMA burst feature ***********************/
  7853. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7854. ((INSTANCE) == TIM2) || \
  7855. ((INSTANCE) == TIM3) || \
  7856. ((INSTANCE) == TIM4) || \
  7857. ((INSTANCE) == TIM5))
  7858. /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
  7859. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7860. ((INSTANCE) == TIM2) || \
  7861. ((INSTANCE) == TIM3) || \
  7862. ((INSTANCE) == TIM4) || \
  7863. ((INSTANCE) == TIM5))
  7864. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  7865. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7866. ((INSTANCE) == TIM2) || \
  7867. ((INSTANCE) == TIM3) || \
  7868. ((INSTANCE) == TIM4) || \
  7869. ((INSTANCE) == TIM5) || \
  7870. ((INSTANCE) == TIM9))
  7871. /****************** TIM Instances : supporting synchronization ****************/
  7872. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  7873. /********************** TIM Instances : 32 bit Counter ************************/
  7874. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
  7875. ((INSTANCE) == TIM5))
  7876. /***************** TIM Instances : external trigger input availabe ************/
  7877. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7878. ((INSTANCE) == TIM2) || \
  7879. ((INSTANCE) == TIM3) || \
  7880. ((INSTANCE) == TIM4) || \
  7881. ((INSTANCE) == TIM5))
  7882. /****************** TIM Instances : remapping capability **********************/
  7883. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
  7884. ((INSTANCE) == TIM5) || \
  7885. ((INSTANCE) == TIM11))
  7886. /******************* TIM Instances : output(s) available **********************/
  7887. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  7888. ((((INSTANCE) == TIM1) && \
  7889. (((CHANNEL) == TIM_CHANNEL_1) || \
  7890. ((CHANNEL) == TIM_CHANNEL_2) || \
  7891. ((CHANNEL) == TIM_CHANNEL_3) || \
  7892. ((CHANNEL) == TIM_CHANNEL_4))) \
  7893. || \
  7894. (((INSTANCE) == TIM2) && \
  7895. (((CHANNEL) == TIM_CHANNEL_1) || \
  7896. ((CHANNEL) == TIM_CHANNEL_2) || \
  7897. ((CHANNEL) == TIM_CHANNEL_3) || \
  7898. ((CHANNEL) == TIM_CHANNEL_4))) \
  7899. || \
  7900. (((INSTANCE) == TIM3) && \
  7901. (((CHANNEL) == TIM_CHANNEL_1) || \
  7902. ((CHANNEL) == TIM_CHANNEL_2) || \
  7903. ((CHANNEL) == TIM_CHANNEL_3) || \
  7904. ((CHANNEL) == TIM_CHANNEL_4))) \
  7905. || \
  7906. (((INSTANCE) == TIM4) && \
  7907. (((CHANNEL) == TIM_CHANNEL_1) || \
  7908. ((CHANNEL) == TIM_CHANNEL_2) || \
  7909. ((CHANNEL) == TIM_CHANNEL_3) || \
  7910. ((CHANNEL) == TIM_CHANNEL_4))) \
  7911. || \
  7912. (((INSTANCE) == TIM5) && \
  7913. (((CHANNEL) == TIM_CHANNEL_1) || \
  7914. ((CHANNEL) == TIM_CHANNEL_2) || \
  7915. ((CHANNEL) == TIM_CHANNEL_3) || \
  7916. ((CHANNEL) == TIM_CHANNEL_4))) \
  7917. || \
  7918. (((INSTANCE) == TIM9) && \
  7919. (((CHANNEL) == TIM_CHANNEL_1) || \
  7920. ((CHANNEL) == TIM_CHANNEL_2))) \
  7921. || \
  7922. (((INSTANCE) == TIM10) && \
  7923. (((CHANNEL) == TIM_CHANNEL_1))) \
  7924. || \
  7925. (((INSTANCE) == TIM11) && \
  7926. (((CHANNEL) == TIM_CHANNEL_1))))
  7927. /************ TIM Instances : complementary output(s) available ***************/
  7928. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  7929. ((((INSTANCE) == TIM1) && \
  7930. (((CHANNEL) == TIM_CHANNEL_1) || \
  7931. ((CHANNEL) == TIM_CHANNEL_2) || \
  7932. ((CHANNEL) == TIM_CHANNEL_3))))
  7933. /****************** TIM Instances : supporting counting mode selection ********/
  7934. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7935. ((INSTANCE) == TIM2) || \
  7936. ((INSTANCE) == TIM3) || \
  7937. ((INSTANCE) == TIM4) || \
  7938. ((INSTANCE) == TIM5))
  7939. /****************** TIM Instances : supporting clock division *****************/
  7940. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7941. ((INSTANCE) == TIM2) || \
  7942. ((INSTANCE) == TIM3) || \
  7943. ((INSTANCE) == TIM4) || \
  7944. ((INSTANCE) == TIM5) || \
  7945. ((INSTANCE) == TIM9) || \
  7946. ((INSTANCE) == TIM10) || \
  7947. ((INSTANCE) == TIM11))
  7948. /****************** TIM Instances : supporting commutation event generation ***/
  7949. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7950. /****************** TIM Instances : supporting OCxREF clear *******************/
  7951. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7952. ((INSTANCE) == TIM2) || \
  7953. ((INSTANCE) == TIM3) || \
  7954. ((INSTANCE) == TIM4) || \
  7955. ((INSTANCE) == TIM5))
  7956. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  7957. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7958. ((INSTANCE) == TIM2) || \
  7959. ((INSTANCE) == TIM3) || \
  7960. ((INSTANCE) == TIM4) || \
  7961. ((INSTANCE) == TIM5) || \
  7962. ((INSTANCE) == TIM9))
  7963. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  7964. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
  7965. ((INSTANCE) == TIM2) || \
  7966. ((INSTANCE) == TIM3) || \
  7967. ((INSTANCE) == TIM4) || \
  7968. ((INSTANCE) == TIM5))
  7969. /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
  7970. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7971. ((INSTANCE) == TIM2) || \
  7972. ((INSTANCE) == TIM3) || \
  7973. ((INSTANCE) == TIM4) || \
  7974. ((INSTANCE) == TIM5) || \
  7975. ((INSTANCE) == TIM9))
  7976. /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
  7977. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7978. ((INSTANCE) == TIM2) || \
  7979. ((INSTANCE) == TIM3) || \
  7980. ((INSTANCE) == TIM4) || \
  7981. ((INSTANCE) == TIM5) || \
  7982. ((INSTANCE) == TIM9))
  7983. /****************** TIM Instances : supporting repetition counter *************/
  7984. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  7985. /****************** TIM Instances : supporting encoder interface **************/
  7986. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7987. ((INSTANCE) == TIM2) || \
  7988. ((INSTANCE) == TIM3) || \
  7989. ((INSTANCE) == TIM4) || \
  7990. ((INSTANCE) == TIM5) || \
  7991. ((INSTANCE) == TIM9))
  7992. /****************** TIM Instances : supporting Hall sensor interface **********/
  7993. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7994. ((INSTANCE) == TIM2) || \
  7995. ((INSTANCE) == TIM3) || \
  7996. ((INSTANCE) == TIM4) || \
  7997. ((INSTANCE) == TIM5))
  7998. /****************** TIM Instances : supporting the break function *************/
  7999. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  8000. /******************** USART Instances : Synchronous mode **********************/
  8001. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  8002. ((INSTANCE) == USART2) || \
  8003. ((INSTANCE) == USART6))
  8004. /******************** UART Instances : Half-Duplex mode **********************/
  8005. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  8006. ((INSTANCE) == USART2) || \
  8007. ((INSTANCE) == USART6))
  8008. /* Legacy defines */
  8009. #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  8010. /****************** UART Instances : Hardware Flow control ********************/
  8011. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  8012. ((INSTANCE) == USART2) || \
  8013. ((INSTANCE) == USART6))
  8014. /******************** UART Instances : LIN mode **********************/
  8015. #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
  8016. /********************* UART Instances : Smart card mode ***********************/
  8017. #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  8018. ((INSTANCE) == USART2) || \
  8019. ((INSTANCE) == USART6))
  8020. /*********************** UART Instances : IRDA mode ***************************/
  8021. #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  8022. ((INSTANCE) == USART2) || \
  8023. ((INSTANCE) == USART6))
  8024. /*********************** PCD Instances ****************************************/
  8025. #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
  8026. /*********************** HCD Instances ****************************************/
  8027. #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
  8028. /****************************** SDIO Instances ********************************/
  8029. #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
  8030. /****************************** IWDG Instances ********************************/
  8031. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  8032. /****************************** WWDG Instances ********************************/
  8033. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  8034. /****************************** USB Exported Constants ************************/
  8035. #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
  8036. #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
  8037. #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
  8038. #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
  8039. /*
  8040. * @brief Specific devices reset values definitions
  8041. */
  8042. #define RCC_PLLCFGR_RST_VALUE 0x24003010U
  8043. #define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
  8044. #define RCC_MAX_FREQUENCY 84000000U /*!< Max frequency of family in Hz*/
  8045. #define RCC_MAX_FREQUENCY_SCALE3 60000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
  8046. #define RCC_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale2, in Hz */
  8047. #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
  8048. #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
  8049. #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
  8050. #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
  8051. #define RCC_PLLN_MIN_VALUE 192U
  8052. #define RCC_PLLN_MAX_VALUE 432U
  8053. #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  8054. #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  8055. #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
  8056. #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
  8057. /**
  8058. * @}
  8059. */
  8060. /**
  8061. * @}
  8062. */
  8063. /**
  8064. * @}
  8065. */
  8066. #ifdef __cplusplus
  8067. }
  8068. #endif /* __cplusplus */
  8069. #endif /* __STM32F401xC_H */
  8070. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/