ARM GAS /tmp/ccQh497L.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f4xx_hal_pwr.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .section .text.HAL_PWR_DeInit,"ax",%progbits 20 .align 1 21 .global HAL_PWR_DeInit 22 .syntax unified 23 .thumb 24 .thumb_func 26 HAL_PWR_DeInit: 27 .LFB130: 28 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @file stm32f4xx_hal_pwr.c 4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @author MCD Application Team 5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver. 6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: 8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Peripheral Control functions 10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @attention 13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *

© Copyright (c) 2017 STMicroelectronics. 15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * All rights reserved.

16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, 18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the 19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * License. You may obtain a copy of the License at: 20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause 21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ 26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #include "stm32f4xx_hal.h" 27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup STM32F4xx_HAL_Driver 29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ ARM GAS /tmp/ccQh497L.s page 2 31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR PWR 33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver 34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED 38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ 40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ 41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants 42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U 49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U 50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U 51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U 52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ 60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ 61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ 62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ 63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions 65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions 70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### 74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data 77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted 78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** write accesses. 79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: 80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the 81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. 82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS /tmp/ccQh497L.s page 3 88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. 90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DeInit(void) 93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 29 .loc 1 93 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 @ link register save eliminated. 94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); 34 .loc 1 94 3 view .LVU1 35 0000 044B ldr r3, .L2 36 0002 1A6A ldr r2, [r3, #32] 37 0004 42F08052 orr r2, r2, #268435456 38 0008 1A62 str r2, [r3, #32] 95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); 39 .loc 1 95 3 view .LVU2 40 000a 1A6A ldr r2, [r3, #32] 41 000c 22F08052 bic r2, r2, #268435456 42 0010 1A62 str r2, [r3, #32] 96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 43 .loc 1 96 1 is_stmt 0 view .LVU3 44 0012 7047 bx lr 45 .L3: 46 .align 2 47 .L2: 48 0014 00380240 .word 1073887232 49 .cfi_endproc 50 .LFE130: 52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits 53 .align 1 54 .global HAL_PWR_EnableBkUpAccess 55 .syntax unified 56 .thumb 57 .thumb_func 59 HAL_PWR_EnableBkUpAccess: 60 .LFB131: 97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 61 .loc 1 106 1 is_stmt 1 view -0 62 .cfi_startproc 63 @ args = 0, pretend = 0, frame = 0 64 @ frame_needed = 0, uses_anonymous_args = 0 65 @ link register save eliminated. 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 66 .loc 1 107 3 view .LVU5 67 .loc 1 107 32 is_stmt 0 view .LVU6 ARM GAS /tmp/ccQh497L.s page 4 68 0000 014B ldr r3, .L5 69 0002 0122 movs r2, #1 70 0004 1A62 str r2, [r3, #32] 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 71 .loc 1 108 1 view .LVU7 72 0006 7047 bx lr 73 .L6: 74 .align 2 75 .L5: 76 0008 00000E42 .word 1108213760 77 .cfi_endproc 78 .LFE131: 80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits 81 .align 1 82 .global HAL_PWR_DisableBkUpAccess 83 .syntax unified 84 .thumb 85 .thumb_func 87 HAL_PWR_DisableBkUpAccess: 88 .LFB132: 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 89 .loc 1 118 1 is_stmt 1 view -0 90 .cfi_startproc 91 @ args = 0, pretend = 0, frame = 0 92 @ frame_needed = 0, uses_anonymous_args = 0 93 @ link register save eliminated. 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; 94 .loc 1 119 3 view .LVU9 95 .loc 1 119 32 is_stmt 0 view .LVU10 96 0000 014B ldr r3, .L8 97 0002 0022 movs r2, #0 98 0004 1A62 str r2, [r3, #32] 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 99 .loc 1 120 1 view .LVU11 100 0006 7047 bx lr 101 .L9: 102 .align 2 103 .L8: 104 0008 00000E42 .word 1108213760 105 .cfi_endproc 106 .LFE132: 108 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits 109 .align 1 110 .global HAL_PWR_ConfigPVD 111 .syntax unified 112 .thumb 113 .thumb_func 115 HAL_PWR_ConfigPVD: ARM GAS /tmp/ccQh497L.s page 5 116 .LVL0: 117 .LFB133: 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Low Power modes configuration functions 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Peripheral Control functions ##### 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** PVD configuration *** 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ========================= 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Wake-up pin configuration *** 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================================ 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Low Power modes configuration *** 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ===================================== 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The devices feature 3 low-power modes: 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** in low power mode 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off. 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Sleep mode *** 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================== 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** functions with 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32F4 family 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** lower power families (STM32L). ARM GAS /tmp/ccQh497L.s page 6 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Stop mode *** 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================= 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** are preserved. 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To minimize the consumption In Stop mode, FLASH can be powered off before 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** It can be switched on again by software after exiting the Stop mode using 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** function with: 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Main regulator ON. 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Low Power regulator ON. 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Standby mode *** 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ==================== 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** circuitry. 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator is OFF. 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Entry: 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Exit: 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Auto-wake-up (AWU) from low-power mode *** 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ============================================= 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Wake-up event, a tamper event or a time-stamp event, without depending on 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** an external interrupt (Auto-wake-up mode). 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) RTC auto-wake-up (AWU) from the Stop and Standby modes 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it ARM GAS /tmp/ccQh497L.s page 7 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTime 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * information for the PVD. 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * detection level. 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 118 .loc 1 253 1 is_stmt 1 view -0 119 .cfi_startproc 120 @ args = 0, pretend = 0, frame = 0 121 @ frame_needed = 0, uses_anonymous_args = 0 122 @ link register save eliminated. 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 123 .loc 1 255 3 view .LVU13 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 124 .loc 1 256 3 view .LVU14 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 125 .loc 1 259 3 view .LVU15 126 0000 1E4A ldr r2, .L15 127 0002 1368 ldr r3, [r2] 128 0004 23F0E003 bic r3, r3, #224 129 0008 0168 ldr r1, [r0] 130 000a 0B43 orrs r3, r3, r1 131 000c 1360 str r3, [r2] 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 132 .loc 1 262 3 view .LVU16 133 000e 1C4B ldr r3, .L15+4 134 0010 5A68 ldr r2, [r3, #4] 135 0012 22F48032 bic r2, r2, #65536 136 0016 5A60 str r2, [r3, #4] 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); 137 .loc 1 263 3 view .LVU17 138 0018 1A68 ldr r2, [r3] 139 001a 22F48032 bic r2, r2, #65536 140 001e 1A60 str r2, [r3] 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 141 .loc 1 264 3 view .LVU18 142 0020 9A68 ldr r2, [r3, #8] ARM GAS /tmp/ccQh497L.s page 8 143 0022 22F48032 bic r2, r2, #65536 144 0026 9A60 str r2, [r3, #8] 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 145 .loc 1 265 3 view .LVU19 146 0028 DA68 ldr r2, [r3, #12] 147 002a 22F48032 bic r2, r2, #65536 148 002e DA60 str r2, [r3, #12] 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure interrupt mode */ 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 149 .loc 1 268 3 view .LVU20 150 .loc 1 268 17 is_stmt 0 view .LVU21 151 0030 4368 ldr r3, [r0, #4] 152 .loc 1 268 5 view .LVU22 153 0032 13F4803F tst r3, #65536 154 0036 04D0 beq .L11 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); 155 .loc 1 270 5 is_stmt 1 view .LVU23 156 0038 114A ldr r2, .L15+4 157 003a 1368 ldr r3, [r2] 158 003c 43F48033 orr r3, r3, #65536 159 0040 1360 str r3, [r2] 160 .L11: 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure event mode */ 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 161 .loc 1 274 3 view .LVU24 162 .loc 1 274 17 is_stmt 0 view .LVU25 163 0042 4368 ldr r3, [r0, #4] 164 .loc 1 274 5 view .LVU26 165 0044 13F4003F tst r3, #131072 166 0048 04D0 beq .L12 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 167 .loc 1 276 5 is_stmt 1 view .LVU27 168 004a 0D4A ldr r2, .L15+4 169 004c 5368 ldr r3, [r2, #4] 170 004e 43F48033 orr r3, r3, #65536 171 0052 5360 str r3, [r2, #4] 172 .L12: 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure the edge */ 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 173 .loc 1 280 3 view .LVU28 174 .loc 1 280 17 is_stmt 0 view .LVU29 175 0054 4368 ldr r3, [r0, #4] 176 .loc 1 280 5 view .LVU30 177 0056 13F0010F tst r3, #1 178 005a 04D0 beq .L13 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 179 .loc 1 282 5 is_stmt 1 view .LVU31 180 005c 084A ldr r2, .L15+4 181 005e 9368 ldr r3, [r2, #8] ARM GAS /tmp/ccQh497L.s page 9 182 0060 43F48033 orr r3, r3, #65536 183 0064 9360 str r3, [r2, #8] 184 .L13: 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 185 .loc 1 285 3 view .LVU32 186 .loc 1 285 17 is_stmt 0 view .LVU33 187 0066 4368 ldr r3, [r0, #4] 188 .loc 1 285 5 view .LVU34 189 0068 13F0020F tst r3, #2 190 006c 04D0 beq .L10 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 191 .loc 1 287 5 is_stmt 1 view .LVU35 192 006e 044A ldr r2, .L15+4 193 0070 D368 ldr r3, [r2, #12] 194 0072 43F48033 orr r3, r3, #65536 195 0076 D360 str r3, [r2, #12] 196 .L10: 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 197 .loc 1 289 1 is_stmt 0 view .LVU36 198 0078 7047 bx lr 199 .L16: 200 007a 00BF .align 2 201 .L15: 202 007c 00700040 .word 1073770496 203 0080 003C0140 .word 1073822720 204 .cfi_endproc 205 .LFE133: 207 .section .text.HAL_PWR_EnablePVD,"ax",%progbits 208 .align 1 209 .global HAL_PWR_EnablePVD 210 .syntax unified 211 .thumb 212 .thumb_func 214 HAL_PWR_EnablePVD: 215 .LFB134: 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 216 .loc 1 296 1 is_stmt 1 view -0 217 .cfi_startproc 218 @ args = 0, pretend = 0, frame = 0 219 @ frame_needed = 0, uses_anonymous_args = 0 220 @ link register save eliminated. 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; 221 .loc 1 297 3 view .LVU38 222 .loc 1 297 33 is_stmt 0 view .LVU39 223 0000 014B ldr r3, .L18 224 0002 0122 movs r2, #1 225 0004 1A61 str r2, [r3, #16] ARM GAS /tmp/ccQh497L.s page 10 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 226 .loc 1 298 1 view .LVU40 227 0006 7047 bx lr 228 .L19: 229 .align 2 230 .L18: 231 0008 00000E42 .word 1108213760 232 .cfi_endproc 233 .LFE134: 235 .section .text.HAL_PWR_DisablePVD,"ax",%progbits 236 .align 1 237 .global HAL_PWR_DisablePVD 238 .syntax unified 239 .thumb 240 .thumb_func 242 HAL_PWR_DisablePVD: 243 .LFB135: 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 244 .loc 1 305 1 is_stmt 1 view -0 245 .cfi_startproc 246 @ args = 0, pretend = 0, frame = 0 247 @ frame_needed = 0, uses_anonymous_args = 0 248 @ link register save eliminated. 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; 249 .loc 1 306 3 view .LVU42 250 .loc 1 306 33 is_stmt 0 view .LVU43 251 0000 014B ldr r3, .L21 252 0002 0022 movs r2, #0 253 0004 1A61 str r2, [r3, #16] 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 254 .loc 1 307 1 view .LVU44 255 0006 7047 bx lr 256 .L22: 257 .align 2 258 .L21: 259 0008 00000E42 .word 1108213760 260 .cfi_endproc 261 .LFE135: 263 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits 264 .align 1 265 .global HAL_PWR_EnableWakeUpPin 266 .syntax unified 267 .thumb 268 .thumb_func 270 HAL_PWR_EnableWakeUpPin: 271 .LVL1: 272 .LFB136: 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Wake-up PINx functionality. 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. ARM GAS /tmp/ccQh497L.s page 11 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 273 .loc 1 319 1 is_stmt 1 view -0 274 .cfi_startproc 275 @ args = 0, pretend = 0, frame = 0 276 @ frame_needed = 0, uses_anonymous_args = 0 277 @ link register save eliminated. 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 278 .loc 1 321 3 view .LVU46 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Enable the wake up pin */ 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); 279 .loc 1 324 3 view .LVU47 280 0000 024A ldr r2, .L24 281 0002 5368 ldr r3, [r2, #4] 282 0004 0343 orrs r3, r3, r0 283 0006 5360 str r3, [r2, #4] 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 284 .loc 1 325 1 is_stmt 0 view .LVU48 285 0008 7047 bx lr 286 .L25: 287 000a 00BF .align 2 288 .L24: 289 000c 00700040 .word 1073770496 290 .cfi_endproc 291 .LFE136: 293 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits 294 .align 1 295 .global HAL_PWR_DisableWakeUpPin 296 .syntax unified 297 .thumb 298 .thumb_func 300 HAL_PWR_DisableWakeUpPin: 301 .LVL2: 302 .LFB137: 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Wake-up PINx functionality. 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 303 .loc 1 337 1 is_stmt 1 view -0 304 .cfi_startproc 305 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccQh497L.s page 12 306 @ frame_needed = 0, uses_anonymous_args = 0 307 @ link register save eliminated. 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 308 .loc 1 339 3 view .LVU50 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Disable the wake up pin */ 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); 309 .loc 1 342 3 view .LVU51 310 0000 024A ldr r2, .L27 311 0002 5368 ldr r3, [r2, #4] 312 0004 23EA0003 bic r3, r3, r0 313 0008 5360 str r3, [r2, #4] 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 314 .loc 1 343 1 is_stmt 0 view .LVU52 315 000a 7047 bx lr 316 .L28: 317 .align 2 318 .L27: 319 000c 00700040 .word 1073770496 320 .cfi_endproc 321 .LFE137: 323 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits 324 .align 1 325 .global HAL_PWR_EnterSLEEPMode 326 .syntax unified 327 .thumb 328 .thumb_func 330 HAL_PWR_EnterSLEEPMode: 331 .LVL3: 332 .LFB138: 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Sleep mode. 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, the systick is stopped to avoid exit from this mode with 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * systick interrupt when used as time base for Timeout 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This parameter is not used for the STM32F4 family and is kept as parameter 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * just to maintain compatibility with the lower power families. 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 333 .loc 1 366 1 is_stmt 1 view -0 334 .cfi_startproc 335 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccQh497L.s page 13 336 @ frame_needed = 0, uses_anonymous_args = 0 337 @ link register save eliminated. 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 338 .loc 1 368 3 view .LVU54 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 339 .loc 1 369 3 view .LVU55 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 340 .loc 1 372 3 view .LVU56 341 0000 064A ldr r2, .L33 342 0002 1369 ldr r3, [r2, #16] 343 0004 23F00403 bic r3, r3, #4 344 0008 1361 str r3, [r2, #16] 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 345 .loc 1 375 3 view .LVU57 346 .loc 1 375 5 is_stmt 0 view .LVU58 347 000a 0129 cmp r1, #1 348 000c 03D0 beq .L32 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 349 .loc 1 383 5 is_stmt 1 view .LVU59 350 .syntax unified 351 @ 383 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 352 000e 40BF sev 353 @ 0 "" 2 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 354 .loc 1 384 5 view .LVU60 355 @ 384 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 356 0010 20BF wfe 357 @ 0 "" 2 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 358 .loc 1 385 5 view .LVU61 359 @ 385 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 360 0012 20BF wfe 361 @ 0 "" 2 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 362 .loc 1 387 1 is_stmt 0 view .LVU62 363 .thumb 364 .syntax unified 365 0014 7047 bx lr 366 .L32: 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 367 .loc 1 378 5 is_stmt 1 view .LVU63 368 .syntax unified 369 @ 378 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 370 0016 30BF wfi ARM GAS /tmp/ccQh497L.s page 14 371 @ 0 "" 2 372 .thumb 373 .syntax unified 374 0018 7047 bx lr 375 .L34: 376 001a 00BF .align 2 377 .L33: 378 001c 00ED00E0 .word -536810240 379 .cfi_endproc 380 .LFE138: 382 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits 383 .align 1 384 .global HAL_PWR_EnterSTOPMode 385 .syntax unified 386 .thumb 387 .thumb_func 389 HAL_PWR_EnterSTOPMode: 390 .LVL4: 391 .LFB139: 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Stop mode. 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * is higher although the startup time is reduced. 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode. 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 392 .loc 1 409 1 view -0 393 .cfi_startproc 394 @ args = 0, pretend = 0, frame = 0 395 @ frame_needed = 0, uses_anonymous_args = 0 396 @ link register save eliminated. 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 397 .loc 1 411 3 view .LVU65 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 398 .loc 1 412 3 view .LVU66 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator val 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); 399 .loc 1 415 3 view .LVU67 400 0000 0B4A ldr r2, .L39 401 0002 1368 ldr r3, [r2] ARM GAS /tmp/ccQh497L.s page 15 402 0004 23F00303 bic r3, r3, #3 403 0008 0343 orrs r3, r3, r0 404 000a 1360 str r3, [r2] 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 405 .loc 1 418 3 view .LVU68 406 000c 094A ldr r2, .L39+4 407 000e 1369 ldr r3, [r2, #16] 408 0010 43F00403 orr r3, r3, #4 409 0014 1361 str r3, [r2, #16] 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) 410 .loc 1 421 3 view .LVU69 411 .loc 1 421 5 is_stmt 0 view .LVU70 412 0016 0129 cmp r1, #1 413 0018 08D0 beq .L38 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 414 .loc 1 429 5 is_stmt 1 view .LVU71 415 .syntax unified 416 @ 429 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 417 001a 40BF sev 418 @ 0 "" 2 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 419 .loc 1 430 5 view .LVU72 420 @ 430 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 421 001c 20BF wfe 422 @ 0 "" 2 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 423 .loc 1 431 5 view .LVU73 424 @ 431 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 425 001e 20BF wfe 426 @ 0 "" 2 427 .thumb 428 .syntax unified 429 .L37: 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 430 .loc 1 434 3 view .LVU74 431 0020 044A ldr r2, .L39+4 432 0022 1369 ldr r3, [r2, #16] 433 0024 23F00403 bic r3, r3, #4 434 0028 1361 str r3, [r2, #16] 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 435 .loc 1 435 1 is_stmt 0 view .LVU75 436 002a 7047 bx lr 437 .L38: 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } ARM GAS /tmp/ccQh497L.s page 16 438 .loc 1 424 5 is_stmt 1 view .LVU76 439 .syntax unified 440 @ 424 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 441 002c 30BF wfi 442 @ 0 "" 2 443 .thumb 444 .syntax unified 445 002e F7E7 b .L37 446 .L40: 447 .align 2 448 .L39: 449 0030 00700040 .word 1073770496 450 0034 00ED00E0 .word -536810240 451 .cfi_endproc 452 .LFE139: 454 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits 455 .align 1 456 .global HAL_PWR_EnterSTANDBYMode 457 .syntax unified 458 .thumb 459 .thumb_func 461 HAL_PWR_EnterSTANDBYMode: 462 .LFB140: 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Standby mode. 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - Reset pad (still available) 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - WKUP pin 1 (PA0) if enabled. 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 463 .loc 1 448 1 view -0 464 .cfi_startproc 465 @ args = 0, pretend = 0, frame = 0 466 @ frame_needed = 0, uses_anonymous_args = 0 467 @ link register save eliminated. 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Standby mode */ 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); 468 .loc 1 450 3 view .LVU78 469 0000 054A ldr r2, .L42 470 0002 1368 ldr r3, [r2] 471 0004 43F00203 orr r3, r3, #2 472 0008 1360 str r3, [r2] 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 473 .loc 1 453 3 view .LVU79 474 000a 044A ldr r2, .L42+4 475 000c 1369 ldr r3, [r2, #16] 476 000e 43F00403 orr r3, r3, #4 477 0012 1361 str r3, [r2, #16] 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS /tmp/ccQh497L.s page 17 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #if defined ( __CC_ARM) 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __force_stores(); 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #endif 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 478 .loc 1 460 3 view .LVU80 479 .syntax unified 480 @ 460 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 481 0014 30BF wfi 482 @ 0 "" 2 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 483 .loc 1 461 1 is_stmt 0 view .LVU81 484 .thumb 485 .syntax unified 486 0016 7047 bx lr 487 .L43: 488 .align 2 489 .L42: 490 0018 00700040 .word 1073770496 491 001c 00ED00E0 .word -536810240 492 .cfi_endproc 493 .LFE140: 495 .section .text.HAL_PWR_PVDCallback,"ax",%progbits 496 .align 1 497 .weak HAL_PWR_PVDCallback 498 .syntax unified 499 .thumb 500 .thumb_func 502 HAL_PWR_PVDCallback: 503 .LFB142: 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_PWR_PVDCallback(); 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 504 .loc 1 486 1 is_stmt 1 view -0 ARM GAS /tmp/ccQh497L.s page 18 505 .cfi_startproc 506 @ args = 0, pretend = 0, frame = 0 507 @ frame_needed = 0, uses_anonymous_args = 0 508 @ link register save eliminated. 487:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, 488:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file 489:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 490:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 509 .loc 1 490 1 view .LVU83 510 0000 7047 bx lr 511 .cfi_endproc 512 .LFE142: 514 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits 515 .align 1 516 .global HAL_PWR_PVD_IRQHandler 517 .syntax unified 518 .thumb 519 .thumb_func 521 HAL_PWR_PVD_IRQHandler: 522 .LFB141: 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 523 .loc 1 469 1 view -0 524 .cfi_startproc 525 @ args = 0, pretend = 0, frame = 0 526 @ frame_needed = 0, uses_anonymous_args = 0 527 0000 08B5 push {r3, lr} 528 .LCFI0: 529 .cfi_def_cfa_offset 8 530 .cfi_offset 3, -8 531 .cfi_offset 14, -4 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 532 .loc 1 471 3 view .LVU85 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 533 .loc 1 471 6 is_stmt 0 view .LVU86 534 0002 064B ldr r3, .L49 535 0004 5B69 ldr r3, [r3, #20] 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 536 .loc 1 471 5 view .LVU87 537 0006 13F4803F tst r3, #65536 538 000a 00D1 bne .L48 539 .L45: 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 540 .loc 1 479 1 view .LVU88 541 000c 08BD pop {r3, pc} 542 .L48: 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 543 .loc 1 474 5 is_stmt 1 view .LVU89 544 000e FFF7FEFF bl HAL_PWR_PVDCallback 545 .LVL5: 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 546 .loc 1 477 5 view .LVU90 547 0012 024B ldr r3, .L49 548 0014 4FF48032 mov r2, #65536 549 0018 5A61 str r2, [r3, #20] 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 550 .loc 1 479 1 is_stmt 0 view .LVU91 551 001a F7E7 b .L45 ARM GAS /tmp/ccQh497L.s page 19 552 .L50: 553 .align 2 554 .L49: 555 001c 003C0140 .word 1073822720 556 .cfi_endproc 557 .LFE141: 559 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits 560 .align 1 561 .global HAL_PWR_EnableSleepOnExit 562 .syntax unified 563 .thumb 564 .thumb_func 566 HAL_PWR_EnableSleepOnExit: 567 .LFB143: 491:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 492:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 493:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 495:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 496:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on 497:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * interruptions handling. 498:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 499:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 500:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) 501:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 568 .loc 1 501 1 is_stmt 1 view -0 569 .cfi_startproc 570 @ args = 0, pretend = 0, frame = 0 571 @ frame_needed = 0, uses_anonymous_args = 0 572 @ link register save eliminated. 502:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ 503:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 573 .loc 1 503 3 view .LVU93 574 0000 024A ldr r2, .L52 575 0002 1369 ldr r3, [r2, #16] 576 0004 43F00203 orr r3, r3, #2 577 0008 1361 str r3, [r2, #16] 504:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 578 .loc 1 504 1 is_stmt 0 view .LVU94 579 000a 7047 bx lr 580 .L53: 581 .align 2 582 .L52: 583 000c 00ED00E0 .word -536810240 584 .cfi_endproc 585 .LFE143: 587 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits 588 .align 1 589 .global HAL_PWR_DisableSleepOnExit 590 .syntax unified 591 .thumb 592 .thumb_func 594 HAL_PWR_DisableSleepOnExit: 595 .LFB144: 505:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 506:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. ARM GAS /tmp/ccQh497L.s page 20 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 511:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) 513:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 596 .loc 1 513 1 is_stmt 1 view -0 597 .cfi_startproc 598 @ args = 0, pretend = 0, frame = 0 599 @ frame_needed = 0, uses_anonymous_args = 0 600 @ link register save eliminated. 514:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 601 .loc 1 515 3 view .LVU96 602 0000 024A ldr r2, .L55 603 0002 1369 ldr r3, [r2, #16] 604 0004 23F00203 bic r3, r3, #2 605 0008 1361 str r3, [r2, #16] 516:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 606 .loc 1 516 1 is_stmt 0 view .LVU97 607 000a 7047 bx lr 608 .L56: 609 .align 2 610 .L55: 611 000c 00ED00E0 .word -536810240 612 .cfi_endproc 613 .LFE144: 615 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits 616 .align 1 617 .global HAL_PWR_EnableSEVOnPend 618 .syntax unified 619 .thumb 620 .thumb_func 622 HAL_PWR_EnableSEVOnPend: 623 .LFB145: 517:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 519:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 521:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 522:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 523:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 524:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) 525:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 624 .loc 1 525 1 is_stmt 1 view -0 625 .cfi_startproc 626 @ args = 0, pretend = 0, frame = 0 627 @ frame_needed = 0, uses_anonymous_args = 0 628 @ link register save eliminated. 526:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ 527:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 629 .loc 1 527 3 view .LVU99 630 0000 024A ldr r2, .L58 631 0002 1369 ldr r3, [r2, #16] 632 0004 43F01003 orr r3, r3, #16 633 0008 1361 str r3, [r2, #16] 528:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } ARM GAS /tmp/ccQh497L.s page 21 634 .loc 1 528 1 is_stmt 0 view .LVU100 635 000a 7047 bx lr 636 .L59: 637 .align 2 638 .L58: 639 000c 00ED00E0 .word -536810240 640 .cfi_endproc 641 .LFE145: 643 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits 644 .align 1 645 .global HAL_PWR_DisableSEVOnPend 646 .syntax unified 647 .thumb 648 .thumb_func 650 HAL_PWR_DisableSEVOnPend: 651 .LFB146: 529:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 530:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 531:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. 532:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 533:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 534:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 535:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 536:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) 537:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 652 .loc 1 537 1 is_stmt 1 view -0 653 .cfi_startproc 654 @ args = 0, pretend = 0, frame = 0 655 @ frame_needed = 0, uses_anonymous_args = 0 656 @ link register save eliminated. 538:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ 539:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 657 .loc 1 539 3 view .LVU102 658 0000 024A ldr r2, .L61 659 0002 1369 ldr r3, [r2, #16] 660 0004 23F01003 bic r3, r3, #16 661 0008 1361 str r3, [r2, #16] 540:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 662 .loc 1 540 1 is_stmt 0 view .LVU103 663 000a 7047 bx lr 664 .L62: 665 .align 2 666 .L61: 667 000c 00ED00E0 .word -536810240 668 .cfi_endproc 669 .LFE146: 671 .text 672 .Letext0: 673 .file 2 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/ 674 .file 3 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/ 675 .file 4 "Drivers/CMSIS/Include/core_cm4.h" 676 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h" 677 .file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 678 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h" ARM GAS /tmp/ccQh497L.s page 22 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f4xx_hal_pwr.c /tmp/ccQh497L.s:20 .text.HAL_PWR_DeInit:0000000000000000 $t /tmp/ccQh497L.s:26 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit /tmp/ccQh497L.s:48 .text.HAL_PWR_DeInit:0000000000000014 $d /tmp/ccQh497L.s:53 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t /tmp/ccQh497L.s:59 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess /tmp/ccQh497L.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000000000008 $d /tmp/ccQh497L.s:81 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t /tmp/ccQh497L.s:87 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess /tmp/ccQh497L.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000000000008 $d /tmp/ccQh497L.s:109 .text.HAL_PWR_ConfigPVD:0000000000000000 $t /tmp/ccQh497L.s:115 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD /tmp/ccQh497L.s:202 .text.HAL_PWR_ConfigPVD:000000000000007c $d /tmp/ccQh497L.s:208 .text.HAL_PWR_EnablePVD:0000000000000000 $t /tmp/ccQh497L.s:214 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD /tmp/ccQh497L.s:231 .text.HAL_PWR_EnablePVD:0000000000000008 $d /tmp/ccQh497L.s:236 .text.HAL_PWR_DisablePVD:0000000000000000 $t /tmp/ccQh497L.s:242 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD /tmp/ccQh497L.s:259 .text.HAL_PWR_DisablePVD:0000000000000008 $d /tmp/ccQh497L.s:264 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t /tmp/ccQh497L.s:270 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin /tmp/ccQh497L.s:289 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d /tmp/ccQh497L.s:294 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t /tmp/ccQh497L.s:300 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin /tmp/ccQh497L.s:319 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d /tmp/ccQh497L.s:324 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t /tmp/ccQh497L.s:330 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode /tmp/ccQh497L.s:378 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d /tmp/ccQh497L.s:383 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t /tmp/ccQh497L.s:389 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode /tmp/ccQh497L.s:449 .text.HAL_PWR_EnterSTOPMode:0000000000000030 $d /tmp/ccQh497L.s:455 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t /tmp/ccQh497L.s:461 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode /tmp/ccQh497L.s:490 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d /tmp/ccQh497L.s:496 .text.HAL_PWR_PVDCallback:0000000000000000 $t /tmp/ccQh497L.s:502 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback /tmp/ccQh497L.s:515 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t /tmp/ccQh497L.s:521 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler /tmp/ccQh497L.s:555 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d /tmp/ccQh497L.s:560 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t /tmp/ccQh497L.s:566 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit /tmp/ccQh497L.s:583 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d /tmp/ccQh497L.s:588 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t /tmp/ccQh497L.s:594 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit /tmp/ccQh497L.s:611 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d /tmp/ccQh497L.s:616 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t /tmp/ccQh497L.s:622 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend /tmp/ccQh497L.s:639 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d /tmp/ccQh497L.s:644 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t /tmp/ccQh497L.s:650 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend /tmp/ccQh497L.s:667 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d NO UNDEFINED SYMBOLS