ARM GAS  /tmp/cc8x624m.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 1
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"system_stm32f4xx.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.SystemInit,"ax",%progbits
  20              		.align	1
  21              		.global	SystemInit
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	SystemInit:
  27              	.LFB130:
  28              		.file 1 "Src/system_stm32f4xx.c"
   1:Src/system_stm32f4xx.c **** /**
   2:Src/system_stm32f4xx.c ****   ******************************************************************************
   3:Src/system_stm32f4xx.c ****   * @file    system_stm32f4xx.c
   4:Src/system_stm32f4xx.c ****   * @author  MCD Application Team
   5:Src/system_stm32f4xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6:Src/system_stm32f4xx.c ****   *
   7:Src/system_stm32f4xx.c ****   *   This file provides two functions and one global variable to be called from 
   8:Src/system_stm32f4xx.c ****   *   user application:
   9:Src/system_stm32f4xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Src/system_stm32f4xx.c ****   *                      before branch to main program. This call is made inside
  11:Src/system_stm32f4xx.c ****   *                      the "startup_stm32f4xx.s" file.
  12:Src/system_stm32f4xx.c ****   *
  13:Src/system_stm32f4xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Src/system_stm32f4xx.c ****   *                                  by the user application to setup the SysTick 
  15:Src/system_stm32f4xx.c ****   *                                  timer or configure other parameters.
  16:Src/system_stm32f4xx.c ****   *                                     
  17:Src/system_stm32f4xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Src/system_stm32f4xx.c ****   *                                 be called whenever the core clock is changed
  19:Src/system_stm32f4xx.c ****   *                                 during program execution.
  20:Src/system_stm32f4xx.c ****   *
  21:Src/system_stm32f4xx.c ****   *
  22:Src/system_stm32f4xx.c ****   ******************************************************************************
  23:Src/system_stm32f4xx.c ****   * @attention
  24:Src/system_stm32f4xx.c ****   *
  25:Src/system_stm32f4xx.c ****   * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  26:Src/system_stm32f4xx.c ****   *
  27:Src/system_stm32f4xx.c ****   * Redistribution and use in source and binary forms, with or without modification,
  28:Src/system_stm32f4xx.c ****   * are permitted provided that the following conditions are met:
  29:Src/system_stm32f4xx.c ****   *   1. Redistributions of source code must retain the above copyright notice,
  30:Src/system_stm32f4xx.c ****   *      this list of conditions and the following disclaimer.
ARM GAS  /tmp/cc8x624m.s 			page 2


  31:Src/system_stm32f4xx.c ****   *   2. Redistributions in binary form must reproduce the above copyright notice,
  32:Src/system_stm32f4xx.c ****   *      this list of conditions and the following disclaimer in the documentation
  33:Src/system_stm32f4xx.c ****   *      and/or other materials provided with the distribution.
  34:Src/system_stm32f4xx.c ****   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  35:Src/system_stm32f4xx.c ****   *      may be used to endorse or promote products derived from this software
  36:Src/system_stm32f4xx.c ****   *      without specific prior written permission.
  37:Src/system_stm32f4xx.c ****   *
  38:Src/system_stm32f4xx.c ****   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  39:Src/system_stm32f4xx.c ****   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  40:Src/system_stm32f4xx.c ****   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  41:Src/system_stm32f4xx.c ****   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  42:Src/system_stm32f4xx.c ****   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  43:Src/system_stm32f4xx.c ****   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  44:Src/system_stm32f4xx.c ****   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  45:Src/system_stm32f4xx.c ****   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  46:Src/system_stm32f4xx.c ****   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47:Src/system_stm32f4xx.c ****   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48:Src/system_stm32f4xx.c ****   *
  49:Src/system_stm32f4xx.c ****   ******************************************************************************
  50:Src/system_stm32f4xx.c ****   */
  51:Src/system_stm32f4xx.c **** 
  52:Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
  53:Src/system_stm32f4xx.c ****   * @{
  54:Src/system_stm32f4xx.c ****   */
  55:Src/system_stm32f4xx.c **** 
  56:Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
  57:Src/system_stm32f4xx.c ****   * @{
  58:Src/system_stm32f4xx.c ****   */  
  59:Src/system_stm32f4xx.c ****   
  60:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
  61:Src/system_stm32f4xx.c ****   * @{
  62:Src/system_stm32f4xx.c ****   */
  63:Src/system_stm32f4xx.c **** 
  64:Src/system_stm32f4xx.c **** 
  65:Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
  66:Src/system_stm32f4xx.c **** 
  67:Src/system_stm32f4xx.c **** #if !defined  (HSE_VALUE) 
  68:Src/system_stm32f4xx.c ****   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
  69:Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
  70:Src/system_stm32f4xx.c **** 
  71:Src/system_stm32f4xx.c **** #if !defined  (HSI_VALUE)
  72:Src/system_stm32f4xx.c ****   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  73:Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
  74:Src/system_stm32f4xx.c **** 
  75:Src/system_stm32f4xx.c **** /**
  76:Src/system_stm32f4xx.c ****   * @}
  77:Src/system_stm32f4xx.c ****   */
  78:Src/system_stm32f4xx.c **** 
  79:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
  80:Src/system_stm32f4xx.c ****   * @{
  81:Src/system_stm32f4xx.c ****   */
  82:Src/system_stm32f4xx.c **** 
  83:Src/system_stm32f4xx.c **** /**
  84:Src/system_stm32f4xx.c ****   * @}
  85:Src/system_stm32f4xx.c ****   */
  86:Src/system_stm32f4xx.c **** 
  87:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
ARM GAS  /tmp/cc8x624m.s 			page 3


  88:Src/system_stm32f4xx.c ****   * @{
  89:Src/system_stm32f4xx.c ****   */
  90:Src/system_stm32f4xx.c **** 
  91:Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
  92:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
  93:Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  94:Src/system_stm32f4xx.c ****  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  95:Src/system_stm32f4xx.c ****  || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
  96:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
  97:Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
  98:Src/system_stm32f4xx.c ****           STM32F412Zx || STM32F412Vx */
  99:Src/system_stm32f4xx.c ****  
 100:Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
 101:Src/system_stm32f4xx.c ****  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 102:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
 103:Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
 104:Src/system_stm32f4xx.c ****           STM32F479xx */
 105:Src/system_stm32f4xx.c **** 
 106:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
 107:Src/system_stm32f4xx.c ****      Internal SRAM. */
 108:Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
 109:Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
 110:Src/system_stm32f4xx.c ****                                    This value must be a multiple of 0x200. */
 111:Src/system_stm32f4xx.c **** /******************************************************************************/
 112:Src/system_stm32f4xx.c **** 
 113:Src/system_stm32f4xx.c **** /**
 114:Src/system_stm32f4xx.c ****   * @}
 115:Src/system_stm32f4xx.c ****   */
 116:Src/system_stm32f4xx.c **** 
 117:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
 118:Src/system_stm32f4xx.c ****   * @{
 119:Src/system_stm32f4xx.c ****   */
 120:Src/system_stm32f4xx.c **** 
 121:Src/system_stm32f4xx.c **** /**
 122:Src/system_stm32f4xx.c ****   * @}
 123:Src/system_stm32f4xx.c ****   */
 124:Src/system_stm32f4xx.c **** 
 125:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
 126:Src/system_stm32f4xx.c ****   * @{
 127:Src/system_stm32f4xx.c ****   */
 128:Src/system_stm32f4xx.c ****   /* This variable is updated in three ways:
 129:Src/system_stm32f4xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 130:Src/system_stm32f4xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 131:Src/system_stm32f4xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
 132:Src/system_stm32f4xx.c ****          Note: If you use this function to configure the system clock; then there
 133:Src/system_stm32f4xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 134:Src/system_stm32f4xx.c ****                variable is updated automatically.
 135:Src/system_stm32f4xx.c ****   */
 136:Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
 137:Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 138:Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 139:Src/system_stm32f4xx.c **** /**
 140:Src/system_stm32f4xx.c ****   * @}
 141:Src/system_stm32f4xx.c ****   */
 142:Src/system_stm32f4xx.c **** 
 143:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 144:Src/system_stm32f4xx.c ****   * @{
ARM GAS  /tmp/cc8x624m.s 			page 4


 145:Src/system_stm32f4xx.c ****   */
 146:Src/system_stm32f4xx.c **** 
 147:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 148:Src/system_stm32f4xx.c ****   static void SystemInit_ExtMemCtl(void); 
 149:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 150:Src/system_stm32f4xx.c **** 
 151:Src/system_stm32f4xx.c **** /**
 152:Src/system_stm32f4xx.c ****   * @}
 153:Src/system_stm32f4xx.c ****   */
 154:Src/system_stm32f4xx.c **** 
 155:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
 156:Src/system_stm32f4xx.c ****   * @{
 157:Src/system_stm32f4xx.c ****   */
 158:Src/system_stm32f4xx.c **** 
 159:Src/system_stm32f4xx.c **** /**
 160:Src/system_stm32f4xx.c ****   * @brief  Setup the microcontroller system
 161:Src/system_stm32f4xx.c ****   *         Initialize the FPU setting, vector table location and External memory 
 162:Src/system_stm32f4xx.c ****   *         configuration.
 163:Src/system_stm32f4xx.c ****   * @param  None
 164:Src/system_stm32f4xx.c ****   * @retval None
 165:Src/system_stm32f4xx.c ****   */
 166:Src/system_stm32f4xx.c **** void SystemInit(void)
 167:Src/system_stm32f4xx.c **** {
  29              		.loc 1 167 1 view -0
  30              		.cfi_startproc
  31              		@ args = 0, pretend = 0, frame = 0
  32              		@ frame_needed = 0, uses_anonymous_args = 0
  33              		@ link register save eliminated.
 168:Src/system_stm32f4xx.c ****   /* FPU settings ------------------------------------------------------------*/
 169:Src/system_stm32f4xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 170:Src/system_stm32f4xx.c ****     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  34              		.loc 1 170 5 view .LVU1
  35              		.loc 1 170 16 is_stmt 0 view .LVU2
  36 0000 0F49     		ldr	r1, .L2
  37 0002 D1F88830 		ldr	r3, [r1, #136]
  38 0006 43F47003 		orr	r3, r3, #15728640
  39 000a C1F88830 		str	r3, [r1, #136]
 171:Src/system_stm32f4xx.c ****   #endif
 172:Src/system_stm32f4xx.c ****   /* Reset the RCC clock configuration to the default reset state ------------*/
 173:Src/system_stm32f4xx.c ****   /* Set HSION bit */
 174:Src/system_stm32f4xx.c ****   RCC->CR |= (uint32_t)0x00000001;
  40              		.loc 1 174 3 is_stmt 1 view .LVU3
  41              		.loc 1 174 11 is_stmt 0 view .LVU4
  42 000e 0D4B     		ldr	r3, .L2+4
  43 0010 1A68     		ldr	r2, [r3]
  44 0012 42F00102 		orr	r2, r2, #1
  45 0016 1A60     		str	r2, [r3]
 175:Src/system_stm32f4xx.c **** 
 176:Src/system_stm32f4xx.c ****   /* Reset CFGR register */
 177:Src/system_stm32f4xx.c ****   RCC->CFGR = 0x00000000;
  46              		.loc 1 177 3 is_stmt 1 view .LVU5
  47              		.loc 1 177 13 is_stmt 0 view .LVU6
  48 0018 0020     		movs	r0, #0
  49 001a 9860     		str	r0, [r3, #8]
 178:Src/system_stm32f4xx.c **** 
 179:Src/system_stm32f4xx.c ****   /* Reset HSEON, CSSON and PLLON bits */
 180:Src/system_stm32f4xx.c ****   RCC->CR &= (uint32_t)0xFEF6FFFF;
ARM GAS  /tmp/cc8x624m.s 			page 5


  50              		.loc 1 180 3 is_stmt 1 view .LVU7
  51              		.loc 1 180 11 is_stmt 0 view .LVU8
  52 001c 1A68     		ldr	r2, [r3]
  53 001e 22F08472 		bic	r2, r2, #17301504
  54 0022 22F48032 		bic	r2, r2, #65536
  55 0026 1A60     		str	r2, [r3]
 181:Src/system_stm32f4xx.c **** 
 182:Src/system_stm32f4xx.c ****   /* Reset PLLCFGR register */
 183:Src/system_stm32f4xx.c ****   RCC->PLLCFGR = 0x24003010;
  56              		.loc 1 183 3 is_stmt 1 view .LVU9
  57              		.loc 1 183 16 is_stmt 0 view .LVU10
  58 0028 074A     		ldr	r2, .L2+8
  59 002a 5A60     		str	r2, [r3, #4]
 184:Src/system_stm32f4xx.c **** 
 185:Src/system_stm32f4xx.c ****   /* Reset HSEBYP bit */
 186:Src/system_stm32f4xx.c ****   RCC->CR &= (uint32_t)0xFFFBFFFF;
  60              		.loc 1 186 3 is_stmt 1 view .LVU11
  61              		.loc 1 186 11 is_stmt 0 view .LVU12
  62 002c 1A68     		ldr	r2, [r3]
  63 002e 22F48022 		bic	r2, r2, #262144
  64 0032 1A60     		str	r2, [r3]
 187:Src/system_stm32f4xx.c **** 
 188:Src/system_stm32f4xx.c ****   /* Disable all interrupts */
 189:Src/system_stm32f4xx.c ****   RCC->CIR = 0x00000000;
  65              		.loc 1 189 3 is_stmt 1 view .LVU13
  66              		.loc 1 189 12 is_stmt 0 view .LVU14
  67 0034 D860     		str	r0, [r3, #12]
 190:Src/system_stm32f4xx.c **** 
 191:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 192:Src/system_stm32f4xx.c ****   SystemInit_ExtMemCtl(); 
 193:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 194:Src/system_stm32f4xx.c **** 
 195:Src/system_stm32f4xx.c ****   /* Configure the Vector Table location add offset address ------------------*/
 196:Src/system_stm32f4xx.c **** #ifdef VECT_TAB_SRAM
 197:Src/system_stm32f4xx.c ****   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 198:Src/system_stm32f4xx.c **** #else
 199:Src/system_stm32f4xx.c ****   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
  68              		.loc 1 199 3 is_stmt 1 view .LVU15
  69              		.loc 1 199 13 is_stmt 0 view .LVU16
  70 0036 4FF00063 		mov	r3, #134217728
  71 003a 8B60     		str	r3, [r1, #8]
 200:Src/system_stm32f4xx.c **** #endif
 201:Src/system_stm32f4xx.c **** }
  72              		.loc 1 201 1 view .LVU17
  73 003c 7047     		bx	lr
  74              	.L3:
  75 003e 00BF     		.align	2
  76              	.L2:
  77 0040 00ED00E0 		.word	-536810240
  78 0044 00380240 		.word	1073887232
  79 0048 10300024 		.word	603992080
  80              		.cfi_endproc
  81              	.LFE130:
  83              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  84              		.align	1
  85              		.global	SystemCoreClockUpdate
  86              		.syntax unified
ARM GAS  /tmp/cc8x624m.s 			page 6


  87              		.thumb
  88              		.thumb_func
  90              	SystemCoreClockUpdate:
  91              	.LFB131:
 202:Src/system_stm32f4xx.c **** 
 203:Src/system_stm32f4xx.c **** /**
 204:Src/system_stm32f4xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 205:Src/system_stm32f4xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 206:Src/system_stm32f4xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 207:Src/system_stm32f4xx.c ****   *         other parameters.
 208:Src/system_stm32f4xx.c ****   *           
 209:Src/system_stm32f4xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 210:Src/system_stm32f4xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 211:Src/system_stm32f4xx.c ****   *         based on this variable will be incorrect.         
 212:Src/system_stm32f4xx.c ****   *     
 213:Src/system_stm32f4xx.c ****   * @note   - The system frequency computed by this function is not the real 
 214:Src/system_stm32f4xx.c ****   *           frequency in the chip. It is calculated based on the predefined 
 215:Src/system_stm32f4xx.c ****   *           constant and the selected clock source:
 216:Src/system_stm32f4xx.c ****   *             
 217:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 218:Src/system_stm32f4xx.c ****   *                                              
 219:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 220:Src/system_stm32f4xx.c ****   *                          
 221:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
 222:Src/system_stm32f4xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 223:Src/system_stm32f4xx.c ****   *         
 224:Src/system_stm32f4xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
 225:Src/system_stm32f4xx.c ****   *             16 MHz) but the real value may vary depending on the variations
 226:Src/system_stm32f4xx.c ****   *             in voltage and temperature.   
 227:Src/system_stm32f4xx.c ****   *    
 228:Src/system_stm32f4xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
 229:Src/system_stm32f4xx.c ****   *              depends on the application requirements), user has to ensure that HSE_VALUE
 230:Src/system_stm32f4xx.c ****   *              is same as the real frequency of the crystal used. Otherwise, this function
 231:Src/system_stm32f4xx.c ****   *              may have wrong result.
 232:Src/system_stm32f4xx.c ****   *                
 233:Src/system_stm32f4xx.c ****   *         - The result of this function could be not correct when using fractional
 234:Src/system_stm32f4xx.c ****   *           value for HSE crystal.
 235:Src/system_stm32f4xx.c ****   *     
 236:Src/system_stm32f4xx.c ****   * @param  None
 237:Src/system_stm32f4xx.c ****   * @retval None
 238:Src/system_stm32f4xx.c ****   */
 239:Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
 240:Src/system_stm32f4xx.c **** {
  92              		.loc 1 240 1 is_stmt 1 view -0
  93              		.cfi_startproc
  94              		@ args = 0, pretend = 0, frame = 0
  95              		@ frame_needed = 0, uses_anonymous_args = 0
  96              		@ link register save eliminated.
 241:Src/system_stm32f4xx.c ****   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
  97              		.loc 1 241 3 view .LVU19
  98              	.LVL0:
 242:Src/system_stm32f4xx.c ****   
 243:Src/system_stm32f4xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 244:Src/system_stm32f4xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
  99              		.loc 1 244 3 view .LVU20
 100              		.loc 1 244 12 is_stmt 0 view .LVU21
 101 0000 224B     		ldr	r3, .L12
ARM GAS  /tmp/cc8x624m.s 			page 7


 102 0002 9B68     		ldr	r3, [r3, #8]
 103              		.loc 1 244 7 view .LVU22
 104 0004 03F00C03 		and	r3, r3, #12
 105              	.LVL1:
 245:Src/system_stm32f4xx.c **** 
 246:Src/system_stm32f4xx.c ****   switch (tmp)
 106              		.loc 1 246 3 is_stmt 1 view .LVU23
 107 0008 042B     		cmp	r3, #4
 108 000a 14D0     		beq	.L5
 109 000c 082B     		cmp	r3, #8
 110 000e 16D0     		beq	.L6
 111 0010 1BB1     		cbz	r3, .L11
 247:Src/system_stm32f4xx.c ****   {
 248:Src/system_stm32f4xx.c ****     case 0x00:  /* HSI used as system clock source */
 249:Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 250:Src/system_stm32f4xx.c ****       break;
 251:Src/system_stm32f4xx.c ****     case 0x04:  /* HSE used as system clock source */
 252:Src/system_stm32f4xx.c ****       SystemCoreClock = HSE_VALUE;
 253:Src/system_stm32f4xx.c ****       break;
 254:Src/system_stm32f4xx.c ****     case 0x08:  /* PLL used as system clock source */
 255:Src/system_stm32f4xx.c **** 
 256:Src/system_stm32f4xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 257:Src/system_stm32f4xx.c ****          SYSCLK = PLL_VCO / PLL_P
 258:Src/system_stm32f4xx.c ****          */    
 259:Src/system_stm32f4xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 260:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 261:Src/system_stm32f4xx.c ****       
 262:Src/system_stm32f4xx.c ****       if (pllsource != 0)
 263:Src/system_stm32f4xx.c ****       {
 264:Src/system_stm32f4xx.c ****         /* HSE used as PLL clock source */
 265:Src/system_stm32f4xx.c ****         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 266:Src/system_stm32f4xx.c ****       }
 267:Src/system_stm32f4xx.c ****       else
 268:Src/system_stm32f4xx.c ****       {
 269:Src/system_stm32f4xx.c ****         /* HSI used as PLL clock source */
 270:Src/system_stm32f4xx.c ****         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 271:Src/system_stm32f4xx.c ****       }
 272:Src/system_stm32f4xx.c **** 
 273:Src/system_stm32f4xx.c ****       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 274:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 275:Src/system_stm32f4xx.c ****       break;
 276:Src/system_stm32f4xx.c ****     default:
 277:Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 112              		.loc 1 277 7 view .LVU24
 113              		.loc 1 277 23 is_stmt 0 view .LVU25
 114 0012 1F4B     		ldr	r3, .L12+4
 115              	.LVL2:
 116              		.loc 1 277 23 view .LVU26
 117 0014 1F4A     		ldr	r2, .L12+8
 118 0016 1A60     		str	r2, [r3]
 278:Src/system_stm32f4xx.c ****       break;
 119              		.loc 1 278 7 is_stmt 1 view .LVU27
 120 0018 02E0     		b	.L8
 121              	.LVL3:
 122              	.L11:
 249:Src/system_stm32f4xx.c ****       break;
 123              		.loc 1 249 7 view .LVU28
ARM GAS  /tmp/cc8x624m.s 			page 8


 249:Src/system_stm32f4xx.c ****       break;
 124              		.loc 1 249 23 is_stmt 0 view .LVU29
 125 001a 1D4B     		ldr	r3, .L12+4
 126              	.LVL4:
 249:Src/system_stm32f4xx.c ****       break;
 127              		.loc 1 249 23 view .LVU30
 128 001c 1D4A     		ldr	r2, .L12+8
 129 001e 1A60     		str	r2, [r3]
 250:Src/system_stm32f4xx.c ****     case 0x04:  /* HSE used as system clock source */
 130              		.loc 1 250 7 is_stmt 1 view .LVU31
 131              	.LVL5:
 132              	.L8:
 279:Src/system_stm32f4xx.c ****   }
 280:Src/system_stm32f4xx.c ****   /* Compute HCLK frequency --------------------------------------------------*/
 281:Src/system_stm32f4xx.c ****   /* Get HCLK prescaler */
 282:Src/system_stm32f4xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 133              		.loc 1 282 3 view .LVU32
 134              		.loc 1 282 28 is_stmt 0 view .LVU33
 135 0020 1A4B     		ldr	r3, .L12
 136 0022 9B68     		ldr	r3, [r3, #8]
 137              		.loc 1 282 52 view .LVU34
 138 0024 C3F30313 		ubfx	r3, r3, #4, #4
 139              		.loc 1 282 22 view .LVU35
 140 0028 1B4A     		ldr	r2, .L12+12
 141 002a D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
 142              	.LVL6:
 283:Src/system_stm32f4xx.c ****   /* HCLK frequency */
 284:Src/system_stm32f4xx.c ****   SystemCoreClock >>= tmp;
 143              		.loc 1 284 3 is_stmt 1 view .LVU36
 144              		.loc 1 284 19 is_stmt 0 view .LVU37
 145 002c 184A     		ldr	r2, .L12+4
 146 002e 1368     		ldr	r3, [r2]
 147 0030 CB40     		lsrs	r3, r3, r1
 148 0032 1360     		str	r3, [r2]
 285:Src/system_stm32f4xx.c **** }
 149              		.loc 1 285 1 view .LVU38
 150 0034 7047     		bx	lr
 151              	.LVL7:
 152              	.L5:
 252:Src/system_stm32f4xx.c ****       break;
 153              		.loc 1 252 7 is_stmt 1 view .LVU39
 252:Src/system_stm32f4xx.c ****       break;
 154              		.loc 1 252 23 is_stmt 0 view .LVU40
 155 0036 164B     		ldr	r3, .L12+4
 156              	.LVL8:
 252:Src/system_stm32f4xx.c ****       break;
 157              		.loc 1 252 23 view .LVU41
 158 0038 184A     		ldr	r2, .L12+16
 159 003a 1A60     		str	r2, [r3]
 253:Src/system_stm32f4xx.c ****     case 0x08:  /* PLL used as system clock source */
 160              		.loc 1 253 7 is_stmt 1 view .LVU42
 161 003c F0E7     		b	.L8
 162              	.LVL9:
 163              	.L6:
 259:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 164              		.loc 1 259 7 view .LVU43
 259:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
ARM GAS  /tmp/cc8x624m.s 			page 9


 165              		.loc 1 259 23 is_stmt 0 view .LVU44
 166 003e 134B     		ldr	r3, .L12
 167              	.LVL10:
 259:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 168              		.loc 1 259 23 view .LVU45
 169 0040 5968     		ldr	r1, [r3, #4]
 170              	.LVL11:
 260:Src/system_stm32f4xx.c ****       
 171              		.loc 1 260 7 is_stmt 1 view .LVU46
 260:Src/system_stm32f4xx.c ****       
 172              		.loc 1 260 17 is_stmt 0 view .LVU47
 173 0042 5A68     		ldr	r2, [r3, #4]
 260:Src/system_stm32f4xx.c ****       
 174              		.loc 1 260 12 view .LVU48
 175 0044 02F03F02 		and	r2, r2, #63
 176              	.LVL12:
 262:Src/system_stm32f4xx.c ****       {
 177              		.loc 1 262 7 is_stmt 1 view .LVU49
 262:Src/system_stm32f4xx.c ****       {
 178              		.loc 1 262 10 is_stmt 0 view .LVU50
 179 0048 11F4800F 		tst	r1, #4194304
 180 004c 13D0     		beq	.L9
 265:Src/system_stm32f4xx.c ****       }
 181              		.loc 1 265 9 is_stmt 1 view .LVU51
 265:Src/system_stm32f4xx.c ****       }
 182              		.loc 1 265 29 is_stmt 0 view .LVU52
 183 004e 134B     		ldr	r3, .L12+16
 184 0050 B3FBF2F3 		udiv	r3, r3, r2
 265:Src/system_stm32f4xx.c ****       }
 185              		.loc 1 265 44 view .LVU53
 186 0054 0D4A     		ldr	r2, .L12
 187              	.LVL13:
 265:Src/system_stm32f4xx.c ****       }
 188              		.loc 1 265 44 view .LVU54
 189 0056 5268     		ldr	r2, [r2, #4]
 265:Src/system_stm32f4xx.c ****       }
 190              		.loc 1 265 74 view .LVU55
 191 0058 C2F38812 		ubfx	r2, r2, #6, #9
 265:Src/system_stm32f4xx.c ****       }
 192              		.loc 1 265 16 view .LVU56
 193 005c 02FB03F3 		mul	r3, r2, r3
 194              	.LVL14:
 195              	.L10:
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 196              		.loc 1 273 7 is_stmt 1 view .LVU57
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 197              		.loc 1 273 20 is_stmt 0 view .LVU58
 198 0060 0A4A     		ldr	r2, .L12
 199 0062 5268     		ldr	r2, [r2, #4]
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 200              		.loc 1 273 50 view .LVU59
 201 0064 C2F30142 		ubfx	r2, r2, #16, #2
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 202              		.loc 1 273 56 view .LVU60
 203 0068 0132     		adds	r2, r2, #1
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 204              		.loc 1 273 12 view .LVU61
ARM GAS  /tmp/cc8x624m.s 			page 10


 205 006a 5200     		lsls	r2, r2, #1
 206              	.LVL15:
 274:Src/system_stm32f4xx.c ****       break;
 207              		.loc 1 274 7 is_stmt 1 view .LVU62
 274:Src/system_stm32f4xx.c ****       break;
 208              		.loc 1 274 31 is_stmt 0 view .LVU63
 209 006c B3FBF2F3 		udiv	r3, r3, r2
 210              	.LVL16:
 274:Src/system_stm32f4xx.c ****       break;
 211              		.loc 1 274 23 view .LVU64
 212 0070 074A     		ldr	r2, .L12+4
 213              	.LVL17:
 274:Src/system_stm32f4xx.c ****       break;
 214              		.loc 1 274 23 view .LVU65
 215 0072 1360     		str	r3, [r2]
 275:Src/system_stm32f4xx.c ****     default:
 216              		.loc 1 275 7 is_stmt 1 view .LVU66
 217 0074 D4E7     		b	.L8
 218              	.LVL18:
 219              	.L9:
 270:Src/system_stm32f4xx.c ****       }
 220              		.loc 1 270 9 view .LVU67
 270:Src/system_stm32f4xx.c ****       }
 221              		.loc 1 270 29 is_stmt 0 view .LVU68
 222 0076 074B     		ldr	r3, .L12+8
 223 0078 B3FBF2F3 		udiv	r3, r3, r2
 270:Src/system_stm32f4xx.c ****       }
 224              		.loc 1 270 44 view .LVU69
 225 007c 034A     		ldr	r2, .L12
 226              	.LVL19:
 270:Src/system_stm32f4xx.c ****       }
 227              		.loc 1 270 44 view .LVU70
 228 007e 5268     		ldr	r2, [r2, #4]
 270:Src/system_stm32f4xx.c ****       }
 229              		.loc 1 270 74 view .LVU71
 230 0080 C2F38812 		ubfx	r2, r2, #6, #9
 270:Src/system_stm32f4xx.c ****       }
 231              		.loc 1 270 16 view .LVU72
 232 0084 02FB03F3 		mul	r3, r2, r3
 233              	.LVL20:
 270:Src/system_stm32f4xx.c ****       }
 234              		.loc 1 270 16 view .LVU73
 235 0088 EAE7     		b	.L10
 236              	.L13:
 237 008a 00BF     		.align	2
 238              	.L12:
 239 008c 00380240 		.word	1073887232
 240 0090 00000000 		.word	.LANCHOR0
 241 0094 0024F400 		.word	16000000
 242 0098 00000000 		.word	.LANCHOR1
 243 009c 40787D01 		.word	25000000
 244              		.cfi_endproc
 245              	.LFE131:
 247              		.global	APBPrescTable
 248              		.global	AHBPrescTable
 249              		.global	SystemCoreClock
 250              		.section	.data.SystemCoreClock,"aw"
ARM GAS  /tmp/cc8x624m.s 			page 11


 251              		.align	2
 252              		.set	.LANCHOR0,. + 0
 255              	SystemCoreClock:
 256 0000 0024F400 		.word	16000000
 257              		.section	.rodata.AHBPrescTable,"a"
 258              		.align	2
 259              		.set	.LANCHOR1,. + 0
 262              	AHBPrescTable:
 263 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
 263      00000000 
 263      01020304 
 263      06
 264 000d 070809   		.ascii	"\007\010\011"
 265              		.section	.rodata.APBPrescTable,"a"
 266              		.align	2
 269              	APBPrescTable:
 270 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
 270      01020304 
 271              		.text
 272              	.Letext0:
 273              		.file 2 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/
 274              		.file 3 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/
 275              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 276              		.file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
 277              		.file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
ARM GAS  /tmp/cc8x624m.s 			page 12


DEFINED SYMBOLS
                            *ABS*:0000000000000000 system_stm32f4xx.c
     /tmp/cc8x624m.s:20     .text.SystemInit:0000000000000000 $t
     /tmp/cc8x624m.s:26     .text.SystemInit:0000000000000000 SystemInit
     /tmp/cc8x624m.s:77     .text.SystemInit:0000000000000040 $d
     /tmp/cc8x624m.s:84     .text.SystemCoreClockUpdate:0000000000000000 $t
     /tmp/cc8x624m.s:90     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
     /tmp/cc8x624m.s:239    .text.SystemCoreClockUpdate:000000000000008c $d
     /tmp/cc8x624m.s:269    .rodata.APBPrescTable:0000000000000000 APBPrescTable
     /tmp/cc8x624m.s:262    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
     /tmp/cc8x624m.s:255    .data.SystemCoreClock:0000000000000000 SystemCoreClock
     /tmp/cc8x624m.s:251    .data.SystemCoreClock:0000000000000000 $d
     /tmp/cc8x624m.s:258    .rodata.AHBPrescTable:0000000000000000 $d
     /tmp/cc8x624m.s:266    .rodata.APBPrescTable:0000000000000000 $d

NO UNDEFINED SYMBOLS