ARM GAS /tmp/ccPRqU3T.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f4xx_hal_cortex.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits 20 .align 1 21 .global HAL_NVIC_SetPriorityGrouping 22 .syntax unified 23 .thumb 24 .thumb_func 26 HAL_NVIC_SetPriorityGrouping: 27 .LVL0: 28 .LFB130: 29 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c" 1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ****************************************************************************** 3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @file stm32f4xx_hal_cortex.c 4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @author MCD Application Team 5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief CORTEX HAL module driver. 6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * functionalities of the CORTEX: 8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * + Peripheral Control functions 10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @verbatim 12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ##### How to use this driver ##### 14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** 18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** =========================================================== 19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). 21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions. 22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() 24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** function according to the following table. 25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). 27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (#) please refer to programming manual for details in how to configure priority. 28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. ARM GAS /tmp/ccPRqU3T.s page 2 30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. 31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): 33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+@) Lowest preemption priority 34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+@) Lowest sub priority 35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) 36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** 39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ======================================================== 40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** Setup SysTick Timer for time base. 42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which 44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** is a CMSIS function that: 45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. 46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value 0x0F. 47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Resets the SysTick Counter register. 48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. 50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Starts the SysTick Counter. 51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined 55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** inside the stm32f4xx_hal_cortex.h file. 56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the 58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct 60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: 62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF 66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @endverbatim 68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ****************************************************************************** 69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @attention 70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** *

© Copyright (c) 2017 STMicroelectronics. 72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * All rights reserved.

73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, 75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the 76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * License. You may obtain a copy of the License at: 77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause 78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ****************************************************************************** 80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ 83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #include "stm32f4xx_hal.h" 84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @addtogroup STM32F4xx_HAL_Driver 86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @{ ARM GAS /tmp/ccPRqU3T.s page 3 87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX 90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief CORTEX HAL module driver 91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @{ 92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED 95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ 97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ 98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ 99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @{ 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Initialization and Configuration functions 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @verbatim 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** Systick functionalities 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @endverbatim 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @{ 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Sets the priority grouping field (preemption priority and subpriority) 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * using the required unlock sequence. 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length. 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be one of the following values: 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 4 bits for subpriority 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 3 bits for subpriority 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 2 bits for subpriority 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 1 bits for subpriority 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 0 bits for subpriority 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) ARM GAS /tmp/ccPRqU3T.s page 4 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 30 .loc 1 144 1 view -0 31 .cfi_startproc 32 @ args = 0, pretend = 0, frame = 0 33 @ frame_needed = 0, uses_anonymous_args = 0 34 @ link register save eliminated. 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 35 .loc 1 146 3 view .LVU1 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); 36 .loc 1 149 3 view .LVU2 37 .LBB38: 38 .LBI38: 39 .file 2 "Drivers/CMSIS/Include/core_cm4.h" 1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm4.h **** * @file core_cm4.h 3:Drivers/CMSIS/Include/core_cm4.h **** * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm4.h **** * @version V5.0.8 5:Drivers/CMSIS/Include/core_cm4.h **** * @date 04. June 2018 6:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm4.h **** /* 8:Drivers/CMSIS/Include/core_cm4.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm4.h **** * 10:Drivers/CMSIS/Include/core_cm4.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm4.h **** * 12:Drivers/CMSIS/Include/core_cm4.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm4.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm4.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm4.h **** * 16:Drivers/CMSIS/Include/core_cm4.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm4.h **** * 18:Drivers/CMSIS/Include/core_cm4.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm4.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm4.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm4.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm4.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm4.h **** */ 24:Drivers/CMSIS/Include/core_cm4.h **** 25:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm4.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm4.h **** #endif 30:Drivers/CMSIS/Include/core_cm4.h **** 31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC 32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC 33:Drivers/CMSIS/Include/core_cm4.h **** 34:Drivers/CMSIS/Include/core_cm4.h **** #include 35:Drivers/CMSIS/Include/core_cm4.h **** 36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm4.h **** #endif 39:Drivers/CMSIS/Include/core_cm4.h **** 40:Drivers/CMSIS/Include/core_cm4.h **** /** 41:Drivers/CMSIS/Include/core_cm4.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions ARM GAS /tmp/ccPRqU3T.s page 5 42:Drivers/CMSIS/Include/core_cm4.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm4.h **** 44:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm4.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm4.h **** 47:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm4.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm4.h **** 50:Drivers/CMSIS/Include/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm4.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm4.h **** */ 53:Drivers/CMSIS/Include/core_cm4.h **** 54:Drivers/CMSIS/Include/core_cm4.h **** 55:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm4.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm4.h **** /** 59:Drivers/CMSIS/Include/core_cm4.h **** \ingroup Cortex_M4 60:Drivers/CMSIS/Include/core_cm4.h **** @{ 61:Drivers/CMSIS/Include/core_cm4.h **** */ 62:Drivers/CMSIS/Include/core_cm4.h **** 63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm4.h **** 65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */ 66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C 67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C 68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL 70:Drivers/CMSIS/Include/core_cm4.h **** 71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M (4U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm4.h **** 73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm4.h **** */ 76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm4.h **** #else 81:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm4.h **** #endif 84:Drivers/CMSIS/Include/core_cm4.h **** #else 85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm4.h **** #endif 87:Drivers/CMSIS/Include/core_cm4.h **** 88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARM_PCS_VFP 90:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm4.h **** #else 93:Drivers/CMSIS/Include/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm4.h **** #endif 96:Drivers/CMSIS/Include/core_cm4.h **** #else 97:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccPRqU3T.s page 6 99:Drivers/CMSIS/Include/core_cm4.h **** 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm4.h **** #else 105:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm4.h **** #endif 108:Drivers/CMSIS/Include/core_cm4.h **** #else 109:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm4.h **** #endif 111:Drivers/CMSIS/Include/core_cm4.h **** 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm4.h **** #else 117:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm4.h **** #endif 120:Drivers/CMSIS/Include/core_cm4.h **** #else 121:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm4.h **** #endif 123:Drivers/CMSIS/Include/core_cm4.h **** 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm4.h **** #else 129:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm4.h **** #endif 132:Drivers/CMSIS/Include/core_cm4.h **** #else 133:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm4.h **** #endif 135:Drivers/CMSIS/Include/core_cm4.h **** 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm4.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm4.h **** #else 141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm4.h **** #endif 144:Drivers/CMSIS/Include/core_cm4.h **** #else 145:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 146:Drivers/CMSIS/Include/core_cm4.h **** #endif 147:Drivers/CMSIS/Include/core_cm4.h **** 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm4.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm4.h **** #else 153:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccPRqU3T.s page 7 156:Drivers/CMSIS/Include/core_cm4.h **** #else 157:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm4.h **** #endif 159:Drivers/CMSIS/Include/core_cm4.h **** 160:Drivers/CMSIS/Include/core_cm4.h **** #endif 161:Drivers/CMSIS/Include/core_cm4.h **** 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm4.h **** 164:Drivers/CMSIS/Include/core_cm4.h **** 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm4.h **** } 167:Drivers/CMSIS/Include/core_cm4.h **** #endif 168:Drivers/CMSIS/Include/core_cm4.h **** 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm4.h **** 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm4.h **** 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm4.h **** 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm4.h **** #endif 179:Drivers/CMSIS/Include/core_cm4.h **** 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CM4_REV 183:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm4.h **** #endif 186:Drivers/CMSIS/Include/core_cm4.h **** 187:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm4.h **** #endif 191:Drivers/CMSIS/Include/core_cm4.h **** 192:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm4.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm4.h **** #endif 196:Drivers/CMSIS/Include/core_cm4.h **** 197:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __NVIC_PRIO_BITS 198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U 199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm4.h **** #endif 201:Drivers/CMSIS/Include/core_cm4.h **** 202:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __Vendor_SysTickConfig 203:Drivers/CMSIS/Include/core_cm4.h **** #define __Vendor_SysTickConfig 0U 204:Drivers/CMSIS/Include/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm4.h **** #endif 206:Drivers/CMSIS/Include/core_cm4.h **** #endif 207:Drivers/CMSIS/Include/core_cm4.h **** 208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */ 209:Drivers/CMSIS/Include/core_cm4.h **** /** 210:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 211:Drivers/CMSIS/Include/core_cm4.h **** 212:Drivers/CMSIS/Include/core_cm4.h **** IO Type Qualifiers are used ARM GAS /tmp/ccPRqU3T.s page 8 213:Drivers/CMSIS/Include/core_cm4.h **** \li to specify the access to peripheral variables. 214:Drivers/CMSIS/Include/core_cm4.h **** \li for automatic generation of peripheral register debug information. 215:Drivers/CMSIS/Include/core_cm4.h **** */ 216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 217:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */ 218:Drivers/CMSIS/Include/core_cm4.h **** #else 219:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 220:Drivers/CMSIS/Include/core_cm4.h **** #endif 221:Drivers/CMSIS/Include/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */ 222:Drivers/CMSIS/Include/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 223:Drivers/CMSIS/Include/core_cm4.h **** 224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */ 225:Drivers/CMSIS/Include/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 226:Drivers/CMSIS/Include/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 227:Drivers/CMSIS/Include/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 228:Drivers/CMSIS/Include/core_cm4.h **** 229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */ 230:Drivers/CMSIS/Include/core_cm4.h **** 231:Drivers/CMSIS/Include/core_cm4.h **** 232:Drivers/CMSIS/Include/core_cm4.h **** 233:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 234:Drivers/CMSIS/Include/core_cm4.h **** * Register Abstraction 235:Drivers/CMSIS/Include/core_cm4.h **** Core Register contain: 236:Drivers/CMSIS/Include/core_cm4.h **** - Core Register 237:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Register 238:Drivers/CMSIS/Include/core_cm4.h **** - Core SCB Register 239:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Register 240:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Register 241:Drivers/CMSIS/Include/core_cm4.h **** - Core MPU Register 242:Drivers/CMSIS/Include/core_cm4.h **** - Core FPU Register 243:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 244:Drivers/CMSIS/Include/core_cm4.h **** /** 245:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions 246:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices. 247:Drivers/CMSIS/Include/core_cm4.h **** */ 248:Drivers/CMSIS/Include/core_cm4.h **** 249:Drivers/CMSIS/Include/core_cm4.h **** /** 250:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 251:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers 252:Drivers/CMSIS/Include/core_cm4.h **** \brief Core Register type definitions. 253:Drivers/CMSIS/Include/core_cm4.h **** @{ 254:Drivers/CMSIS/Include/core_cm4.h **** */ 255:Drivers/CMSIS/Include/core_cm4.h **** 256:Drivers/CMSIS/Include/core_cm4.h **** /** 257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR). 258:Drivers/CMSIS/Include/core_cm4.h **** */ 259:Drivers/CMSIS/Include/core_cm4.h **** typedef union 260:Drivers/CMSIS/Include/core_cm4.h **** { 261:Drivers/CMSIS/Include/core_cm4.h **** struct 262:Drivers/CMSIS/Include/core_cm4.h **** { 263:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 264:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 265:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 266:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 267:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 268:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 269:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ ARM GAS /tmp/ccPRqU3T.s page 9 270:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 271:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 272:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type; 274:Drivers/CMSIS/Include/core_cm4.h **** 275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */ 276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR 277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 278:Drivers/CMSIS/Include/core_cm4.h **** 279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR 280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 281:Drivers/CMSIS/Include/core_cm4.h **** 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR 283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 284:Drivers/CMSIS/Include/core_cm4.h **** 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR 286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 287:Drivers/CMSIS/Include/core_cm4.h **** 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR 289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 290:Drivers/CMSIS/Include/core_cm4.h **** 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR 292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm4.h **** 294:Drivers/CMSIS/Include/core_cm4.h **** 295:Drivers/CMSIS/Include/core_cm4.h **** /** 296:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 297:Drivers/CMSIS/Include/core_cm4.h **** */ 298:Drivers/CMSIS/Include/core_cm4.h **** typedef union 299:Drivers/CMSIS/Include/core_cm4.h **** { 300:Drivers/CMSIS/Include/core_cm4.h **** struct 301:Drivers/CMSIS/Include/core_cm4.h **** { 302:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 303:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 304:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 305:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type; 307:Drivers/CMSIS/Include/core_cm4.h **** 308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */ 309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 311:Drivers/CMSIS/Include/core_cm4.h **** 312:Drivers/CMSIS/Include/core_cm4.h **** 313:Drivers/CMSIS/Include/core_cm4.h **** /** 314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 315:Drivers/CMSIS/Include/core_cm4.h **** */ 316:Drivers/CMSIS/Include/core_cm4.h **** typedef union 317:Drivers/CMSIS/Include/core_cm4.h **** { 318:Drivers/CMSIS/Include/core_cm4.h **** struct 319:Drivers/CMSIS/Include/core_cm4.h **** { 320:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 322:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 323:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 324:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 325:Drivers/CMSIS/Include/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 326:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ ARM GAS /tmp/ccPRqU3T.s page 10 327:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 328:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 329:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 330:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 331:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 332:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 333:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type; 335:Drivers/CMSIS/Include/core_cm4.h **** 336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */ 337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR 338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 339:Drivers/CMSIS/Include/core_cm4.h **** 340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR 341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 342:Drivers/CMSIS/Include/core_cm4.h **** 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR 344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 345:Drivers/CMSIS/Include/core_cm4.h **** 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR 347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 348:Drivers/CMSIS/Include/core_cm4.h **** 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR 350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 351:Drivers/CMSIS/Include/core_cm4.h **** 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm4.h **** 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm4.h **** 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm4.h **** 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm4.h **** 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm4.h **** 367:Drivers/CMSIS/Include/core_cm4.h **** 368:Drivers/CMSIS/Include/core_cm4.h **** /** 369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL). 370:Drivers/CMSIS/Include/core_cm4.h **** */ 371:Drivers/CMSIS/Include/core_cm4.h **** typedef union 372:Drivers/CMSIS/Include/core_cm4.h **** { 373:Drivers/CMSIS/Include/core_cm4.h **** struct 374:Drivers/CMSIS/Include/core_cm4.h **** { 375:Drivers/CMSIS/Include/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 376:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 377:Drivers/CMSIS/Include/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 378:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 379:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 380:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type; 382:Drivers/CMSIS/Include/core_cm4.h **** 383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */ ARM GAS /tmp/ccPRqU3T.s page 11 384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 386:Drivers/CMSIS/Include/core_cm4.h **** 387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 389:Drivers/CMSIS/Include/core_cm4.h **** 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 392:Drivers/CMSIS/Include/core_cm4.h **** 393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */ 394:Drivers/CMSIS/Include/core_cm4.h **** 395:Drivers/CMSIS/Include/core_cm4.h **** 396:Drivers/CMSIS/Include/core_cm4.h **** /** 397:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 398:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 399:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the NVIC Registers 400:Drivers/CMSIS/Include/core_cm4.h **** @{ 401:Drivers/CMSIS/Include/core_cm4.h **** */ 402:Drivers/CMSIS/Include/core_cm4.h **** 403:Drivers/CMSIS/Include/core_cm4.h **** /** 404:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 405:Drivers/CMSIS/Include/core_cm4.h **** */ 406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 407:Drivers/CMSIS/Include/core_cm4.h **** { 408:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 409:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[24U]; 410:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 411:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RSERVED1[24U]; 412:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 413:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[24U]; 414:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register 415:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[24U]; 416:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 417:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[56U]; 418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 419:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[644U]; 420:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 421:Drivers/CMSIS/Include/core_cm4.h **** } NVIC_Type; 422:Drivers/CMSIS/Include/core_cm4.h **** 423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */ 424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 426:Drivers/CMSIS/Include/core_cm4.h **** 427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */ 428:Drivers/CMSIS/Include/core_cm4.h **** 429:Drivers/CMSIS/Include/core_cm4.h **** 430:Drivers/CMSIS/Include/core_cm4.h **** /** 431:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 432:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB) 433:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control Block Registers 434:Drivers/CMSIS/Include/core_cm4.h **** @{ 435:Drivers/CMSIS/Include/core_cm4.h **** */ 436:Drivers/CMSIS/Include/core_cm4.h **** 437:Drivers/CMSIS/Include/core_cm4.h **** /** 438:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control Block (SCB). 439:Drivers/CMSIS/Include/core_cm4.h **** */ 440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct ARM GAS /tmp/ccPRqU3T.s page 12 441:Drivers/CMSIS/Include/core_cm4.h **** { 442:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 443:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 444:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 445:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 446:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 447:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 448:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 449:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 450:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 451:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 452:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 453:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 454:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 455:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 456:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 457:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 458:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 459:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 460:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 461:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[5U]; 462:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type; 464:Drivers/CMSIS/Include/core_cm4.h **** 465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */ 466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 468:Drivers/CMSIS/Include/core_cm4.h **** 469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 471:Drivers/CMSIS/Include/core_cm4.h **** 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 474:Drivers/CMSIS/Include/core_cm4.h **** 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 477:Drivers/CMSIS/Include/core_cm4.h **** 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 480:Drivers/CMSIS/Include/core_cm4.h **** 481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */ 482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 484:Drivers/CMSIS/Include/core_cm4.h **** 485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 487:Drivers/CMSIS/Include/core_cm4.h **** 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 490:Drivers/CMSIS/Include/core_cm4.h **** 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 493:Drivers/CMSIS/Include/core_cm4.h **** 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 496:Drivers/CMSIS/Include/core_cm4.h **** 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ARM GAS /tmp/ccPRqU3T.s page 13 498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 499:Drivers/CMSIS/Include/core_cm4.h **** 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB 501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 502:Drivers/CMSIS/Include/core_cm4.h **** 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 505:Drivers/CMSIS/Include/core_cm4.h **** 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 508:Drivers/CMSIS/Include/core_cm4.h **** 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 511:Drivers/CMSIS/Include/core_cm4.h **** 512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */ 513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm4.h **** 516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 519:Drivers/CMSIS/Include/core_cm4.h **** 520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 522:Drivers/CMSIS/Include/core_cm4.h **** 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 525:Drivers/CMSIS/Include/core_cm4.h **** 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm4.h **** 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm4.h **** 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm4.h **** 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 537:Drivers/CMSIS/Include/core_cm4.h **** 538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */ 539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 541:Drivers/CMSIS/Include/core_cm4.h **** 542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 544:Drivers/CMSIS/Include/core_cm4.h **** 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 547:Drivers/CMSIS/Include/core_cm4.h **** 548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */ 549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 551:Drivers/CMSIS/Include/core_cm4.h **** 552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 554:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 14 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 557:Drivers/CMSIS/Include/core_cm4.h **** 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 560:Drivers/CMSIS/Include/core_cm4.h **** 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm4.h **** 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 566:Drivers/CMSIS/Include/core_cm4.h **** 567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */ 568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 570:Drivers/CMSIS/Include/core_cm4.h **** 571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 573:Drivers/CMSIS/Include/core_cm4.h **** 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 576:Drivers/CMSIS/Include/core_cm4.h **** 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 579:Drivers/CMSIS/Include/core_cm4.h **** 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 582:Drivers/CMSIS/Include/core_cm4.h **** 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm4.h **** 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm4.h **** 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm4.h **** 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 594:Drivers/CMSIS/Include/core_cm4.h **** 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 597:Drivers/CMSIS/Include/core_cm4.h **** 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB 600:Drivers/CMSIS/Include/core_cm4.h **** 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 603:Drivers/CMSIS/Include/core_cm4.h **** 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB 605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB 606:Drivers/CMSIS/Include/core_cm4.h **** 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 609:Drivers/CMSIS/Include/core_cm4.h **** 610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */ 611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB ARM GAS /tmp/ccPRqU3T.s page 15 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm4.h **** 614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm4.h **** 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm4.h **** 620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm4.h **** 624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm4.h **** 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm4.h **** 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm4.h **** 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm4.h **** 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 638:Drivers/CMSIS/Include/core_cm4.h **** 639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 642:Drivers/CMSIS/Include/core_cm4.h **** 643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 645:Drivers/CMSIS/Include/core_cm4.h **** 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 648:Drivers/CMSIS/Include/core_cm4.h **** 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 651:Drivers/CMSIS/Include/core_cm4.h **** 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 654:Drivers/CMSIS/Include/core_cm4.h **** 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB 657:Drivers/CMSIS/Include/core_cm4.h **** 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 660:Drivers/CMSIS/Include/core_cm4.h **** 661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 664:Drivers/CMSIS/Include/core_cm4.h **** 665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 667:Drivers/CMSIS/Include/core_cm4.h **** 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB ARM GAS /tmp/ccPRqU3T.s page 16 669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 670:Drivers/CMSIS/Include/core_cm4.h **** 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 673:Drivers/CMSIS/Include/core_cm4.h **** 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm4.h **** 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm4.h **** 680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */ 681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 683:Drivers/CMSIS/Include/core_cm4.h **** 684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 686:Drivers/CMSIS/Include/core_cm4.h **** 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 689:Drivers/CMSIS/Include/core_cm4.h **** 690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */ 691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 693:Drivers/CMSIS/Include/core_cm4.h **** 694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 696:Drivers/CMSIS/Include/core_cm4.h **** 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 699:Drivers/CMSIS/Include/core_cm4.h **** 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 702:Drivers/CMSIS/Include/core_cm4.h **** 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 705:Drivers/CMSIS/Include/core_cm4.h **** 706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */ 707:Drivers/CMSIS/Include/core_cm4.h **** 708:Drivers/CMSIS/Include/core_cm4.h **** 709:Drivers/CMSIS/Include/core_cm4.h **** /** 710:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB 713:Drivers/CMSIS/Include/core_cm4.h **** @{ 714:Drivers/CMSIS/Include/core_cm4.h **** */ 715:Drivers/CMSIS/Include/core_cm4.h **** 716:Drivers/CMSIS/Include/core_cm4.h **** /** 717:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 718:Drivers/CMSIS/Include/core_cm4.h **** */ 719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 720:Drivers/CMSIS/Include/core_cm4.h **** { 721:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 722:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 723:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type; 725:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 17 726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */ 727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 729:Drivers/CMSIS/Include/core_cm4.h **** 730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */ 731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: 733:Drivers/CMSIS/Include/core_cm4.h **** 734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: 735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: 736:Drivers/CMSIS/Include/core_cm4.h **** 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: 738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: 739:Drivers/CMSIS/Include/core_cm4.h **** 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: 741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: 742:Drivers/CMSIS/Include/core_cm4.h **** 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 745:Drivers/CMSIS/Include/core_cm4.h **** 746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */ 747:Drivers/CMSIS/Include/core_cm4.h **** 748:Drivers/CMSIS/Include/core_cm4.h **** 749:Drivers/CMSIS/Include/core_cm4.h **** /** 750:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 751:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 752:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Timer Registers. 753:Drivers/CMSIS/Include/core_cm4.h **** @{ 754:Drivers/CMSIS/Include/core_cm4.h **** */ 755:Drivers/CMSIS/Include/core_cm4.h **** 756:Drivers/CMSIS/Include/core_cm4.h **** /** 757:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Timer (SysTick). 758:Drivers/CMSIS/Include/core_cm4.h **** */ 759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 760:Drivers/CMSIS/Include/core_cm4.h **** { 761:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 762:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 763:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 764:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type; 766:Drivers/CMSIS/Include/core_cm4.h **** 767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */ 768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 770:Drivers/CMSIS/Include/core_cm4.h **** 771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 773:Drivers/CMSIS/Include/core_cm4.h **** 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 776:Drivers/CMSIS/Include/core_cm4.h **** 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 779:Drivers/CMSIS/Include/core_cm4.h **** 780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */ 781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT ARM GAS /tmp/ccPRqU3T.s page 18 783:Drivers/CMSIS/Include/core_cm4.h **** 784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */ 785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 787:Drivers/CMSIS/Include/core_cm4.h **** 788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */ 789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 791:Drivers/CMSIS/Include/core_cm4.h **** 792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 794:Drivers/CMSIS/Include/core_cm4.h **** 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 797:Drivers/CMSIS/Include/core_cm4.h **** 798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */ 799:Drivers/CMSIS/Include/core_cm4.h **** 800:Drivers/CMSIS/Include/core_cm4.h **** 801:Drivers/CMSIS/Include/core_cm4.h **** /** 802:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 803:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 804:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 805:Drivers/CMSIS/Include/core_cm4.h **** @{ 806:Drivers/CMSIS/Include/core_cm4.h **** */ 807:Drivers/CMSIS/Include/core_cm4.h **** 808:Drivers/CMSIS/Include/core_cm4.h **** /** 809:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 810:Drivers/CMSIS/Include/core_cm4.h **** */ 811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 812:Drivers/CMSIS/Include/core_cm4.h **** { 813:Drivers/CMSIS/Include/core_cm4.h **** __OM union 814:Drivers/CMSIS/Include/core_cm4.h **** { 815:Drivers/CMSIS/Include/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 816:Drivers/CMSIS/Include/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 817:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 818:Drivers/CMSIS/Include/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 819:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[864U]; 820:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 821:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[15U]; 822:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 823:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[15U]; 824:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[29U]; 826:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * 827:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 828:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg 829:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U]; 830:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 831:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 832:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[6U]; 833:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 834:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 835:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 836:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 837:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 838:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 839:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re ARM GAS /tmp/ccPRqU3T.s page 19 840:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 841:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 842:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 843:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 844:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 845:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type; 846:Drivers/CMSIS/Include/core_cm4.h **** 847:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */ 848:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 850:Drivers/CMSIS/Include/core_cm4.h **** 851:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */ 852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 854:Drivers/CMSIS/Include/core_cm4.h **** 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM 856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 857:Drivers/CMSIS/Include/core_cm4.h **** 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 860:Drivers/CMSIS/Include/core_cm4.h **** 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 863:Drivers/CMSIS/Include/core_cm4.h **** 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 866:Drivers/CMSIS/Include/core_cm4.h **** 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 869:Drivers/CMSIS/Include/core_cm4.h **** 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 872:Drivers/CMSIS/Include/core_cm4.h **** 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 875:Drivers/CMSIS/Include/core_cm4.h **** 876:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 878:Drivers/CMSIS/Include/core_cm4.h **** 879:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Write Register Definitions */ 880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM 881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM 882:Drivers/CMSIS/Include/core_cm4.h **** 883:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Read Register Definitions */ 884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM 885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM 886:Drivers/CMSIS/Include/core_cm4.h **** 887:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */ 888:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM 889:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM 890:Drivers/CMSIS/Include/core_cm4.h **** 891:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */ 892:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 893:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 894:Drivers/CMSIS/Include/core_cm4.h **** 895:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 896:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM ARM GAS /tmp/ccPRqU3T.s page 20 897:Drivers/CMSIS/Include/core_cm4.h **** 898:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 899:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM 900:Drivers/CMSIS/Include/core_cm4.h **** 901:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */ 902:Drivers/CMSIS/Include/core_cm4.h **** 903:Drivers/CMSIS/Include/core_cm4.h **** 904:Drivers/CMSIS/Include/core_cm4.h **** /** 905:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 906:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 907:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 908:Drivers/CMSIS/Include/core_cm4.h **** @{ 909:Drivers/CMSIS/Include/core_cm4.h **** */ 910:Drivers/CMSIS/Include/core_cm4.h **** 911:Drivers/CMSIS/Include/core_cm4.h **** /** 912:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 913:Drivers/CMSIS/Include/core_cm4.h **** */ 914:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 915:Drivers/CMSIS/Include/core_cm4.h **** { 916:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 917:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 918:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 919:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 920:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 921:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 922:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 923:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 924:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 925:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 926:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 927:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 928:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 929:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 930:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 931:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[1U]; 932:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 933:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 934:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 935:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[1U]; 936:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 937:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 938:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 939:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type; 940:Drivers/CMSIS/Include/core_cm4.h **** 941:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */ 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 944:Drivers/CMSIS/Include/core_cm4.h **** 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 947:Drivers/CMSIS/Include/core_cm4.h **** 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 950:Drivers/CMSIS/Include/core_cm4.h **** 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 953:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 21 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 956:Drivers/CMSIS/Include/core_cm4.h **** 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 959:Drivers/CMSIS/Include/core_cm4.h **** 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 962:Drivers/CMSIS/Include/core_cm4.h **** 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 965:Drivers/CMSIS/Include/core_cm4.h **** 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR 967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 968:Drivers/CMSIS/Include/core_cm4.h **** 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 971:Drivers/CMSIS/Include/core_cm4.h **** 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 974:Drivers/CMSIS/Include/core_cm4.h **** 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 977:Drivers/CMSIS/Include/core_cm4.h **** 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 980:Drivers/CMSIS/Include/core_cm4.h **** 981:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 983:Drivers/CMSIS/Include/core_cm4.h **** 984:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 985:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 986:Drivers/CMSIS/Include/core_cm4.h **** 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 988:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 989:Drivers/CMSIS/Include/core_cm4.h **** 990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 992:Drivers/CMSIS/Include/core_cm4.h **** 993:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 995:Drivers/CMSIS/Include/core_cm4.h **** 996:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */ 997:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 999:Drivers/CMSIS/Include/core_cm4.h **** 1000:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */ 1001:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 1003:Drivers/CMSIS/Include/core_cm4.h **** 1004:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */ 1005:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 1007:Drivers/CMSIS/Include/core_cm4.h **** 1008:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */ 1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU ARM GAS /tmp/ccPRqU3T.s page 22 1011:Drivers/CMSIS/Include/core_cm4.h **** 1012:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */ 1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL 1014:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1015:Drivers/CMSIS/Include/core_cm4.h **** 1016:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */ 1017:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1019:Drivers/CMSIS/Include/core_cm4.h **** 1020:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */ 1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN 1023:Drivers/CMSIS/Include/core_cm4.h **** 1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1026:Drivers/CMSIS/Include/core_cm4.h **** 1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1029:Drivers/CMSIS/Include/core_cm4.h **** 1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1032:Drivers/CMSIS/Include/core_cm4.h **** 1033:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1034:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1035:Drivers/CMSIS/Include/core_cm4.h **** 1036:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1037:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1038:Drivers/CMSIS/Include/core_cm4.h **** 1039:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1040:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1041:Drivers/CMSIS/Include/core_cm4.h **** 1042:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1043:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1044:Drivers/CMSIS/Include/core_cm4.h **** 1045:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1046:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1047:Drivers/CMSIS/Include/core_cm4.h **** 1048:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */ 1049:Drivers/CMSIS/Include/core_cm4.h **** 1050:Drivers/CMSIS/Include/core_cm4.h **** 1051:Drivers/CMSIS/Include/core_cm4.h **** /** 1052:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1053:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1054:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI) 1055:Drivers/CMSIS/Include/core_cm4.h **** @{ 1056:Drivers/CMSIS/Include/core_cm4.h **** */ 1057:Drivers/CMSIS/Include/core_cm4.h **** 1058:Drivers/CMSIS/Include/core_cm4.h **** /** 1059:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1060:Drivers/CMSIS/Include/core_cm4.h **** */ 1061:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1062:Drivers/CMSIS/Include/core_cm4.h **** { 1063:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1064:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1065:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[2U]; 1066:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1067:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[55U]; ARM GAS /tmp/ccPRqU3T.s page 23 1068:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1069:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U]; 1070:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis 1071:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1072:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1073:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[759U]; 1074:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1075:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1076:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1077:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[1U]; 1078:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1079:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1080:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1081:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[39U]; 1082:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1083:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1084:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED7[8U]; 1085:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1086:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1087:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type; 1088:Drivers/CMSIS/Include/core_cm4.h **** 1089:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1091:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1092:Drivers/CMSIS/Include/core_cm4.h **** 1093:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */ 1094:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1095:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1096:Drivers/CMSIS/Include/core_cm4.h **** 1097:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */ 1098:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1100:Drivers/CMSIS/Include/core_cm4.h **** 1101:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1102:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1103:Drivers/CMSIS/Include/core_cm4.h **** 1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1105:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1106:Drivers/CMSIS/Include/core_cm4.h **** 1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1109:Drivers/CMSIS/Include/core_cm4.h **** 1110:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */ 1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1113:Drivers/CMSIS/Include/core_cm4.h **** 1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1115:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1116:Drivers/CMSIS/Include/core_cm4.h **** 1117:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */ 1118:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1120:Drivers/CMSIS/Include/core_cm4.h **** 1121:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1124:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 24 1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1127:Drivers/CMSIS/Include/core_cm4.h **** 1128:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1130:Drivers/CMSIS/Include/core_cm4.h **** 1131:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1133:Drivers/CMSIS/Include/core_cm4.h **** 1134:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1135:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1136:Drivers/CMSIS/Include/core_cm4.h **** 1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF 1138:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1139:Drivers/CMSIS/Include/core_cm4.h **** 1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1141:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1142:Drivers/CMSIS/Include/core_cm4.h **** 1143:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */ 1144:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1146:Drivers/CMSIS/Include/core_cm4.h **** 1147:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1149:Drivers/CMSIS/Include/core_cm4.h **** 1150:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1153:Drivers/CMSIS/Include/core_cm4.h **** 1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1156:Drivers/CMSIS/Include/core_cm4.h **** 1157:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1159:Drivers/CMSIS/Include/core_cm4.h **** 1160:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1162:Drivers/CMSIS/Include/core_cm4.h **** 1163:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1164:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1165:Drivers/CMSIS/Include/core_cm4.h **** 1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1168:Drivers/CMSIS/Include/core_cm4.h **** 1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1171:Drivers/CMSIS/Include/core_cm4.h **** 1172:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */ 1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1174:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1175:Drivers/CMSIS/Include/core_cm4.h **** 1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1177:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1178:Drivers/CMSIS/Include/core_cm4.h **** 1179:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */ 1180:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC ARM GAS /tmp/ccPRqU3T.s page 25 1182:Drivers/CMSIS/Include/core_cm4.h **** 1183:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */ 1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV 1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1186:Drivers/CMSIS/Include/core_cm4.h **** 1187:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1189:Drivers/CMSIS/Include/core_cm4.h **** 1190:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1192:Drivers/CMSIS/Include/core_cm4.h **** 1193:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV 1194:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV 1195:Drivers/CMSIS/Include/core_cm4.h **** 1196:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1197:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1198:Drivers/CMSIS/Include/core_cm4.h **** 1199:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1200:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1201:Drivers/CMSIS/Include/core_cm4.h **** 1202:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */ 1203:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1204:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1205:Drivers/CMSIS/Include/core_cm4.h **** 1206:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1207:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1208:Drivers/CMSIS/Include/core_cm4.h **** 1209:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */ 1210:Drivers/CMSIS/Include/core_cm4.h **** 1211:Drivers/CMSIS/Include/core_cm4.h **** 1212:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1213:Drivers/CMSIS/Include/core_cm4.h **** /** 1214:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1215:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1216:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1217:Drivers/CMSIS/Include/core_cm4.h **** @{ 1218:Drivers/CMSIS/Include/core_cm4.h **** */ 1219:Drivers/CMSIS/Include/core_cm4.h **** 1220:Drivers/CMSIS/Include/core_cm4.h **** /** 1221:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1222:Drivers/CMSIS/Include/core_cm4.h **** */ 1223:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1224:Drivers/CMSIS/Include/core_cm4.h **** { 1225:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1226:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1227:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1228:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1229:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1230:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1231:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1232:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1233:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1234:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1235:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1236:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type; 1237:Drivers/CMSIS/Include/core_cm4.h **** 1238:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES 4U ARM GAS /tmp/ccPRqU3T.s page 26 1239:Drivers/CMSIS/Include/core_cm4.h **** 1240:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */ 1241:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU 1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1243:Drivers/CMSIS/Include/core_cm4.h **** 1244:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1245:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1246:Drivers/CMSIS/Include/core_cm4.h **** 1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1248:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1249:Drivers/CMSIS/Include/core_cm4.h **** 1250:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */ 1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU 1252:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1253:Drivers/CMSIS/Include/core_cm4.h **** 1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1255:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1256:Drivers/CMSIS/Include/core_cm4.h **** 1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1258:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1259:Drivers/CMSIS/Include/core_cm4.h **** 1260:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */ 1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1262:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1263:Drivers/CMSIS/Include/core_cm4.h **** 1264:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */ 1265:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1267:Drivers/CMSIS/Include/core_cm4.h **** 1268:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1270:Drivers/CMSIS/Include/core_cm4.h **** 1271:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1273:Drivers/CMSIS/Include/core_cm4.h **** 1274:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */ 1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1277:Drivers/CMSIS/Include/core_cm4.h **** 1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1280:Drivers/CMSIS/Include/core_cm4.h **** 1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1283:Drivers/CMSIS/Include/core_cm4.h **** 1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1286:Drivers/CMSIS/Include/core_cm4.h **** 1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1289:Drivers/CMSIS/Include/core_cm4.h **** 1290:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1291:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1292:Drivers/CMSIS/Include/core_cm4.h **** 1293:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1294:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1295:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 27 1296:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1297:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1298:Drivers/CMSIS/Include/core_cm4.h **** 1299:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1300:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1301:Drivers/CMSIS/Include/core_cm4.h **** 1302:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1303:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1304:Drivers/CMSIS/Include/core_cm4.h **** 1305:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */ 1306:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1307:Drivers/CMSIS/Include/core_cm4.h **** 1308:Drivers/CMSIS/Include/core_cm4.h **** 1309:Drivers/CMSIS/Include/core_cm4.h **** /** 1310:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1311:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1312:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU) 1313:Drivers/CMSIS/Include/core_cm4.h **** @{ 1314:Drivers/CMSIS/Include/core_cm4.h **** */ 1315:Drivers/CMSIS/Include/core_cm4.h **** 1316:Drivers/CMSIS/Include/core_cm4.h **** /** 1317:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU). 1318:Drivers/CMSIS/Include/core_cm4.h **** */ 1319:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1320:Drivers/CMSIS/Include/core_cm4.h **** { 1321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 1322:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1323:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1324:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1325:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1326:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1327:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type; 1328:Drivers/CMSIS/Include/core_cm4.h **** 1329:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */ 1330:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1332:Drivers/CMSIS/Include/core_cm4.h **** 1333:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1335:Drivers/CMSIS/Include/core_cm4.h **** 1336:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1338:Drivers/CMSIS/Include/core_cm4.h **** 1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1341:Drivers/CMSIS/Include/core_cm4.h **** 1342:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1343:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1344:Drivers/CMSIS/Include/core_cm4.h **** 1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1346:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1347:Drivers/CMSIS/Include/core_cm4.h **** 1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1350:Drivers/CMSIS/Include/core_cm4.h **** 1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC ARM GAS /tmp/ccPRqU3T.s page 28 1353:Drivers/CMSIS/Include/core_cm4.h **** 1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC 1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1356:Drivers/CMSIS/Include/core_cm4.h **** 1357:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */ 1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1359:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1360:Drivers/CMSIS/Include/core_cm4.h **** 1361:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */ 1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1363:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS 1364:Drivers/CMSIS/Include/core_cm4.h **** 1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1366:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1367:Drivers/CMSIS/Include/core_cm4.h **** 1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1369:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1370:Drivers/CMSIS/Include/core_cm4.h **** 1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1372:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1373:Drivers/CMSIS/Include/core_cm4.h **** 1374:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */ 1375:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1377:Drivers/CMSIS/Include/core_cm4.h **** 1378:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1380:Drivers/CMSIS/Include/core_cm4.h **** 1381:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1383:Drivers/CMSIS/Include/core_cm4.h **** 1384:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1385:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1386:Drivers/CMSIS/Include/core_cm4.h **** 1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1388:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1389:Drivers/CMSIS/Include/core_cm4.h **** 1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1391:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1392:Drivers/CMSIS/Include/core_cm4.h **** 1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1394:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1395:Drivers/CMSIS/Include/core_cm4.h **** 1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1398:Drivers/CMSIS/Include/core_cm4.h **** 1399:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */ 1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1402:Drivers/CMSIS/Include/core_cm4.h **** 1403:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1404:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1405:Drivers/CMSIS/Include/core_cm4.h **** 1406:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1407:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1408:Drivers/CMSIS/Include/core_cm4.h **** 1409:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR ARM GAS /tmp/ccPRqU3T.s page 29 1410:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1411:Drivers/CMSIS/Include/core_cm4.h **** 1412:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */ 1413:Drivers/CMSIS/Include/core_cm4.h **** 1414:Drivers/CMSIS/Include/core_cm4.h **** 1415:Drivers/CMSIS/Include/core_cm4.h **** /** 1416:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1417:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1418:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Core Debug Registers 1419:Drivers/CMSIS/Include/core_cm4.h **** @{ 1420:Drivers/CMSIS/Include/core_cm4.h **** */ 1421:Drivers/CMSIS/Include/core_cm4.h **** 1422:Drivers/CMSIS/Include/core_cm4.h **** /** 1423:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1424:Drivers/CMSIS/Include/core_cm4.h **** */ 1425:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1426:Drivers/CMSIS/Include/core_cm4.h **** { 1427:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1428:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1429:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1430:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1431:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type; 1432:Drivers/CMSIS/Include/core_cm4.h **** 1433:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */ 1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1436:Drivers/CMSIS/Include/core_cm4.h **** 1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1439:Drivers/CMSIS/Include/core_cm4.h **** 1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1442:Drivers/CMSIS/Include/core_cm4.h **** 1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1445:Drivers/CMSIS/Include/core_cm4.h **** 1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1448:Drivers/CMSIS/Include/core_cm4.h **** 1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1451:Drivers/CMSIS/Include/core_cm4.h **** 1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1454:Drivers/CMSIS/Include/core_cm4.h **** 1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1457:Drivers/CMSIS/Include/core_cm4.h **** 1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1460:Drivers/CMSIS/Include/core_cm4.h **** 1461:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1463:Drivers/CMSIS/Include/core_cm4.h **** 1464:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1466:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 30 1467:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1468:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1469:Drivers/CMSIS/Include/core_cm4.h **** 1470:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */ 1471:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1473:Drivers/CMSIS/Include/core_cm4.h **** 1474:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core 1476:Drivers/CMSIS/Include/core_cm4.h **** 1477:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */ 1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1480:Drivers/CMSIS/Include/core_cm4.h **** 1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1483:Drivers/CMSIS/Include/core_cm4.h **** 1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1486:Drivers/CMSIS/Include/core_cm4.h **** 1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1489:Drivers/CMSIS/Include/core_cm4.h **** 1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1492:Drivers/CMSIS/Include/core_cm4.h **** 1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1495:Drivers/CMSIS/Include/core_cm4.h **** 1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1498:Drivers/CMSIS/Include/core_cm4.h **** 1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1501:Drivers/CMSIS/Include/core_cm4.h **** 1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1504:Drivers/CMSIS/Include/core_cm4.h **** 1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1507:Drivers/CMSIS/Include/core_cm4.h **** 1508:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1509:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1510:Drivers/CMSIS/Include/core_cm4.h **** 1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1512:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1513:Drivers/CMSIS/Include/core_cm4.h **** 1514:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1515:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1516:Drivers/CMSIS/Include/core_cm4.h **** 1517:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */ 1518:Drivers/CMSIS/Include/core_cm4.h **** 1519:Drivers/CMSIS/Include/core_cm4.h **** 1520:Drivers/CMSIS/Include/core_cm4.h **** /** 1521:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1522:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1523:Drivers/CMSIS/Include/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). ARM GAS /tmp/ccPRqU3T.s page 31 1524:Drivers/CMSIS/Include/core_cm4.h **** @{ 1525:Drivers/CMSIS/Include/core_cm4.h **** */ 1526:Drivers/CMSIS/Include/core_cm4.h **** 1527:Drivers/CMSIS/Include/core_cm4.h **** /** 1528:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range. 1529:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. 1530:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1531:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted value. 1532:Drivers/CMSIS/Include/core_cm4.h **** */ 1533:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1534:Drivers/CMSIS/Include/core_cm4.h **** 1535:Drivers/CMSIS/Include/core_cm4.h **** /** 1536:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value. 1537:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. 1538:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1539:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted bit field value. 1540:Drivers/CMSIS/Include/core_cm4.h **** */ 1541:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1542:Drivers/CMSIS/Include/core_cm4.h **** 1543:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */ 1544:Drivers/CMSIS/Include/core_cm4.h **** 1545:Drivers/CMSIS/Include/core_cm4.h **** 1546:Drivers/CMSIS/Include/core_cm4.h **** /** 1547:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1548:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions 1549:Drivers/CMSIS/Include/core_cm4.h **** \brief Definitions for base addresses, unions, and structures. 1550:Drivers/CMSIS/Include/core_cm4.h **** @{ 1551:Drivers/CMSIS/Include/core_cm4.h **** */ 1552:Drivers/CMSIS/Include/core_cm4.h **** 1553:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */ 1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1555:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1556:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1557:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1558:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1559:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1560:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1562:Drivers/CMSIS/Include/core_cm4.h **** 1563:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1565:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1566:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1567:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1568:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1569:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1570:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1571:Drivers/CMSIS/Include/core_cm4.h **** 1572:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1573:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1574:Drivers/CMSIS/Include/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1575:Drivers/CMSIS/Include/core_cm4.h **** #endif 1576:Drivers/CMSIS/Include/core_cm4.h **** 1577:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1578:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1579:Drivers/CMSIS/Include/core_cm4.h **** 1580:Drivers/CMSIS/Include/core_cm4.h **** /*@} */ ARM GAS /tmp/ccPRqU3T.s page 32 1581:Drivers/CMSIS/Include/core_cm4.h **** 1582:Drivers/CMSIS/Include/core_cm4.h **** 1583:Drivers/CMSIS/Include/core_cm4.h **** 1584:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 1585:Drivers/CMSIS/Include/core_cm4.h **** * Hardware Abstraction Layer 1586:Drivers/CMSIS/Include/core_cm4.h **** Core Function Interface contains: 1587:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Functions 1588:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Functions 1589:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Functions 1590:Drivers/CMSIS/Include/core_cm4.h **** - Core Register Access Functions 1591:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 1592:Drivers/CMSIS/Include/core_cm4.h **** /** 1593:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1594:Drivers/CMSIS/Include/core_cm4.h **** */ 1595:Drivers/CMSIS/Include/core_cm4.h **** 1596:Drivers/CMSIS/Include/core_cm4.h **** 1597:Drivers/CMSIS/Include/core_cm4.h **** 1598:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## NVIC functions #################################### */ 1599:Drivers/CMSIS/Include/core_cm4.h **** /** 1600:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 1601:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1602:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1603:Drivers/CMSIS/Include/core_cm4.h **** @{ 1604:Drivers/CMSIS/Include/core_cm4.h **** */ 1605:Drivers/CMSIS/Include/core_cm4.h **** 1606:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL 1607:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1608:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1609:Drivers/CMSIS/Include/core_cm4.h **** #endif 1610:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1611:Drivers/CMSIS/Include/core_cm4.h **** #else 1612:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1613:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1614:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1615:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1616:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1617:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1618:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1619:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1620:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetActive __NVIC_GetActive 1621:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriority __NVIC_SetPriority 1622:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriority __NVIC_GetPriority 1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset 1624:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1625:Drivers/CMSIS/Include/core_cm4.h **** 1626:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1627:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1628:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1629:Drivers/CMSIS/Include/core_cm4.h **** #endif 1630:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1631:Drivers/CMSIS/Include/core_cm4.h **** #else 1632:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector 1633:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector 1634:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1635:Drivers/CMSIS/Include/core_cm4.h **** 1636:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET 16 1637:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 33 1638:Drivers/CMSIS/Include/core_cm4.h **** 1639:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1640:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1641:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1642:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1643:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1644:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1645:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1646:Drivers/CMSIS/Include/core_cm4.h **** 1647:Drivers/CMSIS/Include/core_cm4.h **** 1648:Drivers/CMSIS/Include/core_cm4.h **** /** 1649:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Priority Grouping 1650:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence. 1651:Drivers/CMSIS/Include/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1652:Drivers/CMSIS/Include/core_cm4.h **** Only values from 0..7 are used. 1653:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1654:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1655:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Priority grouping field. 1656:Drivers/CMSIS/Include/core_cm4.h **** */ 1657:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 40 .loc 2 1657 22 view .LVU3 41 .LBB39: 1658:Drivers/CMSIS/Include/core_cm4.h **** { 1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t reg_value; 42 .loc 2 1659 3 view .LVU4 1660:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 43 .loc 2 1660 3 view .LVU5 1661:Drivers/CMSIS/Include/core_cm4.h **** 1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register 44 .loc 2 1662 3 view .LVU6 45 .loc 2 1662 14 is_stmt 0 view .LVU7 46 0000 074A ldr r2, .L2 47 0002 D368 ldr r3, [r2, #12] 48 .LVL1: 1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 49 .loc 2 1663 3 is_stmt 1 view .LVU8 50 .loc 2 1663 13 is_stmt 0 view .LVU9 51 0004 23F4E063 bic r3, r3, #1792 52 .LVL2: 53 .loc 2 1663 13 view .LVU10 54 0008 1B04 lsls r3, r3, #16 55 000a 1B0C lsrs r3, r3, #16 56 .LVL3: 1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | 57 .loc 2 1664 3 is_stmt 1 view .LVU11 1665:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1666:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 58 .loc 2 1666 35 is_stmt 0 view .LVU12 59 000c 0002 lsls r0, r0, #8 60 .LVL4: 61 .loc 2 1666 35 view .LVU13 62 000e 00F4E060 and r0, r0, #1792 1665:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 63 .loc 2 1665 62 view .LVU14 64 0012 0343 orrs r3, r3, r0 65 .LVL5: 1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | ARM GAS /tmp/ccPRqU3T.s page 34 66 .loc 2 1664 14 view .LVU15 67 0014 43F0BF63 orr r3, r3, #100139008 68 0018 43F40033 orr r3, r3, #131072 69 .LVL6: 1667:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; 70 .loc 2 1667 3 is_stmt 1 view .LVU16 71 .loc 2 1667 14 is_stmt 0 view .LVU17 72 001c D360 str r3, [r2, #12] 73 .LVL7: 74 .loc 2 1667 14 view .LVU18 75 .LBE39: 76 .LBE38: 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 77 .loc 1 150 1 view .LVU19 78 001e 7047 bx lr 79 .L3: 80 .align 2 81 .L2: 82 0020 00ED00E0 .word -536810240 83 .cfi_endproc 84 .LFE130: 86 .section .text.HAL_NVIC_SetPriority,"ax",%progbits 87 .align 1 88 .global HAL_NVIC_SetPriority 89 .syntax unified 90 .thumb 91 .thumb_func 93 HAL_NVIC_SetPriority: 94 .LVL8: 95 .LFB131: 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel. 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * A lower priority value indicates a higher priority 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * A lower priority value indicates a higher priority. 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 96 .loc 1 166 1 is_stmt 1 view -0 97 .cfi_startproc 98 @ args = 0, pretend = 0, frame = 0 99 @ frame_needed = 0, uses_anonymous_args = 0 100 .loc 1 166 1 is_stmt 0 view .LVU21 101 0000 00B5 push {lr} 102 .LCFI0: 103 .cfi_def_cfa_offset 4 104 .cfi_offset 14, -4 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t prioritygroup = 0x00U; 105 .loc 1 167 3 is_stmt 1 view .LVU22 ARM GAS /tmp/ccPRqU3T.s page 35 106 .LVL9: 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); 107 .loc 1 170 3 view .LVU23 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 108 .loc 1 171 3 view .LVU24 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); 109 .loc 1 173 3 view .LVU25 110 .LBB46: 111 .LBI46: 1668:Drivers/CMSIS/Include/core_cm4.h **** } 1669:Drivers/CMSIS/Include/core_cm4.h **** 1670:Drivers/CMSIS/Include/core_cm4.h **** 1671:Drivers/CMSIS/Include/core_cm4.h **** /** 1672:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Priority Grouping 1673:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1674:Drivers/CMSIS/Include/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1675:Drivers/CMSIS/Include/core_cm4.h **** */ 1676:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 112 .loc 2 1676 26 view .LVU26 113 .LBB47: 1677:Drivers/CMSIS/Include/core_cm4.h **** { 1678:Drivers/CMSIS/Include/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 114 .loc 2 1678 3 view .LVU27 115 .loc 2 1678 26 is_stmt 0 view .LVU28 116 0002 194B ldr r3, .L10 117 0004 DB68 ldr r3, [r3, #12] 118 .loc 2 1678 11 view .LVU29 119 0006 C3F30223 ubfx r3, r3, #8, #3 120 .LVL10: 121 .loc 2 1678 11 view .LVU30 122 .LBE47: 123 .LBE46: 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 124 .loc 1 175 3 is_stmt 1 view .LVU31 125 .LBB48: 126 .LBI48: 1679:Drivers/CMSIS/Include/core_cm4.h **** } 1680:Drivers/CMSIS/Include/core_cm4.h **** 1681:Drivers/CMSIS/Include/core_cm4.h **** 1682:Drivers/CMSIS/Include/core_cm4.h **** /** 1683:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt 1684:Drivers/CMSIS/Include/core_cm4.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1685:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1686:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1687:Drivers/CMSIS/Include/core_cm4.h **** */ 1688:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1689:Drivers/CMSIS/Include/core_cm4.h **** { 1690:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1691:Drivers/CMSIS/Include/core_cm4.h **** { 1692:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1693:Drivers/CMSIS/Include/core_cm4.h **** } 1694:Drivers/CMSIS/Include/core_cm4.h **** } 1695:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccPRqU3T.s page 36 1696:Drivers/CMSIS/Include/core_cm4.h **** 1697:Drivers/CMSIS/Include/core_cm4.h **** /** 1698:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Enable status 1699:Drivers/CMSIS/Include/core_cm4.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1700:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1701:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt is not enabled. 1702:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt is enabled. 1703:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1704:Drivers/CMSIS/Include/core_cm4.h **** */ 1705:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1706:Drivers/CMSIS/Include/core_cm4.h **** { 1707:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1708:Drivers/CMSIS/Include/core_cm4.h **** { 1709:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1710:Drivers/CMSIS/Include/core_cm4.h **** } 1711:Drivers/CMSIS/Include/core_cm4.h **** else 1712:Drivers/CMSIS/Include/core_cm4.h **** { 1713:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1714:Drivers/CMSIS/Include/core_cm4.h **** } 1715:Drivers/CMSIS/Include/core_cm4.h **** } 1716:Drivers/CMSIS/Include/core_cm4.h **** 1717:Drivers/CMSIS/Include/core_cm4.h **** 1718:Drivers/CMSIS/Include/core_cm4.h **** /** 1719:Drivers/CMSIS/Include/core_cm4.h **** \brief Disable Interrupt 1720:Drivers/CMSIS/Include/core_cm4.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1721:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1722:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1723:Drivers/CMSIS/Include/core_cm4.h **** */ 1724:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1725:Drivers/CMSIS/Include/core_cm4.h **** { 1726:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1727:Drivers/CMSIS/Include/core_cm4.h **** { 1728:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1729:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 1730:Drivers/CMSIS/Include/core_cm4.h **** __ISB(); 1731:Drivers/CMSIS/Include/core_cm4.h **** } 1732:Drivers/CMSIS/Include/core_cm4.h **** } 1733:Drivers/CMSIS/Include/core_cm4.h **** 1734:Drivers/CMSIS/Include/core_cm4.h **** 1735:Drivers/CMSIS/Include/core_cm4.h **** /** 1736:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Pending Interrupt 1737:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1738:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1739:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not pending. 1740:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is pending. 1741:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1742:Drivers/CMSIS/Include/core_cm4.h **** */ 1743:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1744:Drivers/CMSIS/Include/core_cm4.h **** { 1745:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1746:Drivers/CMSIS/Include/core_cm4.h **** { 1747:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1748:Drivers/CMSIS/Include/core_cm4.h **** } 1749:Drivers/CMSIS/Include/core_cm4.h **** else 1750:Drivers/CMSIS/Include/core_cm4.h **** { 1751:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1752:Drivers/CMSIS/Include/core_cm4.h **** } ARM GAS /tmp/ccPRqU3T.s page 37 1753:Drivers/CMSIS/Include/core_cm4.h **** } 1754:Drivers/CMSIS/Include/core_cm4.h **** 1755:Drivers/CMSIS/Include/core_cm4.h **** 1756:Drivers/CMSIS/Include/core_cm4.h **** /** 1757:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt 1758:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1759:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1760:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1761:Drivers/CMSIS/Include/core_cm4.h **** */ 1762:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1763:Drivers/CMSIS/Include/core_cm4.h **** { 1764:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1765:Drivers/CMSIS/Include/core_cm4.h **** { 1766:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1767:Drivers/CMSIS/Include/core_cm4.h **** } 1768:Drivers/CMSIS/Include/core_cm4.h **** } 1769:Drivers/CMSIS/Include/core_cm4.h **** 1770:Drivers/CMSIS/Include/core_cm4.h **** 1771:Drivers/CMSIS/Include/core_cm4.h **** /** 1772:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt 1773:Drivers/CMSIS/Include/core_cm4.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1774:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1775:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1776:Drivers/CMSIS/Include/core_cm4.h **** */ 1777:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1778:Drivers/CMSIS/Include/core_cm4.h **** { 1779:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1780:Drivers/CMSIS/Include/core_cm4.h **** { 1781:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1782:Drivers/CMSIS/Include/core_cm4.h **** } 1783:Drivers/CMSIS/Include/core_cm4.h **** } 1784:Drivers/CMSIS/Include/core_cm4.h **** 1785:Drivers/CMSIS/Include/core_cm4.h **** 1786:Drivers/CMSIS/Include/core_cm4.h **** /** 1787:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Active Interrupt 1788:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1789:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1790:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not active. 1791:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is active. 1792:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1793:Drivers/CMSIS/Include/core_cm4.h **** */ 1794:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1795:Drivers/CMSIS/Include/core_cm4.h **** { 1796:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1797:Drivers/CMSIS/Include/core_cm4.h **** { 1798:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1799:Drivers/CMSIS/Include/core_cm4.h **** } 1800:Drivers/CMSIS/Include/core_cm4.h **** else 1801:Drivers/CMSIS/Include/core_cm4.h **** { 1802:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1803:Drivers/CMSIS/Include/core_cm4.h **** } 1804:Drivers/CMSIS/Include/core_cm4.h **** } 1805:Drivers/CMSIS/Include/core_cm4.h **** 1806:Drivers/CMSIS/Include/core_cm4.h **** 1807:Drivers/CMSIS/Include/core_cm4.h **** /** 1808:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Priority 1809:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority of a device specific interrupt or a processor exception. ARM GAS /tmp/ccPRqU3T.s page 38 1810:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1811:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1812:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1813:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set. 1814:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception. 1815:Drivers/CMSIS/Include/core_cm4.h **** */ 1816:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1817:Drivers/CMSIS/Include/core_cm4.h **** { 1818:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1819:Drivers/CMSIS/Include/core_cm4.h **** { 1820:Drivers/CMSIS/Include/core_cm4.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u 1821:Drivers/CMSIS/Include/core_cm4.h **** } 1822:Drivers/CMSIS/Include/core_cm4.h **** else 1823:Drivers/CMSIS/Include/core_cm4.h **** { 1824:Drivers/CMSIS/Include/core_cm4.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u 1825:Drivers/CMSIS/Include/core_cm4.h **** } 1826:Drivers/CMSIS/Include/core_cm4.h **** } 1827:Drivers/CMSIS/Include/core_cm4.h **** 1828:Drivers/CMSIS/Include/core_cm4.h **** 1829:Drivers/CMSIS/Include/core_cm4.h **** /** 1830:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority 1831:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception. 1832:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1833:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1834:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1835:Drivers/CMSIS/Include/core_cm4.h **** \return Interrupt Priority. 1836:Drivers/CMSIS/Include/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc 1837:Drivers/CMSIS/Include/core_cm4.h **** */ 1838:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1839:Drivers/CMSIS/Include/core_cm4.h **** { 1840:Drivers/CMSIS/Include/core_cm4.h **** 1841:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1842:Drivers/CMSIS/Include/core_cm4.h **** { 1843:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 1844:Drivers/CMSIS/Include/core_cm4.h **** } 1845:Drivers/CMSIS/Include/core_cm4.h **** else 1846:Drivers/CMSIS/Include/core_cm4.h **** { 1847:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 1848:Drivers/CMSIS/Include/core_cm4.h **** } 1849:Drivers/CMSIS/Include/core_cm4.h **** } 1850:Drivers/CMSIS/Include/core_cm4.h **** 1851:Drivers/CMSIS/Include/core_cm4.h **** 1852:Drivers/CMSIS/Include/core_cm4.h **** /** 1853:Drivers/CMSIS/Include/core_cm4.h **** \brief Encode Priority 1854:Drivers/CMSIS/Include/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group, 1855:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value, and subpriority value. 1856:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1857:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1858:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. 1859:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 1860:Drivers/CMSIS/Include/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0). 1861:Drivers/CMSIS/Include/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 1862:Drivers/CMSIS/Include/core_cm4.h **** */ 1863:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 127 .loc 2 1863 26 view .LVU32 128 .LBB49: 1864:Drivers/CMSIS/Include/core_cm4.h **** { ARM GAS /tmp/ccPRqU3T.s page 39 1865:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 129 .loc 2 1865 3 view .LVU33 1866:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; 130 .loc 2 1866 3 view .LVU34 1867:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; 131 .loc 2 1867 3 view .LVU35 1868:Drivers/CMSIS/Include/core_cm4.h **** 1869:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 132 .loc 2 1869 3 view .LVU36 133 .loc 2 1869 31 is_stmt 0 view .LVU37 134 000a C3F1070C rsb ip, r3, #7 135 .loc 2 1869 23 view .LVU38 136 000e BCF1040F cmp ip, #4 137 0012 28BF it cs 138 0014 4FF0040C movcs ip, #4 139 .LVL11: 1870:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 140 .loc 2 1870 3 is_stmt 1 view .LVU39 141 .loc 2 1870 44 is_stmt 0 view .LVU40 142 0018 03F1040E add lr, r3, #4 143 .loc 2 1870 109 view .LVU41 144 001c BEF1060F cmp lr, #6 145 0020 18D9 bls .L8 146 0022 033B subs r3, r3, #3 147 .LVL12: 148 .L5: 1871:Drivers/CMSIS/Include/core_cm4.h **** 1872:Drivers/CMSIS/Include/core_cm4.h **** return ( 149 .loc 2 1872 3 is_stmt 1 view .LVU42 1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 150 .loc 2 1873 30 is_stmt 0 view .LVU43 151 0024 4FF0FF3E mov lr, #-1 152 .LVL13: 153 .loc 2 1873 30 view .LVU44 154 0028 0EFA0CFC lsl ip, lr, ip 155 .LVL14: 156 .loc 2 1873 30 view .LVU45 157 002c 21EA0C01 bic r1, r1, ip 158 .LVL15: 159 .loc 2 1873 82 view .LVU46 160 0030 9940 lsls r1, r1, r3 1874:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 161 .loc 2 1874 30 view .LVU47 162 0032 0EFA03F3 lsl r3, lr, r3 163 .LVL16: 164 .loc 2 1874 30 view .LVU48 165 0036 22EA0303 bic r3, r2, r3 1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 166 .loc 2 1873 102 view .LVU49 167 003a 1943 orrs r1, r1, r3 168 .LVL17: 1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 169 .loc 2 1873 102 view .LVU50 170 .LBE49: 171 .LBE48: 172 .LBB51: 173 .LBI51: ARM GAS /tmp/ccPRqU3T.s page 40 1816:Drivers/CMSIS/Include/core_cm4.h **** { 174 .loc 2 1816 22 is_stmt 1 view .LVU51 175 .LBB52: 1818:Drivers/CMSIS/Include/core_cm4.h **** { 176 .loc 2 1818 3 view .LVU52 1818:Drivers/CMSIS/Include/core_cm4.h **** { 177 .loc 2 1818 6 is_stmt 0 view .LVU53 178 003c 0028 cmp r0, #0 179 003e 0BDB blt .L6 1820:Drivers/CMSIS/Include/core_cm4.h **** } 180 .loc 2 1820 5 is_stmt 1 view .LVU54 1820:Drivers/CMSIS/Include/core_cm4.h **** } 181 .loc 2 1820 48 is_stmt 0 view .LVU55 182 0040 0901 lsls r1, r1, #4 183 .LVL18: 1820:Drivers/CMSIS/Include/core_cm4.h **** } 184 .loc 2 1820 48 view .LVU56 185 0042 C9B2 uxtb r1, r1 1820:Drivers/CMSIS/Include/core_cm4.h **** } 186 .loc 2 1820 46 view .LVU57 187 0044 00F16040 add r0, r0, #-536870912 188 .LVL19: 1820:Drivers/CMSIS/Include/core_cm4.h **** } 189 .loc 2 1820 46 view .LVU58 190 0048 00F56140 add r0, r0, #57600 191 004c 80F80013 strb r1, [r0, #768] 192 .LVL20: 193 .L4: 1820:Drivers/CMSIS/Include/core_cm4.h **** } 194 .loc 2 1820 46 view .LVU59 195 .LBE52: 196 .LBE51: 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 197 .loc 1 176 1 view .LVU60 198 0050 5DF804FB ldr pc, [sp], #4 199 .LVL21: 200 .L8: 201 .LBB54: 202 .LBB50: 1870:Drivers/CMSIS/Include/core_cm4.h **** 203 .loc 2 1870 109 view .LVU61 204 0054 0023 movs r3, #0 205 .LVL22: 1870:Drivers/CMSIS/Include/core_cm4.h **** 206 .loc 2 1870 109 view .LVU62 207 0056 E5E7 b .L5 208 .LVL23: 209 .L6: 1870:Drivers/CMSIS/Include/core_cm4.h **** 210 .loc 2 1870 109 view .LVU63 211 .LBE50: 212 .LBE54: 213 .LBB55: 214 .LBB53: 1824:Drivers/CMSIS/Include/core_cm4.h **** } 215 .loc 2 1824 5 is_stmt 1 view .LVU64 1824:Drivers/CMSIS/Include/core_cm4.h **** } ARM GAS /tmp/ccPRqU3T.s page 41 216 .loc 2 1824 32 is_stmt 0 view .LVU65 217 0058 00F00F00 and r0, r0, #15 218 .LVL24: 1824:Drivers/CMSIS/Include/core_cm4.h **** } 219 .loc 2 1824 48 view .LVU66 220 005c 0901 lsls r1, r1, #4 221 .LVL25: 1824:Drivers/CMSIS/Include/core_cm4.h **** } 222 .loc 2 1824 48 view .LVU67 223 005e C9B2 uxtb r1, r1 1824:Drivers/CMSIS/Include/core_cm4.h **** } 224 .loc 2 1824 46 view .LVU68 225 0060 024B ldr r3, .L10+4 226 0062 1954 strb r1, [r3, r0] 227 .LVL26: 1824:Drivers/CMSIS/Include/core_cm4.h **** } 228 .loc 2 1824 46 view .LVU69 229 .LBE53: 230 .LBE55: 231 .loc 1 176 1 view .LVU70 232 0064 F4E7 b .L4 233 .L11: 234 0066 00BF .align 2 235 .L10: 236 0068 00ED00E0 .word -536810240 237 006c 14ED00E0 .word -536810220 238 .cfi_endproc 239 .LFE131: 241 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits 242 .align 1 243 .global HAL_NVIC_EnableIRQ 244 .syntax unified 245 .thumb 246 .thumb_func 248 HAL_NVIC_EnableIRQ: 249 .LVL27: 250 .LFB132: 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * function should be called before. 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 251 .loc 1 188 1 is_stmt 1 view -0 252 .cfi_startproc 253 @ args = 0, pretend = 0, frame = 0 254 @ frame_needed = 0, uses_anonymous_args = 0 255 @ link register save eliminated. 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 256 .loc 1 190 3 view .LVU72 ARM GAS /tmp/ccPRqU3T.s page 42 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Enable interrupt */ 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); 257 .loc 1 193 3 view .LVU73 258 .LBB56: 259 .LBI56: 1688:Drivers/CMSIS/Include/core_cm4.h **** { 260 .loc 2 1688 22 view .LVU74 261 .LBB57: 1690:Drivers/CMSIS/Include/core_cm4.h **** { 262 .loc 2 1690 3 view .LVU75 1690:Drivers/CMSIS/Include/core_cm4.h **** { 263 .loc 2 1690 6 is_stmt 0 view .LVU76 264 0000 0028 cmp r0, #0 265 .LVL28: 1690:Drivers/CMSIS/Include/core_cm4.h **** { 266 .loc 2 1690 6 view .LVU77 267 0002 07DB blt .L12 1692:Drivers/CMSIS/Include/core_cm4.h **** } 268 .loc 2 1692 5 is_stmt 1 view .LVU78 1692:Drivers/CMSIS/Include/core_cm4.h **** } 269 .loc 2 1692 81 is_stmt 0 view .LVU79 270 0004 00F01F02 and r2, r0, #31 1692:Drivers/CMSIS/Include/core_cm4.h **** } 271 .loc 2 1692 34 view .LVU80 272 0008 4009 lsrs r0, r0, #5 1692:Drivers/CMSIS/Include/core_cm4.h **** } 273 .loc 2 1692 45 view .LVU81 274 000a 0123 movs r3, #1 275 000c 9340 lsls r3, r3, r2 1692:Drivers/CMSIS/Include/core_cm4.h **** } 276 .loc 2 1692 43 view .LVU82 277 000e 024A ldr r2, .L14 278 0010 42F82030 str r3, [r2, r0, lsl #2] 279 .LVL29: 280 .L12: 1692:Drivers/CMSIS/Include/core_cm4.h **** } 281 .loc 2 1692 43 view .LVU83 282 .LBE57: 283 .LBE56: 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 284 .loc 1 194 1 view .LVU84 285 0014 7047 bx lr 286 .L15: 287 0016 00BF .align 2 288 .L14: 289 0018 00E100E0 .word -536813312 290 .cfi_endproc 291 .LFE132: 293 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits 294 .align 1 295 .global HAL_NVIC_DisableIRQ 296 .syntax unified 297 .thumb 298 .thumb_func 300 HAL_NVIC_DisableIRQ: 301 .LVL30: ARM GAS /tmp/ccPRqU3T.s page 43 302 .LFB133: 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 303 .loc 1 204 1 is_stmt 1 view -0 304 .cfi_startproc 305 @ args = 0, pretend = 0, frame = 0 306 @ frame_needed = 0, uses_anonymous_args = 0 307 @ link register save eliminated. 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 308 .loc 1 206 3 view .LVU86 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Disable interrupt */ 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); 309 .loc 1 209 3 view .LVU87 310 .LBB64: 311 .LBI64: 1724:Drivers/CMSIS/Include/core_cm4.h **** { 312 .loc 2 1724 22 view .LVU88 313 .LBB65: 1726:Drivers/CMSIS/Include/core_cm4.h **** { 314 .loc 2 1726 3 view .LVU89 1726:Drivers/CMSIS/Include/core_cm4.h **** { 315 .loc 2 1726 6 is_stmt 0 view .LVU90 316 0000 0028 cmp r0, #0 317 .LVL31: 1726:Drivers/CMSIS/Include/core_cm4.h **** { 318 .loc 2 1726 6 view .LVU91 319 0002 0CDB blt .L16 1728:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 320 .loc 2 1728 5 is_stmt 1 view .LVU92 1728:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 321 .loc 2 1728 81 is_stmt 0 view .LVU93 322 0004 00F01F02 and r2, r0, #31 1728:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 323 .loc 2 1728 34 view .LVU94 324 0008 4009 lsrs r0, r0, #5 1728:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 325 .loc 2 1728 45 view .LVU95 326 000a 0123 movs r3, #1 327 000c 9340 lsls r3, r3, r2 1728:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 328 .loc 2 1728 43 view .LVU96 329 000e 2030 adds r0, r0, #32 330 0010 034A ldr r2, .L18 331 0012 42F82030 str r3, [r2, r0, lsl #2] 1729:Drivers/CMSIS/Include/core_cm4.h **** __ISB(); 332 .loc 2 1729 5 is_stmt 1 view .LVU97 333 .LBB66: ARM GAS /tmp/ccPRqU3T.s page 44 334 .LBI66: 335 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED ARM GAS /tmp/ccPRqU3T.s page 45 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccPRqU3T.s page 46 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccPRqU3T.s page 47 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccPRqU3T.s page 48 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) ARM GAS /tmp/ccPRqU3T.s page 49 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. ARM GAS /tmp/ccPRqU3T.s page 50 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) ARM GAS /tmp/ccPRqU3T.s page 51 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccPRqU3T.s page 52 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition ARM GAS /tmp/ccPRqU3T.s page 53 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccPRqU3T.s page 54 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccPRqU3T.s page 55 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) ARM GAS /tmp/ccPRqU3T.s page 56 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) ARM GAS /tmp/ccPRqU3T.s page 57 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) ARM GAS /tmp/ccPRqU3T.s page 58 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccPRqU3T.s page 59 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 336 .loc 3 877 27 view .LVU98 337 .LBB67: 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 338 .loc 3 879 3 view .LVU99 339 .syntax unified 340 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 341 0016 BFF34F8F dsb 0xF 342 @ 0 "" 2 343 .thumb 344 .syntax unified 345 .LBE67: 346 .LBE66: 1730:Drivers/CMSIS/Include/core_cm4.h **** } 347 .loc 2 1730 5 view .LVU100 348 .LBB68: 349 .LBI68: 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { 350 .loc 3 866 27 view .LVU101 351 .LBB69: 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } 352 .loc 3 868 3 view .LVU102 353 .syntax unified 354 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 355 001a BFF36F8F isb 0xF 356 @ 0 "" 2 357 .LVL32: 358 .thumb 359 .syntax unified 360 .L16: 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } 361 .loc 3 868 3 is_stmt 0 view .LVU103 362 .LBE69: ARM GAS /tmp/ccPRqU3T.s page 60 363 .LBE68: 364 .LBE65: 365 .LBE64: 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 366 .loc 1 210 1 view .LVU104 367 001e 7047 bx lr 368 .L19: 369 .align 2 370 .L18: 371 0020 00E100E0 .word -536813312 372 .cfi_endproc 373 .LFE133: 375 .section .text.HAL_NVIC_SystemReset,"ax",%progbits 376 .align 1 377 .global HAL_NVIC_SystemReset 378 .syntax unified 379 .thumb 380 .thumb_func 382 HAL_NVIC_SystemReset: 383 .LFB134: 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 384 .loc 1 217 1 is_stmt 1 view -0 385 .cfi_startproc 386 @ Volatile: function does not return. 387 @ args = 0, pretend = 0, frame = 0 388 @ frame_needed = 0, uses_anonymous_args = 0 389 @ link register save eliminated. 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* System Reset */ 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_SystemReset(); 390 .loc 1 219 3 view .LVU106 391 .LBB76: 392 .LBI76: 1875:Drivers/CMSIS/Include/core_cm4.h **** ); 1876:Drivers/CMSIS/Include/core_cm4.h **** } 1877:Drivers/CMSIS/Include/core_cm4.h **** 1878:Drivers/CMSIS/Include/core_cm4.h **** 1879:Drivers/CMSIS/Include/core_cm4.h **** /** 1880:Drivers/CMSIS/Include/core_cm4.h **** \brief Decode Priority 1881:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to 1882:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value. 1883:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1884:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1885:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC 1886:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. 1887:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1888:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0). 1889:Drivers/CMSIS/Include/core_cm4.h **** */ 1890:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons 1891:Drivers/CMSIS/Include/core_cm4.h **** { 1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 1893:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; ARM GAS /tmp/ccPRqU3T.s page 61 1894:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; 1895:Drivers/CMSIS/Include/core_cm4.h **** 1896:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 1897:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 1898:Drivers/CMSIS/Include/core_cm4.h **** 1899:Drivers/CMSIS/Include/core_cm4.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 1900:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 1901:Drivers/CMSIS/Include/core_cm4.h **** } 1902:Drivers/CMSIS/Include/core_cm4.h **** 1903:Drivers/CMSIS/Include/core_cm4.h **** 1904:Drivers/CMSIS/Include/core_cm4.h **** /** 1905:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Vector 1906:Drivers/CMSIS/Include/core_cm4.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. 1907:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1908:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1909:Drivers/CMSIS/Include/core_cm4.h **** VTOR must been relocated to SRAM before. 1910:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number 1911:Drivers/CMSIS/Include/core_cm4.h **** \param [in] vector Address of interrupt handler function 1912:Drivers/CMSIS/Include/core_cm4.h **** */ 1913:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1914:Drivers/CMSIS/Include/core_cm4.h **** { 1915:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; 1916:Drivers/CMSIS/Include/core_cm4.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1917:Drivers/CMSIS/Include/core_cm4.h **** } 1918:Drivers/CMSIS/Include/core_cm4.h **** 1919:Drivers/CMSIS/Include/core_cm4.h **** 1920:Drivers/CMSIS/Include/core_cm4.h **** /** 1921:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Vector 1922:Drivers/CMSIS/Include/core_cm4.h **** \details Reads an interrupt vector from interrupt vector table. 1923:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1924:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1925:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1926:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function 1927:Drivers/CMSIS/Include/core_cm4.h **** */ 1928:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1929:Drivers/CMSIS/Include/core_cm4.h **** { 1930:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; 1931:Drivers/CMSIS/Include/core_cm4.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 1932:Drivers/CMSIS/Include/core_cm4.h **** } 1933:Drivers/CMSIS/Include/core_cm4.h **** 1934:Drivers/CMSIS/Include/core_cm4.h **** 1935:Drivers/CMSIS/Include/core_cm4.h **** /** 1936:Drivers/CMSIS/Include/core_cm4.h **** \brief System Reset 1937:Drivers/CMSIS/Include/core_cm4.h **** \details Initiates a system reset request to reset the MCU. 1938:Drivers/CMSIS/Include/core_cm4.h **** */ 1939:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 393 .loc 2 1939 34 view .LVU107 394 .LBB77: 1940:Drivers/CMSIS/Include/core_cm4.h **** { 1941:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure all outstanding memor 395 .loc 2 1941 3 view .LVU108 396 .LBB78: 397 .LBI78: 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { 398 .loc 3 877 27 view .LVU109 399 .LBB79: 400 .loc 3 879 3 view .LVU110 ARM GAS /tmp/ccPRqU3T.s page 62 401 .syntax unified 402 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 403 0000 BFF34F8F dsb 0xF 404 @ 0 "" 2 405 .thumb 406 .syntax unified 407 .LBE79: 408 .LBE78: 1942:Drivers/CMSIS/Include/core_cm4.h **** buffered write are completed 1943:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 409 .loc 2 1943 3 view .LVU111 1944:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 410 .loc 2 1944 32 is_stmt 0 view .LVU112 411 0004 0549 ldr r1, .L22 412 0006 CA68 ldr r2, [r1, #12] 413 .loc 2 1944 40 view .LVU113 414 0008 02F4E062 and r2, r2, #1792 1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 415 .loc 2 1943 17 view .LVU114 416 000c 044B ldr r3, .L22+4 417 000e 1343 orrs r3, r3, r2 1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 418 .loc 2 1943 15 view .LVU115 419 0010 CB60 str r3, [r1, #12] 1945:Drivers/CMSIS/Include/core_cm4.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange 1946:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory 420 .loc 2 1946 3 is_stmt 1 view .LVU116 421 .LBB80: 422 .LBI80: 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { 423 .loc 3 877 27 view .LVU117 424 .LBB81: 425 .loc 3 879 3 view .LVU118 426 .syntax unified 427 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 428 0012 BFF34F8F dsb 0xF 429 @ 0 "" 2 430 .thumb 431 .syntax unified 432 .L21: 433 .LBE81: 434 .LBE80: 1947:Drivers/CMSIS/Include/core_cm4.h **** 1948:Drivers/CMSIS/Include/core_cm4.h **** for(;;) /* wait until reset */ 435 .loc 2 1948 3 view .LVU119 1949:Drivers/CMSIS/Include/core_cm4.h **** { 1950:Drivers/CMSIS/Include/core_cm4.h **** __NOP(); 436 .loc 2 1950 5 view .LVU120 437 .syntax unified 438 @ 1950 "Drivers/CMSIS/Include/core_cm4.h" 1 439 0016 00BF nop 440 @ 0 "" 2 1948:Drivers/CMSIS/Include/core_cm4.h **** { 441 .loc 2 1948 8 view .LVU121 442 .thumb 443 .syntax unified 444 0018 FDE7 b .L21 ARM GAS /tmp/ccPRqU3T.s page 63 445 .L23: 446 001a 00BF .align 2 447 .L22: 448 001c 00ED00E0 .word -536810240 449 0020 0400FA05 .word 100270084 450 .LBE77: 451 .LBE76: 452 .cfi_endproc 453 .LFE134: 455 .section .text.HAL_SYSTICK_Config,"ax",%progbits 456 .align 1 457 .global HAL_SYSTICK_Config 458 .syntax unified 459 .thumb 460 .thumb_func 462 HAL_SYSTICK_Config: 463 .LVL33: 464 .LFB135: 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * - 1 Function failed. 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 465 .loc 1 230 1 view -0 466 .cfi_startproc 467 @ args = 0, pretend = 0, frame = 0 468 @ frame_needed = 0, uses_anonymous_args = 0 469 @ link register save eliminated. 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** return SysTick_Config(TicksNumb); 470 .loc 1 231 4 view .LVU123 471 .LBB82: 472 .LBI82: 1951:Drivers/CMSIS/Include/core_cm4.h **** } 1952:Drivers/CMSIS/Include/core_cm4.h **** } 1953:Drivers/CMSIS/Include/core_cm4.h **** 1954:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */ 1955:Drivers/CMSIS/Include/core_cm4.h **** 1956:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## MPU functions #################################### */ 1957:Drivers/CMSIS/Include/core_cm4.h **** 1958:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1959:Drivers/CMSIS/Include/core_cm4.h **** 1960:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h" 1961:Drivers/CMSIS/Include/core_cm4.h **** 1962:Drivers/CMSIS/Include/core_cm4.h **** #endif 1963:Drivers/CMSIS/Include/core_cm4.h **** 1964:Drivers/CMSIS/Include/core_cm4.h **** 1965:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */ 1966:Drivers/CMSIS/Include/core_cm4.h **** /** 1967:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 1968:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions 1969:Drivers/CMSIS/Include/core_cm4.h **** \brief Function that provides FPU type. ARM GAS /tmp/ccPRqU3T.s page 64 1970:Drivers/CMSIS/Include/core_cm4.h **** @{ 1971:Drivers/CMSIS/Include/core_cm4.h **** */ 1972:Drivers/CMSIS/Include/core_cm4.h **** 1973:Drivers/CMSIS/Include/core_cm4.h **** /** 1974:Drivers/CMSIS/Include/core_cm4.h **** \brief get FPU type 1975:Drivers/CMSIS/Include/core_cm4.h **** \details returns the FPU type 1976:Drivers/CMSIS/Include/core_cm4.h **** \returns 1977:Drivers/CMSIS/Include/core_cm4.h **** - \b 0: No FPU 1978:Drivers/CMSIS/Include/core_cm4.h **** - \b 1: Single precision FPU 1979:Drivers/CMSIS/Include/core_cm4.h **** - \b 2: Double + Single precision FPU 1980:Drivers/CMSIS/Include/core_cm4.h **** */ 1981:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1982:Drivers/CMSIS/Include/core_cm4.h **** { 1983:Drivers/CMSIS/Include/core_cm4.h **** uint32_t mvfr0; 1984:Drivers/CMSIS/Include/core_cm4.h **** 1985:Drivers/CMSIS/Include/core_cm4.h **** mvfr0 = FPU->MVFR0; 1986:Drivers/CMSIS/Include/core_cm4.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 1987:Drivers/CMSIS/Include/core_cm4.h **** { 1988:Drivers/CMSIS/Include/core_cm4.h **** return 1U; /* Single precision FPU */ 1989:Drivers/CMSIS/Include/core_cm4.h **** } 1990:Drivers/CMSIS/Include/core_cm4.h **** else 1991:Drivers/CMSIS/Include/core_cm4.h **** { 1992:Drivers/CMSIS/Include/core_cm4.h **** return 0U; /* No FPU */ 1993:Drivers/CMSIS/Include/core_cm4.h **** } 1994:Drivers/CMSIS/Include/core_cm4.h **** } 1995:Drivers/CMSIS/Include/core_cm4.h **** 1996:Drivers/CMSIS/Include/core_cm4.h **** 1997:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */ 1998:Drivers/CMSIS/Include/core_cm4.h **** 1999:Drivers/CMSIS/Include/core_cm4.h **** 2000:Drivers/CMSIS/Include/core_cm4.h **** 2001:Drivers/CMSIS/Include/core_cm4.h **** /* ################################## SysTick function ######################################## 2002:Drivers/CMSIS/Include/core_cm4.h **** /** 2003:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 2004:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2005:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that configure the System. 2006:Drivers/CMSIS/Include/core_cm4.h **** @{ 2007:Drivers/CMSIS/Include/core_cm4.h **** */ 2008:Drivers/CMSIS/Include/core_cm4.h **** 2009:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 2010:Drivers/CMSIS/Include/core_cm4.h **** 2011:Drivers/CMSIS/Include/core_cm4.h **** /** 2012:Drivers/CMSIS/Include/core_cm4.h **** \brief System Tick Configuration 2013:Drivers/CMSIS/Include/core_cm4.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 2014:Drivers/CMSIS/Include/core_cm4.h **** Counter is in free running mode to generate periodic interrupts. 2015:Drivers/CMSIS/Include/core_cm4.h **** \param [in] ticks Number of ticks between two interrupts. 2016:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Function succeeded. 2017:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Function failed. 2018:Drivers/CMSIS/Include/core_cm4.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the 2019:Drivers/CMSIS/Include/core_cm4.h **** function SysTick_Config is not included. In this case, the file device. 2020:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function. 2021:Drivers/CMSIS/Include/core_cm4.h **** */ 2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 473 .loc 2 2022 26 view .LVU124 474 .LBB83: 2023:Drivers/CMSIS/Include/core_cm4.h **** { 2024:Drivers/CMSIS/Include/core_cm4.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) ARM GAS /tmp/ccPRqU3T.s page 65 475 .loc 2 2024 3 view .LVU125 476 .loc 2 2024 14 is_stmt 0 view .LVU126 477 0000 0138 subs r0, r0, #1 478 .LVL34: 479 .loc 2 2024 6 view .LVU127 480 0002 B0F1807F cmp r0, #16777216 481 0006 0BD2 bcs .L26 2025:Drivers/CMSIS/Include/core_cm4.h **** { 2026:Drivers/CMSIS/Include/core_cm4.h **** return (1UL); /* Reload value impossible */ 2027:Drivers/CMSIS/Include/core_cm4.h **** } 2028:Drivers/CMSIS/Include/core_cm4.h **** 2029:Drivers/CMSIS/Include/core_cm4.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 482 .loc 2 2029 3 is_stmt 1 view .LVU128 483 .loc 2 2029 18 is_stmt 0 view .LVU129 484 0008 4FF0E023 mov r3, #-536813568 485 000c 5861 str r0, [r3, #20] 2030:Drivers/CMSIS/Include/core_cm4.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int 486 .loc 2 2030 3 is_stmt 1 view .LVU130 487 .LVL35: 488 .LBB84: 489 .LBI84: 1816:Drivers/CMSIS/Include/core_cm4.h **** { 490 .loc 2 1816 22 view .LVU131 491 .LBB85: 1818:Drivers/CMSIS/Include/core_cm4.h **** { 492 .loc 2 1818 3 view .LVU132 1824:Drivers/CMSIS/Include/core_cm4.h **** } 493 .loc 2 1824 5 view .LVU133 1824:Drivers/CMSIS/Include/core_cm4.h **** } 494 .loc 2 1824 46 is_stmt 0 view .LVU134 495 000e 054A ldr r2, .L27 496 0010 F021 movs r1, #240 497 0012 82F82310 strb r1, [r2, #35] 498 .LVL36: 1824:Drivers/CMSIS/Include/core_cm4.h **** } 499 .loc 2 1824 46 view .LVU135 500 .LBE85: 501 .LBE84: 2031:Drivers/CMSIS/Include/core_cm4.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val 502 .loc 2 2031 3 is_stmt 1 view .LVU136 503 .loc 2 2031 18 is_stmt 0 view .LVU137 504 0016 0020 movs r0, #0 505 .LVL37: 506 .loc 2 2031 18 view .LVU138 507 0018 9861 str r0, [r3, #24] 2032:Drivers/CMSIS/Include/core_cm4.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 508 .loc 2 2032 3 is_stmt 1 view .LVU139 509 .loc 2 2032 18 is_stmt 0 view .LVU140 510 001a 0722 movs r2, #7 511 001c 1A61 str r2, [r3, #16] 2033:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk | 2034:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi 2035:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */ 512 .loc 2 2035 3 is_stmt 1 view .LVU141 513 .loc 2 2035 10 is_stmt 0 view .LVU142 514 001e 7047 bx lr 515 .L26: ARM GAS /tmp/ccPRqU3T.s page 66 2026:Drivers/CMSIS/Include/core_cm4.h **** } 516 .loc 2 2026 12 view .LVU143 517 0020 0120 movs r0, #1 518 .LVL38: 2026:Drivers/CMSIS/Include/core_cm4.h **** } 519 .loc 2 2026 12 view .LVU144 520 .LBE83: 521 .LBE82: 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 522 .loc 1 232 1 view .LVU145 523 0022 7047 bx lr 524 .L28: 525 .align 2 526 .L27: 527 0024 00ED00E0 .word -536810240 528 .cfi_endproc 529 .LFE135: 531 .section .text.HAL_MPU_Disable,"ax",%progbits 532 .align 1 533 .global HAL_MPU_Disable 534 .syntax unified 535 .thumb 536 .thumb_func 538 HAL_MPU_Disable: 539 .LFB136: 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @} 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Cortex control functions 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @verbatim 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ##### Peripheral Control functions ##### 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ============================================================================== 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** [..] 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** @endverbatim 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @{ 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U) 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Disables the MPU 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_Disable(void) 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 540 .loc 1 259 1 is_stmt 1 view -0 541 .cfi_startproc 542 @ args = 0, pretend = 0, frame = 0 543 @ frame_needed = 0, uses_anonymous_args = 0 544 @ link register save eliminated. ARM GAS /tmp/ccPRqU3T.s page 67 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __DMB(); 545 .loc 1 261 3 view .LVU147 546 .LBB86: 547 .LBI86: 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 548 .loc 3 888 27 view .LVU148 549 .LBB87: 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 550 .loc 3 890 3 view .LVU149 551 .syntax unified 552 @ 890 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 553 0000 BFF35F8F dmb 0xF 554 @ 0 "" 2 555 .thumb 556 .syntax unified 557 .LBE87: 558 .LBE86: 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Disable fault exceptions */ 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 559 .loc 1 264 3 view .LVU150 560 .loc 1 264 14 is_stmt 0 view .LVU151 561 0004 044B ldr r3, .L30 562 0006 5A6A ldr r2, [r3, #36] 563 0008 22F48032 bic r2, r2, #65536 564 000c 5A62 str r2, [r3, #36] 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->CTRL = 0U; 565 .loc 1 267 3 is_stmt 1 view .LVU152 566 .loc 1 267 13 is_stmt 0 view .LVU153 567 000e 0022 movs r2, #0 568 0010 C3F89420 str r2, [r3, #148] 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 569 .loc 1 268 1 view .LVU154 570 0014 7047 bx lr 571 .L31: 572 0016 00BF .align 2 573 .L30: 574 0018 00ED00E0 .word -536810240 575 .cfi_endproc 576 .LFE136: 578 .section .text.HAL_MPU_Enable,"ax",%progbits 579 .align 1 580 .global HAL_MPU_Enable 581 .syntax unified 582 .thumb ARM GAS /tmp/ccPRqU3T.s page 68 583 .thumb_func 585 HAL_MPU_Enable: 586 .LVL39: 587 .LFB137: 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Enable the MPU. 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be one of the following values: 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 588 .loc 1 282 1 is_stmt 1 view -0 589 .cfi_startproc 590 @ args = 0, pretend = 0, frame = 0 591 @ frame_needed = 0, uses_anonymous_args = 0 592 @ link register save eliminated. 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Enable the MPU */ 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 593 .loc 1 284 3 view .LVU156 594 .loc 1 284 27 is_stmt 0 view .LVU157 595 0000 40F00100 orr r0, r0, #1 596 .LVL40: 597 .loc 1 284 13 view .LVU158 598 0004 054B ldr r3, .L33 599 0006 C3F89400 str r0, [r3, #148] 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Enable fault exceptions */ 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 600 .loc 1 287 3 is_stmt 1 view .LVU159 601 .loc 1 287 14 is_stmt 0 view .LVU160 602 000a 5A6A ldr r2, [r3, #36] 603 000c 42F48032 orr r2, r2, #65536 604 0010 5A62 str r2, [r3, #36] 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Ensure MPU setting take effects */ 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __DSB(); 605 .loc 1 290 3 is_stmt 1 view .LVU161 606 .LBB88: 607 .LBI88: 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { 608 .loc 3 877 27 view .LVU162 609 .LBB89: 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } 610 .loc 3 879 3 view .LVU163 611 .syntax unified 612 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 613 0012 BFF34F8F dsb 0xF 614 @ 0 "" 2 615 .thumb 616 .syntax unified ARM GAS /tmp/ccPRqU3T.s page 69 617 .LBE89: 618 .LBE88: 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __ISB(); 619 .loc 1 291 3 view .LVU164 620 .LBB90: 621 .LBI90: 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { 622 .loc 3 866 27 view .LVU165 623 .LBB91: 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } 624 .loc 3 868 3 view .LVU166 625 .syntax unified 626 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 627 0016 BFF36F8F isb 0xF 628 @ 0 "" 2 629 .thumb 630 .syntax unified 631 .LBE91: 632 .LBE90: 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 633 .loc 1 292 1 is_stmt 0 view .LVU167 634 001a 7047 bx lr 635 .L34: 636 .align 2 637 .L33: 638 001c 00ED00E0 .word -536810240 639 .cfi_endproc 640 .LFE137: 642 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits 643 .align 1 644 .global HAL_MPU_ConfigRegion 645 .syntax unified 646 .thumb 647 .thumb_func 649 HAL_MPU_ConfigRegion: 650 .LVL41: 651 .LFB138: 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * the initialization and configuration information. 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 652 .loc 1 301 1 is_stmt 1 view -0 653 .cfi_startproc 654 @ args = 0, pretend = 0, frame = 0 655 @ frame_needed = 0, uses_anonymous_args = 0 656 @ link register save eliminated. 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); 657 .loc 1 303 3 view .LVU169 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); 658 .loc 1 304 3 view .LVU170 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ARM GAS /tmp/ccPRqU3T.s page 70 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Set the Region number */ 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; 659 .loc 1 307 3 view .LVU171 660 .loc 1 307 22 is_stmt 0 view .LVU172 661 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2 662 .loc 1 307 12 view .LVU173 663 0002 164B ldr r3, .L38 664 0004 C3F89820 str r2, [r3, #152] 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** if ((MPU_Init->Enable) != RESET) 665 .loc 1 309 3 is_stmt 1 view .LVU174 666 .loc 1 309 16 is_stmt 0 view .LVU175 667 0008 0378 ldrb r3, [r0] @ zero_extendqisi2 668 .loc 1 309 6 view .LVU176 669 000a FBB1 cbz r3, .L36 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); 670 .loc 1 312 5 is_stmt 1 view .LVU177 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); 671 .loc 1 313 5 view .LVU178 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); 672 .loc 1 314 5 view .LVU179 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); 673 .loc 1 315 5 view .LVU180 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); 674 .loc 1 316 5 view .LVU181 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); 675 .loc 1 317 5 view .LVU182 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); 676 .loc 1 318 5 view .LVU183 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); 677 .loc 1 319 5 view .LVU184 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; 678 .loc 1 321 5 view .LVU185 679 .loc 1 321 25 is_stmt 0 view .LVU186 680 000c 4368 ldr r3, [r0, #4] 681 .loc 1 321 15 view .LVU187 682 000e 134A ldr r2, .L38 683 0010 C2F89C30 str r3, [r2, #156] 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 684 .loc 1 322 5 is_stmt 1 view .LVU188 685 .loc 1 322 36 is_stmt 0 view .LVU189 686 0014 017B ldrb r1, [r0, #12] @ zero_extendqisi2 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 687 .loc 1 323 36 view .LVU190 688 0016 C37A ldrb r3, [r0, #11] @ zero_extendqisi2 689 .loc 1 323 62 view .LVU191 690 0018 1B06 lsls r3, r3, #24 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 691 .loc 1 322 84 view .LVU192 692 001a 43EA0173 orr r3, r3, r1, lsl #28 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 693 .loc 1 324 36 view .LVU193 694 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ARM GAS /tmp/ccPRqU3T.s page 71 695 .loc 1 323 84 view .LVU194 696 0020 43EAC143 orr r3, r3, r1, lsl #19 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 697 .loc 1 325 36 view .LVU195 698 0024 417B ldrb r1, [r0, #13] @ zero_extendqisi2 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 699 .loc 1 324 84 view .LVU196 700 0026 43EA8143 orr r3, r3, r1, lsl #18 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 701 .loc 1 326 36 view .LVU197 702 002a 817B ldrb r1, [r0, #14] @ zero_extendqisi2 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 703 .loc 1 325 84 view .LVU198 704 002c 43EA4143 orr r3, r3, r1, lsl #17 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 705 .loc 1 327 36 view .LVU199 706 0030 C17B ldrb r1, [r0, #15] @ zero_extendqisi2 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 707 .loc 1 326 84 view .LVU200 708 0032 43EA0143 orr r3, r3, r1, lsl #16 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 709 .loc 1 328 36 view .LVU201 710 0036 417A ldrb r1, [r0, #9] @ zero_extendqisi2 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 711 .loc 1 327 84 view .LVU202 712 0038 43EA0123 orr r3, r3, r1, lsl #8 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 713 .loc 1 329 36 view .LVU203 714 003c 017A ldrb r1, [r0, #8] @ zero_extendqisi2 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 715 .loc 1 328 84 view .LVU204 716 003e 43EA4103 orr r3, r3, r1, lsl #1 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 717 .loc 1 330 36 view .LVU205 718 0042 0178 ldrb r1, [r0] @ zero_extendqisi2 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 719 .loc 1 329 84 view .LVU206 720 0044 0B43 orrs r3, r3, r1 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 721 .loc 1 322 15 view .LVU207 722 0046 C2F8A030 str r3, [r2, #160] 723 004a 7047 bx lr 724 .L36: 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** else 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RBAR = 0x00U; 725 .loc 1 334 5 is_stmt 1 view .LVU208 726 .loc 1 334 15 is_stmt 0 view .LVU209 727 004c 034B ldr r3, .L38 728 004e 0022 movs r2, #0 729 0050 C3F89C20 str r2, [r3, #156] 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** MPU->RASR = 0x00U; 730 .loc 1 335 5 is_stmt 1 view .LVU210 731 .loc 1 335 15 is_stmt 0 view .LVU211 732 0054 C3F8A020 str r2, [r3, #160] 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } ARM GAS /tmp/ccPRqU3T.s page 72 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 733 .loc 1 337 1 view .LVU212 734 0058 7047 bx lr 735 .L39: 736 005a 00BF .align 2 737 .L38: 738 005c 00ED00E0 .word -536810240 739 .cfi_endproc 740 .LFE138: 742 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits 743 .align 1 744 .global HAL_NVIC_GetPriorityGrouping 745 .syntax unified 746 .thumb 747 .thumb_func 749 HAL_NVIC_GetPriorityGrouping: 750 .LFB139: 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 751 .loc 1 345 1 is_stmt 1 view -0 752 .cfi_startproc 753 @ args = 0, pretend = 0, frame = 0 754 @ frame_needed = 0, uses_anonymous_args = 0 755 @ link register save eliminated. 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); 756 .loc 1 347 3 view .LVU214 757 .LBB92: 758 .LBI92: 1676:Drivers/CMSIS/Include/core_cm4.h **** { 759 .loc 2 1676 26 view .LVU215 760 .LBB93: 1678:Drivers/CMSIS/Include/core_cm4.h **** } 761 .loc 2 1678 3 view .LVU216 1678:Drivers/CMSIS/Include/core_cm4.h **** } 762 .loc 2 1678 26 is_stmt 0 view .LVU217 763 0000 024B ldr r3, .L41 764 0002 D868 ldr r0, [r3, #12] 765 .LBE93: 766 .LBE92: 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 767 .loc 1 348 1 view .LVU218 768 0004 C0F30220 ubfx r0, r0, #8, #3 769 0008 7047 bx lr 770 .L42: 771 000a 00BF .align 2 772 .L41: 773 000c 00ED00E0 .word -536810240 774 .cfi_endproc 775 .LFE139: 777 .section .text.HAL_NVIC_GetPriority,"ax",%progbits ARM GAS /tmp/ccPRqU3T.s page 73 778 .align 1 779 .global HAL_NVIC_GetPriority 780 .syntax unified 781 .thumb 782 .thumb_func 784 HAL_NVIC_GetPriority: 785 .LVL42: 786 .LFB140: 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param PriorityGroup the priority grouping bits length. 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be one of the following values: 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 4 bits for subpriority 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 3 bits for subpriority 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 2 bits for subpriority 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 1 bits for subpriority 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * 0 bits for subpriority 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0). 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 787 .loc 1 372 1 is_stmt 1 view -0 788 .cfi_startproc 789 @ args = 0, pretend = 0, frame = 0 790 @ frame_needed = 0, uses_anonymous_args = 0 791 .loc 1 372 1 is_stmt 0 view .LVU220 792 0000 10B5 push {r4, lr} 793 .LCFI1: 794 .cfi_def_cfa_offset 8 795 .cfi_offset 4, -8 796 .cfi_offset 14, -4 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 797 .loc 1 374 3 is_stmt 1 view .LVU221 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); 798 .loc 1 376 3 view .LVU222 799 .LVL43: 800 .LBB98: 801 .LBI98: 1838:Drivers/CMSIS/Include/core_cm4.h **** { 802 .loc 2 1838 26 view .LVU223 803 .LBB99: 1841:Drivers/CMSIS/Include/core_cm4.h **** { 804 .loc 2 1841 3 view .LVU224 1841:Drivers/CMSIS/Include/core_cm4.h **** { ARM GAS /tmp/ccPRqU3T.s page 74 805 .loc 2 1841 6 is_stmt 0 view .LVU225 806 0002 0028 cmp r0, #0 807 .LVL44: 1841:Drivers/CMSIS/Include/core_cm4.h **** { 808 .loc 2 1841 6 view .LVU226 809 0004 22DB blt .L44 1843:Drivers/CMSIS/Include/core_cm4.h **** } 810 .loc 2 1843 5 is_stmt 1 view .LVU227 1843:Drivers/CMSIS/Include/core_cm4.h **** } 811 .loc 2 1843 31 is_stmt 0 view .LVU228 812 0006 00F16040 add r0, r0, #-536870912 813 000a 00F56140 add r0, r0, #57600 814 000e 90F80003 ldrb r0, [r0, #768] @ zero_extendqisi2 1843:Drivers/CMSIS/Include/core_cm4.h **** } 815 .loc 2 1843 64 view .LVU229 816 0012 0009 lsrs r0, r0, #4 817 .L45: 818 .LVL45: 1843:Drivers/CMSIS/Include/core_cm4.h **** } 819 .loc 2 1843 64 view .LVU230 820 .LBE99: 821 .LBE98: 822 .LBB101: 823 .LBI101: 1890:Drivers/CMSIS/Include/core_cm4.h **** { 824 .loc 2 1890 22 is_stmt 1 view .LVU231 825 .LBB102: 1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; 826 .loc 2 1892 3 view .LVU232 1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; 827 .loc 2 1892 12 is_stmt 0 view .LVU233 828 0014 01F00701 and r1, r1, #7 829 .LVL46: 1893:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; 830 .loc 2 1893 3 is_stmt 1 view .LVU234 1894:Drivers/CMSIS/Include/core_cm4.h **** 831 .loc 2 1894 3 view .LVU235 1896:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 832 .loc 2 1896 3 view .LVU236 1896:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 833 .loc 2 1896 31 is_stmt 0 view .LVU237 834 0018 C1F1070C rsb ip, r1, #7 1896:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 835 .loc 2 1896 23 view .LVU238 836 001c BCF1040F cmp ip, #4 837 0020 28BF it cs 838 0022 4FF0040C movcs ip, #4 839 .LVL47: 1897:Drivers/CMSIS/Include/core_cm4.h **** 840 .loc 2 1897 3 is_stmt 1 view .LVU239 1897:Drivers/CMSIS/Include/core_cm4.h **** 841 .loc 2 1897 44 is_stmt 0 view .LVU240 842 0026 0C1D adds r4, r1, #4 1897:Drivers/CMSIS/Include/core_cm4.h **** 843 .loc 2 1897 109 view .LVU241 844 0028 062C cmp r4, #6 845 002a 15D9 bls .L47 ARM GAS /tmp/ccPRqU3T.s page 75 846 002c 0339 subs r1, r1, #3 847 .LVL48: 848 .L46: 1899:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 849 .loc 2 1899 3 is_stmt 1 view .LVU242 1899:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 850 .loc 2 1899 33 is_stmt 0 view .LVU243 851 002e 20FA01F4 lsr r4, r0, r1 852 .LVL49: 1899:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 853 .loc 2 1899 53 view .LVU244 854 0032 4FF0FF3E mov lr, #-1 855 0036 0EFA0CFC lsl ip, lr, ip 856 .LVL50: 1899:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 857 .loc 2 1899 53 view .LVU245 858 003a 24EA0C04 bic r4, r4, ip 1899:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 859 .loc 2 1899 21 view .LVU246 860 003e 1460 str r4, [r2] 1900:Drivers/CMSIS/Include/core_cm4.h **** } 861 .loc 2 1900 3 is_stmt 1 view .LVU247 1900:Drivers/CMSIS/Include/core_cm4.h **** } 862 .loc 2 1900 53 is_stmt 0 view .LVU248 863 0040 0EFA01F1 lsl r1, lr, r1 864 .LVL51: 1900:Drivers/CMSIS/Include/core_cm4.h **** } 865 .loc 2 1900 53 view .LVU249 866 0044 20EA0100 bic r0, r0, r1 867 .LVL52: 1900:Drivers/CMSIS/Include/core_cm4.h **** } 868 .loc 2 1900 21 view .LVU250 869 0048 1860 str r0, [r3] 870 .LVL53: 1900:Drivers/CMSIS/Include/core_cm4.h **** } 871 .loc 2 1900 21 view .LVU251 872 .LBE102: 873 .LBE101: 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 874 .loc 1 377 1 view .LVU252 875 004a 10BD pop {r4, pc} 876 .LVL54: 877 .L44: 878 .LBB104: 879 .LBB100: 1847:Drivers/CMSIS/Include/core_cm4.h **** } 880 .loc 2 1847 5 is_stmt 1 view .LVU253 1847:Drivers/CMSIS/Include/core_cm4.h **** } 881 .loc 2 1847 50 is_stmt 0 view .LVU254 882 004c 00F00F00 and r0, r0, #15 1847:Drivers/CMSIS/Include/core_cm4.h **** } 883 .loc 2 1847 31 view .LVU255 884 0050 024C ldr r4, .L49 885 0052 205C ldrb r0, [r4, r0] @ zero_extendqisi2 1847:Drivers/CMSIS/Include/core_cm4.h **** } 886 .loc 2 1847 64 view .LVU256 887 0054 0009 lsrs r0, r0, #4 ARM GAS /tmp/ccPRqU3T.s page 76 888 0056 DDE7 b .L45 889 .LVL55: 890 .L47: 1847:Drivers/CMSIS/Include/core_cm4.h **** } 891 .loc 2 1847 64 view .LVU257 892 .LBE100: 893 .LBE104: 894 .LBB105: 895 .LBB103: 1897:Drivers/CMSIS/Include/core_cm4.h **** 896 .loc 2 1897 109 view .LVU258 897 0058 0021 movs r1, #0 898 .LVL56: 1897:Drivers/CMSIS/Include/core_cm4.h **** 899 .loc 2 1897 109 view .LVU259 900 005a E8E7 b .L46 901 .L50: 902 .align 2 903 .L49: 904 005c 14ED00E0 .word -536810220 905 .LBE103: 906 .LBE105: 907 .cfi_endproc 908 .LFE140: 910 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits 911 .align 1 912 .global HAL_NVIC_SetPendingIRQ 913 .syntax unified 914 .thumb 915 .thumb_func 917 HAL_NVIC_SetPendingIRQ: 918 .LVL57: 919 .LFB141: 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 920 .loc 1 387 1 is_stmt 1 view -0 921 .cfi_startproc 922 @ args = 0, pretend = 0, frame = 0 923 @ frame_needed = 0, uses_anonymous_args = 0 924 @ link register save eliminated. 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 925 .loc 1 389 3 view .LVU261 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Set interrupt pending */ 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); 926 .loc 1 392 3 view .LVU262 927 .LBB106: 928 .LBI106: ARM GAS /tmp/ccPRqU3T.s page 77 1762:Drivers/CMSIS/Include/core_cm4.h **** { 929 .loc 2 1762 22 view .LVU263 930 .LBB107: 1764:Drivers/CMSIS/Include/core_cm4.h **** { 931 .loc 2 1764 3 view .LVU264 1764:Drivers/CMSIS/Include/core_cm4.h **** { 932 .loc 2 1764 6 is_stmt 0 view .LVU265 933 0000 0028 cmp r0, #0 934 .LVL58: 1764:Drivers/CMSIS/Include/core_cm4.h **** { 935 .loc 2 1764 6 view .LVU266 936 0002 08DB blt .L51 1766:Drivers/CMSIS/Include/core_cm4.h **** } 937 .loc 2 1766 5 is_stmt 1 view .LVU267 1766:Drivers/CMSIS/Include/core_cm4.h **** } 938 .loc 2 1766 81 is_stmt 0 view .LVU268 939 0004 00F01F02 and r2, r0, #31 1766:Drivers/CMSIS/Include/core_cm4.h **** } 940 .loc 2 1766 34 view .LVU269 941 0008 4009 lsrs r0, r0, #5 1766:Drivers/CMSIS/Include/core_cm4.h **** } 942 .loc 2 1766 45 view .LVU270 943 000a 0123 movs r3, #1 944 000c 9340 lsls r3, r3, r2 1766:Drivers/CMSIS/Include/core_cm4.h **** } 945 .loc 2 1766 43 view .LVU271 946 000e 4030 adds r0, r0, #64 947 0010 014A ldr r2, .L53 948 0012 42F82030 str r3, [r2, r0, lsl #2] 949 .LVL59: 950 .L51: 1766:Drivers/CMSIS/Include/core_cm4.h **** } 951 .loc 2 1766 43 view .LVU272 952 .LBE107: 953 .LBE106: 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 954 .loc 1 393 1 view .LVU273 955 0016 7047 bx lr 956 .L54: 957 .align 2 958 .L53: 959 0018 00E100E0 .word -536813312 960 .cfi_endproc 961 .LFE141: 963 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits 964 .align 1 965 .global HAL_NVIC_GetPendingIRQ 966 .syntax unified 967 .thumb 968 .thumb_func 970 HAL_NVIC_GetPendingIRQ: 971 .LVL60: 972 .LFB142: 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). ARM GAS /tmp/ccPRqU3T.s page 78 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * - 1 Interrupt status is pending. 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 973 .loc 1 405 1 is_stmt 1 view -0 974 .cfi_startproc 975 @ args = 0, pretend = 0, frame = 0 976 @ frame_needed = 0, uses_anonymous_args = 0 977 @ link register save eliminated. 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 978 .loc 1 407 3 view .LVU275 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Return 1 if pending else 0 */ 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); 979 .loc 1 410 3 view .LVU276 980 .LBB108: 981 .LBI108: 1743:Drivers/CMSIS/Include/core_cm4.h **** { 982 .loc 2 1743 26 view .LVU277 983 .LBB109: 1745:Drivers/CMSIS/Include/core_cm4.h **** { 984 .loc 2 1745 3 view .LVU278 1745:Drivers/CMSIS/Include/core_cm4.h **** { 985 .loc 2 1745 6 is_stmt 0 view .LVU279 986 0000 0028 cmp r0, #0 987 .LVL61: 1745:Drivers/CMSIS/Include/core_cm4.h **** { 988 .loc 2 1745 6 view .LVU280 989 0002 0BDB blt .L57 1747:Drivers/CMSIS/Include/core_cm4.h **** } 990 .loc 2 1747 5 is_stmt 1 view .LVU281 1747:Drivers/CMSIS/Include/core_cm4.h **** } 991 .loc 2 1747 54 is_stmt 0 view .LVU282 992 0004 4309 lsrs r3, r0, #5 1747:Drivers/CMSIS/Include/core_cm4.h **** } 993 .loc 2 1747 35 view .LVU283 994 0006 4033 adds r3, r3, #64 995 0008 054A ldr r2, .L58 996 000a 52F82330 ldr r3, [r2, r3, lsl #2] 1747:Drivers/CMSIS/Include/core_cm4.h **** } 997 .loc 2 1747 91 view .LVU284 998 000e 00F01F00 and r0, r0, #31 1747:Drivers/CMSIS/Include/core_cm4.h **** } 999 .loc 2 1747 103 view .LVU285 1000 0012 23FA00F0 lsr r0, r3, r0 1747:Drivers/CMSIS/Include/core_cm4.h **** } 1001 .loc 2 1747 12 view .LVU286 1002 0016 00F00100 and r0, r0, #1 1003 001a 7047 bx lr 1004 .L57: 1751:Drivers/CMSIS/Include/core_cm4.h **** } 1005 .loc 2 1751 11 view .LVU287 ARM GAS /tmp/ccPRqU3T.s page 79 1006 001c 0020 movs r0, #0 1007 .LVL62: 1751:Drivers/CMSIS/Include/core_cm4.h **** } 1008 .loc 2 1751 11 view .LVU288 1009 .LBE109: 1010 .LBE108: 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1011 .loc 1 411 1 view .LVU289 1012 001e 7047 bx lr 1013 .L59: 1014 .align 2 1015 .L58: 1016 0020 00E100E0 .word -536813312 1017 .cfi_endproc 1018 .LFE142: 1020 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits 1021 .align 1 1022 .global HAL_NVIC_ClearPendingIRQ 1023 .syntax unified 1024 .thumb 1025 .thumb_func 1027 HAL_NVIC_ClearPendingIRQ: 1028 .LVL63: 1029 .LFB143: 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number. 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 1030 .loc 1 421 1 is_stmt 1 view -0 1031 .cfi_startproc 1032 @ args = 0, pretend = 0, frame = 0 1033 @ frame_needed = 0, uses_anonymous_args = 0 1034 @ link register save eliminated. 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 1035 .loc 1 423 3 view .LVU291 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Clear pending interrupt */ 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); 1036 .loc 1 426 3 view .LVU292 1037 .LBB110: 1038 .LBI110: 1777:Drivers/CMSIS/Include/core_cm4.h **** { 1039 .loc 2 1777 22 view .LVU293 1040 .LBB111: 1779:Drivers/CMSIS/Include/core_cm4.h **** { 1041 .loc 2 1779 3 view .LVU294 1779:Drivers/CMSIS/Include/core_cm4.h **** { 1042 .loc 2 1779 6 is_stmt 0 view .LVU295 1043 0000 0028 cmp r0, #0 1044 .LVL64: ARM GAS /tmp/ccPRqU3T.s page 80 1779:Drivers/CMSIS/Include/core_cm4.h **** { 1045 .loc 2 1779 6 view .LVU296 1046 0002 08DB blt .L60 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1047 .loc 2 1781 5 is_stmt 1 view .LVU297 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1048 .loc 2 1781 81 is_stmt 0 view .LVU298 1049 0004 00F01F02 and r2, r0, #31 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1050 .loc 2 1781 34 view .LVU299 1051 0008 4009 lsrs r0, r0, #5 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1052 .loc 2 1781 45 view .LVU300 1053 000a 0123 movs r3, #1 1054 000c 9340 lsls r3, r3, r2 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1055 .loc 2 1781 43 view .LVU301 1056 000e 6030 adds r0, r0, #96 1057 0010 014A ldr r2, .L62 1058 0012 42F82030 str r3, [r2, r0, lsl #2] 1059 .LVL65: 1060 .L60: 1781:Drivers/CMSIS/Include/core_cm4.h **** } 1061 .loc 2 1781 43 view .LVU302 1062 .LBE111: 1063 .LBE110: 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1064 .loc 1 427 1 view .LVU303 1065 0016 7047 bx lr 1066 .L63: 1067 .align 2 1068 .L62: 1069 0018 00E100E0 .word -536813312 1070 .cfi_endproc 1071 .LFE143: 1073 .section .text.HAL_NVIC_GetActive,"ax",%progbits 1074 .align 1 1075 .global HAL_NVIC_GetActive 1076 .syntax unified 1077 .thumb 1078 .thumb_func 1080 HAL_NVIC_GetActive: 1081 .LVL66: 1082 .LFB144: 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param IRQn External interrupt number 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * - 1 Interrupt status is pending. 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 1083 .loc 1 438 1 is_stmt 1 view -0 1084 .cfi_startproc ARM GAS /tmp/ccPRqU3T.s page 81 1085 @ args = 0, pretend = 0, frame = 0 1086 @ frame_needed = 0, uses_anonymous_args = 0 1087 @ link register save eliminated. 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 1088 .loc 1 440 3 view .LVU305 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Return 1 if active else 0 */ 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** return NVIC_GetActive(IRQn); 1089 .loc 1 443 3 view .LVU306 1090 .LBB112: 1091 .LBI112: 1794:Drivers/CMSIS/Include/core_cm4.h **** { 1092 .loc 2 1794 26 view .LVU307 1093 .LBB113: 1796:Drivers/CMSIS/Include/core_cm4.h **** { 1094 .loc 2 1796 3 view .LVU308 1796:Drivers/CMSIS/Include/core_cm4.h **** { 1095 .loc 2 1796 6 is_stmt 0 view .LVU309 1096 0000 0028 cmp r0, #0 1097 .LVL67: 1796:Drivers/CMSIS/Include/core_cm4.h **** { 1098 .loc 2 1796 6 view .LVU310 1099 0002 0BDB blt .L66 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1100 .loc 2 1798 5 is_stmt 1 view .LVU311 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1101 .loc 2 1798 54 is_stmt 0 view .LVU312 1102 0004 4309 lsrs r3, r0, #5 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1103 .loc 2 1798 35 view .LVU313 1104 0006 8033 adds r3, r3, #128 1105 0008 054A ldr r2, .L67 1106 000a 52F82330 ldr r3, [r2, r3, lsl #2] 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1107 .loc 2 1798 91 view .LVU314 1108 000e 00F01F00 and r0, r0, #31 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1109 .loc 2 1798 103 view .LVU315 1110 0012 23FA00F0 lsr r0, r3, r0 1798:Drivers/CMSIS/Include/core_cm4.h **** } 1111 .loc 2 1798 12 view .LVU316 1112 0016 00F00100 and r0, r0, #1 1113 001a 7047 bx lr 1114 .L66: 1802:Drivers/CMSIS/Include/core_cm4.h **** } 1115 .loc 2 1802 11 view .LVU317 1116 001c 0020 movs r0, #0 1117 .LVL68: 1802:Drivers/CMSIS/Include/core_cm4.h **** } 1118 .loc 2 1802 11 view .LVU318 1119 .LBE113: 1120 .LBE112: 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1121 .loc 1 444 1 view .LVU319 1122 001e 7047 bx lr 1123 .L68: ARM GAS /tmp/ccPRqU3T.s page 82 1124 .align 2 1125 .L67: 1126 0020 00E100E0 .word -536813312 1127 .cfi_endproc 1128 .LFE144: 1130 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits 1131 .align 1 1132 .global HAL_SYSTICK_CLKSourceConfig 1133 .syntax unified 1134 .thumb 1135 .thumb_func 1137 HAL_SYSTICK_CLKSourceConfig: 1138 .LVL69: 1139 .LFB145: 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief Configures the SysTick clock source. 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * This parameter can be one of the following values: 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 1140 .loc 1 455 1 is_stmt 1 view -0 1141 .cfi_startproc 1142 @ args = 0, pretend = 0, frame = 0 1143 @ frame_needed = 0, uses_anonymous_args = 0 1144 @ link register save eliminated. 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* Check the parameters */ 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 1145 .loc 1 457 3 view .LVU321 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 1146 .loc 1 458 3 view .LVU322 1147 .loc 1 458 6 is_stmt 0 view .LVU323 1148 0000 0428 cmp r0, #4 1149 0002 06D0 beq .L72 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** else 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 1150 .loc 1 464 5 is_stmt 1 view .LVU324 1151 .loc 1 464 19 is_stmt 0 view .LVU325 1152 0004 4FF0E022 mov r2, #-536813568 1153 0008 1369 ldr r3, [r2, #16] 1154 000a 23F00403 bic r3, r3, #4 1155 000e 1361 str r3, [r2, #16] 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1156 .loc 1 466 1 view .LVU326 1157 0010 7047 bx lr 1158 .L72: 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1159 .loc 1 460 5 is_stmt 1 view .LVU327 ARM GAS /tmp/ccPRqU3T.s page 83 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1160 .loc 1 460 19 is_stmt 0 view .LVU328 1161 0012 4FF0E022 mov r2, #-536813568 1162 0016 1369 ldr r3, [r2, #16] 1163 0018 43F00403 orr r3, r3, #4 1164 001c 1361 str r3, [r2, #16] 1165 001e 7047 bx lr 1166 .cfi_endproc 1167 .LFE145: 1169 .section .text.HAL_SYSTICK_Callback,"ax",%progbits 1170 .align 1 1171 .weak HAL_SYSTICK_Callback 1172 .syntax unified 1173 .thumb 1174 .thumb_func 1176 HAL_SYSTICK_Callback: 1177 .LFB147: 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /** 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @brief SYSTICK callback. 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** * @retval None 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** { 1178 .loc 1 482 1 is_stmt 1 view -0 1179 .cfi_startproc 1180 @ args = 0, pretend = 0, frame = 0 1181 @ frame_needed = 0, uses_anonymous_args = 0 1182 @ link register save eliminated. 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** */ 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1183 .loc 1 486 1 view .LVU330 1184 0000 7047 bx lr 1185 .cfi_endproc 1186 .LFE147: 1188 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits 1189 .align 1 1190 .global HAL_SYSTICK_IRQHandler 1191 .syntax unified 1192 .thumb 1193 .thumb_func 1195 HAL_SYSTICK_IRQHandler: 1196 .LFB146: 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 1197 .loc 1 473 1 view -0 1198 .cfi_startproc ARM GAS /tmp/ccPRqU3T.s page 84 1199 @ args = 0, pretend = 0, frame = 0 1200 @ frame_needed = 0, uses_anonymous_args = 0 1201 0000 08B5 push {r3, lr} 1202 .LCFI2: 1203 .cfi_def_cfa_offset 8 1204 .cfi_offset 3, -8 1205 .cfi_offset 14, -4 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** } 1206 .loc 1 474 3 view .LVU332 1207 0002 FFF7FEFF bl HAL_SYSTICK_Callback 1208 .LVL70: 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c **** 1209 .loc 1 475 1 is_stmt 0 view .LVU333 1210 0006 08BD pop {r3, pc} 1211 .cfi_endproc 1212 .LFE146: 1214 .text 1215 .Letext0: 1216 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h" 1217 .file 5 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/ 1218 .file 6 "/home/gitc/\346\241\214\351\235\242/gcc-arm-none-eabi-10.3-2021.10/arm-none-eabi/include/ 1219 .file 7 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 1220 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h" ARM GAS /tmp/ccPRqU3T.s page 85 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f4xx_hal_cortex.c /tmp/ccPRqU3T.s:20 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t /tmp/ccPRqU3T.s:26 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping /tmp/ccPRqU3T.s:82 .text.HAL_NVIC_SetPriorityGrouping:0000000000000020 $d /tmp/ccPRqU3T.s:87 .text.HAL_NVIC_SetPriority:0000000000000000 $t /tmp/ccPRqU3T.s:93 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority /tmp/ccPRqU3T.s:236 .text.HAL_NVIC_SetPriority:0000000000000068 $d /tmp/ccPRqU3T.s:242 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t /tmp/ccPRqU3T.s:248 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ /tmp/ccPRqU3T.s:289 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d /tmp/ccPRqU3T.s:294 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t /tmp/ccPRqU3T.s:300 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ /tmp/ccPRqU3T.s:371 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d /tmp/ccPRqU3T.s:376 .text.HAL_NVIC_SystemReset:0000000000000000 $t /tmp/ccPRqU3T.s:382 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset /tmp/ccPRqU3T.s:448 .text.HAL_NVIC_SystemReset:000000000000001c $d /tmp/ccPRqU3T.s:456 .text.HAL_SYSTICK_Config:0000000000000000 $t /tmp/ccPRqU3T.s:462 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config /tmp/ccPRqU3T.s:527 .text.HAL_SYSTICK_Config:0000000000000024 $d /tmp/ccPRqU3T.s:532 .text.HAL_MPU_Disable:0000000000000000 $t /tmp/ccPRqU3T.s:538 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable /tmp/ccPRqU3T.s:574 .text.HAL_MPU_Disable:0000000000000018 $d /tmp/ccPRqU3T.s:579 .text.HAL_MPU_Enable:0000000000000000 $t /tmp/ccPRqU3T.s:585 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable /tmp/ccPRqU3T.s:638 .text.HAL_MPU_Enable:000000000000001c $d /tmp/ccPRqU3T.s:643 .text.HAL_MPU_ConfigRegion:0000000000000000 $t /tmp/ccPRqU3T.s:649 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion /tmp/ccPRqU3T.s:738 .text.HAL_MPU_ConfigRegion:000000000000005c $d /tmp/ccPRqU3T.s:743 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t /tmp/ccPRqU3T.s:749 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping /tmp/ccPRqU3T.s:773 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d /tmp/ccPRqU3T.s:778 .text.HAL_NVIC_GetPriority:0000000000000000 $t /tmp/ccPRqU3T.s:784 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority /tmp/ccPRqU3T.s:904 .text.HAL_NVIC_GetPriority:000000000000005c $d /tmp/ccPRqU3T.s:911 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t /tmp/ccPRqU3T.s:917 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ /tmp/ccPRqU3T.s:959 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d /tmp/ccPRqU3T.s:964 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t /tmp/ccPRqU3T.s:970 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ /tmp/ccPRqU3T.s:1016 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d /tmp/ccPRqU3T.s:1021 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t /tmp/ccPRqU3T.s:1027 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ /tmp/ccPRqU3T.s:1069 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d /tmp/ccPRqU3T.s:1074 .text.HAL_NVIC_GetActive:0000000000000000 $t /tmp/ccPRqU3T.s:1080 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive /tmp/ccPRqU3T.s:1126 .text.HAL_NVIC_GetActive:0000000000000020 $d /tmp/ccPRqU3T.s:1131 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t /tmp/ccPRqU3T.s:1137 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig /tmp/ccPRqU3T.s:1170 .text.HAL_SYSTICK_Callback:0000000000000000 $t /tmp/ccPRqU3T.s:1176 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback /tmp/ccPRqU3T.s:1189 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t /tmp/ccPRqU3T.s:1195 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler NO UNDEFINED SYMBOLS