// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
//       refer to STM32F40x STM32F41x datasheets
//       refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
//  Debug MCU configuration register (DBGMCU_CR)
//     DBG_STANDBY               Debug Standby Mode
//     DBG_STOP                  Debug Stop Mode
//     DBG_SLEEP                 Debug Sleep Mode
// 
DbgMCU_CR = 0x00000007;
//  Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
//                                    Reserved bits must be kept at reset value
//    DBG_CAN2_STOP             CAN2 stopped when core is halted
//    DBG_CAN1_STOP             CAN2 stopped when core is halted
//    DBG_I2C3_SMBUS_TIMEOUT    I2C3 SMBUS timeout mode stopped when core is halted
//    DBG_I2C2_SMBUS_TIMEOUT    I2C2 SMBUS timeout mode stopped when core is halted
//    DBG_I2C1_SMBUS_TIMEOUT    I2C1 SMBUS timeout mode stopped when core is halted
//    DBG_IWDG_STOP             Independent watchdog stopped when core is halted
//    DBG_WWDG_STOP             Window watchdog stopped when core is halted
//    DBG_RTC_STOP              RTC stopped when core is halted
//     DBG_TIM14_STOP            TIM14 counter stopped when core is halted
//     DBG_TIM13_STOP            TIM13 counter stopped when core is halted
//     DBG_TIM12_STOP            TIM12 counter stopped when core is halted
//     DBG_TIM7_STOP             TIM7 counter stopped when core is halted
//     DBG_TIM6_STOP             TIM6 counter stopped when core is halted
//     DBG_TIM5_STOP             TIM5 counter stopped when core is halted
//     DBG_TIM4_STOP             TIM4 counter stopped when core is halted
//     DBG_TIM3_STOP             TIM3 counter stopped when core is halted
//     DBG_TIM2_STOP             TIM2 counter stopped when core is halted
// 
DbgMCU_APB1_Fz = 0x00000000;
//  Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
//                                    Reserved bits must be kept at reset value
//    DBG_TIM11_STOP            TIM11 counter stopped when core is halted
//    DBG_TIM10_STOP            TIM10 counter stopped when core is halted
//    DBG_TIM9_STOP             TIM9 counter stopped when core is halted
//     DBG_TIM8_STOP             TIM8 counter stopped when core is halted
//     DBG_TIM1_STOP             TIM1 counter stopped when core is halted
// 
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>