coffeeproject20230512/coffeeproject/app/main/CTO20220622/build/system_stm32f4xx.lst

ARM GAS  /tmp/ccwdC0Nl.s 			page 1


   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 1
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"system_stm32f4xx.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.SystemInit,"ax",%progbits
  18              		.align	1
  19              		.global	SystemInit
  20              		.syntax unified
  21              		.thumb
  22              		.thumb_func
  23              		.fpu fpv4-sp-d16
  25              	SystemInit:
  26              	.LFB130:
  27              		.file 1 "Src/system_stm32f4xx.c"
   1:Src/system_stm32f4xx.c **** /**
   2:Src/system_stm32f4xx.c ****   ******************************************************************************
   3:Src/system_stm32f4xx.c ****   * @file    system_stm32f4xx.c
   4:Src/system_stm32f4xx.c ****   * @author  MCD Application Team
   5:Src/system_stm32f4xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6:Src/system_stm32f4xx.c ****   *
   7:Src/system_stm32f4xx.c ****   *   This file provides two functions and one global variable to be called from 
   8:Src/system_stm32f4xx.c ****   *   user application:
   9:Src/system_stm32f4xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Src/system_stm32f4xx.c ****   *                      before branch to main program. This call is made inside
  11:Src/system_stm32f4xx.c ****   *                      the "startup_stm32f4xx.s" file.
  12:Src/system_stm32f4xx.c ****   *
  13:Src/system_stm32f4xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Src/system_stm32f4xx.c ****   *                                  by the user application to setup the SysTick 
  15:Src/system_stm32f4xx.c ****   *                                  timer or configure other parameters.
  16:Src/system_stm32f4xx.c ****   *                                     
  17:Src/system_stm32f4xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Src/system_stm32f4xx.c ****   *                                 be called whenever the core clock is changed
  19:Src/system_stm32f4xx.c ****   *                                 during program execution.
  20:Src/system_stm32f4xx.c ****   *
  21:Src/system_stm32f4xx.c ****   *
  22:Src/system_stm32f4xx.c ****   ******************************************************************************
  23:Src/system_stm32f4xx.c ****   * @attention
  24:Src/system_stm32f4xx.c ****   *
  25:Src/system_stm32f4xx.c ****   * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  26:Src/system_stm32f4xx.c ****   *
  27:Src/system_stm32f4xx.c ****   * Redistribution and use in source and binary forms, with or without modification,
  28:Src/system_stm32f4xx.c ****   * are permitted provided that the following conditions are met:
  29:Src/system_stm32f4xx.c ****   *   1. Redistributions of source code must retain the above copyright notice,
  30:Src/system_stm32f4xx.c ****   *      this list of conditions and the following disclaimer.
  31:Src/system_stm32f4xx.c ****   *   2. Redistributions in binary form must reproduce the above copyright notice,
ARM GAS  /tmp/ccwdC0Nl.s 			page 2


  32:Src/system_stm32f4xx.c ****   *      this list of conditions and the following disclaimer in the documentation
  33:Src/system_stm32f4xx.c ****   *      and/or other materials provided with the distribution.
  34:Src/system_stm32f4xx.c ****   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  35:Src/system_stm32f4xx.c ****   *      may be used to endorse or promote products derived from this software
  36:Src/system_stm32f4xx.c ****   *      without specific prior written permission.
  37:Src/system_stm32f4xx.c ****   *
  38:Src/system_stm32f4xx.c ****   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  39:Src/system_stm32f4xx.c ****   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  40:Src/system_stm32f4xx.c ****   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  41:Src/system_stm32f4xx.c ****   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  42:Src/system_stm32f4xx.c ****   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  43:Src/system_stm32f4xx.c ****   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  44:Src/system_stm32f4xx.c ****   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  45:Src/system_stm32f4xx.c ****   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  46:Src/system_stm32f4xx.c ****   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47:Src/system_stm32f4xx.c ****   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48:Src/system_stm32f4xx.c ****   *
  49:Src/system_stm32f4xx.c ****   ******************************************************************************
  50:Src/system_stm32f4xx.c ****   */
  51:Src/system_stm32f4xx.c **** 
  52:Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
  53:Src/system_stm32f4xx.c ****   * @{
  54:Src/system_stm32f4xx.c ****   */
  55:Src/system_stm32f4xx.c **** 
  56:Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
  57:Src/system_stm32f4xx.c ****   * @{
  58:Src/system_stm32f4xx.c ****   */  
  59:Src/system_stm32f4xx.c ****   
  60:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
  61:Src/system_stm32f4xx.c ****   * @{
  62:Src/system_stm32f4xx.c ****   */
  63:Src/system_stm32f4xx.c **** 
  64:Src/system_stm32f4xx.c **** 
  65:Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
  66:Src/system_stm32f4xx.c **** 
  67:Src/system_stm32f4xx.c **** #if !defined  (HSE_VALUE) 
  68:Src/system_stm32f4xx.c ****   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
  69:Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
  70:Src/system_stm32f4xx.c **** 
  71:Src/system_stm32f4xx.c **** #if !defined  (HSI_VALUE)
  72:Src/system_stm32f4xx.c ****   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  73:Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
  74:Src/system_stm32f4xx.c **** 
  75:Src/system_stm32f4xx.c **** /**
  76:Src/system_stm32f4xx.c ****   * @}
  77:Src/system_stm32f4xx.c ****   */
  78:Src/system_stm32f4xx.c **** 
  79:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
  80:Src/system_stm32f4xx.c ****   * @{
  81:Src/system_stm32f4xx.c ****   */
  82:Src/system_stm32f4xx.c **** 
  83:Src/system_stm32f4xx.c **** /**
  84:Src/system_stm32f4xx.c ****   * @}
  85:Src/system_stm32f4xx.c ****   */
  86:Src/system_stm32f4xx.c **** 
  87:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
  88:Src/system_stm32f4xx.c ****   * @{
ARM GAS  /tmp/ccwdC0Nl.s 			page 3


  89:Src/system_stm32f4xx.c ****   */
  90:Src/system_stm32f4xx.c **** 
  91:Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
  92:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
  93:Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  94:Src/system_stm32f4xx.c ****  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  95:Src/system_stm32f4xx.c ****  || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
  96:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
  97:Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
  98:Src/system_stm32f4xx.c ****           STM32F412Zx || STM32F412Vx */
  99:Src/system_stm32f4xx.c ****  
 100:Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
 101:Src/system_stm32f4xx.c ****  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
 102:Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
 103:Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
 104:Src/system_stm32f4xx.c ****           STM32F479xx */
 105:Src/system_stm32f4xx.c **** 
 106:Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
 107:Src/system_stm32f4xx.c ****      Internal SRAM. */
 108:Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
 109:Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
 110:Src/system_stm32f4xx.c ****                                    This value must be a multiple of 0x200. */
 111:Src/system_stm32f4xx.c **** /******************************************************************************/
 112:Src/system_stm32f4xx.c **** 
 113:Src/system_stm32f4xx.c **** /**
 114:Src/system_stm32f4xx.c ****   * @}
 115:Src/system_stm32f4xx.c ****   */
 116:Src/system_stm32f4xx.c **** 
 117:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
 118:Src/system_stm32f4xx.c ****   * @{
 119:Src/system_stm32f4xx.c ****   */
 120:Src/system_stm32f4xx.c **** 
 121:Src/system_stm32f4xx.c **** /**
 122:Src/system_stm32f4xx.c ****   * @}
 123:Src/system_stm32f4xx.c ****   */
 124:Src/system_stm32f4xx.c **** 
 125:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
 126:Src/system_stm32f4xx.c ****   * @{
 127:Src/system_stm32f4xx.c ****   */
 128:Src/system_stm32f4xx.c ****   /* This variable is updated in three ways:
 129:Src/system_stm32f4xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 130:Src/system_stm32f4xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 131:Src/system_stm32f4xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
 132:Src/system_stm32f4xx.c ****          Note: If you use this function to configure the system clock; then there
 133:Src/system_stm32f4xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 134:Src/system_stm32f4xx.c ****                variable is updated automatically.
 135:Src/system_stm32f4xx.c ****   */
 136:Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
 137:Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 138:Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 139:Src/system_stm32f4xx.c **** /**
 140:Src/system_stm32f4xx.c ****   * @}
 141:Src/system_stm32f4xx.c ****   */
 142:Src/system_stm32f4xx.c **** 
 143:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 144:Src/system_stm32f4xx.c ****   * @{
 145:Src/system_stm32f4xx.c ****   */
ARM GAS  /tmp/ccwdC0Nl.s 			page 4


 146:Src/system_stm32f4xx.c **** 
 147:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 148:Src/system_stm32f4xx.c ****   static void SystemInit_ExtMemCtl(void); 
 149:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 150:Src/system_stm32f4xx.c **** 
 151:Src/system_stm32f4xx.c **** /**
 152:Src/system_stm32f4xx.c ****   * @}
 153:Src/system_stm32f4xx.c ****   */
 154:Src/system_stm32f4xx.c **** 
 155:Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
 156:Src/system_stm32f4xx.c ****   * @{
 157:Src/system_stm32f4xx.c ****   */
 158:Src/system_stm32f4xx.c **** 
 159:Src/system_stm32f4xx.c **** /**
 160:Src/system_stm32f4xx.c ****   * @brief  Setup the microcontroller system
 161:Src/system_stm32f4xx.c ****   *         Initialize the FPU setting, vector table location and External memory 
 162:Src/system_stm32f4xx.c ****   *         configuration.
 163:Src/system_stm32f4xx.c ****   * @param  None
 164:Src/system_stm32f4xx.c ****   * @retval None
 165:Src/system_stm32f4xx.c ****   */
 166:Src/system_stm32f4xx.c **** void SystemInit(void)
 167:Src/system_stm32f4xx.c **** {
  28              		.loc 1 167 0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
 168:Src/system_stm32f4xx.c ****   /* FPU settings ------------------------------------------------------------*/
 169:Src/system_stm32f4xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 170:Src/system_stm32f4xx.c ****     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  33              		.loc 1 170 0
  34 0000 0F49     		ldr	r1, .L2
  35 0002 D1F88830 		ldr	r3, [r1, #136]
  36 0006 43F47003 		orr	r3, r3, #15728640
  37 000a C1F88830 		str	r3, [r1, #136]
 171:Src/system_stm32f4xx.c ****   #endif
 172:Src/system_stm32f4xx.c ****   /* Reset the RCC clock configuration to the default reset state ------------*/
 173:Src/system_stm32f4xx.c ****   /* Set HSION bit */
 174:Src/system_stm32f4xx.c ****   RCC->CR |= (uint32_t)0x00000001;
  38              		.loc 1 174 0
  39 000e 0D4B     		ldr	r3, .L2+4
  40 0010 1A68     		ldr	r2, [r3]
  41 0012 42F00102 		orr	r2, r2, #1
  42 0016 1A60     		str	r2, [r3]
 175:Src/system_stm32f4xx.c **** 
 176:Src/system_stm32f4xx.c ****   /* Reset CFGR register */
 177:Src/system_stm32f4xx.c ****   RCC->CFGR = 0x00000000;
  43              		.loc 1 177 0
  44 0018 0020     		movs	r0, #0
  45 001a 9860     		str	r0, [r3, #8]
 178:Src/system_stm32f4xx.c **** 
 179:Src/system_stm32f4xx.c ****   /* Reset HSEON, CSSON and PLLON bits */
 180:Src/system_stm32f4xx.c ****   RCC->CR &= (uint32_t)0xFEF6FFFF;
  46              		.loc 1 180 0
  47 001c 1A68     		ldr	r2, [r3]
  48 001e 22F08472 		bic	r2, r2, #17301504
  49 0022 22F48032 		bic	r2, r2, #65536
ARM GAS  /tmp/ccwdC0Nl.s 			page 5


  50 0026 1A60     		str	r2, [r3]
 181:Src/system_stm32f4xx.c **** 
 182:Src/system_stm32f4xx.c ****   /* Reset PLLCFGR register */
 183:Src/system_stm32f4xx.c ****   RCC->PLLCFGR = 0x24003010;
  51              		.loc 1 183 0
  52 0028 074A     		ldr	r2, .L2+8
  53 002a 5A60     		str	r2, [r3, #4]
 184:Src/system_stm32f4xx.c **** 
 185:Src/system_stm32f4xx.c ****   /* Reset HSEBYP bit */
 186:Src/system_stm32f4xx.c ****   RCC->CR &= (uint32_t)0xFFFBFFFF;
  54              		.loc 1 186 0
  55 002c 1A68     		ldr	r2, [r3]
  56 002e 22F48022 		bic	r2, r2, #262144
  57 0032 1A60     		str	r2, [r3]
 187:Src/system_stm32f4xx.c **** 
 188:Src/system_stm32f4xx.c ****   /* Disable all interrupts */
 189:Src/system_stm32f4xx.c ****   RCC->CIR = 0x00000000;
  58              		.loc 1 189 0
  59 0034 D860     		str	r0, [r3, #12]
 190:Src/system_stm32f4xx.c **** 
 191:Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 192:Src/system_stm32f4xx.c ****   SystemInit_ExtMemCtl(); 
 193:Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 194:Src/system_stm32f4xx.c **** 
 195:Src/system_stm32f4xx.c ****   /* Configure the Vector Table location add offset address ------------------*/
 196:Src/system_stm32f4xx.c **** #ifdef VECT_TAB_SRAM
 197:Src/system_stm32f4xx.c ****   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 198:Src/system_stm32f4xx.c **** #else
 199:Src/system_stm32f4xx.c ****   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
  60              		.loc 1 199 0
  61 0036 4FF00063 		mov	r3, #134217728
  62 003a 8B60     		str	r3, [r1, #8]
  63 003c 7047     		bx	lr
  64              	.L3:
  65 003e 00BF     		.align	2
  66              	.L2:
  67 0040 00ED00E0 		.word	-536810240
  68 0044 00380240 		.word	1073887232
  69 0048 10300024 		.word	603992080
  70              		.cfi_endproc
  71              	.LFE130:
  73              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  74              		.align	1
  75              		.global	SystemCoreClockUpdate
  76              		.syntax unified
  77              		.thumb
  78              		.thumb_func
  79              		.fpu fpv4-sp-d16
  81              	SystemCoreClockUpdate:
  82              	.LFB131:
 200:Src/system_stm32f4xx.c **** #endif
 201:Src/system_stm32f4xx.c **** }
 202:Src/system_stm32f4xx.c **** 
 203:Src/system_stm32f4xx.c **** /**
 204:Src/system_stm32f4xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 205:Src/system_stm32f4xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 206:Src/system_stm32f4xx.c ****   *         be used by the user application to setup the SysTick timer or configure
ARM GAS  /tmp/ccwdC0Nl.s 			page 6


 207:Src/system_stm32f4xx.c ****   *         other parameters.
 208:Src/system_stm32f4xx.c ****   *           
 209:Src/system_stm32f4xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 210:Src/system_stm32f4xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 211:Src/system_stm32f4xx.c ****   *         based on this variable will be incorrect.         
 212:Src/system_stm32f4xx.c ****   *     
 213:Src/system_stm32f4xx.c ****   * @note   - The system frequency computed by this function is not the real 
 214:Src/system_stm32f4xx.c ****   *           frequency in the chip. It is calculated based on the predefined 
 215:Src/system_stm32f4xx.c ****   *           constant and the selected clock source:
 216:Src/system_stm32f4xx.c ****   *             
 217:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 218:Src/system_stm32f4xx.c ****   *                                              
 219:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 220:Src/system_stm32f4xx.c ****   *                          
 221:Src/system_stm32f4xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
 222:Src/system_stm32f4xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 223:Src/system_stm32f4xx.c ****   *         
 224:Src/system_stm32f4xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
 225:Src/system_stm32f4xx.c ****   *             16 MHz) but the real value may vary depending on the variations
 226:Src/system_stm32f4xx.c ****   *             in voltage and temperature.   
 227:Src/system_stm32f4xx.c ****   *    
 228:Src/system_stm32f4xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
 229:Src/system_stm32f4xx.c ****   *              depends on the application requirements), user has to ensure that HSE_VALUE
 230:Src/system_stm32f4xx.c ****   *              is same as the real frequency of the crystal used. Otherwise, this function
 231:Src/system_stm32f4xx.c ****   *              may have wrong result.
 232:Src/system_stm32f4xx.c ****   *                
 233:Src/system_stm32f4xx.c ****   *         - The result of this function could be not correct when using fractional
 234:Src/system_stm32f4xx.c ****   *           value for HSE crystal.
 235:Src/system_stm32f4xx.c ****   *     
 236:Src/system_stm32f4xx.c ****   * @param  None
 237:Src/system_stm32f4xx.c ****   * @retval None
 238:Src/system_stm32f4xx.c ****   */
 239:Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
 240:Src/system_stm32f4xx.c **** {
  83              		.loc 1 240 0
  84              		.cfi_startproc
  85              		@ args = 0, pretend = 0, frame = 0
  86              		@ frame_needed = 0, uses_anonymous_args = 0
  87              		@ link register save eliminated.
  88              	.LVL0:
 241:Src/system_stm32f4xx.c ****   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 242:Src/system_stm32f4xx.c ****   
 243:Src/system_stm32f4xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 244:Src/system_stm32f4xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
  89              		.loc 1 244 0
  90 0000 224B     		ldr	r3, .L14
  91 0002 9B68     		ldr	r3, [r3, #8]
  92 0004 03F00C03 		and	r3, r3, #12
  93              	.LVL1:
 245:Src/system_stm32f4xx.c **** 
 246:Src/system_stm32f4xx.c ****   switch (tmp)
  94              		.loc 1 246 0
  95 0008 042B     		cmp	r3, #4
  96 000a 14D0     		beq	.L6
  97 000c 082B     		cmp	r3, #8
  98 000e 16D0     		beq	.L7
  99 0010 1BB1     		cbz	r3, .L13
ARM GAS  /tmp/ccwdC0Nl.s 			page 7


 247:Src/system_stm32f4xx.c ****   {
 248:Src/system_stm32f4xx.c ****     case 0x00:  /* HSI used as system clock source */
 249:Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 250:Src/system_stm32f4xx.c ****       break;
 251:Src/system_stm32f4xx.c ****     case 0x04:  /* HSE used as system clock source */
 252:Src/system_stm32f4xx.c ****       SystemCoreClock = HSE_VALUE;
 253:Src/system_stm32f4xx.c ****       break;
 254:Src/system_stm32f4xx.c ****     case 0x08:  /* PLL used as system clock source */
 255:Src/system_stm32f4xx.c **** 
 256:Src/system_stm32f4xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 257:Src/system_stm32f4xx.c ****          SYSCLK = PLL_VCO / PLL_P
 258:Src/system_stm32f4xx.c ****          */    
 259:Src/system_stm32f4xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 260:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 261:Src/system_stm32f4xx.c ****       
 262:Src/system_stm32f4xx.c ****       if (pllsource != 0)
 263:Src/system_stm32f4xx.c ****       {
 264:Src/system_stm32f4xx.c ****         /* HSE used as PLL clock source */
 265:Src/system_stm32f4xx.c ****         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 266:Src/system_stm32f4xx.c ****       }
 267:Src/system_stm32f4xx.c ****       else
 268:Src/system_stm32f4xx.c ****       {
 269:Src/system_stm32f4xx.c ****         /* HSI used as PLL clock source */
 270:Src/system_stm32f4xx.c ****         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 271:Src/system_stm32f4xx.c ****       }
 272:Src/system_stm32f4xx.c **** 
 273:Src/system_stm32f4xx.c ****       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 274:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 275:Src/system_stm32f4xx.c ****       break;
 276:Src/system_stm32f4xx.c ****     default:
 277:Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 100              		.loc 1 277 0
 101 0012 1F4A     		ldr	r2, .L14+4
 102 0014 1F4B     		ldr	r3, .L14+8
 103              	.LVL2:
 104 0016 1A60     		str	r2, [r3]
 278:Src/system_stm32f4xx.c ****       break;
 105              		.loc 1 278 0
 106 0018 02E0     		b	.L9
 107              	.LVL3:
 108              	.L13:
 249:Src/system_stm32f4xx.c ****       break;
 109              		.loc 1 249 0
 110 001a 1D4A     		ldr	r2, .L14+4
 111 001c 1D4B     		ldr	r3, .L14+8
 112              	.LVL4:
 113 001e 1A60     		str	r2, [r3]
 114              	.LVL5:
 115              	.L9:
 279:Src/system_stm32f4xx.c ****   }
 280:Src/system_stm32f4xx.c ****   /* Compute HCLK frequency --------------------------------------------------*/
 281:Src/system_stm32f4xx.c ****   /* Get HCLK prescaler */
 282:Src/system_stm32f4xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 116              		.loc 1 282 0
 117 0020 1A4B     		ldr	r3, .L14
 118 0022 9B68     		ldr	r3, [r3, #8]
 119 0024 C3F30313 		ubfx	r3, r3, #4, #4
ARM GAS  /tmp/ccwdC0Nl.s 			page 8


 120 0028 1B4A     		ldr	r2, .L14+12
 121 002a D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
 122              	.LVL6:
 283:Src/system_stm32f4xx.c ****   /* HCLK frequency */
 284:Src/system_stm32f4xx.c ****   SystemCoreClock >>= tmp;
 123              		.loc 1 284 0
 124 002c 194A     		ldr	r2, .L14+8
 125 002e 1368     		ldr	r3, [r2]
 126 0030 CB40     		lsrs	r3, r3, r1
 127 0032 1360     		str	r3, [r2]
 128 0034 7047     		bx	lr
 129              	.LVL7:
 130              	.L6:
 252:Src/system_stm32f4xx.c ****       break;
 131              		.loc 1 252 0
 132 0036 194A     		ldr	r2, .L14+16
 133 0038 164B     		ldr	r3, .L14+8
 134              	.LVL8:
 135 003a 1A60     		str	r2, [r3]
 253:Src/system_stm32f4xx.c ****     case 0x08:  /* PLL used as system clock source */
 136              		.loc 1 253 0
 137 003c F0E7     		b	.L9
 138              	.LVL9:
 139              	.L7:
 259:Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 140              		.loc 1 259 0
 141 003e 134B     		ldr	r3, .L14
 142              	.LVL10:
 143 0040 5A68     		ldr	r2, [r3, #4]
 144              	.LVL11:
 260:Src/system_stm32f4xx.c ****       
 145              		.loc 1 260 0
 146 0042 5B68     		ldr	r3, [r3, #4]
 147 0044 03F03F03 		and	r3, r3, #63
 148              	.LVL12:
 262:Src/system_stm32f4xx.c ****       {
 149              		.loc 1 262 0
 150 0048 12F4800F 		tst	r2, #4194304
 151 004c 13D0     		beq	.L10
 265:Src/system_stm32f4xx.c ****       }
 152              		.loc 1 265 0
 153 004e 134A     		ldr	r2, .L14+16
 154              	.LVL13:
 155 0050 B2FBF3F2 		udiv	r2, r2, r3
 156 0054 0D4B     		ldr	r3, .L14
 157              	.LVL14:
 158 0056 5B68     		ldr	r3, [r3, #4]
 159 0058 C3F38813 		ubfx	r3, r3, #6, #9
 160 005c 03FB02F3 		mul	r3, r3, r2
 161              	.LVL15:
 162              	.L11:
 273:Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 163              		.loc 1 273 0
 164 0060 0A4A     		ldr	r2, .L14
 165 0062 5268     		ldr	r2, [r2, #4]
 166 0064 C2F30142 		ubfx	r2, r2, #16, #2
 167 0068 0132     		adds	r2, r2, #1
ARM GAS  /tmp/ccwdC0Nl.s 			page 9


 168 006a 5200     		lsls	r2, r2, #1
 169              	.LVL16:
 274:Src/system_stm32f4xx.c ****       break;
 170              		.loc 1 274 0
 171 006c B3FBF2F3 		udiv	r3, r3, r2
 172              	.LVL17:
 173 0070 084A     		ldr	r2, .L14+8
 174              	.LVL18:
 175 0072 1360     		str	r3, [r2]
 275:Src/system_stm32f4xx.c ****     default:
 176              		.loc 1 275 0
 177 0074 D4E7     		b	.L9
 178              	.LVL19:
 179              	.L10:
 270:Src/system_stm32f4xx.c ****       }
 180              		.loc 1 270 0
 181 0076 064A     		ldr	r2, .L14+4
 182              	.LVL20:
 183 0078 B2FBF3F2 		udiv	r2, r2, r3
 184 007c 034B     		ldr	r3, .L14
 185              	.LVL21:
 186 007e 5B68     		ldr	r3, [r3, #4]
 187 0080 C3F38813 		ubfx	r3, r3, #6, #9
 188 0084 03FB02F3 		mul	r3, r3, r2
 189              	.LVL22:
 190 0088 EAE7     		b	.L11
 191              	.L15:
 192 008a 00BF     		.align	2
 193              	.L14:
 194 008c 00380240 		.word	1073887232
 195 0090 0024F400 		.word	16000000
 196 0094 00000000 		.word	.LANCHOR0
 197 0098 00000000 		.word	.LANCHOR1
 198 009c 40787D01 		.word	25000000
 199              		.cfi_endproc
 200              	.LFE131:
 202              		.global	APBPrescTable
 203              		.global	AHBPrescTable
 204              		.global	SystemCoreClock
 205              		.section	.data.SystemCoreClock,"aw",%progbits
 206              		.align	2
 207              		.set	.LANCHOR0,. + 0
 210              	SystemCoreClock:
 211 0000 0024F400 		.word	16000000
 212              		.section	.rodata.AHBPrescTable,"a",%progbits
 213              		.align	2
 214              		.set	.LANCHOR1,. + 0
 217              	AHBPrescTable:
 218 0000 00       		.byte	0
 219 0001 00       		.byte	0
 220 0002 00       		.byte	0
 221 0003 00       		.byte	0
 222 0004 00       		.byte	0
 223 0005 00       		.byte	0
 224 0006 00       		.byte	0
 225 0007 00       		.byte	0
 226 0008 01       		.byte	1
ARM GAS  /tmp/ccwdC0Nl.s 			page 10


 227 0009 02       		.byte	2
 228 000a 03       		.byte	3
 229 000b 04       		.byte	4
 230 000c 06       		.byte	6
 231 000d 07       		.byte	7
 232 000e 08       		.byte	8
 233 000f 09       		.byte	9
 234              		.section	.rodata.APBPrescTable,"a",%progbits
 235              		.align	2
 238              	APBPrescTable:
 239 0000 00       		.byte	0
 240 0001 00       		.byte	0
 241 0002 00       		.byte	0
 242 0003 00       		.byte	0
 243 0004 01       		.byte	1
 244 0005 02       		.byte	2
 245 0006 03       		.byte	3
 246 0007 04       		.byte	4
 247              		.text
 248              	.Letext0:
 249              		.file 2 "/usr/include/newlib/machine/_default_types.h"
 250              		.file 3 "/usr/include/newlib/sys/_stdint.h"
 251              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 252              		.file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
 253              		.file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h"
ARM GAS  /tmp/ccwdC0Nl.s 			page 11


DEFINED SYMBOLS
                            *ABS*:0000000000000000 system_stm32f4xx.c
     /tmp/ccwdC0Nl.s:18     .text.SystemInit:0000000000000000 $t
     /tmp/ccwdC0Nl.s:25     .text.SystemInit:0000000000000000 SystemInit
     /tmp/ccwdC0Nl.s:67     .text.SystemInit:0000000000000040 $d
     /tmp/ccwdC0Nl.s:74     .text.SystemCoreClockUpdate:0000000000000000 $t
     /tmp/ccwdC0Nl.s:81     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
     /tmp/ccwdC0Nl.s:194    .text.SystemCoreClockUpdate:000000000000008c $d
     /tmp/ccwdC0Nl.s:238    .rodata.APBPrescTable:0000000000000000 APBPrescTable
     /tmp/ccwdC0Nl.s:217    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
     /tmp/ccwdC0Nl.s:210    .data.SystemCoreClock:0000000000000000 SystemCoreClock
     /tmp/ccwdC0Nl.s:206    .data.SystemCoreClock:0000000000000000 $d
     /tmp/ccwdC0Nl.s:213    .rodata.AHBPrescTable:0000000000000000 $d
     /tmp/ccwdC0Nl.s:235    .rodata.APBPrescTable:0000000000000000 $d
                     .debug_frame:0000000000000010 $d

NO UNDEFINED SYMBOLS