ARM GAS /tmp/ccaqA7YX.s page 1 1 .cpu cortex-m4 2 .eabi_attribute 27, 1 3 .eabi_attribute 28, 1 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 1 12 .eabi_attribute 18, 4 13 .file "stm32f4xx_hal_pwr.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .section .text.HAL_PWR_DeInit,"ax",%progbits 18 .align 1 19 .global HAL_PWR_DeInit 20 .syntax unified 21 .thumb 22 .thumb_func 23 .fpu fpv4-sp-d16 25 HAL_PWR_DeInit: 26 .LFB130: 27 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @file stm32f4xx_hal_pwr.c 4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @author MCD Application Team 5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver. 6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: 8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Peripheral Control functions 10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @attention 13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *

© Copyright (c) 2017 STMicroelectronics. 15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * All rights reserved.

16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, 18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the 19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * License. You may obtain a copy of the License at: 20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause 21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ 26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #include "stm32f4xx_hal.h" 27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup STM32F4xx_HAL_Driver 29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS /tmp/ccaqA7YX.s page 2 32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR PWR 33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver 34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED 38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ 40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ 41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants 42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U 49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U 50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U 51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U 52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ 60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ 61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ 62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ 63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions 65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions 70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### 74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data 77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted 78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** write accesses. 79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: 80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the 81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. 82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** ARM GAS /tmp/ccaqA7YX.s page 3 89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. 90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DeInit(void) 93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 28 .loc 1 93 0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); 33 .loc 1 94 0 34 0000 044B ldr r3, .L2 35 0002 1A6A ldr r2, [r3, #32] 36 0004 42F08052 orr r2, r2, #268435456 37 0008 1A62 str r2, [r3, #32] 95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); 38 .loc 1 95 0 39 000a 1A6A ldr r2, [r3, #32] 40 000c 22F08052 bic r2, r2, #268435456 41 0010 1A62 str r2, [r3, #32] 42 0012 7047 bx lr 43 .L3: 44 .align 2 45 .L2: 46 0014 00380240 .word 1073887232 47 .cfi_endproc 48 .LFE130: 50 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits 51 .align 1 52 .global HAL_PWR_EnableBkUpAccess 53 .syntax unified 54 .thumb 55 .thumb_func 56 .fpu fpv4-sp-d16 58 HAL_PWR_EnableBkUpAccess: 59 .LFB131: 96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 60 .loc 1 106 0 61 .cfi_startproc 62 @ args = 0, pretend = 0, frame = 0 63 @ frame_needed = 0, uses_anonymous_args = 0 64 @ link register save eliminated. 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 65 .loc 1 107 0 66 0000 0122 movs r2, #1 67 0002 014B ldr r3, .L5 ARM GAS /tmp/ccaqA7YX.s page 4 68 0004 1A60 str r2, [r3] 69 0006 7047 bx lr 70 .L6: 71 .align 2 72 .L5: 73 0008 20000E42 .word 1108213792 74 .cfi_endproc 75 .LFE131: 77 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits 78 .align 1 79 .global HAL_PWR_DisableBkUpAccess 80 .syntax unified 81 .thumb 82 .thumb_func 83 .fpu fpv4-sp-d16 85 HAL_PWR_DisableBkUpAccess: 86 .LFB132: 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 87 .loc 1 118 0 88 .cfi_startproc 89 @ args = 0, pretend = 0, frame = 0 90 @ frame_needed = 0, uses_anonymous_args = 0 91 @ link register save eliminated. 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; 92 .loc 1 119 0 93 0000 0022 movs r2, #0 94 0002 014B ldr r3, .L8 95 0004 1A60 str r2, [r3] 96 0006 7047 bx lr 97 .L9: 98 .align 2 99 .L8: 100 0008 20000E42 .word 1108213792 101 .cfi_endproc 102 .LFE132: 104 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits 105 .align 1 106 .global HAL_PWR_ConfigPVD 107 .syntax unified 108 .thumb 109 .thumb_func 110 .fpu fpv4-sp-d16 112 HAL_PWR_ConfigPVD: 113 .LFB133: 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** ARM GAS /tmp/ccaqA7YX.s page 5 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Low Power modes configuration functions 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Peripheral Control functions ##### 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** PVD configuration *** 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ========================= 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Wake-up pin configuration *** 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================================ 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Low Power modes configuration *** 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ===================================== 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The devices feature 3 low-power modes: 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** in low power mode 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off. 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Sleep mode *** 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================== 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** functions with 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32F4 family 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** lower power families (STM32L). 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS /tmp/ccaqA7YX.s page 6 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Stop mode *** 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================= 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** are preserved. 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To minimize the consumption In Stop mode, FLASH can be powered off before 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** It can be switched on again by software after exiting the Stop mode using 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** function with: 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Main regulator ON. 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Low Power regulator ON. 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Standby mode *** 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ==================== 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** circuitry. 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator is OFF. 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Entry: 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Exit: 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Auto-wake-up (AWU) from low-power mode *** 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ============================================= 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Wake-up event, a tamper event or a time-stamp event, without depending on 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** an external interrupt (Auto-wake-up mode). 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) RTC auto-wake-up (AWU) from the Stop and Standby modes 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to ARM GAS /tmp/ccaqA7YX.s page 7 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTime 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * information for the PVD. 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * detection level. 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 114 .loc 1 253 0 115 .cfi_startproc 116 @ args = 0, pretend = 0, frame = 0 117 @ frame_needed = 0, uses_anonymous_args = 0 118 @ link register save eliminated. 119 .LVL0: 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 120 .loc 1 259 0 121 0000 1E4A ldr r2, .L15 122 0002 1368 ldr r3, [r2] 123 0004 23F0E003 bic r3, r3, #224 124 0008 0168 ldr r1, [r0] 125 000a 0B43 orrs r3, r3, r1 126 000c 1360 str r3, [r2] 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 127 .loc 1 262 0 128 000e 1C4B ldr r3, .L15+4 129 0010 5A68 ldr r2, [r3, #4] 130 0012 22F48032 bic r2, r2, #65536 131 0016 5A60 str r2, [r3, #4] 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); 132 .loc 1 263 0 133 0018 1A68 ldr r2, [r3] 134 001a 22F48032 bic r2, r2, #65536 135 001e 1A60 str r2, [r3] 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 136 .loc 1 264 0 137 0020 9A68 ldr r2, [r3, #8] 138 0022 22F48032 bic r2, r2, #65536 139 0026 9A60 str r2, [r3, #8] 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 140 .loc 1 265 0 141 0028 DA68 ldr r2, [r3, #12] ARM GAS /tmp/ccaqA7YX.s page 8 142 002a 22F48032 bic r2, r2, #65536 143 002e DA60 str r2, [r3, #12] 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure interrupt mode */ 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 144 .loc 1 268 0 145 0030 4368 ldr r3, [r0, #4] 146 0032 13F4803F tst r3, #65536 147 0036 04D0 beq .L11 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); 148 .loc 1 270 0 149 0038 114A ldr r2, .L15+4 150 003a 1368 ldr r3, [r2] 151 003c 43F48033 orr r3, r3, #65536 152 0040 1360 str r3, [r2] 153 .L11: 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure event mode */ 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 154 .loc 1 274 0 155 0042 4368 ldr r3, [r0, #4] 156 0044 13F4003F tst r3, #131072 157 0048 04D0 beq .L12 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 158 .loc 1 276 0 159 004a 0D4A ldr r2, .L15+4 160 004c 5368 ldr r3, [r2, #4] 161 004e 43F48033 orr r3, r3, #65536 162 0052 5360 str r3, [r2, #4] 163 .L12: 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure the edge */ 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 164 .loc 1 280 0 165 0054 4368 ldr r3, [r0, #4] 166 0056 13F0010F tst r3, #1 167 005a 04D0 beq .L13 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 168 .loc 1 282 0 169 005c 084A ldr r2, .L15+4 170 005e 9368 ldr r3, [r2, #8] 171 0060 43F48033 orr r3, r3, #65536 172 0064 9360 str r3, [r2, #8] 173 .L13: 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 174 .loc 1 285 0 175 0066 4368 ldr r3, [r0, #4] 176 0068 13F0020F tst r3, #2 177 006c 04D0 beq .L10 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { ARM GAS /tmp/ccaqA7YX.s page 9 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 178 .loc 1 287 0 179 006e 044A ldr r2, .L15+4 180 0070 D368 ldr r3, [r2, #12] 181 0072 43F48033 orr r3, r3, #65536 182 0076 D360 str r3, [r2, #12] 183 .L10: 184 0078 7047 bx lr 185 .L16: 186 007a 00BF .align 2 187 .L15: 188 007c 00700040 .word 1073770496 189 0080 003C0140 .word 1073822720 190 .cfi_endproc 191 .LFE133: 193 .section .text.HAL_PWR_EnablePVD,"ax",%progbits 194 .align 1 195 .global HAL_PWR_EnablePVD 196 .syntax unified 197 .thumb 198 .thumb_func 199 .fpu fpv4-sp-d16 201 HAL_PWR_EnablePVD: 202 .LFB134: 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 203 .loc 1 296 0 204 .cfi_startproc 205 @ args = 0, pretend = 0, frame = 0 206 @ frame_needed = 0, uses_anonymous_args = 0 207 @ link register save eliminated. 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; 208 .loc 1 297 0 209 0000 0122 movs r2, #1 210 0002 014B ldr r3, .L18 211 0004 1A60 str r2, [r3] 212 0006 7047 bx lr 213 .L19: 214 .align 2 215 .L18: 216 0008 10000E42 .word 1108213776 217 .cfi_endproc 218 .LFE134: 220 .section .text.HAL_PWR_DisablePVD,"ax",%progbits 221 .align 1 222 .global HAL_PWR_DisablePVD 223 .syntax unified 224 .thumb 225 .thumb_func 226 .fpu fpv4-sp-d16 ARM GAS /tmp/ccaqA7YX.s page 10 228 HAL_PWR_DisablePVD: 229 .LFB135: 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 230 .loc 1 305 0 231 .cfi_startproc 232 @ args = 0, pretend = 0, frame = 0 233 @ frame_needed = 0, uses_anonymous_args = 0 234 @ link register save eliminated. 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; 235 .loc 1 306 0 236 0000 0022 movs r2, #0 237 0002 014B ldr r3, .L21 238 0004 1A60 str r2, [r3] 239 0006 7047 bx lr 240 .L22: 241 .align 2 242 .L21: 243 0008 10000E42 .word 1108213776 244 .cfi_endproc 245 .LFE135: 247 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits 248 .align 1 249 .global HAL_PWR_EnableWakeUpPin 250 .syntax unified 251 .thumb 252 .thumb_func 253 .fpu fpv4-sp-d16 255 HAL_PWR_EnableWakeUpPin: 256 .LFB136: 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Wake-up PINx functionality. 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 257 .loc 1 319 0 258 .cfi_startproc 259 @ args = 0, pretend = 0, frame = 0 260 @ frame_needed = 0, uses_anonymous_args = 0 261 @ link register save eliminated. 262 .LVL1: 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); ARM GAS /tmp/ccaqA7YX.s page 11 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Enable the wake up pin */ 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); 263 .loc 1 324 0 264 0000 024A ldr r2, .L24 265 0002 5368 ldr r3, [r2, #4] 266 0004 1843 orrs r0, r0, r3 267 .LVL2: 268 0006 5060 str r0, [r2, #4] 269 0008 7047 bx lr 270 .L25: 271 000a 00BF .align 2 272 .L24: 273 000c 00700040 .word 1073770496 274 .cfi_endproc 275 .LFE136: 277 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits 278 .align 1 279 .global HAL_PWR_DisableWakeUpPin 280 .syntax unified 281 .thumb 282 .thumb_func 283 .fpu fpv4-sp-d16 285 HAL_PWR_DisableWakeUpPin: 286 .LFB137: 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Wake-up PINx functionality. 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 287 .loc 1 337 0 288 .cfi_startproc 289 @ args = 0, pretend = 0, frame = 0 290 @ frame_needed = 0, uses_anonymous_args = 0 291 @ link register save eliminated. 292 .LVL3: 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Disable the wake up pin */ 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); 293 .loc 1 342 0 294 0000 024A ldr r2, .L27 295 0002 5368 ldr r3, [r2, #4] 296 0004 23EA0000 bic r0, r3, r0 297 .LVL4: 298 0008 5060 str r0, [r2, #4] 299 000a 7047 bx lr 300 .L28: ARM GAS /tmp/ccaqA7YX.s page 12 301 .align 2 302 .L27: 303 000c 00700040 .word 1073770496 304 .cfi_endproc 305 .LFE137: 307 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits 308 .align 1 309 .global HAL_PWR_EnterSLEEPMode 310 .syntax unified 311 .thumb 312 .thumb_func 313 .fpu fpv4-sp-d16 315 HAL_PWR_EnterSLEEPMode: 316 .LFB138: 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Sleep mode. 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, the systick is stopped to avoid exit from this mode with 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * systick interrupt when used as time base for Timeout 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This parameter is not used for the STM32F4 family and is kept as parameter 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * just to maintain compatibility with the lower power families. 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 317 .loc 1 366 0 318 .cfi_startproc 319 @ args = 0, pretend = 0, frame = 0 320 @ frame_needed = 0, uses_anonymous_args = 0 321 @ link register save eliminated. 322 .LVL5: 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 323 .loc 1 372 0 324 0000 064A ldr r2, .L33 325 0002 1369 ldr r3, [r2, #16] 326 0004 23F00403 bic r3, r3, #4 327 0008 1361 str r3, [r2, #16] 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ ARM GAS /tmp/ccaqA7YX.s page 13 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 328 .loc 1 375 0 329 000a 0129 cmp r1, #1 330 000c 03D0 beq .L32 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 331 .loc 1 383 0 332 .syntax unified 333 @ 383 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 334 000e 40BF sev 335 @ 0 "" 2 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 336 .loc 1 384 0 337 @ 384 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 338 0010 20BF wfe 339 @ 0 "" 2 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 340 .loc 1 385 0 341 @ 385 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 342 0012 20BF wfe 343 @ 0 "" 2 344 .thumb 345 .syntax unified 346 0014 7047 bx lr 347 .L32: 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 348 .loc 1 378 0 349 .syntax unified 350 @ 378 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 351 0016 30BF wfi 352 @ 0 "" 2 353 .thumb 354 .syntax unified 355 0018 7047 bx lr 356 .L34: 357 001a 00BF .align 2 358 .L33: 359 001c 00ED00E0 .word -536810240 360 .cfi_endproc 361 .LFE138: 363 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits 364 .align 1 365 .global HAL_PWR_EnterSTOPMode 366 .syntax unified 367 .thumb 368 .thumb_func 369 .fpu fpv4-sp-d16 371 HAL_PWR_EnterSTOPMode: 372 .LFB139: 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } ARM GAS /tmp/ccaqA7YX.s page 14 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Stop mode. 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * is higher although the startup time is reduced. 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode. 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 373 .loc 1 409 0 374 .cfi_startproc 375 @ args = 0, pretend = 0, frame = 0 376 @ frame_needed = 0, uses_anonymous_args = 0 377 @ link register save eliminated. 378 .LVL6: 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator val 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); 379 .loc 1 415 0 380 0000 0B4A ldr r2, .L39 381 0002 1368 ldr r3, [r2] 382 0004 23F00303 bic r3, r3, #3 383 0008 1843 orrs r0, r0, r3 384 .LVL7: 385 000a 1060 str r0, [r2] 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 386 .loc 1 418 0 387 000c 094A ldr r2, .L39+4 388 000e 1369 ldr r3, [r2, #16] 389 0010 43F00403 orr r3, r3, #4 390 0014 1361 str r3, [r2, #16] 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) 391 .loc 1 421 0 392 0016 0129 cmp r1, #1 393 0018 08D0 beq .L38 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ ARM GAS /tmp/ccaqA7YX.s page 15 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 394 .loc 1 429 0 395 .syntax unified 396 @ 429 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 397 001a 40BF sev 398 @ 0 "" 2 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 399 .loc 1 430 0 400 @ 430 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 401 001c 20BF wfe 402 @ 0 "" 2 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 403 .loc 1 431 0 404 @ 431 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 405 001e 20BF wfe 406 @ 0 "" 2 407 .thumb 408 .syntax unified 409 .L37: 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 410 .loc 1 434 0 411 0020 044A ldr r2, .L39+4 412 0022 1369 ldr r3, [r2, #16] 413 0024 23F00403 bic r3, r3, #4 414 0028 1361 str r3, [r2, #16] 415 002a 7047 bx lr 416 .L38: 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 417 .loc 1 424 0 418 .syntax unified 419 @ 424 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 420 002c 30BF wfi 421 @ 0 "" 2 422 .thumb 423 .syntax unified 424 002e F7E7 b .L37 425 .L40: 426 .align 2 427 .L39: 428 0030 00700040 .word 1073770496 429 0034 00ED00E0 .word -536810240 430 .cfi_endproc 431 .LFE139: 433 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits 434 .align 1 435 .global HAL_PWR_EnterSTANDBYMode 436 .syntax unified 437 .thumb 438 .thumb_func 439 .fpu fpv4-sp-d16 ARM GAS /tmp/ccaqA7YX.s page 16 441 HAL_PWR_EnterSTANDBYMode: 442 .LFB140: 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Standby mode. 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - Reset pad (still available) 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - WKUP pin 1 (PA0) if enabled. 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 443 .loc 1 448 0 444 .cfi_startproc 445 @ args = 0, pretend = 0, frame = 0 446 @ frame_needed = 0, uses_anonymous_args = 0 447 @ link register save eliminated. 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Standby mode */ 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); 448 .loc 1 450 0 449 0000 054A ldr r2, .L42 450 0002 1368 ldr r3, [r2] 451 0004 43F00203 orr r3, r3, #2 452 0008 1360 str r3, [r2] 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 453 .loc 1 453 0 454 000a 044A ldr r2, .L42+4 455 000c 1369 ldr r3, [r2, #16] 456 000e 43F00403 orr r3, r3, #4 457 0012 1361 str r3, [r2, #16] 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #if defined ( __CC_ARM) 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __force_stores(); 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #endif 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 458 .loc 1 460 0 459 .syntax unified 460 @ 460 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 461 0014 30BF wfi 462 @ 0 "" 2 463 .thumb 464 .syntax unified 465 0016 7047 bx lr 466 .L43: 467 .align 2 468 .L42: 469 0018 00700040 .word 1073770496 470 001c 00ED00E0 .word -536810240 471 .cfi_endproc ARM GAS /tmp/ccaqA7YX.s page 17 472 .LFE140: 474 .section .text.HAL_PWR_PVDCallback,"ax",%progbits 475 .align 1 476 .weak HAL_PWR_PVDCallback 477 .syntax unified 478 .thumb 479 .thumb_func 480 .fpu fpv4-sp-d16 482 HAL_PWR_PVDCallback: 483 .LFB142: 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_PWR_PVDCallback(); 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 484 .loc 1 486 0 485 .cfi_startproc 486 @ args = 0, pretend = 0, frame = 0 487 @ frame_needed = 0, uses_anonymous_args = 0 488 @ link register save eliminated. 489 0000 7047 bx lr 490 .cfi_endproc 491 .LFE142: 493 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits 494 .align 1 495 .global HAL_PWR_PVD_IRQHandler 496 .syntax unified 497 .thumb 498 .thumb_func 499 .fpu fpv4-sp-d16 501 HAL_PWR_PVD_IRQHandler: 502 .LFB141: 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 503 .loc 1 469 0 504 .cfi_startproc 505 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccaqA7YX.s page 18 506 @ frame_needed = 0, uses_anonymous_args = 0 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 507 .loc 1 469 0 508 0000 08B5 push {r3, lr} 509 .LCFI0: 510 .cfi_def_cfa_offset 8 511 .cfi_offset 3, -8 512 .cfi_offset 14, -4 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 513 .loc 1 471 0 514 0002 064B ldr r3, .L49 515 0004 5B69 ldr r3, [r3, #20] 516 0006 13F4803F tst r3, #65536 517 000a 00D1 bne .L48 518 .L45: 519 000c 08BD pop {r3, pc} 520 .L48: 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 521 .loc 1 474 0 522 000e FFF7FEFF bl HAL_PWR_PVDCallback 523 .LVL8: 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 524 .loc 1 477 0 525 0012 4FF48032 mov r2, #65536 526 0016 014B ldr r3, .L49 527 0018 5A61 str r2, [r3, #20] 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 528 .loc 1 479 0 529 001a F7E7 b .L45 530 .L50: 531 .align 2 532 .L49: 533 001c 003C0140 .word 1073822720 534 .cfi_endproc 535 .LFE141: 537 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits 538 .align 1 539 .global HAL_PWR_EnableSleepOnExit 540 .syntax unified 541 .thumb 542 .thumb_func 543 .fpu fpv4-sp-d16 545 HAL_PWR_EnableSleepOnExit: 546 .LFB143: 487:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, 488:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file 489:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 490:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 491:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 492:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 493:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 495:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 496:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on 497:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * interruptions handling. 498:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 499:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ ARM GAS /tmp/ccaqA7YX.s page 19 500:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) 501:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 547 .loc 1 501 0 548 .cfi_startproc 549 @ args = 0, pretend = 0, frame = 0 550 @ frame_needed = 0, uses_anonymous_args = 0 551 @ link register save eliminated. 502:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ 503:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 552 .loc 1 503 0 553 0000 024A ldr r2, .L52 554 0002 1369 ldr r3, [r2, #16] 555 0004 43F00203 orr r3, r3, #2 556 0008 1361 str r3, [r2, #16] 557 000a 7047 bx lr 558 .L53: 559 .align 2 560 .L52: 561 000c 00ED00E0 .word -536810240 562 .cfi_endproc 563 .LFE143: 565 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits 566 .align 1 567 .global HAL_PWR_DisableSleepOnExit 568 .syntax unified 569 .thumb 570 .thumb_func 571 .fpu fpv4-sp-d16 573 HAL_PWR_DisableSleepOnExit: 574 .LFB144: 504:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 505:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 506:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 511:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) 513:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 575 .loc 1 513 0 576 .cfi_startproc 577 @ args = 0, pretend = 0, frame = 0 578 @ frame_needed = 0, uses_anonymous_args = 0 579 @ link register save eliminated. 514:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 580 .loc 1 515 0 581 0000 024A ldr r2, .L55 582 0002 1369 ldr r3, [r2, #16] 583 0004 23F00203 bic r3, r3, #2 584 0008 1361 str r3, [r2, #16] 585 000a 7047 bx lr 586 .L56: 587 .align 2 588 .L55: 589 000c 00ED00E0 .word -536810240 ARM GAS /tmp/ccaqA7YX.s page 20 590 .cfi_endproc 591 .LFE144: 593 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits 594 .align 1 595 .global HAL_PWR_EnableSEVOnPend 596 .syntax unified 597 .thumb 598 .thumb_func 599 .fpu fpv4-sp-d16 601 HAL_PWR_EnableSEVOnPend: 602 .LFB145: 516:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 517:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 519:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 521:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 522:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 523:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 524:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) 525:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 603 .loc 1 525 0 604 .cfi_startproc 605 @ args = 0, pretend = 0, frame = 0 606 @ frame_needed = 0, uses_anonymous_args = 0 607 @ link register save eliminated. 526:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ 527:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 608 .loc 1 527 0 609 0000 024A ldr r2, .L58 610 0002 1369 ldr r3, [r2, #16] 611 0004 43F01003 orr r3, r3, #16 612 0008 1361 str r3, [r2, #16] 613 000a 7047 bx lr 614 .L59: 615 .align 2 616 .L58: 617 000c 00ED00E0 .word -536810240 618 .cfi_endproc 619 .LFE145: 621 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits 622 .align 1 623 .global HAL_PWR_DisableSEVOnPend 624 .syntax unified 625 .thumb 626 .thumb_func 627 .fpu fpv4-sp-d16 629 HAL_PWR_DisableSEVOnPend: 630 .LFB146: 528:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 529:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 530:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 531:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. 532:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 533:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 534:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 535:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ ARM GAS /tmp/ccaqA7YX.s page 21 536:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) 537:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 631 .loc 1 537 0 632 .cfi_startproc 633 @ args = 0, pretend = 0, frame = 0 634 @ frame_needed = 0, uses_anonymous_args = 0 635 @ link register save eliminated. 538:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ 539:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 636 .loc 1 539 0 637 0000 024A ldr r2, .L61 638 0002 1369 ldr r3, [r2, #16] 639 0004 23F01003 bic r3, r3, #16 640 0008 1361 str r3, [r2, #16] 641 000a 7047 bx lr 642 .L62: 643 .align 2 644 .L61: 645 000c 00ED00E0 .word -536810240 646 .cfi_endproc 647 .LFE146: 649 .text 650 .Letext0: 651 .file 2 "/usr/include/newlib/machine/_default_types.h" 652 .file 3 "/usr/include/newlib/sys/_stdint.h" 653 .file 4 "Drivers/CMSIS/Include/core_cm4.h" 654 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" 655 .file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h" 656 .file 7 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 657 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h" ARM GAS /tmp/ccaqA7YX.s page 22 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f4xx_hal_pwr.c /tmp/ccaqA7YX.s:18 .text.HAL_PWR_DeInit:0000000000000000 $t /tmp/ccaqA7YX.s:25 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit /tmp/ccaqA7YX.s:46 .text.HAL_PWR_DeInit:0000000000000014 $d /tmp/ccaqA7YX.s:51 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t /tmp/ccaqA7YX.s:58 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess /tmp/ccaqA7YX.s:73 .text.HAL_PWR_EnableBkUpAccess:0000000000000008 $d /tmp/ccaqA7YX.s:78 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t /tmp/ccaqA7YX.s:85 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess /tmp/ccaqA7YX.s:100 .text.HAL_PWR_DisableBkUpAccess:0000000000000008 $d /tmp/ccaqA7YX.s:105 .text.HAL_PWR_ConfigPVD:0000000000000000 $t /tmp/ccaqA7YX.s:112 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD /tmp/ccaqA7YX.s:188 .text.HAL_PWR_ConfigPVD:000000000000007c $d /tmp/ccaqA7YX.s:194 .text.HAL_PWR_EnablePVD:0000000000000000 $t /tmp/ccaqA7YX.s:201 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD /tmp/ccaqA7YX.s:216 .text.HAL_PWR_EnablePVD:0000000000000008 $d /tmp/ccaqA7YX.s:221 .text.HAL_PWR_DisablePVD:0000000000000000 $t /tmp/ccaqA7YX.s:228 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD /tmp/ccaqA7YX.s:243 .text.HAL_PWR_DisablePVD:0000000000000008 $d /tmp/ccaqA7YX.s:248 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t /tmp/ccaqA7YX.s:255 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin /tmp/ccaqA7YX.s:273 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d /tmp/ccaqA7YX.s:278 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t /tmp/ccaqA7YX.s:285 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin /tmp/ccaqA7YX.s:303 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d /tmp/ccaqA7YX.s:308 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t /tmp/ccaqA7YX.s:315 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode /tmp/ccaqA7YX.s:359 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d /tmp/ccaqA7YX.s:364 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t /tmp/ccaqA7YX.s:371 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode /tmp/ccaqA7YX.s:428 .text.HAL_PWR_EnterSTOPMode:0000000000000030 $d /tmp/ccaqA7YX.s:434 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t /tmp/ccaqA7YX.s:441 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode /tmp/ccaqA7YX.s:469 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d /tmp/ccaqA7YX.s:475 .text.HAL_PWR_PVDCallback:0000000000000000 $t /tmp/ccaqA7YX.s:482 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback /tmp/ccaqA7YX.s:494 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t /tmp/ccaqA7YX.s:501 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler /tmp/ccaqA7YX.s:533 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d /tmp/ccaqA7YX.s:538 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t /tmp/ccaqA7YX.s:545 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit /tmp/ccaqA7YX.s:561 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d /tmp/ccaqA7YX.s:566 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t /tmp/ccaqA7YX.s:573 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit /tmp/ccaqA7YX.s:589 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d /tmp/ccaqA7YX.s:594 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t /tmp/ccaqA7YX.s:601 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend /tmp/ccaqA7YX.s:617 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d /tmp/ccaqA7YX.s:622 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t /tmp/ccaqA7YX.s:629 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend /tmp/ccaqA7YX.s:645 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d .debug_frame:0000000000000010 $d NO UNDEFINED SYMBOLS