startup_stm32f407xx.s 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521
  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32f407xx.s
  4. * @author MCD Application Team
  5. * @brief STM32F407xx Devices vector table for GCC based toolchains.
  6. * This module performs:
  7. * - Set the initial SP
  8. * - Set the initial PC == Reset_Handler,
  9. * - Set the vector table entries with the exceptions ISR address
  10. * - Branches to main in the C library (which eventually
  11. * calls main()).
  12. * After Reset the Cortex-M4 processor is in Thread mode,
  13. * priority is Privileged, and the Stack is set to Main.
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  18. *
  19. * Redistribution and use in source and binary forms, with or without modification,
  20. * are permitted provided that the following conditions are met:
  21. * 1. Redistributions of source code must retain the above copyright notice,
  22. * this list of conditions and the following disclaimer.
  23. * 2. Redistributions in binary form must reproduce the above copyright notice,
  24. * this list of conditions and the following disclaimer in the documentation
  25. * and/or other materials provided with the distribution.
  26. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  27. * may be used to endorse or promote products derived from this software
  28. * without specific prior written permission.
  29. *
  30. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. ******************************************************************************
  42. */
  43. .syntax unified
  44. .cpu cortex-m4
  45. .fpu softvfp
  46. .thumb
  47. .global g_pfnVectors
  48. .global Default_Handler
  49. /* start address for the initialization values of the .data section.
  50. defined in linker script */
  51. .word _sidata
  52. /* start address for the .data section. defined in linker script */
  53. .word _sdata
  54. /* end address for the .data section. defined in linker script */
  55. .word _edata
  56. /* start address for the .bss section. defined in linker script */
  57. .word _sbss
  58. /* end address for the .bss section. defined in linker script */
  59. .word _ebss
  60. /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  61. /**
  62. * @brief This is the code that gets called when the processor first
  63. * starts execution following a reset event. Only the absolutely
  64. * necessary set is performed, after which the application
  65. * supplied main() routine is called.
  66. * @param None
  67. * @retval : None
  68. */
  69. .section .text.Reset_Handler
  70. .weak Reset_Handler
  71. .type Reset_Handler, %function
  72. Reset_Handler:
  73. ldr sp, =_estack /* set stack pointer */
  74. /* Copy the data segment initializers from flash to SRAM */
  75. movs r1, #0
  76. b LoopCopyDataInit
  77. CopyDataInit:
  78. ldr r3, =_sidata
  79. ldr r3, [r3, r1]
  80. str r3, [r0, r1]
  81. adds r1, r1, #4
  82. LoopCopyDataInit:
  83. ldr r0, =_sdata
  84. ldr r3, =_edata
  85. adds r2, r0, r1
  86. cmp r2, r3
  87. bcc CopyDataInit
  88. ldr r2, =_sbss
  89. b LoopFillZerobss
  90. /* Zero fill the bss segment. */
  91. FillZerobss:
  92. movs r3, #0
  93. str r3, [r2], #4
  94. LoopFillZerobss:
  95. ldr r3, = _ebss
  96. cmp r2, r3
  97. bcc FillZerobss
  98. /* Call the clock system intitialization function.*/
  99. bl SystemInit
  100. /* Call static constructors */
  101. bl __libc_init_array
  102. /* Call the application's entry point.*/
  103. bl main
  104. bx lr
  105. .size Reset_Handler, .-Reset_Handler
  106. /**
  107. * @brief This is the code that gets called when the processor receives an
  108. * unexpected interrupt. This simply enters an infinite loop, preserving
  109. * the system state for examination by a debugger.
  110. * @param None
  111. * @retval None
  112. */
  113. .section .text.Default_Handler,"ax",%progbits
  114. Default_Handler:
  115. Infinite_Loop:
  116. b Infinite_Loop
  117. .size Default_Handler, .-Default_Handler
  118. /******************************************************************************
  119. *
  120. * The minimal vector table for a Cortex M3. Note that the proper constructs
  121. * must be placed on this to ensure that it ends up at physical address
  122. * 0x0000.0000.
  123. *
  124. *******************************************************************************/
  125. .section .isr_vector,"a",%progbits
  126. .type g_pfnVectors, %object
  127. .size g_pfnVectors, .-g_pfnVectors
  128. g_pfnVectors:
  129. .word _estack
  130. .word Reset_Handler
  131. .word NMI_Handler
  132. .word HardFault_Handler
  133. .word MemManage_Handler
  134. .word BusFault_Handler
  135. .word UsageFault_Handler
  136. .word 0
  137. .word 0
  138. .word 0
  139. .word 0
  140. .word SVC_Handler
  141. .word DebugMon_Handler
  142. .word 0
  143. .word PendSV_Handler
  144. .word SysTick_Handler
  145. /* External Interrupts */
  146. .word WWDG_IRQHandler /* Window WatchDog */
  147. .word PVD_IRQHandler /* PVD through EXTI Line detection */
  148. .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
  149. .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
  150. .word FLASH_IRQHandler /* FLASH */
  151. .word RCC_IRQHandler /* RCC */
  152. .word EXTI0_IRQHandler /* EXTI Line0 */
  153. .word EXTI1_IRQHandler /* EXTI Line1 */
  154. .word EXTI2_IRQHandler /* EXTI Line2 */
  155. .word EXTI3_IRQHandler /* EXTI Line3 */
  156. .word EXTI4_IRQHandler /* EXTI Line4 */
  157. .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
  158. .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
  159. .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
  160. .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
  161. .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
  162. .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
  163. .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
  164. .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
  165. .word CAN1_TX_IRQHandler /* CAN1 TX */
  166. .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
  167. .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
  168. .word CAN1_SCE_IRQHandler /* CAN1 SCE */
  169. .word EXTI9_5_IRQHandler /* External Line[9:5]s */
  170. .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
  171. .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
  172. .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
  173. .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
  174. .word TIM2_IRQHandler /* TIM2 */
  175. .word TIM3_IRQHandler /* TIM3 */
  176. .word TIM4_IRQHandler /* TIM4 */
  177. .word I2C1_EV_IRQHandler /* I2C1 Event */
  178. .word I2C1_ER_IRQHandler /* I2C1 Error */
  179. .word I2C2_EV_IRQHandler /* I2C2 Event */
  180. .word I2C2_ER_IRQHandler /* I2C2 Error */
  181. .word SPI1_IRQHandler /* SPI1 */
  182. .word SPI2_IRQHandler /* SPI2 */
  183. .word USART1_IRQHandler /* USART1 */
  184. .word USART2_IRQHandler /* USART2 */
  185. .word USART3_IRQHandler /* USART3 */
  186. .word EXTI15_10_IRQHandler /* External Line[15:10]s */
  187. .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
  188. .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
  189. .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
  190. .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
  191. .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
  192. .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
  193. .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
  194. .word FSMC_IRQHandler /* FSMC */
  195. .word SDIO_IRQHandler /* SDIO */
  196. .word TIM5_IRQHandler /* TIM5 */
  197. .word SPI3_IRQHandler /* SPI3 */
  198. .word UART4_IRQHandler /* UART4 */
  199. .word UART5_IRQHandler /* UART5 */
  200. .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
  201. .word TIM7_IRQHandler /* TIM7 */
  202. .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
  203. .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
  204. .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
  205. .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
  206. .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
  207. .word ETH_IRQHandler /* Ethernet */
  208. .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
  209. .word CAN2_TX_IRQHandler /* CAN2 TX */
  210. .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
  211. .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
  212. .word CAN2_SCE_IRQHandler /* CAN2 SCE */
  213. .word OTG_FS_IRQHandler /* USB OTG FS */
  214. .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
  215. .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
  216. .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
  217. .word USART6_IRQHandler /* USART6 */
  218. .word I2C3_EV_IRQHandler /* I2C3 event */
  219. .word I2C3_ER_IRQHandler /* I2C3 error */
  220. .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
  221. .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
  222. .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
  223. .word OTG_HS_IRQHandler /* USB OTG HS */
  224. .word DCMI_IRQHandler /* DCMI */
  225. .word 0 /* CRYP crypto */
  226. .word HASH_RNG_IRQHandler /* Hash and Rng */
  227. .word FPU_IRQHandler /* FPU */
  228. /*******************************************************************************
  229. *
  230. * Provide weak aliases for each Exception handler to the Default_Handler.
  231. * As they are weak aliases, any function with the same name will override
  232. * this definition.
  233. *
  234. *******************************************************************************/
  235. .weak NMI_Handler
  236. .thumb_set NMI_Handler,Default_Handler
  237. .weak HardFault_Handler
  238. .thumb_set HardFault_Handler,Default_Handler
  239. .weak MemManage_Handler
  240. .thumb_set MemManage_Handler,Default_Handler
  241. .weak BusFault_Handler
  242. .thumb_set BusFault_Handler,Default_Handler
  243. .weak UsageFault_Handler
  244. .thumb_set UsageFault_Handler,Default_Handler
  245. .weak SVC_Handler
  246. .thumb_set SVC_Handler,Default_Handler
  247. .weak DebugMon_Handler
  248. .thumb_set DebugMon_Handler,Default_Handler
  249. .weak PendSV_Handler
  250. .thumb_set PendSV_Handler,Default_Handler
  251. .weak SysTick_Handler
  252. .thumb_set SysTick_Handler,Default_Handler
  253. .weak WWDG_IRQHandler
  254. .thumb_set WWDG_IRQHandler,Default_Handler
  255. .weak PVD_IRQHandler
  256. .thumb_set PVD_IRQHandler,Default_Handler
  257. .weak TAMP_STAMP_IRQHandler
  258. .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
  259. .weak RTC_WKUP_IRQHandler
  260. .thumb_set RTC_WKUP_IRQHandler,Default_Handler
  261. .weak FLASH_IRQHandler
  262. .thumb_set FLASH_IRQHandler,Default_Handler
  263. .weak RCC_IRQHandler
  264. .thumb_set RCC_IRQHandler,Default_Handler
  265. .weak EXTI0_IRQHandler
  266. .thumb_set EXTI0_IRQHandler,Default_Handler
  267. .weak EXTI1_IRQHandler
  268. .thumb_set EXTI1_IRQHandler,Default_Handler
  269. .weak EXTI2_IRQHandler
  270. .thumb_set EXTI2_IRQHandler,Default_Handler
  271. .weak EXTI3_IRQHandler
  272. .thumb_set EXTI3_IRQHandler,Default_Handler
  273. .weak EXTI4_IRQHandler
  274. .thumb_set EXTI4_IRQHandler,Default_Handler
  275. .weak DMA1_Stream0_IRQHandler
  276. .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
  277. .weak DMA1_Stream1_IRQHandler
  278. .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
  279. .weak DMA1_Stream2_IRQHandler
  280. .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
  281. .weak DMA1_Stream3_IRQHandler
  282. .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
  283. .weak DMA1_Stream4_IRQHandler
  284. .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
  285. .weak DMA1_Stream5_IRQHandler
  286. .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
  287. .weak DMA1_Stream6_IRQHandler
  288. .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
  289. .weak ADC_IRQHandler
  290. .thumb_set ADC_IRQHandler,Default_Handler
  291. .weak CAN1_TX_IRQHandler
  292. .thumb_set CAN1_TX_IRQHandler,Default_Handler
  293. .weak CAN1_RX0_IRQHandler
  294. .thumb_set CAN1_RX0_IRQHandler,Default_Handler
  295. .weak CAN1_RX1_IRQHandler
  296. .thumb_set CAN1_RX1_IRQHandler,Default_Handler
  297. .weak CAN1_SCE_IRQHandler
  298. .thumb_set CAN1_SCE_IRQHandler,Default_Handler
  299. .weak EXTI9_5_IRQHandler
  300. .thumb_set EXTI9_5_IRQHandler,Default_Handler
  301. .weak TIM1_BRK_TIM9_IRQHandler
  302. .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
  303. .weak TIM1_UP_TIM10_IRQHandler
  304. .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
  305. .weak TIM1_TRG_COM_TIM11_IRQHandler
  306. .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
  307. .weak TIM1_CC_IRQHandler
  308. .thumb_set TIM1_CC_IRQHandler,Default_Handler
  309. .weak TIM2_IRQHandler
  310. .thumb_set TIM2_IRQHandler,Default_Handler
  311. .weak TIM3_IRQHandler
  312. .thumb_set TIM3_IRQHandler,Default_Handler
  313. .weak TIM4_IRQHandler
  314. .thumb_set TIM4_IRQHandler,Default_Handler
  315. .weak I2C1_EV_IRQHandler
  316. .thumb_set I2C1_EV_IRQHandler,Default_Handler
  317. .weak I2C1_ER_IRQHandler
  318. .thumb_set I2C1_ER_IRQHandler,Default_Handler
  319. .weak I2C2_EV_IRQHandler
  320. .thumb_set I2C2_EV_IRQHandler,Default_Handler
  321. .weak I2C2_ER_IRQHandler
  322. .thumb_set I2C2_ER_IRQHandler,Default_Handler
  323. .weak SPI1_IRQHandler
  324. .thumb_set SPI1_IRQHandler,Default_Handler
  325. .weak SPI2_IRQHandler
  326. .thumb_set SPI2_IRQHandler,Default_Handler
  327. .weak USART1_IRQHandler
  328. .thumb_set USART1_IRQHandler,Default_Handler
  329. .weak USART2_IRQHandler
  330. .thumb_set USART2_IRQHandler,Default_Handler
  331. .weak USART3_IRQHandler
  332. .thumb_set USART3_IRQHandler,Default_Handler
  333. .weak EXTI15_10_IRQHandler
  334. .thumb_set EXTI15_10_IRQHandler,Default_Handler
  335. .weak RTC_Alarm_IRQHandler
  336. .thumb_set RTC_Alarm_IRQHandler,Default_Handler
  337. .weak OTG_FS_WKUP_IRQHandler
  338. .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
  339. .weak TIM8_BRK_TIM12_IRQHandler
  340. .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
  341. .weak TIM8_UP_TIM13_IRQHandler
  342. .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
  343. .weak TIM8_TRG_COM_TIM14_IRQHandler
  344. .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
  345. .weak TIM8_CC_IRQHandler
  346. .thumb_set TIM8_CC_IRQHandler,Default_Handler
  347. .weak DMA1_Stream7_IRQHandler
  348. .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
  349. .weak FSMC_IRQHandler
  350. .thumb_set FSMC_IRQHandler,Default_Handler
  351. .weak SDIO_IRQHandler
  352. .thumb_set SDIO_IRQHandler,Default_Handler
  353. .weak TIM5_IRQHandler
  354. .thumb_set TIM5_IRQHandler,Default_Handler
  355. .weak SPI3_IRQHandler
  356. .thumb_set SPI3_IRQHandler,Default_Handler
  357. .weak UART4_IRQHandler
  358. .thumb_set UART4_IRQHandler,Default_Handler
  359. .weak UART5_IRQHandler
  360. .thumb_set UART5_IRQHandler,Default_Handler
  361. .weak TIM6_DAC_IRQHandler
  362. .thumb_set TIM6_DAC_IRQHandler,Default_Handler
  363. .weak TIM7_IRQHandler
  364. .thumb_set TIM7_IRQHandler,Default_Handler
  365. .weak DMA2_Stream0_IRQHandler
  366. .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
  367. .weak DMA2_Stream1_IRQHandler
  368. .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
  369. .weak DMA2_Stream2_IRQHandler
  370. .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
  371. .weak DMA2_Stream3_IRQHandler
  372. .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
  373. .weak DMA2_Stream4_IRQHandler
  374. .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
  375. .weak ETH_IRQHandler
  376. .thumb_set ETH_IRQHandler,Default_Handler
  377. .weak ETH_WKUP_IRQHandler
  378. .thumb_set ETH_WKUP_IRQHandler,Default_Handler
  379. .weak CAN2_TX_IRQHandler
  380. .thumb_set CAN2_TX_IRQHandler,Default_Handler
  381. .weak CAN2_RX0_IRQHandler
  382. .thumb_set CAN2_RX0_IRQHandler,Default_Handler
  383. .weak CAN2_RX1_IRQHandler
  384. .thumb_set CAN2_RX1_IRQHandler,Default_Handler
  385. .weak CAN2_SCE_IRQHandler
  386. .thumb_set CAN2_SCE_IRQHandler,Default_Handler
  387. .weak OTG_FS_IRQHandler
  388. .thumb_set OTG_FS_IRQHandler,Default_Handler
  389. .weak DMA2_Stream5_IRQHandler
  390. .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
  391. .weak DMA2_Stream6_IRQHandler
  392. .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
  393. .weak DMA2_Stream7_IRQHandler
  394. .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
  395. .weak USART6_IRQHandler
  396. .thumb_set USART6_IRQHandler,Default_Handler
  397. .weak I2C3_EV_IRQHandler
  398. .thumb_set I2C3_EV_IRQHandler,Default_Handler
  399. .weak I2C3_ER_IRQHandler
  400. .thumb_set I2C3_ER_IRQHandler,Default_Handler
  401. .weak OTG_HS_EP1_OUT_IRQHandler
  402. .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
  403. .weak OTG_HS_EP1_IN_IRQHandler
  404. .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
  405. .weak OTG_HS_WKUP_IRQHandler
  406. .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
  407. .weak OTG_HS_IRQHandler
  408. .thumb_set OTG_HS_IRQHandler,Default_Handler
  409. .weak DCMI_IRQHandler
  410. .thumb_set DCMI_IRQHandler,Default_Handler
  411. .weak HASH_RNG_IRQHandler
  412. .thumb_set HASH_RNG_IRQHandler,Default_Handler
  413. .weak FPU_IRQHandler
  414. .thumb_set FPU_IRQHandler,Default_Handler
  415. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/